2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
42 #include "i915_debugfs.h"
44 #include "intel_atomic.h"
45 #include "intel_audio.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
48 #include "intel_display_types.h"
50 #include "intel_dpio_phy.h"
51 #include "intel_fifo_underrun.h"
52 #include "intel_gmbus.h"
53 #include "intel_hdcp.h"
54 #include "intel_hdmi.h"
55 #include "intel_hotplug.h"
56 #include "intel_lspcon.h"
57 #include "intel_panel.h"
58 #include "intel_sdvo.h"
59 #include "intel_sideband.h"
61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
63 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
69 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
70 struct drm_i915_private *dev_priv = to_i915(dev);
73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
76 "HDMI port enabled, expecting disabled\n");
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
81 enum transcoder cpu_transcoder)
83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
84 TRANS_DDI_FUNC_ENABLE,
85 "HDMI transcoder function enabled, expecting disabled\n");
88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
90 struct intel_digital_port *intel_dig_port =
91 container_of(encoder, struct intel_digital_port, base.base);
92 return &intel_dig_port->hdmi;
95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
97 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
100 static u32 g4x_infoframe_index(unsigned int type)
103 case HDMI_PACKET_TYPE_GAMUT_METADATA:
104 return VIDEO_DIP_SELECT_GAMUT;
105 case HDMI_INFOFRAME_TYPE_AVI:
106 return VIDEO_DIP_SELECT_AVI;
107 case HDMI_INFOFRAME_TYPE_SPD:
108 return VIDEO_DIP_SELECT_SPD;
109 case HDMI_INFOFRAME_TYPE_VENDOR:
110 return VIDEO_DIP_SELECT_VENDOR;
117 static u32 g4x_infoframe_enable(unsigned int type)
120 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
121 return VIDEO_DIP_ENABLE_GCP;
122 case HDMI_PACKET_TYPE_GAMUT_METADATA:
123 return VIDEO_DIP_ENABLE_GAMUT;
126 case HDMI_INFOFRAME_TYPE_AVI:
127 return VIDEO_DIP_ENABLE_AVI;
128 case HDMI_INFOFRAME_TYPE_SPD:
129 return VIDEO_DIP_ENABLE_SPD;
130 case HDMI_INFOFRAME_TYPE_VENDOR:
131 return VIDEO_DIP_ENABLE_VENDOR;
132 case HDMI_INFOFRAME_TYPE_DRM:
140 static u32 hsw_infoframe_enable(unsigned int type)
143 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
144 return VIDEO_DIP_ENABLE_GCP_HSW;
145 case HDMI_PACKET_TYPE_GAMUT_METADATA:
146 return VIDEO_DIP_ENABLE_GMP_HSW;
148 return VIDEO_DIP_ENABLE_VSC_HSW;
150 return VDIP_ENABLE_PPS;
151 case HDMI_INFOFRAME_TYPE_AVI:
152 return VIDEO_DIP_ENABLE_AVI_HSW;
153 case HDMI_INFOFRAME_TYPE_SPD:
154 return VIDEO_DIP_ENABLE_SPD_HSW;
155 case HDMI_INFOFRAME_TYPE_VENDOR:
156 return VIDEO_DIP_ENABLE_VS_HSW;
157 case HDMI_INFOFRAME_TYPE_DRM:
158 return VIDEO_DIP_ENABLE_DRM_GLK;
166 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
167 enum transcoder cpu_transcoder,
172 case HDMI_PACKET_TYPE_GAMUT_METADATA:
173 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
175 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
177 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
178 case HDMI_INFOFRAME_TYPE_AVI:
179 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
180 case HDMI_INFOFRAME_TYPE_SPD:
181 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
182 case HDMI_INFOFRAME_TYPE_VENDOR:
183 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
184 case HDMI_INFOFRAME_TYPE_DRM:
185 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
188 return INVALID_MMIO_REG;
192 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
197 return VIDEO_DIP_VSC_DATA_SIZE;
199 return VIDEO_DIP_PPS_DATA_SIZE;
200 case HDMI_PACKET_TYPE_GAMUT_METADATA:
201 if (INTEL_GEN(dev_priv) >= 11)
202 return VIDEO_DIP_GMP_DATA_SIZE;
204 return VIDEO_DIP_DATA_SIZE;
206 return VIDEO_DIP_DATA_SIZE;
210 static void g4x_write_infoframe(struct intel_encoder *encoder,
211 const struct intel_crtc_state *crtc_state,
213 const void *frame, ssize_t len)
215 const u32 *data = frame;
216 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
217 u32 val = I915_READ(VIDEO_DIP_CTL);
220 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
222 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
223 val |= g4x_infoframe_index(type);
225 val &= ~g4x_infoframe_enable(type);
227 I915_WRITE(VIDEO_DIP_CTL, val);
229 for (i = 0; i < len; i += 4) {
230 I915_WRITE(VIDEO_DIP_DATA, *data);
233 /* Write every possible data byte to force correct ECC calculation. */
234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
235 I915_WRITE(VIDEO_DIP_DATA, 0);
237 val |= g4x_infoframe_enable(type);
238 val &= ~VIDEO_DIP_FREQ_MASK;
239 val |= VIDEO_DIP_FREQ_VSYNC;
241 I915_WRITE(VIDEO_DIP_CTL, val);
242 POSTING_READ(VIDEO_DIP_CTL);
245 static void g4x_read_infoframe(struct intel_encoder *encoder,
246 const struct intel_crtc_state *crtc_state,
248 void *frame, ssize_t len)
250 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
251 u32 val, *data = frame;
254 val = I915_READ(VIDEO_DIP_CTL);
256 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
257 val |= g4x_infoframe_index(type);
259 I915_WRITE(VIDEO_DIP_CTL, val);
261 for (i = 0; i < len; i += 4)
262 *data++ = I915_READ(VIDEO_DIP_DATA);
265 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
266 const struct intel_crtc_state *pipe_config)
268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
269 u32 val = I915_READ(VIDEO_DIP_CTL);
271 if ((val & VIDEO_DIP_ENABLE) == 0)
274 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
277 return val & (VIDEO_DIP_ENABLE_AVI |
278 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
281 static void ibx_write_infoframe(struct intel_encoder *encoder,
282 const struct intel_crtc_state *crtc_state,
284 const void *frame, ssize_t len)
286 const u32 *data = frame;
287 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
289 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
290 u32 val = I915_READ(reg);
293 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
295 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
296 val |= g4x_infoframe_index(type);
298 val &= ~g4x_infoframe_enable(type);
300 I915_WRITE(reg, val);
302 for (i = 0; i < len; i += 4) {
303 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
306 /* Write every possible data byte to force correct ECC calculation. */
307 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
308 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
310 val |= g4x_infoframe_enable(type);
311 val &= ~VIDEO_DIP_FREQ_MASK;
312 val |= VIDEO_DIP_FREQ_VSYNC;
314 I915_WRITE(reg, val);
318 static void ibx_read_infoframe(struct intel_encoder *encoder,
319 const struct intel_crtc_state *crtc_state,
321 void *frame, ssize_t len)
323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
325 u32 val, *data = frame;
328 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
330 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
331 val |= g4x_infoframe_index(type);
333 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
335 for (i = 0; i < len; i += 4)
336 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
339 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
340 const struct intel_crtc_state *pipe_config)
342 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
343 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
344 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
345 u32 val = I915_READ(reg);
347 if ((val & VIDEO_DIP_ENABLE) == 0)
350 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
353 return val & (VIDEO_DIP_ENABLE_AVI |
354 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
355 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
358 static void cpt_write_infoframe(struct intel_encoder *encoder,
359 const struct intel_crtc_state *crtc_state,
361 const void *frame, ssize_t len)
363 const u32 *data = frame;
364 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
366 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
367 u32 val = I915_READ(reg);
370 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
372 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
373 val |= g4x_infoframe_index(type);
375 /* The DIP control register spec says that we need to update the AVI
376 * infoframe without clearing its enable bit */
377 if (type != HDMI_INFOFRAME_TYPE_AVI)
378 val &= ~g4x_infoframe_enable(type);
380 I915_WRITE(reg, val);
382 for (i = 0; i < len; i += 4) {
383 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
386 /* Write every possible data byte to force correct ECC calculation. */
387 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
388 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
390 val |= g4x_infoframe_enable(type);
391 val &= ~VIDEO_DIP_FREQ_MASK;
392 val |= VIDEO_DIP_FREQ_VSYNC;
394 I915_WRITE(reg, val);
398 static void cpt_read_infoframe(struct intel_encoder *encoder,
399 const struct intel_crtc_state *crtc_state,
401 void *frame, ssize_t len)
403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
404 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
405 u32 val, *data = frame;
408 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
410 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
411 val |= g4x_infoframe_index(type);
413 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
415 for (i = 0; i < len; i += 4)
416 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
419 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
420 const struct intel_crtc_state *pipe_config)
422 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
423 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
424 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
426 if ((val & VIDEO_DIP_ENABLE) == 0)
429 return val & (VIDEO_DIP_ENABLE_AVI |
430 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
431 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
434 static void vlv_write_infoframe(struct intel_encoder *encoder,
435 const struct intel_crtc_state *crtc_state,
437 const void *frame, ssize_t len)
439 const u32 *data = frame;
440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
442 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
443 u32 val = I915_READ(reg);
446 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
448 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
449 val |= g4x_infoframe_index(type);
451 val &= ~g4x_infoframe_enable(type);
453 I915_WRITE(reg, val);
455 for (i = 0; i < len; i += 4) {
456 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
459 /* Write every possible data byte to force correct ECC calculation. */
460 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
461 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
463 val |= g4x_infoframe_enable(type);
464 val &= ~VIDEO_DIP_FREQ_MASK;
465 val |= VIDEO_DIP_FREQ_VSYNC;
467 I915_WRITE(reg, val);
471 static void vlv_read_infoframe(struct intel_encoder *encoder,
472 const struct intel_crtc_state *crtc_state,
474 void *frame, ssize_t len)
476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
477 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
478 u32 val, *data = frame;
481 val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
483 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
484 val |= g4x_infoframe_index(type);
486 I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
488 for (i = 0; i < len; i += 4)
489 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
492 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
493 const struct intel_crtc_state *pipe_config)
495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
496 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
497 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
499 if ((val & VIDEO_DIP_ENABLE) == 0)
502 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
505 return val & (VIDEO_DIP_ENABLE_AVI |
506 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
507 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
510 static void hsw_write_infoframe(struct intel_encoder *encoder,
511 const struct intel_crtc_state *crtc_state,
513 const void *frame, ssize_t len)
515 const u32 *data = frame;
516 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
517 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
518 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
521 u32 val = I915_READ(ctl_reg);
523 data_size = hsw_dip_data_size(dev_priv, type);
525 WARN_ON(len > data_size);
527 val &= ~hsw_infoframe_enable(type);
528 I915_WRITE(ctl_reg, val);
530 for (i = 0; i < len; i += 4) {
531 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
532 type, i >> 2), *data);
535 /* Write every possible data byte to force correct ECC calculation. */
536 for (; i < data_size; i += 4)
537 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
540 val |= hsw_infoframe_enable(type);
541 I915_WRITE(ctl_reg, val);
542 POSTING_READ(ctl_reg);
545 static void hsw_read_infoframe(struct intel_encoder *encoder,
546 const struct intel_crtc_state *crtc_state,
548 void *frame, ssize_t len)
550 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
552 u32 val, *data = frame;
555 val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
557 for (i = 0; i < len; i += 4)
558 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
562 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
563 const struct intel_crtc_state *pipe_config)
565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
566 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
569 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
570 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
571 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
573 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
574 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
579 static const u8 infoframe_type_to_idx[] = {
580 HDMI_PACKET_TYPE_GENERAL_CONTROL,
581 HDMI_PACKET_TYPE_GAMUT_METADATA,
583 HDMI_INFOFRAME_TYPE_AVI,
584 HDMI_INFOFRAME_TYPE_SPD,
585 HDMI_INFOFRAME_TYPE_VENDOR,
586 HDMI_INFOFRAME_TYPE_DRM,
589 u32 intel_hdmi_infoframe_enable(unsigned int type)
593 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
594 if (infoframe_type_to_idx[i] == type)
601 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
602 const struct intel_crtc_state *crtc_state)
604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
605 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
609 val = dig_port->infoframes_enabled(encoder, crtc_state);
611 /* map from hardware bits to dip idx */
612 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
613 unsigned int type = infoframe_type_to_idx[i];
615 if (HAS_DDI(dev_priv)) {
616 if (val & hsw_infoframe_enable(type))
619 if (val & g4x_infoframe_enable(type))
628 * The data we write to the DIP data buffer registers is 1 byte bigger than the
629 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
630 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
631 * used for both technologies.
633 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
634 * DW1: DB3 | DB2 | DB1 | DB0
635 * DW2: DB7 | DB6 | DB5 | DB4
638 * (HB is Header Byte, DB is Data Byte)
640 * The hdmi pack() functions don't know about that hardware specific hole so we
641 * trick them by giving an offset into the buffer and moving back the header
644 static void intel_write_infoframe(struct intel_encoder *encoder,
645 const struct intel_crtc_state *crtc_state,
646 enum hdmi_infoframe_type type,
647 const union hdmi_infoframe *frame)
649 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
650 u8 buffer[VIDEO_DIP_DATA_SIZE];
653 if ((crtc_state->infoframes.enable &
654 intel_hdmi_infoframe_enable(type)) == 0)
657 if (WARN_ON(frame->any.type != type))
660 /* see comment above for the reason for this offset */
661 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
662 if (WARN_ON(len < 0))
665 /* Insert the 'hole' (see big comment above) at position 3 */
666 memmove(&buffer[0], &buffer[1], 3);
670 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
673 void intel_read_infoframe(struct intel_encoder *encoder,
674 const struct intel_crtc_state *crtc_state,
675 enum hdmi_infoframe_type type,
676 union hdmi_infoframe *frame)
678 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
679 u8 buffer[VIDEO_DIP_DATA_SIZE];
682 if ((crtc_state->infoframes.enable &
683 intel_hdmi_infoframe_enable(type)) == 0)
686 intel_dig_port->read_infoframe(encoder, crtc_state,
687 type, buffer, sizeof(buffer));
689 /* Fill the 'hole' (see big comment above) at position 3 */
690 memmove(&buffer[1], &buffer[0], 3);
692 /* see comment above for the reason for this offset */
693 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
695 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
699 if (frame->any.type != type)
700 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
701 frame->any.type, type);
705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
706 struct intel_crtc_state *crtc_state,
707 struct drm_connector_state *conn_state)
709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
710 const struct drm_display_mode *adjusted_mode =
711 &crtc_state->base.adjusted_mode;
712 struct drm_connector *connector = conn_state->connector;
715 if (!crtc_state->has_infoframe)
718 crtc_state->infoframes.enable |=
719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
727 frame->colorspace = HDMI_COLORSPACE_YUV420;
728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
729 frame->colorspace = HDMI_COLORSPACE_YUV444;
731 frame->colorspace = HDMI_COLORSPACE_RGB;
733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
735 /* nonsense combination */
736 WARN_ON(crtc_state->limited_color_range &&
737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
740 drm_hdmi_avi_infoframe_quant_range(frame, connector,
742 crtc_state->limited_color_range ?
743 HDMI_QUANTIZATION_RANGE_LIMITED :
744 HDMI_QUANTIZATION_RANGE_FULL);
746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
750 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
752 /* TODO: handle pixel repetition for YCBCR420 outputs */
754 ret = hdmi_avi_infoframe_check(frame);
762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
763 struct intel_crtc_state *crtc_state,
764 struct drm_connector_state *conn_state)
766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
769 if (!crtc_state->has_infoframe)
772 crtc_state->infoframes.enable |=
773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
779 frame->sdi = HDMI_SPD_SDI_PC;
781 ret = hdmi_spd_infoframe_check(frame);
789 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
790 struct intel_crtc_state *crtc_state,
791 struct drm_connector_state *conn_state)
793 struct hdmi_vendor_infoframe *frame =
794 &crtc_state->infoframes.hdmi.vendor.hdmi;
795 const struct drm_display_info *info =
796 &conn_state->connector->display_info;
799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
802 crtc_state->infoframes.enable |=
803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
806 conn_state->connector,
807 &crtc_state->base.adjusted_mode);
811 ret = hdmi_vendor_infoframe_check(frame);
819 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
820 struct intel_crtc_state *crtc_state,
821 struct drm_connector_state *conn_state)
823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
827 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
830 if (!crtc_state->has_infoframe)
833 if (!conn_state->hdr_output_metadata)
836 crtc_state->infoframes.enable |=
837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
841 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
845 ret = hdmi_drm_infoframe_check(frame);
852 static void g4x_set_infoframes(struct intel_encoder *encoder,
854 const struct intel_crtc_state *crtc_state,
855 const struct drm_connector_state *conn_state)
857 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
858 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
859 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
860 i915_reg_t reg = VIDEO_DIP_CTL;
861 u32 val = I915_READ(reg);
862 u32 port = VIDEO_DIP_PORT(encoder->port);
864 assert_hdmi_port_disabled(intel_hdmi);
866 /* If the registers were not initialized yet, they might be zeroes,
867 * which means we're selecting the AVI DIP and we're setting its
868 * frequency to once. This seems to really confuse the HW and make
869 * things stop working (the register spec says the AVI always needs to
870 * be sent every VSync). So here we avoid writing to the register more
871 * than we need and also explicitly select the AVI DIP and explicitly
872 * set its frequency to every VSync. Avoiding to write it twice seems to
873 * be enough to solve the problem, but being defensive shouldn't hurt us
875 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
878 if (!(val & VIDEO_DIP_ENABLE))
880 if (port != (val & VIDEO_DIP_PORT_MASK)) {
881 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
882 (val & VIDEO_DIP_PORT_MASK) >> 29);
885 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
886 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
887 I915_WRITE(reg, val);
892 if (port != (val & VIDEO_DIP_PORT_MASK)) {
893 if (val & VIDEO_DIP_ENABLE) {
894 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
895 (val & VIDEO_DIP_PORT_MASK) >> 29);
898 val &= ~VIDEO_DIP_PORT_MASK;
902 val |= VIDEO_DIP_ENABLE;
903 val &= ~(VIDEO_DIP_ENABLE_AVI |
904 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
906 I915_WRITE(reg, val);
909 intel_write_infoframe(encoder, crtc_state,
910 HDMI_INFOFRAME_TYPE_AVI,
911 &crtc_state->infoframes.avi);
912 intel_write_infoframe(encoder, crtc_state,
913 HDMI_INFOFRAME_TYPE_SPD,
914 &crtc_state->infoframes.spd);
915 intel_write_infoframe(encoder, crtc_state,
916 HDMI_INFOFRAME_TYPE_VENDOR,
917 &crtc_state->infoframes.hdmi);
921 * Determine if default_phase=1 can be indicated in the GCP infoframe.
923 * From HDMI specification 1.4a:
924 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
925 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
926 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
927 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
930 static bool gcp_default_phase_possible(int pipe_bpp,
931 const struct drm_display_mode *mode)
933 unsigned int pixels_per_group;
937 /* 4 pixels in 5 clocks */
938 pixels_per_group = 4;
941 /* 2 pixels in 3 clocks */
942 pixels_per_group = 2;
945 /* 1 pixel in 2 clocks */
946 pixels_per_group = 1;
949 /* phase information not relevant for 8bpc */
953 return mode->crtc_hdisplay % pixels_per_group == 0 &&
954 mode->crtc_htotal % pixels_per_group == 0 &&
955 mode->crtc_hblank_start % pixels_per_group == 0 &&
956 mode->crtc_hblank_end % pixels_per_group == 0 &&
957 mode->crtc_hsync_start % pixels_per_group == 0 &&
958 mode->crtc_hsync_end % pixels_per_group == 0 &&
959 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
960 mode->crtc_htotal/2 % pixels_per_group == 0);
963 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
964 const struct intel_crtc_state *crtc_state,
965 const struct drm_connector_state *conn_state)
967 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
968 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
971 if ((crtc_state->infoframes.enable &
972 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
975 if (HAS_DDI(dev_priv))
976 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
977 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
978 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
979 else if (HAS_PCH_SPLIT(dev_priv))
980 reg = TVIDEO_DIP_GCP(crtc->pipe);
984 I915_WRITE(reg, crtc_state->infoframes.gcp);
989 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
990 struct intel_crtc_state *crtc_state)
992 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
996 if ((crtc_state->infoframes.enable &
997 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1000 if (HAS_DDI(dev_priv))
1001 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1002 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1003 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1004 else if (HAS_PCH_SPLIT(dev_priv))
1005 reg = TVIDEO_DIP_GCP(crtc->pipe);
1009 crtc_state->infoframes.gcp = I915_READ(reg);
1012 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1013 struct intel_crtc_state *crtc_state,
1014 struct drm_connector_state *conn_state)
1016 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1018 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1021 crtc_state->infoframes.enable |=
1022 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1024 /* Indicate color indication for deep color mode */
1025 if (crtc_state->pipe_bpp > 24)
1026 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1028 /* Enable default_phase whenever the display mode is suitably aligned */
1029 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1030 &crtc_state->base.adjusted_mode))
1031 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1034 static void ibx_set_infoframes(struct intel_encoder *encoder,
1036 const struct intel_crtc_state *crtc_state,
1037 const struct drm_connector_state *conn_state)
1039 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1041 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1042 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1043 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1044 u32 val = I915_READ(reg);
1045 u32 port = VIDEO_DIP_PORT(encoder->port);
1047 assert_hdmi_port_disabled(intel_hdmi);
1049 /* See the big comment in g4x_set_infoframes() */
1050 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1053 if (!(val & VIDEO_DIP_ENABLE))
1055 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1056 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1057 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1058 I915_WRITE(reg, val);
1063 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1064 WARN(val & VIDEO_DIP_ENABLE,
1065 "DIP already enabled on port %c\n",
1066 (val & VIDEO_DIP_PORT_MASK) >> 29);
1067 val &= ~VIDEO_DIP_PORT_MASK;
1071 val |= VIDEO_DIP_ENABLE;
1072 val &= ~(VIDEO_DIP_ENABLE_AVI |
1073 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1074 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1076 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1077 val |= VIDEO_DIP_ENABLE_GCP;
1079 I915_WRITE(reg, val);
1082 intel_write_infoframe(encoder, crtc_state,
1083 HDMI_INFOFRAME_TYPE_AVI,
1084 &crtc_state->infoframes.avi);
1085 intel_write_infoframe(encoder, crtc_state,
1086 HDMI_INFOFRAME_TYPE_SPD,
1087 &crtc_state->infoframes.spd);
1088 intel_write_infoframe(encoder, crtc_state,
1089 HDMI_INFOFRAME_TYPE_VENDOR,
1090 &crtc_state->infoframes.hdmi);
1093 static void cpt_set_infoframes(struct intel_encoder *encoder,
1095 const struct intel_crtc_state *crtc_state,
1096 const struct drm_connector_state *conn_state)
1098 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1100 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1101 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1102 u32 val = I915_READ(reg);
1104 assert_hdmi_port_disabled(intel_hdmi);
1106 /* See the big comment in g4x_set_infoframes() */
1107 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1110 if (!(val & VIDEO_DIP_ENABLE))
1112 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1113 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1114 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1115 I915_WRITE(reg, val);
1120 /* Set both together, unset both together: see the spec. */
1121 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1122 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1123 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1125 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1126 val |= VIDEO_DIP_ENABLE_GCP;
1128 I915_WRITE(reg, val);
1131 intel_write_infoframe(encoder, crtc_state,
1132 HDMI_INFOFRAME_TYPE_AVI,
1133 &crtc_state->infoframes.avi);
1134 intel_write_infoframe(encoder, crtc_state,
1135 HDMI_INFOFRAME_TYPE_SPD,
1136 &crtc_state->infoframes.spd);
1137 intel_write_infoframe(encoder, crtc_state,
1138 HDMI_INFOFRAME_TYPE_VENDOR,
1139 &crtc_state->infoframes.hdmi);
1142 static void vlv_set_infoframes(struct intel_encoder *encoder,
1144 const struct intel_crtc_state *crtc_state,
1145 const struct drm_connector_state *conn_state)
1147 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1149 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1150 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1151 u32 val = I915_READ(reg);
1152 u32 port = VIDEO_DIP_PORT(encoder->port);
1154 assert_hdmi_port_disabled(intel_hdmi);
1156 /* See the big comment in g4x_set_infoframes() */
1157 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1160 if (!(val & VIDEO_DIP_ENABLE))
1162 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1163 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1164 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1165 I915_WRITE(reg, val);
1170 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1171 WARN(val & VIDEO_DIP_ENABLE,
1172 "DIP already enabled on port %c\n",
1173 (val & VIDEO_DIP_PORT_MASK) >> 29);
1174 val &= ~VIDEO_DIP_PORT_MASK;
1178 val |= VIDEO_DIP_ENABLE;
1179 val &= ~(VIDEO_DIP_ENABLE_AVI |
1180 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1181 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1183 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1184 val |= VIDEO_DIP_ENABLE_GCP;
1186 I915_WRITE(reg, val);
1189 intel_write_infoframe(encoder, crtc_state,
1190 HDMI_INFOFRAME_TYPE_AVI,
1191 &crtc_state->infoframes.avi);
1192 intel_write_infoframe(encoder, crtc_state,
1193 HDMI_INFOFRAME_TYPE_SPD,
1194 &crtc_state->infoframes.spd);
1195 intel_write_infoframe(encoder, crtc_state,
1196 HDMI_INFOFRAME_TYPE_VENDOR,
1197 &crtc_state->infoframes.hdmi);
1200 static void hsw_set_infoframes(struct intel_encoder *encoder,
1202 const struct intel_crtc_state *crtc_state,
1203 const struct drm_connector_state *conn_state)
1205 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1206 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1207 u32 val = I915_READ(reg);
1209 assert_hdmi_transcoder_func_disabled(dev_priv,
1210 crtc_state->cpu_transcoder);
1212 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1213 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1214 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1215 VIDEO_DIP_ENABLE_DRM_GLK);
1218 I915_WRITE(reg, val);
1223 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1224 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1226 I915_WRITE(reg, val);
1229 intel_write_infoframe(encoder, crtc_state,
1230 HDMI_INFOFRAME_TYPE_AVI,
1231 &crtc_state->infoframes.avi);
1232 intel_write_infoframe(encoder, crtc_state,
1233 HDMI_INFOFRAME_TYPE_SPD,
1234 &crtc_state->infoframes.spd);
1235 intel_write_infoframe(encoder, crtc_state,
1236 HDMI_INFOFRAME_TYPE_VENDOR,
1237 &crtc_state->infoframes.hdmi);
1238 intel_write_infoframe(encoder, crtc_state,
1239 HDMI_INFOFRAME_TYPE_DRM,
1240 &crtc_state->infoframes.drm);
1243 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1245 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1246 struct i2c_adapter *adapter =
1247 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1249 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1252 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1253 enable ? "Enabling" : "Disabling");
1255 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1259 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1260 unsigned int offset, void *buffer, size_t size)
1262 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1263 struct drm_i915_private *dev_priv =
1264 intel_dig_port->base.base.dev->dev_private;
1265 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1268 u8 start = offset & 0xff;
1269 struct i2c_msg msgs[] = {
1271 .addr = DRM_HDCP_DDC_ADDR,
1277 .addr = DRM_HDCP_DDC_ADDR,
1283 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1284 if (ret == ARRAY_SIZE(msgs))
1286 return ret >= 0 ? -EIO : ret;
1289 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1290 unsigned int offset, void *buffer, size_t size)
1292 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1293 struct drm_i915_private *dev_priv =
1294 intel_dig_port->base.base.dev->dev_private;
1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1301 write_buf = kzalloc(size + 1, GFP_KERNEL);
1305 write_buf[0] = offset & 0xff;
1306 memcpy(&write_buf[1], buffer, size);
1308 msg.addr = DRM_HDCP_DDC_ADDR;
1311 msg.buf = write_buf;
1313 ret = i2c_transfer(adapter, &msg, 1);
1324 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1327 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1328 struct drm_i915_private *dev_priv =
1329 intel_dig_port->base.base.dev->dev_private;
1330 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1334 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1337 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1341 ret = intel_gmbus_output_aksv(adapter);
1343 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1349 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1353 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1356 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1361 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1365 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1366 bstatus, DRM_HDCP_BSTATUS_LEN);
1368 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1373 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1374 bool *repeater_present)
1379 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1381 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1384 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1389 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1393 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1394 ri_prime, DRM_HDCP_RI_LEN);
1396 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1401 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1407 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1409 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1412 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1417 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1418 int num_downstream, u8 *ksv_fifo)
1421 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1422 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1424 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1431 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1436 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1439 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1440 part, DRM_HDCP_V_PRIME_PART_LEN);
1442 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1446 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1448 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1449 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1450 struct drm_crtc *crtc = connector->base.state->crtc;
1451 struct intel_crtc *intel_crtc = container_of(crtc,
1452 struct intel_crtc, base);
1457 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1458 if (scanline > 100 && scanline < 200)
1460 usleep_range(25, 50);
1463 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1465 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1468 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1470 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1478 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1481 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1482 struct intel_connector *connector = hdmi->attached_connector;
1483 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1487 usleep_range(6, 60); /* Bspec says >= 6us */
1489 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1491 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1492 enable ? "Enable" : "Disable", ret);
1497 * WA: To fix incorrect positioning of the window of
1498 * opportunity and enc_en signalling in KABYLAKE.
1500 if (IS_KABYLAKE(dev_priv) && enable)
1501 return kbl_repositioning_enc_en_signal(connector);
1507 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1509 struct drm_i915_private *dev_priv =
1510 intel_dig_port->base.base.dev->dev_private;
1511 struct intel_connector *connector =
1512 intel_dig_port->hdmi.attached_connector;
1513 enum port port = intel_dig_port->base.port;
1514 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1518 u8 shim[DRM_HDCP_RI_LEN];
1521 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1525 I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
1527 /* Wait for Ri prime match */
1528 if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
1529 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1530 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1531 I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
1538 struct hdcp2_hdmi_msg_timeout {
1543 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1544 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1545 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1546 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1547 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1548 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1552 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1555 return intel_hdmi_hdcp_read(intel_dig_port,
1556 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1558 HDCP_2_2_HDMI_RXSTATUS_LEN);
1561 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1565 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1567 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1569 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1572 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1573 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1574 return hdcp2_msg_timeout[i].timeout;
1581 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1582 u8 msg_id, bool *msg_ready,
1585 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1588 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1590 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1594 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1597 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1598 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1601 *msg_ready = *msg_sz;
1607 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1608 u8 msg_id, bool paired)
1610 bool msg_ready = false;
1614 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1618 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1621 !ret && msg_ready && msg_sz, timeout * 1000,
1624 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1625 msg_id, ret, timeout);
1627 return ret ? ret : msg_sz;
1631 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1632 void *buf, size_t size)
1634 unsigned int offset;
1636 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1637 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1641 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1642 u8 msg_id, void *buf, size_t size)
1644 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1645 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1646 unsigned int offset;
1649 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1655 * Available msg size should be equal to or lesser than the
1659 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1664 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1665 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1667 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1673 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1675 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1678 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1683 * Re-auth request and Link Integrity Failures are represented by
1684 * same bit. i.e reauth_req.
1686 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1687 ret = HDCP_REAUTH_REQUEST;
1688 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1689 ret = HDCP_TOPOLOGY_CHANGE;
1695 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1702 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1703 &hdcp2_version, sizeof(hdcp2_version));
1704 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1711 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1713 return HDCP_PROTOCOL_HDMI;
1716 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1717 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1718 .read_bksv = intel_hdmi_hdcp_read_bksv,
1719 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1720 .repeater_present = intel_hdmi_hdcp_repeater_present,
1721 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1722 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1723 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1724 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1725 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1726 .check_link = intel_hdmi_hdcp_check_link,
1727 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1728 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1729 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1730 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1731 .protocol = HDCP_PROTOCOL_HDMI,
1734 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1735 const struct intel_crtc_state *crtc_state)
1737 struct drm_device *dev = encoder->base.dev;
1738 struct drm_i915_private *dev_priv = to_i915(dev);
1739 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1740 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1741 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1744 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1746 hdmi_val = SDVO_ENCODING_HDMI;
1747 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1748 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1749 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1750 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1751 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1752 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1754 if (crtc_state->pipe_bpp > 24)
1755 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1757 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1759 if (crtc_state->has_hdmi_sink)
1760 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1762 if (HAS_PCH_CPT(dev_priv))
1763 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1764 else if (IS_CHERRYVIEW(dev_priv))
1765 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1767 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1769 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1770 POSTING_READ(intel_hdmi->hdmi_reg);
1773 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1777 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1778 intel_wakeref_t wakeref;
1781 wakeref = intel_display_power_get_if_enabled(dev_priv,
1782 encoder->power_domain);
1786 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1788 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1793 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1794 struct intel_crtc_state *pipe_config)
1796 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1797 struct drm_device *dev = encoder->base.dev;
1798 struct drm_i915_private *dev_priv = to_i915(dev);
1802 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1804 tmp = I915_READ(intel_hdmi->hdmi_reg);
1806 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1807 flags |= DRM_MODE_FLAG_PHSYNC;
1809 flags |= DRM_MODE_FLAG_NHSYNC;
1811 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1812 flags |= DRM_MODE_FLAG_PVSYNC;
1814 flags |= DRM_MODE_FLAG_NVSYNC;
1816 if (tmp & HDMI_MODE_SELECT_HDMI)
1817 pipe_config->has_hdmi_sink = true;
1819 pipe_config->infoframes.enable |=
1820 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1822 if (pipe_config->infoframes.enable)
1823 pipe_config->has_infoframe = true;
1825 if (tmp & HDMI_AUDIO_ENABLE)
1826 pipe_config->has_audio = true;
1828 if (!HAS_PCH_SPLIT(dev_priv) &&
1829 tmp & HDMI_COLOR_RANGE_16_235)
1830 pipe_config->limited_color_range = true;
1832 pipe_config->base.adjusted_mode.flags |= flags;
1834 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1835 dotclock = pipe_config->port_clock * 2 / 3;
1837 dotclock = pipe_config->port_clock;
1839 if (pipe_config->pixel_multiplier)
1840 dotclock /= pipe_config->pixel_multiplier;
1842 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1844 pipe_config->lane_count = 4;
1846 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1848 intel_read_infoframe(encoder, pipe_config,
1849 HDMI_INFOFRAME_TYPE_AVI,
1850 &pipe_config->infoframes.avi);
1851 intel_read_infoframe(encoder, pipe_config,
1852 HDMI_INFOFRAME_TYPE_SPD,
1853 &pipe_config->infoframes.spd);
1854 intel_read_infoframe(encoder, pipe_config,
1855 HDMI_INFOFRAME_TYPE_VENDOR,
1856 &pipe_config->infoframes.hdmi);
1859 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1860 const struct intel_crtc_state *pipe_config,
1861 const struct drm_connector_state *conn_state)
1863 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1865 WARN_ON(!pipe_config->has_hdmi_sink);
1866 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1867 pipe_name(crtc->pipe));
1868 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1871 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1872 const struct intel_crtc_state *pipe_config,
1873 const struct drm_connector_state *conn_state)
1875 struct drm_device *dev = encoder->base.dev;
1876 struct drm_i915_private *dev_priv = to_i915(dev);
1877 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1880 temp = I915_READ(intel_hdmi->hdmi_reg);
1882 temp |= SDVO_ENABLE;
1883 if (pipe_config->has_audio)
1884 temp |= HDMI_AUDIO_ENABLE;
1886 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1887 POSTING_READ(intel_hdmi->hdmi_reg);
1889 if (pipe_config->has_audio)
1890 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1893 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1894 const struct intel_crtc_state *pipe_config,
1895 const struct drm_connector_state *conn_state)
1897 struct drm_device *dev = encoder->base.dev;
1898 struct drm_i915_private *dev_priv = to_i915(dev);
1899 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1902 temp = I915_READ(intel_hdmi->hdmi_reg);
1904 temp |= SDVO_ENABLE;
1905 if (pipe_config->has_audio)
1906 temp |= HDMI_AUDIO_ENABLE;
1909 * HW workaround, need to write this twice for issue
1910 * that may result in first write getting masked.
1912 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1913 POSTING_READ(intel_hdmi->hdmi_reg);
1914 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1915 POSTING_READ(intel_hdmi->hdmi_reg);
1918 * HW workaround, need to toggle enable bit off and on
1919 * for 12bpc with pixel repeat.
1921 * FIXME: BSpec says this should be done at the end of
1922 * of the modeset sequence, so not sure if this isn't too soon.
1924 if (pipe_config->pipe_bpp > 24 &&
1925 pipe_config->pixel_multiplier > 1) {
1926 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1927 POSTING_READ(intel_hdmi->hdmi_reg);
1930 * HW workaround, need to write this twice for issue
1931 * that may result in first write getting masked.
1933 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1934 POSTING_READ(intel_hdmi->hdmi_reg);
1935 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1936 POSTING_READ(intel_hdmi->hdmi_reg);
1939 if (pipe_config->has_audio)
1940 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1943 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1944 const struct intel_crtc_state *pipe_config,
1945 const struct drm_connector_state *conn_state)
1947 struct drm_device *dev = encoder->base.dev;
1948 struct drm_i915_private *dev_priv = to_i915(dev);
1949 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1950 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1951 enum pipe pipe = crtc->pipe;
1954 temp = I915_READ(intel_hdmi->hdmi_reg);
1956 temp |= SDVO_ENABLE;
1957 if (pipe_config->has_audio)
1958 temp |= HDMI_AUDIO_ENABLE;
1961 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1963 * The procedure for 12bpc is as follows:
1964 * 1. disable HDMI clock gating
1965 * 2. enable HDMI with 8bpc
1966 * 3. enable HDMI with 12bpc
1967 * 4. enable HDMI clock gating
1970 if (pipe_config->pipe_bpp > 24) {
1971 I915_WRITE(TRANS_CHICKEN1(pipe),
1972 I915_READ(TRANS_CHICKEN1(pipe)) |
1973 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1975 temp &= ~SDVO_COLOR_FORMAT_MASK;
1976 temp |= SDVO_COLOR_FORMAT_8bpc;
1979 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1980 POSTING_READ(intel_hdmi->hdmi_reg);
1982 if (pipe_config->pipe_bpp > 24) {
1983 temp &= ~SDVO_COLOR_FORMAT_MASK;
1984 temp |= HDMI_COLOR_FORMAT_12bpc;
1986 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1987 POSTING_READ(intel_hdmi->hdmi_reg);
1989 I915_WRITE(TRANS_CHICKEN1(pipe),
1990 I915_READ(TRANS_CHICKEN1(pipe)) &
1991 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1994 if (pipe_config->has_audio)
1995 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1998 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1999 const struct intel_crtc_state *pipe_config,
2000 const struct drm_connector_state *conn_state)
2004 static void intel_disable_hdmi(struct intel_encoder *encoder,
2005 const struct intel_crtc_state *old_crtc_state,
2006 const struct drm_connector_state *old_conn_state)
2008 struct drm_device *dev = encoder->base.dev;
2009 struct drm_i915_private *dev_priv = to_i915(dev);
2010 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2011 struct intel_digital_port *intel_dig_port =
2012 hdmi_to_dig_port(intel_hdmi);
2013 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2016 temp = I915_READ(intel_hdmi->hdmi_reg);
2018 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2019 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2020 POSTING_READ(intel_hdmi->hdmi_reg);
2023 * HW workaround for IBX, we need to move the port
2024 * to transcoder A after disabling it to allow the
2025 * matching DP port to be enabled on transcoder A.
2027 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2029 * We get CPU/PCH FIFO underruns on the other pipe when
2030 * doing the workaround. Sweep them under the rug.
2032 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2033 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2035 temp &= ~SDVO_PIPE_SEL_MASK;
2036 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2038 * HW workaround, need to write this twice for issue
2039 * that may result in first write getting masked.
2041 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2042 POSTING_READ(intel_hdmi->hdmi_reg);
2043 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2044 POSTING_READ(intel_hdmi->hdmi_reg);
2046 temp &= ~SDVO_ENABLE;
2047 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2048 POSTING_READ(intel_hdmi->hdmi_reg);
2050 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2051 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2052 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2055 intel_dig_port->set_infoframes(encoder,
2057 old_crtc_state, old_conn_state);
2059 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2062 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2063 const struct intel_crtc_state *old_crtc_state,
2064 const struct drm_connector_state *old_conn_state)
2066 if (old_crtc_state->has_audio)
2067 intel_audio_codec_disable(encoder,
2068 old_crtc_state, old_conn_state);
2070 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2073 static void pch_disable_hdmi(struct intel_encoder *encoder,
2074 const struct intel_crtc_state *old_crtc_state,
2075 const struct drm_connector_state *old_conn_state)
2077 if (old_crtc_state->has_audio)
2078 intel_audio_codec_disable(encoder,
2079 old_crtc_state, old_conn_state);
2082 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2083 const struct intel_crtc_state *old_crtc_state,
2084 const struct drm_connector_state *old_conn_state)
2086 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2089 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2092 const struct ddi_vbt_port_info *info =
2093 &dev_priv->vbt.ddi_port_info[encoder->port];
2096 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2097 max_tmds_clock = 594000;
2098 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2099 max_tmds_clock = 300000;
2100 else if (INTEL_GEN(dev_priv) >= 5)
2101 max_tmds_clock = 225000;
2103 max_tmds_clock = 165000;
2105 if (info->max_tmds_clock)
2106 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2108 return max_tmds_clock;
2111 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2112 bool respect_downstream_limits,
2115 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2116 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2118 if (respect_downstream_limits) {
2119 struct intel_connector *connector = hdmi->attached_connector;
2120 const struct drm_display_info *info = &connector->base.display_info;
2122 if (hdmi->dp_dual_mode.max_tmds_clock)
2123 max_tmds_clock = min(max_tmds_clock,
2124 hdmi->dp_dual_mode.max_tmds_clock);
2126 if (info->max_tmds_clock)
2127 max_tmds_clock = min(max_tmds_clock,
2128 info->max_tmds_clock);
2129 else if (!hdmi->has_hdmi_sink || force_dvi)
2130 max_tmds_clock = min(max_tmds_clock, 165000);
2133 return max_tmds_clock;
2136 static enum drm_mode_status
2137 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2138 int clock, bool respect_downstream_limits,
2141 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2144 return MODE_CLOCK_LOW;
2145 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2146 return MODE_CLOCK_HIGH;
2148 /* BXT DPLL can't generate 223-240 MHz */
2149 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2150 return MODE_CLOCK_RANGE;
2152 /* CHV DPLL can't generate 216-240 MHz */
2153 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2154 return MODE_CLOCK_RANGE;
2159 static enum drm_mode_status
2160 intel_hdmi_mode_valid(struct drm_connector *connector,
2161 struct drm_display_mode *mode)
2163 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2164 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2165 struct drm_i915_private *dev_priv = to_i915(dev);
2166 enum drm_mode_status status;
2168 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2170 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2172 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2173 return MODE_NO_DBLESCAN;
2175 clock = mode->clock;
2177 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2180 if (clock > max_dotclk)
2181 return MODE_CLOCK_HIGH;
2183 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2186 if (drm_mode_is_420_only(&connector->display_info, mode))
2189 /* check if we can do 8bpc */
2190 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2192 if (hdmi->has_hdmi_sink && !force_dvi) {
2193 /* if we can't do 8bpc we may still be able to do 12bpc */
2194 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2195 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2198 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2199 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2200 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2203 if (status != MODE_OK)
2206 return intel_mode_valid_max_plane_size(dev_priv, mode);
2209 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2212 struct drm_i915_private *dev_priv =
2213 to_i915(crtc_state->base.crtc->dev);
2214 struct drm_atomic_state *state = crtc_state->base.state;
2215 struct drm_connector_state *connector_state;
2216 struct drm_connector *connector;
2217 const struct drm_display_mode *adjusted_mode =
2218 &crtc_state->base.adjusted_mode;
2221 if (HAS_GMCH(dev_priv))
2224 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2227 if (crtc_state->pipe_bpp < bpc * 3)
2230 if (!crtc_state->has_hdmi_sink)
2234 * HDMI deep color affects the clocks, so it's only possible
2235 * when not cloning with other encoder types.
2237 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2240 for_each_new_connector_in_state(state, connector, connector_state, i) {
2241 const struct drm_display_info *info = &connector->display_info;
2243 if (connector_state->crtc != crtc_state->base.crtc)
2246 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2247 const struct drm_hdmi_info *hdmi = &info->hdmi;
2249 if (bpc == 12 && !(hdmi->y420_dc_modes &
2250 DRM_EDID_YCBCR420_DC_36))
2252 else if (bpc == 10 && !(hdmi->y420_dc_modes &
2253 DRM_EDID_YCBCR420_DC_30))
2256 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2257 DRM_EDID_HDMI_DC_36))
2259 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2260 DRM_EDID_HDMI_DC_30))
2265 /* Display WA #1139: glk */
2266 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2267 adjusted_mode->htotal > 5460)
2270 /* Display Wa_1405510057:icl */
2271 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2272 bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2273 (adjusted_mode->crtc_hblank_end -
2274 adjusted_mode->crtc_hblank_start) % 8 == 2)
2281 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2282 struct intel_crtc_state *config)
2284 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2286 if (!connector->ycbcr_420_allowed) {
2287 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2291 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2293 /* YCBCR 420 output conversion needs a scaler */
2294 if (skl_update_scaler_crtc(config)) {
2295 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2299 intel_pch_panel_fitting(intel_crtc, config,
2300 DRM_MODE_SCALE_FULLSCREEN);
2305 static int intel_hdmi_port_clock(int clock, int bpc)
2308 * Need to adjust the port link by:
2312 return clock * bpc / 8;
2315 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2316 struct intel_crtc_state *crtc_state,
2317 int clock, bool force_dvi)
2319 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2322 for (bpc = 12; bpc >= 10; bpc -= 2) {
2323 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2324 hdmi_port_clock_valid(intel_hdmi,
2325 intel_hdmi_port_clock(clock, bpc),
2326 true, force_dvi) == MODE_OK)
2333 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2334 struct intel_crtc_state *crtc_state,
2337 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2338 const struct drm_display_mode *adjusted_mode =
2339 &crtc_state->base.adjusted_mode;
2340 int bpc, clock = adjusted_mode->crtc_clock;
2342 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2345 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2346 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2349 bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
2352 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2355 * pipe_bpp could already be below 8bpc due to
2356 * FDI bandwidth constraints. We shouldn't bump it
2357 * back up to 8bpc in that case.
2359 if (crtc_state->pipe_bpp > bpc * 3)
2360 crtc_state->pipe_bpp = bpc * 3;
2362 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2363 bpc, crtc_state->pipe_bpp);
2365 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2366 false, force_dvi) != MODE_OK) {
2367 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2368 crtc_state->port_clock);
2375 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2376 const struct drm_connector_state *conn_state)
2378 const struct intel_digital_connector_state *intel_conn_state =
2379 to_intel_digital_connector_state(conn_state);
2380 const struct drm_display_mode *adjusted_mode =
2381 &crtc_state->base.adjusted_mode;
2384 * Our YCbCr output is always limited range.
2385 * crtc_state->limited_color_range only applies to RGB,
2386 * and it must never be set for YCbCr or we risk setting
2387 * some conflicting bits in PIPECONF which will mess up
2388 * the colors on the monitor.
2390 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2393 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2394 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2395 return crtc_state->has_hdmi_sink &&
2396 drm_default_rgb_quant_range(adjusted_mode) ==
2397 HDMI_QUANTIZATION_RANGE_LIMITED;
2399 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2403 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2404 struct intel_crtc_state *pipe_config,
2405 struct drm_connector_state *conn_state)
2407 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2409 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2410 struct drm_connector *connector = conn_state->connector;
2411 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2412 struct intel_digital_connector_state *intel_conn_state =
2413 to_intel_digital_connector_state(conn_state);
2414 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2417 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2420 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2421 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2423 if (pipe_config->has_hdmi_sink)
2424 pipe_config->has_infoframe = true;
2426 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2427 pipe_config->pixel_multiplier = 2;
2429 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2430 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
2431 DRM_ERROR("Can't support YCBCR420 output\n");
2436 pipe_config->limited_color_range =
2437 intel_hdmi_limited_color_range(pipe_config, conn_state);
2439 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2440 pipe_config->has_pch_encoder = true;
2442 if (pipe_config->has_hdmi_sink) {
2443 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2444 pipe_config->has_audio = intel_hdmi->has_audio;
2446 pipe_config->has_audio =
2447 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2450 ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
2454 /* Set user selected PAR to incoming mode's member */
2455 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2457 pipe_config->lane_count = 4;
2459 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2460 IS_GEMINILAKE(dev_priv))) {
2461 if (scdc->scrambling.low_rates)
2462 pipe_config->hdmi_scrambling = true;
2464 if (pipe_config->port_clock > 340000) {
2465 pipe_config->hdmi_scrambling = true;
2466 pipe_config->hdmi_high_tmds_clock_ratio = true;
2470 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2472 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2473 DRM_DEBUG_KMS("bad AVI infoframe\n");
2477 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2478 DRM_DEBUG_KMS("bad SPD infoframe\n");
2482 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2483 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2487 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2488 DRM_DEBUG_KMS("bad DRM infoframe\n");
2496 intel_hdmi_unset_edid(struct drm_connector *connector)
2498 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2500 intel_hdmi->has_hdmi_sink = false;
2501 intel_hdmi->has_audio = false;
2503 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2504 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2506 kfree(to_intel_connector(connector)->detect_edid);
2507 to_intel_connector(connector)->detect_edid = NULL;
2511 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2513 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2514 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2515 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2516 struct i2c_adapter *adapter =
2517 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2518 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2521 * Type 1 DVI adaptors are not required to implement any
2522 * registers, so we can't always detect their presence.
2523 * Ideally we should be able to check the state of the
2524 * CONFIG1 pin, but no such luck on our hardware.
2526 * The only method left to us is to check the VBT to see
2527 * if the port is a dual mode capable DP port. But let's
2528 * only do that when we sucesfully read the EDID, to avoid
2529 * confusing log messages about DP dual mode adaptors when
2530 * there's nothing connected to the port.
2532 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2533 /* An overridden EDID imply that we want this port for testing.
2534 * Make sure not to set limits for that port.
2536 if (has_edid && !connector->override_edid &&
2537 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2538 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2539 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2541 type = DRM_DP_DUAL_MODE_NONE;
2545 if (type == DRM_DP_DUAL_MODE_NONE)
2548 hdmi->dp_dual_mode.type = type;
2549 hdmi->dp_dual_mode.max_tmds_clock =
2550 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2552 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2553 drm_dp_get_dual_mode_type_name(type),
2554 hdmi->dp_dual_mode.max_tmds_clock);
2558 intel_hdmi_set_edid(struct drm_connector *connector)
2560 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2561 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2562 intel_wakeref_t wakeref;
2564 bool connected = false;
2565 struct i2c_adapter *i2c;
2567 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2569 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2571 edid = drm_get_edid(connector, i2c);
2573 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2574 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2575 intel_gmbus_force_bit(i2c, true);
2576 edid = drm_get_edid(connector, i2c);
2577 intel_gmbus_force_bit(i2c, false);
2580 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2582 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2584 to_intel_connector(connector)->detect_edid = edid;
2585 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2586 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2587 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2592 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2597 static enum drm_connector_status
2598 intel_hdmi_detect(struct drm_connector *connector, bool force)
2600 enum drm_connector_status status = connector_status_disconnected;
2601 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2602 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2603 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2604 intel_wakeref_t wakeref;
2606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2607 connector->base.id, connector->name);
2609 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2611 if (INTEL_GEN(dev_priv) >= 11 &&
2612 !intel_digital_port_connected(encoder))
2615 intel_hdmi_unset_edid(connector);
2617 if (intel_hdmi_set_edid(connector))
2618 status = connector_status_connected;
2621 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2623 if (status != connector_status_connected)
2624 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2627 * Make sure the refs for power wells enabled during detect are
2628 * dropped to avoid a new detect cycle triggered by HPD polling.
2630 intel_display_power_flush_work(dev_priv);
2636 intel_hdmi_force(struct drm_connector *connector)
2638 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2639 connector->base.id, connector->name);
2641 intel_hdmi_unset_edid(connector);
2643 if (connector->status != connector_status_connected)
2646 intel_hdmi_set_edid(connector);
2649 static int intel_hdmi_get_modes(struct drm_connector *connector)
2653 edid = to_intel_connector(connector)->detect_edid;
2657 return intel_connector_update_modes(connector, edid);
2660 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2661 const struct intel_crtc_state *pipe_config,
2662 const struct drm_connector_state *conn_state)
2664 struct intel_digital_port *intel_dig_port =
2665 enc_to_dig_port(&encoder->base);
2667 intel_hdmi_prepare(encoder, pipe_config);
2669 intel_dig_port->set_infoframes(encoder,
2670 pipe_config->has_infoframe,
2671 pipe_config, conn_state);
2674 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2675 const struct intel_crtc_state *pipe_config,
2676 const struct drm_connector_state *conn_state)
2678 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2681 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2684 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2687 dport->set_infoframes(encoder,
2688 pipe_config->has_infoframe,
2689 pipe_config, conn_state);
2691 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2693 vlv_wait_port_ready(dev_priv, dport, 0x0);
2696 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2697 const struct intel_crtc_state *pipe_config,
2698 const struct drm_connector_state *conn_state)
2700 intel_hdmi_prepare(encoder, pipe_config);
2702 vlv_phy_pre_pll_enable(encoder, pipe_config);
2705 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2706 const struct intel_crtc_state *pipe_config,
2707 const struct drm_connector_state *conn_state)
2709 intel_hdmi_prepare(encoder, pipe_config);
2711 chv_phy_pre_pll_enable(encoder, pipe_config);
2714 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2715 const struct intel_crtc_state *old_crtc_state,
2716 const struct drm_connector_state *old_conn_state)
2718 chv_phy_post_pll_disable(encoder, old_crtc_state);
2721 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2722 const struct intel_crtc_state *old_crtc_state,
2723 const struct drm_connector_state *old_conn_state)
2725 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2726 vlv_phy_reset_lanes(encoder, old_crtc_state);
2729 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2730 const struct intel_crtc_state *old_crtc_state,
2731 const struct drm_connector_state *old_conn_state)
2733 struct drm_device *dev = encoder->base.dev;
2734 struct drm_i915_private *dev_priv = to_i915(dev);
2736 vlv_dpio_get(dev_priv);
2738 /* Assert data lane reset */
2739 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2741 vlv_dpio_put(dev_priv);
2744 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2745 const struct intel_crtc_state *pipe_config,
2746 const struct drm_connector_state *conn_state)
2748 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2749 struct drm_device *dev = encoder->base.dev;
2750 struct drm_i915_private *dev_priv = to_i915(dev);
2752 chv_phy_pre_encoder_enable(encoder, pipe_config);
2754 /* FIXME: Program the support xxx V-dB */
2756 chv_set_phy_signal_level(encoder, 128, 102, false);
2758 dport->set_infoframes(encoder,
2759 pipe_config->has_infoframe,
2760 pipe_config, conn_state);
2762 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2764 vlv_wait_port_ready(dev_priv, dport, 0x0);
2766 /* Second common lane will stay alive on its own now */
2767 chv_phy_release_cl2_override(encoder);
2770 static struct i2c_adapter *
2771 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2773 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2774 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2776 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2779 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2781 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2782 struct kobject *i2c_kobj = &adapter->dev.kobj;
2783 struct kobject *connector_kobj = &connector->kdev->kobj;
2786 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2788 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2791 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2793 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2794 struct kobject *i2c_kobj = &adapter->dev.kobj;
2795 struct kobject *connector_kobj = &connector->kdev->kobj;
2797 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2801 intel_hdmi_connector_register(struct drm_connector *connector)
2805 ret = intel_connector_register(connector);
2809 i915_debugfs_connector_add(connector);
2811 intel_hdmi_create_i2c_symlink(connector);
2816 static void intel_hdmi_destroy(struct drm_connector *connector)
2818 struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier;
2820 cec_notifier_conn_unregister(n);
2822 intel_connector_destroy(connector);
2825 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2827 intel_hdmi_remove_i2c_symlink(connector);
2829 intel_connector_unregister(connector);
2832 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2833 .detect = intel_hdmi_detect,
2834 .force = intel_hdmi_force,
2835 .fill_modes = drm_helper_probe_single_connector_modes,
2836 .atomic_get_property = intel_digital_connector_atomic_get_property,
2837 .atomic_set_property = intel_digital_connector_atomic_set_property,
2838 .late_register = intel_hdmi_connector_register,
2839 .early_unregister = intel_hdmi_connector_unregister,
2840 .destroy = intel_hdmi_destroy,
2841 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2842 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2845 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2846 .get_modes = intel_hdmi_get_modes,
2847 .mode_valid = intel_hdmi_mode_valid,
2848 .atomic_check = intel_digital_connector_atomic_check,
2851 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2852 .destroy = intel_encoder_destroy,
2856 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2858 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2859 struct intel_digital_port *intel_dig_port =
2860 hdmi_to_dig_port(intel_hdmi);
2862 intel_attach_force_audio_property(connector);
2863 intel_attach_broadcast_rgb_property(connector);
2864 intel_attach_aspect_ratio_property(connector);
2867 * Attach Colorspace property for Non LSPCON based device
2868 * ToDo: This needs to be extended for LSPCON implementation
2869 * as well. Will be implemented separately.
2871 if (!intel_dig_port->lspcon.active)
2872 intel_attach_colorspace_property(connector);
2874 drm_connector_attach_content_type_property(connector);
2875 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2877 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2878 drm_object_attach_property(&connector->base,
2879 connector->dev->mode_config.hdr_output_metadata_property, 0);
2881 if (!HAS_GMCH(dev_priv))
2882 drm_connector_attach_max_bpc_property(connector, 8, 12);
2886 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2887 * @encoder: intel_encoder
2888 * @connector: drm_connector
2889 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2890 * or reset the high tmds clock ratio for scrambling
2891 * @scrambling: bool to Indicate if the function needs to set or reset
2894 * This function handles scrambling on HDMI 2.0 capable sinks.
2895 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2896 * it enables scrambling. This should be called before enabling the HDMI
2897 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2898 * detect a scrambled clock within 100 ms.
2901 * True on success, false on failure.
2903 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2904 struct drm_connector *connector,
2905 bool high_tmds_clock_ratio,
2908 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2909 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2910 struct drm_scrambling *sink_scrambling =
2911 &connector->display_info.hdmi.scdc.scrambling;
2912 struct i2c_adapter *adapter =
2913 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2915 if (!sink_scrambling->supported)
2918 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2919 connector->base.id, connector->name,
2920 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2922 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2923 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2924 high_tmds_clock_ratio) &&
2925 drm_scdc_set_scrambling(adapter, scrambling);
2928 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2934 ddc_pin = GMBUS_PIN_DPB;
2937 ddc_pin = GMBUS_PIN_DPC;
2940 ddc_pin = GMBUS_PIN_DPD_CHV;
2944 ddc_pin = GMBUS_PIN_DPB;
2950 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2956 ddc_pin = GMBUS_PIN_1_BXT;
2959 ddc_pin = GMBUS_PIN_2_BXT;
2963 ddc_pin = GMBUS_PIN_1_BXT;
2969 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2976 ddc_pin = GMBUS_PIN_1_BXT;
2979 ddc_pin = GMBUS_PIN_2_BXT;
2982 ddc_pin = GMBUS_PIN_4_CNP;
2985 ddc_pin = GMBUS_PIN_3_BXT;
2989 ddc_pin = GMBUS_PIN_1_BXT;
2995 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2997 enum phy phy = intel_port_to_phy(dev_priv, port);
2999 if (intel_phy_is_combo(dev_priv, phy))
3000 return GMBUS_PIN_1_BXT + port;
3001 else if (intel_phy_is_tc(dev_priv, phy))
3002 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
3004 WARN(1, "Unknown port:%c\n", port_name(port));
3005 return GMBUS_PIN_2_BXT;
3008 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3010 enum phy phy = intel_port_to_phy(dev_priv, port);
3015 ddc_pin = GMBUS_PIN_1_BXT;
3018 ddc_pin = GMBUS_PIN_2_BXT;
3021 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3025 ddc_pin = GMBUS_PIN_1_BXT;
3031 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3038 ddc_pin = GMBUS_PIN_DPB;
3041 ddc_pin = GMBUS_PIN_DPC;
3044 ddc_pin = GMBUS_PIN_DPD;
3048 ddc_pin = GMBUS_PIN_DPB;
3054 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
3057 const struct ddi_vbt_port_info *info =
3058 &dev_priv->vbt.ddi_port_info[port];
3061 if (info->alternate_ddc_pin) {
3062 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3063 info->alternate_ddc_pin, port_name(port));
3064 return info->alternate_ddc_pin;
3067 if (HAS_PCH_MCC(dev_priv))
3068 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3069 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3070 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3071 else if (HAS_PCH_CNP(dev_priv))
3072 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3073 else if (IS_GEN9_LP(dev_priv))
3074 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3075 else if (IS_CHERRYVIEW(dev_priv))
3076 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3078 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3080 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3081 ddc_pin, port_name(port));
3086 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3088 struct drm_i915_private *dev_priv =
3089 to_i915(intel_dig_port->base.base.dev);
3091 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3092 intel_dig_port->write_infoframe = vlv_write_infoframe;
3093 intel_dig_port->read_infoframe = vlv_read_infoframe;
3094 intel_dig_port->set_infoframes = vlv_set_infoframes;
3095 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3096 } else if (IS_G4X(dev_priv)) {
3097 intel_dig_port->write_infoframe = g4x_write_infoframe;
3098 intel_dig_port->read_infoframe = g4x_read_infoframe;
3099 intel_dig_port->set_infoframes = g4x_set_infoframes;
3100 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3101 } else if (HAS_DDI(dev_priv)) {
3102 if (intel_dig_port->lspcon.active) {
3103 intel_dig_port->write_infoframe = lspcon_write_infoframe;
3104 intel_dig_port->read_infoframe = lspcon_read_infoframe;
3105 intel_dig_port->set_infoframes = lspcon_set_infoframes;
3106 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3108 intel_dig_port->write_infoframe = hsw_write_infoframe;
3109 intel_dig_port->read_infoframe = hsw_read_infoframe;
3110 intel_dig_port->set_infoframes = hsw_set_infoframes;
3111 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3113 } else if (HAS_PCH_IBX(dev_priv)) {
3114 intel_dig_port->write_infoframe = ibx_write_infoframe;
3115 intel_dig_port->read_infoframe = ibx_read_infoframe;
3116 intel_dig_port->set_infoframes = ibx_set_infoframes;
3117 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3119 intel_dig_port->write_infoframe = cpt_write_infoframe;
3120 intel_dig_port->read_infoframe = cpt_read_infoframe;
3121 intel_dig_port->set_infoframes = cpt_set_infoframes;
3122 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3126 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3127 struct intel_connector *intel_connector)
3129 struct drm_connector *connector = &intel_connector->base;
3130 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3131 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3132 struct drm_device *dev = intel_encoder->base.dev;
3133 struct drm_i915_private *dev_priv = to_i915(dev);
3134 enum port port = intel_encoder->port;
3135 struct cec_connector_info conn_info;
3137 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3138 intel_encoder->base.base.id, intel_encoder->base.name);
3140 if (WARN(intel_dig_port->max_lanes < 4,
3141 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3142 intel_dig_port->max_lanes, intel_encoder->base.base.id,
3143 intel_encoder->base.name))
3146 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3147 DRM_MODE_CONNECTOR_HDMIA);
3148 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3150 connector->interlace_allowed = 1;
3151 connector->doublescan_allowed = 0;
3152 connector->stereo_allowed = 1;
3154 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3155 connector->ycbcr_420_allowed = true;
3157 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3159 if (WARN_ON(port == PORT_A))
3161 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3163 if (HAS_DDI(dev_priv))
3164 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3166 intel_connector->get_hw_state = intel_connector_get_hw_state;
3168 intel_hdmi_add_properties(intel_hdmi, connector);
3170 intel_connector_attach_encoder(intel_connector, intel_encoder);
3171 intel_hdmi->attached_connector = intel_connector;
3173 if (is_hdcp_supported(dev_priv, port)) {
3174 int ret = intel_hdcp_init(intel_connector,
3175 &intel_hdmi_hdcp_shim);
3177 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3180 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3181 * 0xd. Failure to do so will result in spurious interrupts being
3182 * generated on the port when a cable is not attached.
3184 if (IS_G45(dev_priv)) {
3185 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3186 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3189 cec_fill_conn_info_from_drm(&conn_info, connector);
3191 intel_hdmi->cec_notifier =
3192 cec_notifier_conn_register(dev->dev, port_identifier(port),
3194 if (!intel_hdmi->cec_notifier)
3195 DRM_DEBUG_KMS("CEC notifier get failed\n");
3198 static enum intel_hotplug_state
3199 intel_hdmi_hotplug(struct intel_encoder *encoder,
3200 struct intel_connector *connector, bool irq_received)
3202 enum intel_hotplug_state state;
3204 state = intel_encoder_hotplug(encoder, connector, irq_received);
3207 * On many platforms the HDMI live state signal is known to be
3208 * unreliable, so we can't use it to detect if a sink is connected or
3209 * not. Instead we detect if it's connected based on whether we can
3210 * read the EDID or not. That in turn has a problem during disconnect,
3211 * since the HPD interrupt may be raised before the DDC lines get
3212 * disconnected (due to how the required length of DDC vs. HPD
3213 * connector pins are specified) and so we'll still be able to get a
3214 * valid EDID. To solve this schedule another detection cycle if this
3215 * time around we didn't detect any change in the sink's connection
3218 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3219 state = INTEL_HOTPLUG_RETRY;
3224 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3225 i915_reg_t hdmi_reg, enum port port)
3227 struct intel_digital_port *intel_dig_port;
3228 struct intel_encoder *intel_encoder;
3229 struct intel_connector *intel_connector;
3231 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3232 if (!intel_dig_port)
3235 intel_connector = intel_connector_alloc();
3236 if (!intel_connector) {
3237 kfree(intel_dig_port);
3241 intel_encoder = &intel_dig_port->base;
3243 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3244 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3245 "HDMI %c", port_name(port));
3247 intel_encoder->hotplug = intel_hdmi_hotplug;
3248 intel_encoder->compute_config = intel_hdmi_compute_config;
3249 if (HAS_PCH_SPLIT(dev_priv)) {
3250 intel_encoder->disable = pch_disable_hdmi;
3251 intel_encoder->post_disable = pch_post_disable_hdmi;
3253 intel_encoder->disable = g4x_disable_hdmi;
3255 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3256 intel_encoder->get_config = intel_hdmi_get_config;
3257 if (IS_CHERRYVIEW(dev_priv)) {
3258 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3259 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3260 intel_encoder->enable = vlv_enable_hdmi;
3261 intel_encoder->post_disable = chv_hdmi_post_disable;
3262 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3263 } else if (IS_VALLEYVIEW(dev_priv)) {
3264 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3265 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3266 intel_encoder->enable = vlv_enable_hdmi;
3267 intel_encoder->post_disable = vlv_hdmi_post_disable;
3269 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3270 if (HAS_PCH_CPT(dev_priv))
3271 intel_encoder->enable = cpt_enable_hdmi;
3272 else if (HAS_PCH_IBX(dev_priv))
3273 intel_encoder->enable = ibx_enable_hdmi;
3275 intel_encoder->enable = g4x_enable_hdmi;
3278 intel_encoder->type = INTEL_OUTPUT_HDMI;
3279 intel_encoder->power_domain = intel_port_to_power_domain(port);
3280 intel_encoder->port = port;
3281 if (IS_CHERRYVIEW(dev_priv)) {
3283 intel_encoder->pipe_mask = BIT(PIPE_C);
3285 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
3287 intel_encoder->pipe_mask = ~0;
3289 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3291 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3292 * to work on real hardware. And since g4x can send infoframes to
3293 * only one port anyway, nothing is lost by allowing it.
3295 if (IS_G4X(dev_priv))
3296 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3298 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3299 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3300 intel_dig_port->max_lanes = 4;
3302 intel_infoframe_init(intel_dig_port);
3304 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3305 intel_hdmi_init_connector(intel_dig_port, intel_connector);