drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_drv.h"
  34 #include "i915_reg.h"
  35 #include "intel_atomic.h"
  36 #include "intel_backlight.h"
  37 #include "intel_connector.h"
  38 #include "intel_crtc.h"
  39 #include "intel_de.h"
  40 #include "intel_display_types.h"
  41 #include "intel_dsi.h"
  42 #include "intel_dsi_vbt.h"
  43 #include "intel_fifo_underrun.h"
  44 #include "intel_panel.h"
  45 #include "skl_scaler.h"
  46 #include "vlv_dsi.h"
  47 #include "vlv_dsi_pll.h"
  48 #include "vlv_dsi_regs.h"
  49 #include "vlv_sideband.h"
  50
  51 /* return pixels in terms of txbyteclkhs */
  52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  53                        u16 burst_mode_ratio)
  54 {
  55         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  56                                          8 * 100), lane_count);
  57 }
  58
  59 /* return pixels equvalent to txbyteclkhs */
  60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  61                         u16 burst_mode_ratio)
  62 {
  63         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  64                                                 (bpp * burst_mode_ratio));
  65 }
  66
  67 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  68 {
  69         /* It just so happens the VBT matches register contents. */
  70         switch (fmt) {
  71         case VID_MODE_FORMAT_RGB888:
  72                 return MIPI_DSI_FMT_RGB888;
  73         case VID_MODE_FORMAT_RGB666:
  74                 return MIPI_DSI_FMT_RGB666;
  75         case VID_MODE_FORMAT_RGB666_PACKED:
  76                 return MIPI_DSI_FMT_RGB666_PACKED;
  77         case VID_MODE_FORMAT_RGB565:
  78                 return MIPI_DSI_FMT_RGB565;
  79         default:
  80                 MISSING_CASE(fmt);
  81                 return MIPI_DSI_FMT_RGB666;
  82         }
  83 }
  84
  85 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  86 {
  87         struct drm_encoder *encoder = &intel_dsi->base.base;
  88         struct drm_device *dev = encoder->dev;
  89         struct drm_i915_private *dev_priv = to_i915(dev);
  90         u32 mask;
  91
  92         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  93                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  94
  95         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  96                                   mask, 100))
  97                 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
  98 }
  99
 100 static void write_data(struct drm_i915_private *dev_priv,
 101                        i915_reg_t reg,
 102                        const u8 *data, u32 len)
 103 {
 104         u32 i, j;
 105
 106         for (i = 0; i < len; i += 4) {
 107                 u32 val = 0;
 108
 109                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 110                         val |= *data++ << 8 * j;
 111
 112                 intel_de_write(dev_priv, reg, val);
 113         }
 114 }
 115
 116 static void read_data(struct drm_i915_private *dev_priv,
 117                       i915_reg_t reg,
 118                       u8 *data, u32 len)
 119 {
 120         u32 i, j;
 121
 122         for (i = 0; i < len; i += 4) {
 123                 u32 val = intel_de_read(dev_priv, reg);
 124
 125                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 126                         *data++ = val >> 8 * j;
 127         }
 128 }
 129
 130 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 131                                        const struct mipi_dsi_msg *msg)
 132 {
 133         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 134         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 135         struct drm_i915_private *dev_priv = to_i915(dev);
 136         enum port port = intel_dsi_host->port;
 137         struct mipi_dsi_packet packet;
 138         ssize_t ret;
 139         const u8 *header;
 140         i915_reg_t data_reg, ctrl_reg;
 141         u32 data_mask, ctrl_mask;
 142
 143         ret = mipi_dsi_create_packet(&packet, msg);
 144         if (ret < 0)
 145                 return ret;
 146
 147         header = packet.header;
 148
 149         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 150                 data_reg = MIPI_LP_GEN_DATA(port);
 151                 data_mask = LP_DATA_FIFO_FULL;
 152                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 153                 ctrl_mask = LP_CTRL_FIFO_FULL;
 154         } else {
 155                 data_reg = MIPI_HS_GEN_DATA(port);
 156                 data_mask = HS_DATA_FIFO_FULL;
 157                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 158                 ctrl_mask = HS_CTRL_FIFO_FULL;
 159         }
 160
 161         /* note: this is never true for reads */
 162         if (packet.payload_length) {
 163                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 164                                             data_mask, 50))
 165                         drm_err(&dev_priv->drm,
 166                                 "Timeout waiting for HS/LP DATA FIFO !full\n");
 167
 168                 write_data(dev_priv, data_reg, packet.payload,
 169                            packet.payload_length);
 170         }
 171
 172         if (msg->rx_len) {
 173                 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
 174                                GEN_READ_DATA_AVAIL);
 175         }
 176
 177         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 178                                     ctrl_mask, 50)) {
 179                 drm_err(&dev_priv->drm,
 180                         "Timeout waiting for HS/LP CTRL FIFO !full\n");
 181         }
 182
 183         intel_de_write(dev_priv, ctrl_reg,
 184                        header[2] << 16 | header[1] << 8 | header[0]);
 185
 186         /* ->rx_len is set only for reads */
 187         if (msg->rx_len) {
 188                 data_mask = GEN_READ_DATA_AVAIL;
 189                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 190                                           data_mask, 50))
 191                         drm_err(&dev_priv->drm,
 192                                 "Timeout waiting for read data.\n");
 193
 194                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 195         }
 196
 197         /* XXX: fix for reads and writes */
 198         return 4 + packet.payload_length;
 199 }
 200
 201 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 202                                  struct mipi_dsi_device *dsi)
 203 {
 204         return 0;
 205 }
 206
 207 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 208                                  struct mipi_dsi_device *dsi)
 209 {
 210         return 0;
 211 }
 212
 213 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 214         .attach = intel_dsi_host_attach,
 215         .detach = intel_dsi_host_detach,
 216         .transfer = intel_dsi_host_transfer,
 217 };
 218
 219 /*
 220  * send a video mode command
 221  *
 222  * XXX: commands with data in MIPI_DPI_DATA?
 223  */
 224 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 225                         enum port port)
 226 {
 227         struct drm_encoder *encoder = &intel_dsi->base.base;
 228         struct drm_device *dev = encoder->dev;
 229         struct drm_i915_private *dev_priv = to_i915(dev);
 230         u32 mask;
 231
 232         /* XXX: pipe, hs */
 233         if (hs)
 234                 cmd &= ~DPI_LP_MODE;
 235         else
 236                 cmd |= DPI_LP_MODE;
 237
 238         /* clear bit */
 239         intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 240
 241         /* XXX: old code skips write if control unchanged */
 242         if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
 243                 drm_dbg_kms(&dev_priv->drm,
 244                             "Same special packet %02x twice in a row.\n", cmd);
 245
 246         intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
 247
 248         mask = SPL_PKT_SENT_INTERRUPT;
 249         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 250                 drm_err(&dev_priv->drm,
 251                         "Video mode command 0x%08x send failed.\n", cmd);
 252
 253         return 0;
 254 }
 255
 256 static void band_gap_reset(struct drm_i915_private *dev_priv)
 257 {
 258         vlv_flisdsi_get(dev_priv);
 259
 260         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 261         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 262         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 263         udelay(150);
 264         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 265         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 266
 267         vlv_flisdsi_put(dev_priv);
 268 }
 269
 270 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 271                                     struct intel_crtc_state *pipe_config,
 272                                     struct drm_connector_state *conn_state)
 273 {
 274         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 275         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 276                                                    base);
 277         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 278         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 279         int ret;
 280
 281         drm_dbg_kms(&dev_priv->drm, "\n");
 282         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 283         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 284
 285         ret = intel_panel_compute_config(intel_connector, adjusted_mode);
 286         if (ret)
 287                 return ret;
 288
 289         ret = intel_panel_fitting(pipe_config, conn_state);
 290         if (ret)
 291                 return ret;
 292
 293         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 294                 return -EINVAL;
 295
 296         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 297         adjusted_mode->flags = 0;
 298
 299         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 300                 pipe_config->pipe_bpp = 24;
 301         else
 302                 pipe_config->pipe_bpp = 18;
 303
 304         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 305                 /* Enable Frame time stamp based scanline reporting */
 306                 pipe_config->mode_flags |=
 307                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 308
 309                 /* Dual link goes to DSI transcoder A. */
 310                 if (intel_dsi->ports == BIT(PORT_C))
 311                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 312                 else
 313                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 314
 315                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 316                 if (ret)
 317                         return -EINVAL;
 318         } else {
 319                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 320                 if (ret)
 321                         return -EINVAL;
 322         }
 323
 324         pipe_config->clock_set = true;
 325
 326         return 0;
 327 }
 328
 329 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 330 {
 331         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 332         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 333         enum port port;
 334         bool cold_boot = false;
 335
 336         /* Set the MIPI mode
 337          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 338          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 339          */
 340         for_each_dsi_port(port, intel_dsi->ports)
 341                 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
 342
 343         /* Put the IO into reset */
 344         intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
 345
 346         /* Program LP Wake */
 347         for_each_dsi_port(port, intel_dsi->ports) {
 348                 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 349                 intel_de_rmw(dev_priv, MIPI_CTRL(port),
 350                              GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
 351         }
 352
 353         /* Wait for Pwr ACK */
 354         for_each_dsi_port(port, intel_dsi->ports) {
 355                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 356                                           GLK_MIPIIO_PORT_POWERED, 20))
 357                         drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
 358         }
 359
 360         /* Check for cold boot scenario */
 361         for_each_dsi_port(port, intel_dsi->ports) {
 362                 cold_boot |=
 363                         !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
 364         }
 365
 366         return cold_boot;
 367 }
 368
 369 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 370 {
 371         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 372         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 373         enum port port;
 374
 375         /* Wait for MIPI PHY status bit to set */
 376         for_each_dsi_port(port, intel_dsi->ports) {
 377                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 378                                           GLK_PHY_STATUS_PORT_READY, 20))
 379                         drm_err(&dev_priv->drm, "PHY is not ON\n");
 380         }
 381
 382         /* Get IO out of reset */
 383         intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
 384
 385         /* Get IO out of Low power state*/
 386         for_each_dsi_port(port, intel_dsi->ports) {
 387                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 388                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 389                                      ULPS_STATE_MASK, DEVICE_READY);
 390                         usleep_range(10, 15);
 391                 } else {
 392                         /* Enter ULPS */
 393                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 394                                      ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
 395
 396                         /* Wait for ULPS active */
 397                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 398                                                     GLK_ULPS_NOT_ACTIVE, 20))
 399                                 drm_err(&dev_priv->drm, "ULPS not active\n");
 400
 401                         /* Exit ULPS */
 402                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 403                                      ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
 404
 405                         /* Enter Normal Mode */
 406                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 407                                      ULPS_STATE_MASK,
 408                                      ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 409
 410                         intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
 411                 }
 412         }
 413
 414         /* Wait for Stop state */
 415         for_each_dsi_port(port, intel_dsi->ports) {
 416                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 417                                           GLK_DATA_LANE_STOP_STATE, 20))
 418                         drm_err(&dev_priv->drm,
 419                                 "Date lane not in STOP state\n");
 420         }
 421
 422         /* Wait for AFE LATCH */
 423         for_each_dsi_port(port, intel_dsi->ports) {
 424                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 425                                           AFE_LATCHOUT, 20))
 426                         drm_err(&dev_priv->drm,
 427                                 "D-PHY not entering LP-11 state\n");
 428         }
 429 }
 430
 431 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 432 {
 433         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 434         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 435         enum port port;
 436         u32 val;
 437
 438         drm_dbg_kms(&dev_priv->drm, "\n");
 439
 440         /* Enable MIPI PHY transparent latch */
 441         for_each_dsi_port(port, intel_dsi->ports) {
 442                 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
 443                 usleep_range(2000, 2500);
 444         }
 445
 446         /* Clear ULPS and set device ready */
 447         for_each_dsi_port(port, intel_dsi->ports) {
 448                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 449                 val &= ~ULPS_STATE_MASK;
 450                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 451                 usleep_range(2000, 2500);
 452                 val |= DEVICE_READY;
 453                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 454         }
 455 }
 456
 457 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 458 {
 459         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 460         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 461         enum port port;
 462
 463         drm_dbg_kms(&dev_priv->drm, "\n");
 464
 465         vlv_flisdsi_get(dev_priv);
 466         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 467          * needed everytime after power gate */
 468         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 469         vlv_flisdsi_put(dev_priv);
 470
 471         /* bandgap reset is needed after everytime we do power gate */
 472         band_gap_reset(dev_priv);
 473
 474         for_each_dsi_port(port, intel_dsi->ports) {
 475
 476                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 477                                ULPS_STATE_ENTER);
 478                 usleep_range(2500, 3000);
 479
 480                 /* Enable MIPI PHY transparent latch
 481                  * Common bit for both MIPI Port A & MIPI Port C
 482                  * No similar bit in MIPI Port C reg
 483                  */
 484                 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
 485                 usleep_range(1000, 1500);
 486
 487                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 488                                ULPS_STATE_EXIT);
 489                 usleep_range(2500, 3000);
 490
 491                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 492                                DEVICE_READY);
 493                 usleep_range(2500, 3000);
 494         }
 495 }
 496
 497 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 498 {
 499         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 500
 501         if (IS_GEMINILAKE(dev_priv))
 502                 glk_dsi_device_ready(encoder);
 503         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 504                 bxt_dsi_device_ready(encoder);
 505         else
 506                 vlv_dsi_device_ready(encoder);
 507 }
 508
 509 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 510 {
 511         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 512         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 513         enum port port;
 514
 515         /* Enter ULPS */
 516         for_each_dsi_port(port, intel_dsi->ports)
 517                 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 518                              ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
 519
 520         /* Wait for MIPI PHY status bit to unset */
 521         for_each_dsi_port(port, intel_dsi->ports) {
 522                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 523                                             GLK_PHY_STATUS_PORT_READY, 20))
 524                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 525         }
 526
 527         /* Wait for Pwr ACK bit to unset */
 528         for_each_dsi_port(port, intel_dsi->ports) {
 529                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 530                                             GLK_MIPIIO_PORT_POWERED, 20))
 531                         drm_err(&dev_priv->drm,
 532                                 "MIPI IO Port is not powergated\n");
 533         }
 534 }
 535
 536 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 537 {
 538         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 539         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 540         enum port port;
 541
 542         /* Put the IO into reset */
 543         intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
 544
 545         /* Wait for MIPI PHY status bit to unset */
 546         for_each_dsi_port(port, intel_dsi->ports) {
 547                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 548                                             GLK_PHY_STATUS_PORT_READY, 20))
 549                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 550         }
 551
 552         /* Clear MIPI mode */
 553         for_each_dsi_port(port, intel_dsi->ports)
 554                 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
 555 }
 556
 557 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 558 {
 559         glk_dsi_enter_low_power_mode(encoder);
 560         glk_dsi_disable_mipi_io(encoder);
 561 }
 562
 563 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 564 {
 565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 566         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 567         enum port port;
 568
 569         drm_dbg_kms(&dev_priv->drm, "\n");
 570         for_each_dsi_port(port, intel_dsi->ports) {
 571                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 572                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 573                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 574
 575                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 576                                DEVICE_READY | ULPS_STATE_ENTER);
 577                 usleep_range(2000, 2500);
 578
 579                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 580                                DEVICE_READY | ULPS_STATE_EXIT);
 581                 usleep_range(2000, 2500);
 582
 583                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 584                                DEVICE_READY | ULPS_STATE_ENTER);
 585                 usleep_range(2000, 2500);
 586
 587                 /*
 588                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 589                  * Port A only. MIPI Port C has no similar bit for checking.
 590                  */
 591                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
 592                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 593                                             AFE_LATCHOUT, 30))
 594                         drm_err(&dev_priv->drm, "DSI LP not going Low\n");
 595
 596                 /* Disable MIPI PHY transparent latch */
 597                 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
 598                 usleep_range(1000, 1500);
 599
 600                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
 601                 usleep_range(2000, 2500);
 602         }
 603 }
 604
 605 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 606                                   const struct intel_crtc_state *crtc_state)
 607 {
 608         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 609         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 610         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 611         enum port port;
 612
 613         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 614                 u32 temp = intel_dsi->pixel_overlap;
 615
 616                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 617                         for_each_dsi_port(port, intel_dsi->ports)
 618                                 intel_de_rmw(dev_priv, MIPI_CTRL(port),
 619                                              BXT_PIXEL_OVERLAP_CNT_MASK,
 620                                              temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
 621                 } else {
 622                         intel_de_rmw(dev_priv, VLV_CHICKEN_3,
 623                                      PIXEL_OVERLAP_CNT_MASK,
 624                                      temp << PIXEL_OVERLAP_CNT_SHIFT);
 625                 }
 626         }
 627
 628         for_each_dsi_port(port, intel_dsi->ports) {
 629                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 630                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 631                 u32 temp;
 632
 633                 temp = intel_de_read(dev_priv, port_ctrl);
 634
 635                 temp &= ~LANE_CONFIGURATION_MASK;
 636                 temp &= ~DUAL_LINK_MODE_MASK;
 637
 638                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 639                         temp |= (intel_dsi->dual_link - 1)
 640                                                 << DUAL_LINK_MODE_SHIFT;
 641                         if (IS_BROXTON(dev_priv))
 642                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 643                         else
 644                                 temp |= crtc->pipe ?
 645                                         LANE_CONFIGURATION_DUAL_LINK_B :
 646                                         LANE_CONFIGURATION_DUAL_LINK_A;
 647                 }
 648
 649                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 650                         temp |= DITHERING_ENABLE;
 651
 652                 /* assert ip_tg_enable signal */
 653                 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
 654                 intel_de_posting_read(dev_priv, port_ctrl);
 655         }
 656 }
 657
 658 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 659 {
 660         struct drm_device *dev = encoder->base.dev;
 661         struct drm_i915_private *dev_priv = to_i915(dev);
 662         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 663         enum port port;
 664
 665         for_each_dsi_port(port, intel_dsi->ports) {
 666                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 667                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 668
 669                 /* de-assert ip_tg_enable signal */
 670                 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0);
 671                 intel_de_posting_read(dev_priv, port_ctrl);
 672         }
 673 }
 674 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 675                               const struct intel_crtc_state *pipe_config);
 676 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 677
 678 /*
 679  * Panel enable/disable sequences from the VBT spec.
 680  *
 681  * Note the spec has AssertReset / DeassertReset swapped from their
 682  * usual naming. We use the normal names to avoid confusion (so below
 683  * they are swapped compared to the spec).
 684  *
 685  * Steps starting with MIPI refer to VBT sequences, note that for v2
 686  * VBTs several steps which have a VBT in v2 are expected to be handled
 687  * directly by the driver, by directly driving gpios for example.
 688  *
 689  * v2 video mode seq         v3 video mode seq         command mode seq
 690  * - power on                - MIPIPanelPowerOn        - power on
 691  * - wait t1+t2                                        - wait t1+t2
 692  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 693  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 694  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 695  *                                                     - MIPITearOn
 696  *                                                     - MIPIDisplayOn
 697  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 698  * - MIPIDisplayOn           - MIPIDisplayOn
 699  * - wait t5                                           - wait t5
 700  * - backlight on            - MIPIBacklightOn         - backlight on
 701  * ...                       ...                       ... issue mem cmds ...
 702  * - backlight off           - MIPIBacklightOff        - backlight off
 703  * - wait t6                                           - wait t6
 704  * - MIPIDisplayOff
 705  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 706  *                                                     - MIPITearOff
 707  *                           - MIPIDisplayOff          - MIPIDisplayOff
 708  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 709  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 710  * - wait t3                                           - wait t3
 711  * - power off               - MIPIPanelPowerOff       - power off
 712  * - wait t4                                           - wait t4
 713  */
 714
 715 /*
 716  * DSI port enable has to be done before pipe and plane enable, so we do it in
 717  * the pre_enable hook instead of the enable hook.
 718  */
 719 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 720                                  struct intel_encoder *encoder,
 721                                  const struct intel_crtc_state *pipe_config,
 722                                  const struct drm_connector_state *conn_state)
 723 {
 724         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 725         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 727         enum pipe pipe = crtc->pipe;
 728         enum port port;
 729         bool glk_cold_boot = false;
 730
 731         drm_dbg_kms(&dev_priv->drm, "\n");
 732
 733         intel_dsi_wait_panel_power_cycle(intel_dsi);
 734
 735         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 736
 737         /*
 738          * The BIOS may leave the PLL in a wonky state where it doesn't
 739          * lock. It needs to be fully powered down to fix it.
 740          */
 741         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 742                 bxt_dsi_pll_disable(encoder);
 743                 bxt_dsi_pll_enable(encoder, pipe_config);
 744         } else {
 745                 vlv_dsi_pll_disable(encoder);
 746                 vlv_dsi_pll_enable(encoder, pipe_config);
 747         }
 748
 749         if (IS_BROXTON(dev_priv)) {
 750                 /* Add MIPI IO reset programming for modeset */
 751                 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
 752
 753                 /* Power up DSI regulator */
 754                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 755                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 756         }
 757
 758         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 759                 /* Disable DPOunit clock gating, can stall pipe */
 760                 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
 761                              0, DPOUNIT_CLOCK_GATE_DISABLE);
 762         }
 763
 764         if (!IS_GEMINILAKE(dev_priv))
 765                 intel_dsi_prepare(encoder, pipe_config);
 766
 767         /* Give the panel time to power-on and then deassert its reset */
 768         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 769         msleep(intel_dsi->panel_on_delay);
 770         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 771
 772         if (IS_GEMINILAKE(dev_priv)) {
 773                 glk_cold_boot = glk_dsi_enable_io(encoder);
 774
 775                 /* Prepare port in cold boot(s3/s4) scenario */
 776                 if (glk_cold_boot)
 777                         intel_dsi_prepare(encoder, pipe_config);
 778         }
 779
 780         /* Put device in ready state (LP-11) */
 781         intel_dsi_device_ready(encoder);
 782
 783         /* Prepare port in normal boot scenario */
 784         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 785                 intel_dsi_prepare(encoder, pipe_config);
 786
 787         /* Send initialization commands in LP mode */
 788         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 789
 790         /*
 791          * Enable port in pre-enable phase itself because as per hw team
 792          * recommendation, port should be enabled before plane & pipe
 793          */
 794         if (is_cmd_mode(intel_dsi)) {
 795                 for_each_dsi_port(port, intel_dsi->ports)
 796                         intel_de_write(dev_priv,
 797                                        MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 798                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 799                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 800         } else {
 801                 msleep(20); /* XXX */
 802                 for_each_dsi_port(port, intel_dsi->ports)
 803                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 804                 msleep(100);
 805
 806                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 807
 808                 intel_dsi_port_enable(encoder, pipe_config);
 809         }
 810
 811         intel_backlight_enable(pipe_config, conn_state);
 812         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 813 }
 814
 815 static void bxt_dsi_enable(struct intel_atomic_state *state,
 816                            struct intel_encoder *encoder,
 817                            const struct intel_crtc_state *crtc_state,
 818                            const struct drm_connector_state *conn_state)
 819 {
 820         intel_crtc_vblank_on(crtc_state);
 821 }
 822
 823 /*
 824  * DSI port disable has to be done after pipe and plane disable, so we do it in
 825  * the post_disable hook.
 826  */
 827 static void intel_dsi_disable(struct intel_atomic_state *state,
 828                               struct intel_encoder *encoder,
 829                               const struct intel_crtc_state *old_crtc_state,
 830                               const struct drm_connector_state *old_conn_state)
 831 {
 832         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 833         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 834         enum port port;
 835
 836         drm_dbg_kms(&i915->drm, "\n");
 837
 838         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 839         intel_backlight_disable(old_conn_state);
 840
 841         /*
 842          * According to the spec we should send SHUTDOWN before
 843          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 844          * has shown that the v3 sequence works for v2 VBTs too
 845          */
 846         if (is_vid_mode(intel_dsi)) {
 847                 /* Send Shutdown command to the panel in LP mode */
 848                 for_each_dsi_port(port, intel_dsi->ports)
 849                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 850                 msleep(10);
 851         }
 852 }
 853
 854 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 855 {
 856         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 857
 858         if (IS_GEMINILAKE(dev_priv))
 859                 glk_dsi_clear_device_ready(encoder);
 860         else
 861                 vlv_dsi_clear_device_ready(encoder);
 862 }
 863
 864 static void intel_dsi_post_disable(struct intel_atomic_state *state,
 865                                    struct intel_encoder *encoder,
 866                                    const struct intel_crtc_state *old_crtc_state,
 867                                    const struct drm_connector_state *old_conn_state)
 868 {
 869         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 870         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 871         enum port port;
 872
 873         drm_dbg_kms(&dev_priv->drm, "\n");
 874
 875         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 876                 intel_crtc_vblank_off(old_crtc_state);
 877
 878                 skl_scaler_disable(old_crtc_state);
 879         }
 880
 881         if (is_vid_mode(intel_dsi)) {
 882                 for_each_dsi_port(port, intel_dsi->ports)
 883                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 884
 885                 intel_dsi_port_disable(encoder);
 886                 usleep_range(2000, 5000);
 887         }
 888
 889         intel_dsi_unprepare(encoder);
 890
 891         /*
 892          * if disable packets are sent before sending shutdown packet then in
 893          * some next enable sequence send turn on packet error is observed
 894          */
 895         if (is_cmd_mode(intel_dsi))
 896                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 897         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 898
 899         /* Transition to LP-00 */
 900         intel_dsi_clear_device_ready(encoder);
 901
 902         if (IS_BROXTON(dev_priv)) {
 903                 /* Power down DSI regulator to save power */
 904                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 905                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
 906                                HS_IO_CTRL_SELECT);
 907
 908                 /* Add MIPI IO reset programming for modeset */
 909                 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
 910         }
 911
 912         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 913                 bxt_dsi_pll_disable(encoder);
 914         } else {
 915                 vlv_dsi_pll_disable(encoder);
 916
 917                 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
 918                              DPOUNIT_CLOCK_GATE_DISABLE, 0);
 919         }
 920
 921         /* Assert reset */
 922         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 923
 924         msleep(intel_dsi->panel_off_delay);
 925         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 926
 927         intel_dsi->panel_power_off_time = ktime_get_boottime();
 928 }
 929
 930 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 931                                    enum pipe *pipe)
 932 {
 933         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 934         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 935         intel_wakeref_t wakeref;
 936         enum port port;
 937         bool active = false;
 938
 939         drm_dbg_kms(&dev_priv->drm, "\n");
 940
 941         wakeref = intel_display_power_get_if_enabled(dev_priv,
 942                                                      encoder->power_domain);
 943         if (!wakeref)
 944                 return false;
 945
 946         /*
 947          * On Broxton the PLL needs to be enabled with a valid divider
 948          * configuration, otherwise accessing DSI registers will hang the
 949          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 950          */
 951         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
 952             !bxt_dsi_pll_is_enabled(dev_priv))
 953                 goto out_put_power;
 954
 955         /* XXX: this only works for one DSI output */
 956         for_each_dsi_port(port, intel_dsi->ports) {
 957                 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 958                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 959                 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
 960
 961                 /*
 962                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 963                  * bit in port C control register does not get set. As a
 964                  * workaround, check pipe B conf instead.
 965                  */
 966                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 967                     port == PORT_C)
 968                         enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
 969
 970                 /* Try command mode if video mode not enabled */
 971                 if (!enabled) {
 972                         u32 tmp = intel_de_read(dev_priv,
 973                                                 MIPI_DSI_FUNC_PRG(port));
 974                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 975                 }
 976
 977                 if (!enabled)
 978                         continue;
 979
 980                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
 981                         continue;
 982
 983                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 984                         u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 985                         tmp &= BXT_PIPE_SELECT_MASK;
 986                         tmp >>= BXT_PIPE_SELECT_SHIFT;
 987
 988                         if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
 989                                 continue;
 990
 991                         *pipe = tmp;
 992                 } else {
 993                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 994                 }
 995
 996                 active = true;
 997                 break;
 998         }
 999
1000 out_put_power:
1001         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1002
1003         return active;
1004 }
1005
1006 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1007                                     struct intel_crtc_state *pipe_config)
1008 {
1009         struct drm_device *dev = encoder->base.dev;
1010         struct drm_i915_private *dev_priv = to_i915(dev);
1011         struct drm_display_mode *adjusted_mode =
1012                                         &pipe_config->hw.adjusted_mode;
1013         struct drm_display_mode *adjusted_mode_sw;
1014         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1015         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1016         unsigned int lane_count = intel_dsi->lane_count;
1017         unsigned int bpp, fmt;
1018         enum port port;
1019         u16 hactive, hfp, hsync, hbp, vfp, vsync;
1020         u16 hfp_sw, hsync_sw, hbp_sw;
1021         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1022                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1023
1024         /* FIXME: hw readout should not depend on SW state */
1025         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1026
1027         /*
1028          * Atleast one port is active as encoder->get_config called only if
1029          * encoder->get_hw_state() returns true.
1030          */
1031         for_each_dsi_port(port, intel_dsi->ports) {
1032                 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1033                         break;
1034         }
1035
1036         fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1037         bpp = mipi_dsi_pixel_format_to_bpp(
1038                         pixel_format_from_register_bits(fmt));
1039
1040         pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1041
1042         /* Enable Frame time stamo based scanline reporting */
1043         pipe_config->mode_flags |=
1044                 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1045
1046         /* In terms of pixels */
1047         adjusted_mode->crtc_hdisplay =
1048                                 intel_de_read(dev_priv,
1049                                               BXT_MIPI_TRANS_HACTIVE(port));
1050         adjusted_mode->crtc_vdisplay =
1051                                 intel_de_read(dev_priv,
1052                                               BXT_MIPI_TRANS_VACTIVE(port));
1053         adjusted_mode->crtc_vtotal =
1054                                 intel_de_read(dev_priv,
1055                                               BXT_MIPI_TRANS_VTOTAL(port));
1056
1057         hactive = adjusted_mode->crtc_hdisplay;
1058         hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1059
1060         /*
1061          * Meaningful for video mode non-burst sync pulse mode only,
1062          * can be zero for non-burst sync events and burst modes
1063          */
1064         hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1065         hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1066
1067         /* harizontal values are in terms of high speed byte clock */
1068         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1069                                                 intel_dsi->burst_mode_ratio);
1070         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1071                                                 intel_dsi->burst_mode_ratio);
1072         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1073                                                 intel_dsi->burst_mode_ratio);
1074
1075         if (intel_dsi->dual_link) {
1076                 hfp *= 2;
1077                 hsync *= 2;
1078                 hbp *= 2;
1079         }
1080
1081         /* vertical values are in terms of lines */
1082         vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1083         vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1084
1085         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1086         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1087         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1088         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1089         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1090
1091         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1092         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1093         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1094         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1095
1096         /*
1097          * In BXT DSI there is no regs programmed with few horizontal timings
1098          * in Pixels but txbyteclkhs.. So retrieval process adds some
1099          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1100          * Actually here for the given adjusted_mode, we are calculating the
1101          * value programmed to the port and then back to the horizontal timing
1102          * param in pixels. This is the expected value, including roundup errors
1103          * And if that is same as retrieved value from port, then
1104          * (HW state) adjusted_mode's horizontal timings are corrected to
1105          * match with SW state to nullify the errors.
1106          */
1107         /* Calculating the value programmed to the Port register */
1108         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1109                                         adjusted_mode_sw->crtc_hdisplay;
1110         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1111                                         adjusted_mode_sw->crtc_hsync_start;
1112         hbp_sw = adjusted_mode_sw->crtc_htotal -
1113                                         adjusted_mode_sw->crtc_hsync_end;
1114
1115         if (intel_dsi->dual_link) {
1116                 hfp_sw /= 2;
1117                 hsync_sw /= 2;
1118                 hbp_sw /= 2;
1119         }
1120
1121         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1122                                                 intel_dsi->burst_mode_ratio);
1123         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1124                             intel_dsi->burst_mode_ratio);
1125         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1126                                                 intel_dsi->burst_mode_ratio);
1127
1128         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1129         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1130                                                 intel_dsi->burst_mode_ratio);
1131         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1132                                                 intel_dsi->burst_mode_ratio);
1133         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1134                                                 intel_dsi->burst_mode_ratio);
1135
1136         if (intel_dsi->dual_link) {
1137                 hfp_sw *= 2;
1138                 hsync_sw *= 2;
1139                 hbp_sw *= 2;
1140         }
1141
1142         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1143                                                         hsync_sw + hbp_sw;
1144         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1145         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1146         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1147         crtc_hblank_end_sw = crtc_htotal_sw;
1148
1149         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1150                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1151
1152         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1153                 adjusted_mode->crtc_hsync_start =
1154                                         adjusted_mode_sw->crtc_hsync_start;
1155
1156         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1157                 adjusted_mode->crtc_hsync_end =
1158                                         adjusted_mode_sw->crtc_hsync_end;
1159
1160         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1161                 adjusted_mode->crtc_hblank_start =
1162                                         adjusted_mode_sw->crtc_hblank_start;
1163
1164         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1165                 adjusted_mode->crtc_hblank_end =
1166                                         adjusted_mode_sw->crtc_hblank_end;
1167 }
1168
1169 static void intel_dsi_get_config(struct intel_encoder *encoder,
1170                                  struct intel_crtc_state *pipe_config)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1173         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1174         u32 pclk;
1175
1176         drm_dbg_kms(&dev_priv->drm, "\n");
1177
1178         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1179
1180         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1181                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1182                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1183         } else {
1184                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1185         }
1186
1187         pipe_config->port_clock = pclk;
1188
1189         /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1190         pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1191         if (intel_dsi->dual_link)
1192                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1193 }
1194
1195 /* return txclkesc cycles in terms of divider and duration in us */
1196 static u16 txclkesc(u32 divider, unsigned int us)
1197 {
1198         switch (divider) {
1199         case ESCAPE_CLOCK_DIVIDER_1:
1200         default:
1201                 return 20 * us;
1202         case ESCAPE_CLOCK_DIVIDER_2:
1203                 return 10 * us;
1204         case ESCAPE_CLOCK_DIVIDER_4:
1205                 return 5 * us;
1206         }
1207 }
1208
1209 static void set_dsi_timings(struct drm_encoder *encoder,
1210                             const struct drm_display_mode *adjusted_mode)
1211 {
1212         struct drm_device *dev = encoder->dev;
1213         struct drm_i915_private *dev_priv = to_i915(dev);
1214         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1215         enum port port;
1216         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1217         unsigned int lane_count = intel_dsi->lane_count;
1218
1219         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1220
1221         hactive = adjusted_mode->crtc_hdisplay;
1222         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1223         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1224         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1225
1226         if (intel_dsi->dual_link) {
1227                 hactive /= 2;
1228                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1229                         hactive += intel_dsi->pixel_overlap;
1230                 hfp /= 2;
1231                 hsync /= 2;
1232                 hbp /= 2;
1233         }
1234
1235         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1236         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1237         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1238
1239         /* horizontal values are in terms of high speed byte clock */
1240         hactive = txbyteclkhs(hactive, bpp, lane_count,
1241                               intel_dsi->burst_mode_ratio);
1242         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1243         hsync = txbyteclkhs(hsync, bpp, lane_count,
1244                             intel_dsi->burst_mode_ratio);
1245         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1246
1247         for_each_dsi_port(port, intel_dsi->ports) {
1248                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1249                         /*
1250                          * Program hdisplay and vdisplay on MIPI transcoder.
1251                          * This is different from calculated hactive and
1252                          * vactive, as they are calculated per channel basis,
1253                          * whereas these values should be based on resolution.
1254                          */
1255                         intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1256                                        adjusted_mode->crtc_hdisplay);
1257                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1258                                        adjusted_mode->crtc_vdisplay);
1259                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1260                                        adjusted_mode->crtc_vtotal);
1261                 }
1262
1263                 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1264                                hactive);
1265                 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1266
1267                 /* meaningful for video mode non-burst sync pulse mode only,
1268                  * can be zero for non-burst sync events and burst modes */
1269                 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1270                                hsync);
1271                 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1272
1273                 /* vertical values are in terms of lines */
1274                 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1275                 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1276                                vsync);
1277                 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1278         }
1279 }
1280
1281 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1282 {
1283         switch (fmt) {
1284         case MIPI_DSI_FMT_RGB888:
1285                 return VID_MODE_FORMAT_RGB888;
1286         case MIPI_DSI_FMT_RGB666:
1287                 return VID_MODE_FORMAT_RGB666;
1288         case MIPI_DSI_FMT_RGB666_PACKED:
1289                 return VID_MODE_FORMAT_RGB666_PACKED;
1290         case MIPI_DSI_FMT_RGB565:
1291                 return VID_MODE_FORMAT_RGB565;
1292         default:
1293                 MISSING_CASE(fmt);
1294                 return VID_MODE_FORMAT_RGB666;
1295         }
1296 }
1297
1298 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1299                               const struct intel_crtc_state *pipe_config)
1300 {
1301         struct drm_encoder *encoder = &intel_encoder->base;
1302         struct drm_device *dev = encoder->dev;
1303         struct drm_i915_private *dev_priv = to_i915(dev);
1304         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1305         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1306         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1307         enum port port;
1308         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1309         u32 val, tmp;
1310         u16 mode_hdisplay;
1311
1312         drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1313
1314         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1315
1316         if (intel_dsi->dual_link) {
1317                 mode_hdisplay /= 2;
1318                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1319                         mode_hdisplay += intel_dsi->pixel_overlap;
1320         }
1321
1322         for_each_dsi_port(port, intel_dsi->ports) {
1323                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1324                         /*
1325                          * escape clock divider, 20MHz, shared for A and C.
1326                          * device ready must be off when doing this! txclkesc?
1327                          */
1328                         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1329                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1330                         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1331                                        tmp | ESCAPE_CLOCK_DIVIDER_1);
1332
1333                         /* read request priority is per pipe */
1334                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1335                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1336                         intel_de_write(dev_priv, MIPI_CTRL(port),
1337                                        tmp | READ_REQUEST_PRIORITY_HIGH);
1338                 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1339                         enum pipe pipe = crtc->pipe;
1340
1341                         intel_de_rmw(dev_priv, MIPI_CTRL(port),
1342                                      BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1343                 }
1344
1345                 /* XXX: why here, why like this? handling in irq handler?! */
1346                 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1347                 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1348
1349                 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1350                                intel_dsi->dphy_reg);
1351
1352                 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1353                                adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1354         }
1355
1356         set_dsi_timings(encoder, adjusted_mode);
1357
1358         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1359         if (is_cmd_mode(intel_dsi)) {
1360                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1361                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1362         } else {
1363                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1364                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1365         }
1366
1367         tmp = 0;
1368         if (intel_dsi->eotp_pkt == 0)
1369                 tmp |= EOT_DISABLE;
1370         if (intel_dsi->clock_stop)
1371                 tmp |= CLOCKSTOP;
1372
1373         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1374                 tmp |= BXT_DPHY_DEFEATURE_EN;
1375                 if (!is_cmd_mode(intel_dsi))
1376                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1377         }
1378
1379         for_each_dsi_port(port, intel_dsi->ports) {
1380                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1381
1382                 /* timeouts for recovery. one frame IIUC. if counter expires,
1383                  * EOT and stop state. */
1384
1385                 /*
1386                  * In burst mode, value greater than one DPI line Time in byte
1387                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1388                  * said value is recommended.
1389                  *
1390                  * In non-burst mode, Value greater than one DPI frame time in
1391                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1392                  * said value is recommended.
1393                  *
1394                  * In DBI only mode, value greater than one DBI frame time in
1395                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1396                  * said value is recommended.
1397                  */
1398
1399                 if (is_vid_mode(intel_dsi) &&
1400                         intel_dsi->video_mode == BURST_MODE) {
1401                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1402                                        txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1403                 } else {
1404                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1405                                        txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1406                 }
1407                 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1408                                intel_dsi->lp_rx_timeout);
1409                 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1410                                intel_dsi->turn_arnd_val);
1411                 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1412                                intel_dsi->rst_timer_val);
1413
1414                 /* dphy stuff */
1415
1416                 /* in terms of low power clock */
1417                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1418                                txclkesc(intel_dsi->escape_clk_div, 100));
1419
1420                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1421                     !intel_dsi->dual_link) {
1422                         /*
1423                          * BXT spec says write MIPI_INIT_COUNT for
1424                          * both the ports, even if only one is
1425                          * getting used. So write the other port
1426                          * if not in dual link mode.
1427                          */
1428                         intel_de_write(dev_priv,
1429                                        MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1430                                        intel_dsi->init_count);
1431                 }
1432
1433                 /* recovery disables */
1434                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1435
1436                 /* in terms of low power clock */
1437                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1438                                intel_dsi->init_count);
1439
1440                 /* in terms of txbyteclkhs. actual high to low switch +
1441                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1442                  *
1443                  * XXX: write MIPI_STOP_STATE_STALL?
1444                  */
1445                 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1446                                intel_dsi->hs_to_lp_count);
1447
1448                 /* XXX: low power clock equivalence in terms of byte clock.
1449                  * the number of byte clocks occupied in one low power clock.
1450                  * based on txbyteclkhs and txclkesc.
1451                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1452                  * ) / 105.???
1453                  */
1454                 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1455                                intel_dsi->lp_byte_clk);
1456
1457                 if (IS_GEMINILAKE(dev_priv)) {
1458                         intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1459                                        intel_dsi->lp_byte_clk);
1460                         /* Shadow of DPHY reg */
1461                         intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1462                                        intel_dsi->dphy_reg);
1463                 }
1464
1465                 /* the bw essential for transmitting 16 long packets containing
1466                  * 252 bytes meant for dcs write memory command is programmed in
1467                  * this register in terms of byte clocks. based on dsi transfer
1468                  * rate and the number of lanes configured the time taken to
1469                  * transmit 16 long packets in a dsi stream varies. */
1470                 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1471                                intel_dsi->bw_timer);
1472
1473                 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1474                                intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1475
1476                 if (is_vid_mode(intel_dsi)) {
1477                         u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1478
1479                         /*
1480                          * Some panels might have resolution which is not a
1481                          * multiple of 64 like 1366 x 768. Enable RANDOM
1482                          * resolution support for such panels by default.
1483                          */
1484                         fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1485
1486                         switch (intel_dsi->video_mode) {
1487                         default:
1488                                 MISSING_CASE(intel_dsi->video_mode);
1489                                 fallthrough;
1490                         case NON_BURST_SYNC_EVENTS:
1491                                 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1492                                 break;
1493                         case NON_BURST_SYNC_PULSE:
1494                                 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1495                                 break;
1496                         case BURST_MODE:
1497                                 fmt |= VIDEO_MODE_BURST;
1498                                 break;
1499                         }
1500
1501                         intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1502                 }
1503         }
1504 }
1505
1506 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1507 {
1508         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1509         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1510         enum port port;
1511
1512         if (IS_GEMINILAKE(dev_priv))
1513                 return;
1514
1515         for_each_dsi_port(port, intel_dsi->ports) {
1516                 /* Panel commands can be sent when clock is in LP11 */
1517                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1518
1519                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1520                         bxt_dsi_reset_clocks(encoder, port);
1521                 else
1522                         vlv_dsi_reset_clocks(encoder, port);
1523                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1524
1525                 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
1526
1527                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1528         }
1529 }
1530
1531 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1532 {
1533         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1534
1535         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1536         intel_encoder_destroy(encoder);
1537 }
1538
1539 static const struct drm_encoder_funcs intel_dsi_funcs = {
1540         .destroy = intel_dsi_encoder_destroy,
1541 };
1542
1543 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1544         .get_modes = intel_dsi_get_modes,
1545         .mode_valid = intel_dsi_mode_valid,
1546         .atomic_check = intel_digital_connector_atomic_check,
1547 };
1548
1549 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1550         .detect = intel_panel_detect,
1551         .late_register = intel_connector_register,
1552         .early_unregister = intel_connector_unregister,
1553         .destroy = intel_connector_destroy,
1554         .fill_modes = drm_helper_probe_single_connector_modes,
1555         .atomic_get_property = intel_digital_connector_atomic_get_property,
1556         .atomic_set_property = intel_digital_connector_atomic_set_property,
1557         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1558         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1559 };
1560
1561 static void vlv_dsi_add_properties(struct intel_connector *connector)
1562 {
1563         const struct drm_display_mode *fixed_mode =
1564                 intel_panel_preferred_fixed_mode(connector);
1565
1566         intel_attach_scaling_mode_property(&connector->base);
1567
1568         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1569                                                        intel_dsi_get_panel_orientation(connector),
1570                                                        fixed_mode->hdisplay,
1571                                                        fixed_mode->vdisplay);
1572 }
1573
1574 #define NS_KHZ_RATIO            1000000
1575
1576 #define PREPARE_CNT_MAX         0x3F
1577 #define EXIT_ZERO_CNT_MAX       0x3F
1578 #define CLK_ZERO_CNT_MAX        0xFF
1579 #define TRAIL_CNT_MAX           0x1F
1580
1581 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1582 {
1583         struct drm_device *dev = intel_dsi->base.base.dev;
1584         struct drm_i915_private *dev_priv = to_i915(dev);
1585         struct intel_connector *connector = intel_dsi->attached_connector;
1586         struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1587         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1588         u32 ui_num, ui_den;
1589         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1590         u32 ths_prepare_ns, tclk_trail_ns;
1591         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1592         u32 lp_to_hs_switch, hs_to_lp_switch;
1593         u32 mul;
1594
1595         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1596
1597         switch (intel_dsi->lane_count) {
1598         case 1:
1599         case 2:
1600                 extra_byte_count = 2;
1601                 break;
1602         case 3:
1603                 extra_byte_count = 4;
1604                 break;
1605         case 4:
1606         default:
1607                 extra_byte_count = 3;
1608                 break;
1609         }
1610
1611         /* in Kbps */
1612         ui_num = NS_KHZ_RATIO;
1613         ui_den = intel_dsi_bitrate(intel_dsi);
1614
1615         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1616         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1617
1618         /*
1619          * B060
1620          * LP byte clock = TLPX/ (8UI)
1621          */
1622         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1623
1624         /* DDR clock period = 2 * UI
1625          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1626          * UI(nsec) = 10^6 / bitrate
1627          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1628          * DDR clock count  = ns_value / DDR clock period
1629          *
1630          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1631          * HS byte clock count for other platform in HS ddr clock count
1632          */
1633         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1634         ths_prepare_ns = max(mipi_config->ths_prepare,
1635                              mipi_config->tclk_prepare);
1636
1637         /* prepare count */
1638         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1639
1640         if (prepare_cnt > PREPARE_CNT_MAX) {
1641                 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1642                             prepare_cnt);
1643                 prepare_cnt = PREPARE_CNT_MAX;
1644         }
1645
1646         /* exit zero count */
1647         exit_zero_cnt = DIV_ROUND_UP(
1648                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1649                                 ui_num * mul
1650                                 );
1651
1652         /*
1653          * Exit zero is unified val ths_zero and ths_exit
1654          * minimum value for ths_exit = 110ns
1655          * min (exit_zero_cnt * 2) = 110/UI
1656          * exit_zero_cnt = 55/UI
1657          */
1658         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1659                 exit_zero_cnt += 1;
1660
1661         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1662                 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1663                             exit_zero_cnt);
1664                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1665         }
1666
1667         /* clk zero count */
1668         clk_zero_cnt = DIV_ROUND_UP(
1669                                 (tclk_prepare_clkzero - ths_prepare_ns)
1670                                 * ui_den, ui_num * mul);
1671
1672         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1673                 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1674                             clk_zero_cnt);
1675                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1676         }
1677
1678         /* trail count */
1679         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1680         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1681
1682         if (trail_cnt > TRAIL_CNT_MAX) {
1683                 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1684                             trail_cnt);
1685                 trail_cnt = TRAIL_CNT_MAX;
1686         }
1687
1688         /* B080 */
1689         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1690                                                 clk_zero_cnt << 8 | prepare_cnt;
1691
1692         /*
1693          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1694          *                                      mul + 10UI + Extra Byte Count
1695          *
1696          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1697          * Extra Byte Count is calculated according to number of lanes.
1698          * High Low Switch Count is the Max of LP to HS and
1699          * HS to LP switch count
1700          *
1701          */
1702         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1703
1704         /* B044 */
1705         /* FIXME:
1706          * The comment above does not match with the code */
1707         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1708                                                 exit_zero_cnt * mul + 10, 8);
1709
1710         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1711
1712         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1713         intel_dsi->hs_to_lp_count += extra_byte_count;
1714
1715         /* B088 */
1716         /* LP -> HS for clock lanes
1717          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1718          *                                              extra byte count
1719          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1720          *                                      2(in UI) + extra byte count
1721          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1722          *                                      8 + extra byte count
1723          */
1724         intel_dsi->clk_lp_to_hs_count =
1725                 DIV_ROUND_UP(
1726                         4 * tlpx_ui + prepare_cnt * 2 +
1727                         clk_zero_cnt * 2,
1728                         8);
1729
1730         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1731
1732         /* HS->LP for Clock Lanes
1733          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1734          *                                              Extra byte count
1735          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1736          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1737          *                                              Extra byte count
1738          */
1739         intel_dsi->clk_hs_to_lp_count =
1740                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1741                         8);
1742         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1743
1744         intel_dsi_log_params(intel_dsi);
1745 }
1746
1747 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1748 {
1749         struct intel_dsi *intel_dsi;
1750         struct intel_encoder *intel_encoder;
1751         struct drm_encoder *encoder;
1752         struct intel_connector *intel_connector;
1753         struct drm_connector *connector;
1754         struct drm_display_mode *current_mode;
1755         enum port port;
1756         enum pipe pipe;
1757
1758         drm_dbg_kms(&dev_priv->drm, "\n");
1759
1760         /* There is no detection method for MIPI so rely on VBT */
1761         if (!intel_bios_is_dsi_present(dev_priv, &port))
1762                 return;
1763
1764         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1765                 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1766         else
1767                 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1768
1769         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1770         if (!intel_dsi)
1771                 return;
1772
1773         intel_connector = intel_connector_alloc();
1774         if (!intel_connector) {
1775                 kfree(intel_dsi);
1776                 return;
1777         }
1778
1779         intel_encoder = &intel_dsi->base;
1780         encoder = &intel_encoder->base;
1781         intel_dsi->attached_connector = intel_connector;
1782
1783         connector = &intel_connector->base;
1784
1785         drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1786                          "DSI %c", port_name(port));
1787
1788         intel_encoder->compute_config = intel_dsi_compute_config;
1789         intel_encoder->pre_enable = intel_dsi_pre_enable;
1790         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1791                 intel_encoder->enable = bxt_dsi_enable;
1792         intel_encoder->disable = intel_dsi_disable;
1793         intel_encoder->post_disable = intel_dsi_post_disable;
1794         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1795         intel_encoder->get_config = intel_dsi_get_config;
1796         intel_encoder->update_pipe = intel_backlight_update;
1797         intel_encoder->shutdown = intel_dsi_shutdown;
1798
1799         intel_connector->get_hw_state = intel_connector_get_hw_state;
1800
1801         intel_encoder->port = port;
1802         intel_encoder->type = INTEL_OUTPUT_DSI;
1803         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1804         intel_encoder->cloneable = 0;
1805
1806         /*
1807          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1808          * port C. BXT isn't limited like this.
1809          */
1810         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1811                 intel_encoder->pipe_mask = ~0;
1812         else if (port == PORT_A)
1813                 intel_encoder->pipe_mask = BIT(PIPE_A);
1814         else
1815                 intel_encoder->pipe_mask = BIT(PIPE_B);
1816
1817         intel_dsi->panel_power_off_time = ktime_get_boottime();
1818
1819         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL);
1820
1821         if (intel_connector->panel.vbt.dsi.config->dual_link)
1822                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1823         else
1824                 intel_dsi->ports = BIT(port);
1825
1826         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1827                 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1828
1829         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1830                 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1831
1832         /* Create a DSI host (and a device) for each port. */
1833         for_each_dsi_port(port, intel_dsi->ports) {
1834                 struct intel_dsi_host *host;
1835
1836                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1837                                            port);
1838                 if (!host)
1839                         goto err;
1840
1841                 intel_dsi->dsi_hosts[port] = host;
1842         }
1843
1844         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1845                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1846                 goto err;
1847         }
1848
1849         /* Use clock read-back from current hw-state for fastboot */
1850         current_mode = intel_encoder_current_mode(intel_encoder);
1851         if (current_mode) {
1852                 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1853                             intel_dsi->pclk, current_mode->clock);
1854                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1855                                             current_mode->clock)) {
1856                         drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1857                         intel_dsi->pclk = current_mode->clock;
1858                 }
1859
1860                 kfree(current_mode);
1861         }
1862
1863         vlv_dphy_param_init(intel_dsi);
1864
1865         intel_dsi_vbt_gpio_init(intel_dsi,
1866                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1867
1868         drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs,
1869                            DRM_MODE_CONNECTOR_DSI);
1870
1871         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1872
1873         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1874
1875         intel_connector_attach_encoder(intel_connector, intel_encoder);
1876
1877         mutex_lock(&dev_priv->drm.mode_config.mutex);
1878         intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1879         mutex_unlock(&dev_priv->drm.mode_config.mutex);
1880
1881         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1882                 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1883                 goto err_cleanup_connector;
1884         }
1885
1886         intel_panel_init(intel_connector, NULL);
1887
1888         intel_backlight_setup(intel_connector, INVALID_PIPE);
1889
1890         vlv_dsi_add_properties(intel_connector);
1891
1892         return;
1893
1894 err_cleanup_connector:
1895         drm_connector_cleanup(&intel_connector->base);
1896 err:
1897         drm_encoder_cleanup(&intel_encoder->base);
1898         kfree(intel_dsi);
1899         kfree(intel_connector);
1900 }