2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008,2010 Intel Corporation
7 #include <linux/intel-iommu.h>
8 #include <linux/dma-resv.h>
9 #include <linux/sync_file.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_syncobj.h>
13 #include <drm/i915_drm.h>
15 #include "display/intel_frontbuffer.h"
17 #include "gem/i915_gem_ioctls.h"
18 #include "gt/intel_context.h"
19 #include "gt/intel_engine_pool.h"
20 #include "gt/intel_gt.h"
21 #include "gt/intel_gt_pm.h"
22 #include "gt/intel_ring.h"
25 #include "i915_gem_clflush.h"
26 #include "i915_gem_context.h"
27 #include "i915_gem_ioctls.h"
28 #include "i915_sw_fence_work.h"
29 #include "i915_trace.h"
35 #define DBG_FORCE_RELOC 0 /* choose one of the above! */
38 #define __EXEC_OBJECT_HAS_REF BIT(31)
39 #define __EXEC_OBJECT_HAS_PIN BIT(30)
40 #define __EXEC_OBJECT_HAS_FENCE BIT(29)
41 #define __EXEC_OBJECT_NEEDS_MAP BIT(28)
42 #define __EXEC_OBJECT_NEEDS_BIAS BIT(27)
43 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */
44 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
46 #define __EXEC_HAS_RELOC BIT(31)
47 #define __EXEC_VALIDATED BIT(30)
48 #define __EXEC_INTERNAL_FLAGS (~0u << 30)
49 #define UPDATE PIN_OFFSET_FIXED
51 #define BATCH_OFFSET_BIAS (256*1024)
53 #define __I915_EXEC_ILLEGAL_FLAGS \
54 (__I915_EXEC_UNKNOWN_FLAGS | \
55 I915_EXEC_CONSTANTS_MASK | \
56 I915_EXEC_RESOURCE_STREAMER)
58 /* Catch emission of unexpected errors for CI! */
59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
62 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
68 * DOC: User command execution
70 * Userspace submits commands to be executed on the GPU as an instruction
71 * stream within a GEM object we call a batchbuffer. This instructions may
72 * refer to other GEM objects containing auxiliary state such as kernels,
73 * samplers, render targets and even secondary batchbuffers. Userspace does
74 * not know where in the GPU memory these objects reside and so before the
75 * batchbuffer is passed to the GPU for execution, those addresses in the
76 * batchbuffer and auxiliary objects are updated. This is known as relocation,
77 * or patching. To try and avoid having to relocate each object on the next
78 * execution, userspace is told the location of those objects in this pass,
79 * but this remains just a hint as the kernel may choose a new location for
80 * any object in the future.
82 * At the level of talking to the hardware, submitting a batchbuffer for the
83 * GPU to execute is to add content to a buffer from which the HW
84 * command streamer is reading.
86 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
87 * Execlists, this command is not placed on the same buffer as the
90 * 2. Add a command to invalidate caches to the buffer.
92 * 3. Add a batchbuffer start command to the buffer; the start command is
93 * essentially a token together with the GPU address of the batchbuffer
96 * 4. Add a pipeline flush to the buffer.
98 * 5. Add a memory write command to the buffer to record when the GPU
99 * is done executing the batchbuffer. The memory write writes the
100 * global sequence number of the request, ``i915_request::global_seqno``;
101 * the i915 driver uses the current value in the register to determine
102 * if the GPU has completed the batchbuffer.
104 * 6. Add a user interrupt command to the buffer. This command instructs
105 * the GPU to issue an interrupt when the command, pipeline flush and
106 * memory write are completed.
108 * 7. Inform the hardware of the additional commands added to the buffer
109 * (by updating the tail pointer).
111 * Processing an execbuf ioctl is conceptually split up into a few phases.
113 * 1. Validation - Ensure all the pointers, handles and flags are valid.
114 * 2. Reservation - Assign GPU address space for every object
115 * 3. Relocation - Update any addresses to point to the final locations
116 * 4. Serialisation - Order the request with respect to its dependencies
117 * 5. Construction - Construct a request to execute the batchbuffer
118 * 6. Submission (at some point in the future execution)
120 * Reserving resources for the execbuf is the most complicated phase. We
121 * neither want to have to migrate the object in the address space, nor do
122 * we want to have to update any relocations pointing to this object. Ideally,
123 * we want to leave the object where it is and for all the existing relocations
124 * to match. If the object is given a new address, or if userspace thinks the
125 * object is elsewhere, we have to parse all the relocation entries and update
126 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
127 * all the target addresses in all of its objects match the value in the
128 * relocation entries and that they all match the presumed offsets given by the
129 * list of execbuffer objects. Using this knowledge, we know that if we haven't
130 * moved any buffers, all the relocation entries are valid and we can skip
131 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
132 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
134 * The addresses written in the objects must match the corresponding
135 * reloc.presumed_offset which in turn must match the corresponding
138 * Any render targets written to in the batch must be flagged with
141 * To avoid stalling, execobject.offset should match the current
142 * address of that object within the active context.
144 * The reservation is done is multiple phases. First we try and keep any
145 * object already bound in its current location - so as long as meets the
146 * constraints imposed by the new execbuffer. Any object left unbound after the
147 * first pass is then fitted into any available idle space. If an object does
148 * not fit, all objects are removed from the reservation and the process rerun
149 * after sorting the objects into a priority order (more difficult to fit
150 * objects are tried first). Failing that, the entire VM is cleared and we try
151 * to fit the execbuf once last time before concluding that it simply will not
154 * A small complication to all of this is that we allow userspace not only to
155 * specify an alignment and a size for the object in the address space, but
156 * we also allow userspace to specify the exact offset. This objects are
157 * simpler to place (the location is known a priori) all we have to do is make
158 * sure the space is available.
160 * Once all the objects are in place, patching up the buried pointers to point
161 * to the final locations is a fairly simple job of walking over the relocation
162 * entry arrays, looking up the right address and rewriting the value into
163 * the object. Simple! ... The relocation entries are stored in user memory
164 * and so to access them we have to copy them into a local buffer. That copy
165 * has to avoid taking any pagefaults as they may lead back to a GEM object
166 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
167 * the relocation into multiple passes. First we try to do everything within an
168 * atomic context (avoid the pagefaults) which requires that we never wait. If
169 * we detect that we may wait, or if we need to fault, then we have to fallback
170 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
171 * bells yet?) Dropping the mutex means that we lose all the state we have
172 * built up so far for the execbuf and we must reset any global data. However,
173 * we do leave the objects pinned in their final locations - which is a
174 * potential issue for concurrent execbufs. Once we have left the mutex, we can
175 * allocate and copy all the relocation entries into a large array at our
176 * leisure, reacquire the mutex, reclaim all the objects and other state and
177 * then proceed to update any incorrect addresses with the objects.
179 * As we process the relocation entries, we maintain a record of whether the
180 * object is being written to. Using NORELOC, we expect userspace to provide
181 * this information instead. We also check whether we can skip the relocation
182 * by comparing the expected value inside the relocation entry with the target's
183 * final address. If they differ, we have to map the current object and rewrite
184 * the 4 or 8 byte pointer within.
186 * Serialising an execbuf is quite simple according to the rules of the GEM
187 * ABI. Execution within each context is ordered by the order of submission.
188 * Writes to any GEM object are in order of submission and are exclusive. Reads
189 * from a GEM object are unordered with respect to other reads, but ordered by
190 * writes. A write submitted after a read cannot occur before the read, and
191 * similarly any read submitted after a write cannot occur before the write.
192 * Writes are ordered between engines such that only one write occurs at any
193 * time (completing any reads beforehand) - using semaphores where available
194 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
195 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
196 * reads before starting, and any read (either using set-domain or pread) must
197 * flush all GPU writes before starting. (Note we only employ a barrier before,
198 * we currently rely on userspace not concurrently starting a new execution
199 * whilst reading or writing to an object. This may be an advantage or not
200 * depending on how much you trust userspace not to shoot themselves in the
201 * foot.) Serialisation may just result in the request being inserted into
202 * a DAG awaiting its turn, but most simple is to wait on the CPU until
203 * all dependencies are resolved.
205 * After all of that, is just a matter of closing the request and handing it to
206 * the hardware (well, leaving it in a queue to be executed). However, we also
207 * offer the ability for batchbuffers to be run with elevated privileges so
208 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
209 * Before any batch is given extra privileges we first must check that it
210 * contains no nefarious instructions, we check that each instruction is from
211 * our whitelist and all registers are also from an allowed list. We first
212 * copy the user's batchbuffer to a shadow (so that the user doesn't have
213 * access to it, either by the CPU or GPU as we scan it) and then parse each
214 * instruction. If everything is ok, we set a flag telling the hardware to run
215 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
218 struct i915_execbuffer {
219 struct drm_i915_private *i915; /** i915 backpointer */
220 struct drm_file *file; /** per-file lookup tables and limits */
221 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
222 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
223 struct i915_vma **vma;
226 struct intel_engine_cs *engine; /** engine to queue the request to */
227 struct intel_context *context; /* logical state for the request */
228 struct i915_gem_context *gem_context; /** caller's context */
230 struct i915_request *request; /** our request to build */
231 struct i915_vma *batch; /** identity of the batch obj/vma */
232 struct i915_vma *trampoline; /** trampoline used for chaining */
234 /** actual size of execobj[] as we may extend it for the cmdparser */
235 unsigned int buffer_count;
237 /** list of vma not yet bound during reservation phase */
238 struct list_head unbound;
240 /** list of vma that have execobj.relocation_count */
241 struct list_head relocs;
244 * Track the most recently used object for relocations, as we
245 * frequently have to perform multiple relocations within the same
249 struct drm_mm_node node; /** temporary GTT binding */
250 unsigned long vaddr; /** Current kmap address */
251 unsigned long page; /** Currently mapped page index */
252 unsigned int gen; /** Cached value of INTEL_GEN */
253 bool use_64bit_reloc : 1;
256 bool needs_unfenced : 1;
258 struct i915_request *rq;
260 unsigned int rq_size;
263 u64 invalid_flags; /** Set of execobj.flags that are invalid */
264 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
266 u32 batch_start_offset; /** Location within object of batch */
267 u32 batch_len; /** Length of batch within object */
268 u32 batch_flags; /** Flags composed for emit_bb_start() */
271 * Indicate either the size of the hastable used to resolve
272 * relocation handles, or if negative that we are using a direct
273 * index into the execobj[].
276 struct hlist_head *buckets; /** ht for relocation handles */
279 #define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
281 static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
283 return intel_engine_requires_cmd_parser(eb->engine) ||
284 (intel_engine_using_cmd_parser(eb->engine) &&
285 eb->args->batch_len);
288 static int eb_create(struct i915_execbuffer *eb)
290 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
291 unsigned int size = 1 + ilog2(eb->buffer_count);
294 * Without a 1:1 association between relocation handles and
295 * the execobject[] index, we instead create a hashtable.
296 * We size it dynamically based on available memory, starting
297 * first with 1:1 assocative hash and scaling back until
298 * the allocation succeeds.
300 * Later on we use a positive lut_size to indicate we are
301 * using this hashtable, and a negative value to indicate a
307 /* While we can still reduce the allocation size, don't
308 * raise a warning and allow the allocation to fail.
309 * On the last pass though, we want to try as hard
310 * as possible to perform the allocation and warn
315 flags |= __GFP_NORETRY | __GFP_NOWARN;
317 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
328 eb->lut_size = -eb->buffer_count;
335 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
336 const struct i915_vma *vma,
339 if (vma->node.size < entry->pad_to_size)
342 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
345 if (flags & EXEC_OBJECT_PINNED &&
346 vma->node.start != entry->offset)
349 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
350 vma->node.start < BATCH_OFFSET_BIAS)
353 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
354 (vma->node.start + vma->node.size - 1) >> 32)
357 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
358 !i915_vma_is_map_and_fenceable(vma))
365 eb_pin_vma(struct i915_execbuffer *eb,
366 const struct drm_i915_gem_exec_object2 *entry,
367 struct i915_vma *vma)
369 unsigned int exec_flags = *vma->exec_flags;
373 pin_flags = vma->node.start;
375 pin_flags = entry->offset & PIN_OFFSET_MASK;
377 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
378 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT))
379 pin_flags |= PIN_GLOBAL;
381 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags)))
384 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
385 if (unlikely(i915_vma_pin_fence(vma))) {
391 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
394 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
395 return !eb_vma_misplaced(entry, vma, exec_flags);
398 static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
400 GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
402 if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
403 __i915_vma_unpin_fence(vma);
405 __i915_vma_unpin(vma);
409 eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags)
411 if (!(*flags & __EXEC_OBJECT_HAS_PIN))
414 __eb_unreserve_vma(vma, *flags);
415 *flags &= ~__EXEC_OBJECT_RESERVED;
419 eb_validate_vma(struct i915_execbuffer *eb,
420 struct drm_i915_gem_exec_object2 *entry,
421 struct i915_vma *vma)
423 if (unlikely(entry->flags & eb->invalid_flags))
426 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
430 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
431 * any non-page-aligned or non-canonical addresses.
433 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
434 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
437 /* pad_to_size was once a reserved field, so sanitize it */
438 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
439 if (unlikely(offset_in_page(entry->pad_to_size)))
442 entry->pad_to_size = 0;
445 if (unlikely(vma->exec_flags)) {
446 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
447 entry->handle, (int)(entry - eb->exec));
452 * From drm_mm perspective address space is continuous,
453 * so from this point we're always using non-canonical
456 entry->offset = gen8_noncanonical_addr(entry->offset);
458 if (!eb->reloc_cache.has_fence) {
459 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
461 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
462 eb->reloc_cache.needs_unfenced) &&
463 i915_gem_object_is_tiled(vma->obj))
464 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
467 if (!(entry->flags & EXEC_OBJECT_PINNED))
468 entry->flags |= eb->context_flags;
474 eb_add_vma(struct i915_execbuffer *eb,
475 unsigned int i, unsigned batch_idx,
476 struct i915_vma *vma)
478 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
481 GEM_BUG_ON(i915_vma_is_closed(vma));
483 if (!(eb->args->flags & __EXEC_VALIDATED)) {
484 err = eb_validate_vma(eb, entry, vma);
489 if (eb->lut_size > 0) {
490 vma->exec_handle = entry->handle;
491 hlist_add_head(&vma->exec_node,
492 &eb->buckets[hash_32(entry->handle,
496 if (entry->relocation_count)
497 list_add_tail(&vma->reloc_link, &eb->relocs);
500 * Stash a pointer from the vma to execobj, so we can query its flags,
501 * size, alignment etc as provided by the user. Also we stash a pointer
502 * to the vma inside the execobj so that we can use a direct lookup
503 * to find the right target VMA when doing relocations.
506 eb->flags[i] = entry->flags;
507 vma->exec_flags = &eb->flags[i];
510 * SNA is doing fancy tricks with compressing batch buffers, which leads
511 * to negative relocation deltas. Usually that works out ok since the
512 * relocate address is still positive, except when the batch is placed
513 * very low in the GTT. Ensure this doesn't happen.
515 * Note that actual hangs have only been observed on gen7, but for
516 * paranoia do it everywhere.
518 if (i == batch_idx) {
519 if (entry->relocation_count &&
520 !(eb->flags[i] & EXEC_OBJECT_PINNED))
521 eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS;
522 if (eb->reloc_cache.has_fence)
523 eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE;
529 if (eb_pin_vma(eb, entry, vma)) {
530 if (entry->offset != vma->node.start) {
531 entry->offset = vma->node.start | UPDATE;
532 eb->args->flags |= __EXEC_HAS_RELOC;
535 eb_unreserve_vma(vma, vma->exec_flags);
537 list_add_tail(&vma->exec_link, &eb->unbound);
538 if (drm_mm_node_allocated(&vma->node))
539 err = i915_vma_unbind(vma);
541 vma->exec_flags = NULL;
546 static inline int use_cpu_reloc(const struct reloc_cache *cache,
547 const struct drm_i915_gem_object *obj)
549 if (!i915_gem_object_has_struct_page(obj))
552 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
555 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
558 return (cache->has_llc ||
560 obj->cache_level != I915_CACHE_NONE);
563 static int eb_reserve_vma(const struct i915_execbuffer *eb,
564 struct i915_vma *vma)
566 struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
567 unsigned int exec_flags = *vma->exec_flags;
571 pin_flags = PIN_USER | PIN_NONBLOCK;
572 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
573 pin_flags |= PIN_GLOBAL;
576 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
577 * limit address to the first 4GBs for unflagged objects.
579 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
580 pin_flags |= PIN_ZONE_4G;
582 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
583 pin_flags |= PIN_MAPPABLE;
585 if (exec_flags & EXEC_OBJECT_PINNED) {
586 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
587 pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */
588 } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) {
589 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
592 err = i915_vma_pin(vma,
593 entry->pad_to_size, entry->alignment,
598 if (entry->offset != vma->node.start) {
599 entry->offset = vma->node.start | UPDATE;
600 eb->args->flags |= __EXEC_HAS_RELOC;
603 if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) {
604 err = i915_vma_pin_fence(vma);
611 exec_flags |= __EXEC_OBJECT_HAS_FENCE;
614 *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN;
615 GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags));
620 static int eb_reserve(struct i915_execbuffer *eb)
622 const unsigned int count = eb->buffer_count;
623 struct list_head last;
624 struct i915_vma *vma;
625 unsigned int i, pass;
629 * Attempt to pin all of the buffers into the GTT.
630 * This is done in 3 phases:
632 * 1a. Unbind all objects that do not match the GTT constraints for
633 * the execbuffer (fenceable, mappable, alignment etc).
634 * 1b. Increment pin count for already bound objects.
635 * 2. Bind new objects.
636 * 3. Decrement pin count.
638 * This avoid unnecessary unbinding of later objects in order to make
639 * room for the earlier objects *unless* we need to defragment.
645 list_for_each_entry(vma, &eb->unbound, exec_link) {
646 err = eb_reserve_vma(eb, vma);
653 /* Resort *all* the objects into priority order */
654 INIT_LIST_HEAD(&eb->unbound);
655 INIT_LIST_HEAD(&last);
656 for (i = 0; i < count; i++) {
657 unsigned int flags = eb->flags[i];
658 struct i915_vma *vma = eb->vma[i];
660 if (flags & EXEC_OBJECT_PINNED &&
661 flags & __EXEC_OBJECT_HAS_PIN)
664 eb_unreserve_vma(vma, &eb->flags[i]);
666 if (flags & EXEC_OBJECT_PINNED)
667 /* Pinned must have their slot */
668 list_add(&vma->exec_link, &eb->unbound);
669 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
670 /* Map require the lowest 256MiB (aperture) */
671 list_add_tail(&vma->exec_link, &eb->unbound);
672 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
673 /* Prioritise 4GiB region for restricted bo */
674 list_add(&vma->exec_link, &last);
676 list_add_tail(&vma->exec_link, &last);
678 list_splice_tail(&last, &eb->unbound);
685 /* Too fragmented, unbind everything and retry */
686 mutex_lock(&eb->context->vm->mutex);
687 err = i915_gem_evict_vm(eb->context->vm);
688 mutex_unlock(&eb->context->vm->mutex);
699 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
701 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
704 return eb->buffer_count - 1;
707 static int eb_select_context(struct i915_execbuffer *eb)
709 struct i915_gem_context *ctx;
711 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
715 eb->gem_context = ctx;
716 if (rcu_access_pointer(ctx->vm))
717 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
719 eb->context_flags = 0;
720 if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
721 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
726 static int eb_lookup_vmas(struct i915_execbuffer *eb)
728 struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
729 struct drm_i915_gem_object *obj;
730 unsigned int i, batch;
733 INIT_LIST_HEAD(&eb->relocs);
734 INIT_LIST_HEAD(&eb->unbound);
736 batch = eb_batch_index(eb);
738 mutex_lock(&eb->gem_context->mutex);
739 if (unlikely(i915_gem_context_is_closed(eb->gem_context))) {
744 for (i = 0; i < eb->buffer_count; i++) {
745 u32 handle = eb->exec[i].handle;
746 struct i915_lut_handle *lut;
747 struct i915_vma *vma;
749 vma = radix_tree_lookup(handles_vma, handle);
753 obj = i915_gem_object_lookup(eb->file, handle);
754 if (unlikely(!obj)) {
759 vma = i915_vma_instance(obj, eb->context->vm, NULL);
765 lut = i915_lut_handle_alloc();
766 if (unlikely(!lut)) {
771 err = radix_tree_insert(handles_vma, handle, vma);
773 i915_lut_handle_free(lut);
777 /* transfer ref to lut */
778 if (!atomic_fetch_inc(&vma->open_count))
779 i915_vma_reopen(vma);
780 lut->handle = handle;
781 lut->ctx = eb->gem_context;
783 i915_gem_object_lock(obj);
784 list_add(&lut->obj_link, &obj->lut_list);
785 i915_gem_object_unlock(obj);
788 err = eb_add_vma(eb, i, batch, vma);
792 GEM_BUG_ON(vma != eb->vma[i]);
793 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
794 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
795 eb_vma_misplaced(&eb->exec[i], vma, eb->flags[i]));
798 mutex_unlock(&eb->gem_context->mutex);
800 eb->args->flags |= __EXEC_VALIDATED;
801 return eb_reserve(eb);
804 i915_gem_object_put(obj);
808 mutex_unlock(&eb->gem_context->mutex);
812 static struct i915_vma *
813 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
815 if (eb->lut_size < 0) {
816 if (handle >= -eb->lut_size)
818 return eb->vma[handle];
820 struct hlist_head *head;
821 struct i915_vma *vma;
823 head = &eb->buckets[hash_32(handle, eb->lut_size)];
824 hlist_for_each_entry(vma, head, exec_node) {
825 if (vma->exec_handle == handle)
832 static void eb_release_vmas(const struct i915_execbuffer *eb)
834 const unsigned int count = eb->buffer_count;
837 for (i = 0; i < count; i++) {
838 struct i915_vma *vma = eb->vma[i];
839 unsigned int flags = eb->flags[i];
844 GEM_BUG_ON(vma->exec_flags != &eb->flags[i]);
845 vma->exec_flags = NULL;
848 if (flags & __EXEC_OBJECT_HAS_PIN)
849 __eb_unreserve_vma(vma, flags);
851 if (flags & __EXEC_OBJECT_HAS_REF)
856 static void eb_reset_vmas(const struct i915_execbuffer *eb)
859 if (eb->lut_size > 0)
860 memset(eb->buckets, 0,
861 sizeof(struct hlist_head) << eb->lut_size);
864 static void eb_destroy(const struct i915_execbuffer *eb)
866 GEM_BUG_ON(eb->reloc_cache.rq);
868 if (eb->lut_size > 0)
873 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
874 const struct i915_vma *target)
876 return gen8_canonical_addr((int)reloc->delta + target->node.start);
879 static void reloc_cache_init(struct reloc_cache *cache,
880 struct drm_i915_private *i915)
884 /* Must be a variable in the struct to allow GCC to unroll. */
885 cache->gen = INTEL_GEN(i915);
886 cache->has_llc = HAS_LLC(i915);
887 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
888 cache->has_fence = cache->gen < 4;
889 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
890 cache->node.flags = 0;
895 static inline void *unmask_page(unsigned long p)
897 return (void *)(uintptr_t)(p & PAGE_MASK);
900 static inline unsigned int unmask_flags(unsigned long p)
902 return p & ~PAGE_MASK;
905 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
907 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
909 struct drm_i915_private *i915 =
910 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
914 static void reloc_gpu_flush(struct reloc_cache *cache)
916 GEM_BUG_ON(cache->rq_size >= cache->rq->batch->obj->base.size / sizeof(u32));
917 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
919 __i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);
920 i915_gem_object_unpin_map(cache->rq->batch->obj);
922 intel_gt_chipset_flush(cache->rq->engine->gt);
924 i915_request_add(cache->rq);
928 static void reloc_cache_reset(struct reloc_cache *cache)
933 reloc_gpu_flush(cache);
938 vaddr = unmask_page(cache->vaddr);
939 if (cache->vaddr & KMAP) {
940 if (cache->vaddr & CLFLUSH_AFTER)
943 kunmap_atomic(vaddr);
944 i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm);
946 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
948 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
949 io_mapping_unmap_atomic((void __iomem *)vaddr);
951 if (drm_mm_node_allocated(&cache->node)) {
952 ggtt->vm.clear_range(&ggtt->vm,
955 mutex_lock(&ggtt->vm.mutex);
956 drm_mm_remove_node(&cache->node);
957 mutex_unlock(&ggtt->vm.mutex);
959 i915_vma_unpin((struct i915_vma *)cache->node.mm);
967 static void *reloc_kmap(struct drm_i915_gem_object *obj,
968 struct reloc_cache *cache,
974 kunmap_atomic(unmask_page(cache->vaddr));
976 unsigned int flushes;
979 err = i915_gem_object_prepare_write(obj, &flushes);
983 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
984 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
986 cache->vaddr = flushes | KMAP;
987 cache->node.mm = (void *)obj;
992 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
993 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
999 static void *reloc_iomap(struct drm_i915_gem_object *obj,
1000 struct reloc_cache *cache,
1003 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1004 unsigned long offset;
1008 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1009 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1011 struct i915_vma *vma;
1014 if (i915_gem_object_is_tiled(obj))
1015 return ERR_PTR(-EINVAL);
1017 if (use_cpu_reloc(cache, obj))
1020 i915_gem_object_lock(obj);
1021 err = i915_gem_object_set_to_gtt_domain(obj, true);
1022 i915_gem_object_unlock(obj);
1024 return ERR_PTR(err);
1026 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1028 PIN_NONBLOCK /* NOWARN */ |
1031 memset(&cache->node, 0, sizeof(cache->node));
1032 mutex_lock(&ggtt->vm.mutex);
1033 err = drm_mm_insert_node_in_range
1034 (&ggtt->vm.mm, &cache->node,
1035 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1036 0, ggtt->mappable_end,
1038 mutex_unlock(&ggtt->vm.mutex);
1039 if (err) /* no inactive aperture space, use cpu reloc */
1042 cache->node.start = vma->node.start;
1043 cache->node.mm = (void *)vma;
1047 offset = cache->node.start;
1048 if (drm_mm_node_allocated(&cache->node)) {
1049 ggtt->vm.insert_page(&ggtt->vm,
1050 i915_gem_object_get_dma_address(obj, page),
1051 offset, I915_CACHE_NONE, 0);
1053 offset += page << PAGE_SHIFT;
1056 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1059 cache->vaddr = (unsigned long)vaddr;
1064 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1065 struct reloc_cache *cache,
1070 if (cache->page == page) {
1071 vaddr = unmask_page(cache->vaddr);
1074 if ((cache->vaddr & KMAP) == 0)
1075 vaddr = reloc_iomap(obj, cache, page);
1077 vaddr = reloc_kmap(obj, cache, page);
1083 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1085 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1086 if (flushes & CLFLUSH_BEFORE) {
1094 * Writes to the same cacheline are serialised by the CPU
1095 * (including clflush). On the write path, we only require
1096 * that it hits memory in an orderly fashion and place
1097 * mb barriers at the start and end of the relocation phase
1098 * to ensure ordering of clflush wrt to the system.
1100 if (flushes & CLFLUSH_AFTER)
1106 static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
1108 struct drm_i915_gem_object *obj = vma->obj;
1113 if (obj->cache_dirty & ~obj->cache_coherent)
1114 i915_gem_clflush_object(obj, 0);
1115 obj->write_domain = 0;
1117 err = i915_request_await_object(rq, vma->obj, true);
1119 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1121 i915_vma_unlock(vma);
1126 static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1127 struct i915_vma *vma,
1130 struct reloc_cache *cache = &eb->reloc_cache;
1131 struct intel_engine_pool_node *pool;
1132 struct i915_request *rq;
1133 struct i915_vma *batch;
1137 pool = intel_engine_get_pool(eb->engine, PAGE_SIZE);
1139 return PTR_ERR(pool);
1141 cmd = i915_gem_object_pin_map(pool->obj,
1150 batch = i915_vma_instance(pool->obj, vma->vm, NULL);
1151 if (IS_ERR(batch)) {
1152 err = PTR_ERR(batch);
1156 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1160 rq = i915_request_create(eb->context);
1166 err = intel_engine_pool_mark_active(pool, rq);
1170 err = reloc_move_to_gpu(rq, vma);
1174 err = eb->engine->emit_bb_start(rq,
1175 batch->node.start, PAGE_SIZE,
1176 cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
1180 i915_vma_lock(batch);
1181 err = i915_request_await_object(rq, batch->obj, false);
1183 err = i915_vma_move_to_active(batch, rq, 0);
1184 i915_vma_unlock(batch);
1189 i915_vma_unpin(batch);
1192 cache->rq_cmd = cmd;
1195 /* Return with batch mapping (cmd) still pinned */
1199 i915_request_skip(rq, err);
1201 i915_request_add(rq);
1203 i915_vma_unpin(batch);
1205 i915_gem_object_unpin_map(pool->obj);
1207 intel_engine_pool_put(pool);
1211 static u32 *reloc_gpu(struct i915_execbuffer *eb,
1212 struct i915_vma *vma,
1215 struct reloc_cache *cache = &eb->reloc_cache;
1218 if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1))
1219 reloc_gpu_flush(cache);
1221 if (unlikely(!cache->rq)) {
1224 if (!intel_engine_can_store_dword(eb->engine))
1225 return ERR_PTR(-ENODEV);
1227 err = __reloc_gpu_alloc(eb, vma, len);
1229 return ERR_PTR(err);
1232 cmd = cache->rq_cmd + cache->rq_size;
1233 cache->rq_size += len;
1239 relocate_entry(struct i915_vma *vma,
1240 const struct drm_i915_gem_relocation_entry *reloc,
1241 struct i915_execbuffer *eb,
1242 const struct i915_vma *target)
1244 u64 offset = reloc->offset;
1245 u64 target_offset = relocation_target(reloc, target);
1246 bool wide = eb->reloc_cache.use_64bit_reloc;
1249 if (!eb->reloc_cache.vaddr &&
1250 (DBG_FORCE_RELOC == FORCE_GPU_RELOC ||
1251 !dma_resv_test_signaled_rcu(vma->resv, true))) {
1252 const unsigned int gen = eb->reloc_cache.gen;
1258 len = offset & 7 ? 8 : 5;
1264 batch = reloc_gpu(eb, vma, len);
1268 addr = gen8_canonical_addr(vma->node.start + offset);
1271 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1272 *batch++ = lower_32_bits(addr);
1273 *batch++ = upper_32_bits(addr);
1274 *batch++ = lower_32_bits(target_offset);
1276 addr = gen8_canonical_addr(addr + 4);
1278 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1279 *batch++ = lower_32_bits(addr);
1280 *batch++ = upper_32_bits(addr);
1281 *batch++ = upper_32_bits(target_offset);
1283 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1284 *batch++ = lower_32_bits(addr);
1285 *batch++ = upper_32_bits(addr);
1286 *batch++ = lower_32_bits(target_offset);
1287 *batch++ = upper_32_bits(target_offset);
1289 } else if (gen >= 6) {
1290 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1293 *batch++ = target_offset;
1294 } else if (gen >= 4) {
1295 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1298 *batch++ = target_offset;
1300 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1302 *batch++ = target_offset;
1309 vaddr = reloc_vaddr(vma->obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1311 return PTR_ERR(vaddr);
1313 clflush_write32(vaddr + offset_in_page(offset),
1314 lower_32_bits(target_offset),
1315 eb->reloc_cache.vaddr);
1318 offset += sizeof(u32);
1319 target_offset >>= 32;
1325 return target->node.start | UPDATE;
1329 eb_relocate_entry(struct i915_execbuffer *eb,
1330 struct i915_vma *vma,
1331 const struct drm_i915_gem_relocation_entry *reloc)
1333 struct i915_vma *target;
1336 /* we've already hold a reference to all valid objects */
1337 target = eb_get_vma(eb, reloc->target_handle);
1338 if (unlikely(!target))
1341 /* Validate that the target is in a valid r/w GPU domain */
1342 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1343 DRM_DEBUG("reloc with multiple write domains: "
1344 "target %d offset %d "
1345 "read %08x write %08x",
1346 reloc->target_handle,
1347 (int) reloc->offset,
1348 reloc->read_domains,
1349 reloc->write_domain);
1352 if (unlikely((reloc->write_domain | reloc->read_domains)
1353 & ~I915_GEM_GPU_DOMAINS)) {
1354 DRM_DEBUG("reloc with read/write non-GPU domains: "
1355 "target %d offset %d "
1356 "read %08x write %08x",
1357 reloc->target_handle,
1358 (int) reloc->offset,
1359 reloc->read_domains,
1360 reloc->write_domain);
1364 if (reloc->write_domain) {
1365 *target->exec_flags |= EXEC_OBJECT_WRITE;
1368 * Sandybridge PPGTT errata: We need a global gtt mapping
1369 * for MI and pipe_control writes because the gpu doesn't
1370 * properly redirect them through the ppgtt for non_secure
1373 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1374 IS_GEN(eb->i915, 6)) {
1375 err = i915_vma_bind(target, target->obj->cache_level,
1378 "Unexpected failure to bind target VMA!"))
1384 * If the relocation already has the right value in it, no
1385 * more work needs to be done.
1387 if (!DBG_FORCE_RELOC &&
1388 gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1391 /* Check that the relocation address is valid... */
1392 if (unlikely(reloc->offset >
1393 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1394 DRM_DEBUG("Relocation beyond object bounds: "
1395 "target %d offset %d size %d.\n",
1396 reloc->target_handle,
1401 if (unlikely(reloc->offset & 3)) {
1402 DRM_DEBUG("Relocation not 4-byte aligned: "
1403 "target %d offset %d.\n",
1404 reloc->target_handle,
1405 (int)reloc->offset);
1410 * If we write into the object, we need to force the synchronisation
1411 * barrier, either with an asynchronous clflush or if we executed the
1412 * patching using the GPU (though that should be serialised by the
1413 * timeline). To be completely sure, and since we are required to
1414 * do relocations we are already stalling, disable the user's opt
1415 * out of our synchronisation.
1417 *vma->exec_flags &= ~EXEC_OBJECT_ASYNC;
1419 /* and update the user's relocation entry */
1420 return relocate_entry(vma, reloc, eb, target);
1423 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1425 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1426 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1427 struct drm_i915_gem_relocation_entry __user *urelocs;
1428 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1429 unsigned int remain;
1431 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1432 remain = entry->relocation_count;
1433 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1437 * We must check that the entire relocation array is safe
1438 * to read. However, if the array is not writable the user loses
1439 * the updated relocation values.
1441 if (unlikely(!access_ok(urelocs, remain*sizeof(*urelocs))))
1445 struct drm_i915_gem_relocation_entry *r = stack;
1446 unsigned int count =
1447 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1448 unsigned int copied;
1451 * This is the fast path and we cannot handle a pagefault
1452 * whilst holding the struct mutex lest the user pass in the
1453 * relocations contained within a mmaped bo. For in such a case
1454 * we, the page fault handler would call i915_gem_fault() and
1455 * we would try to acquire the struct mutex again. Obviously
1456 * this is bad and so lockdep complains vehemently.
1458 pagefault_disable();
1459 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1461 if (unlikely(copied)) {
1468 u64 offset = eb_relocate_entry(eb, vma, r);
1470 if (likely(offset == 0)) {
1471 } else if ((s64)offset < 0) {
1472 remain = (int)offset;
1476 * Note that reporting an error now
1477 * leaves everything in an inconsistent
1478 * state as we have *already* changed
1479 * the relocation value inside the
1480 * object. As we have not changed the
1481 * reloc.presumed_offset or will not
1482 * change the execobject.offset, on the
1483 * call we may not rewrite the value
1484 * inside the object, leaving it
1485 * dangling and causing a GPU hang. Unless
1486 * userspace dynamically rebuilds the
1487 * relocations on each execbuf rather than
1488 * presume a static tree.
1490 * We did previously check if the relocations
1491 * were writable (access_ok), an error now
1492 * would be a strange race with mprotect,
1493 * having already demonstrated that we
1494 * can read from this userspace address.
1496 offset = gen8_canonical_addr(offset & ~UPDATE);
1497 if (unlikely(__put_user(offset, &urelocs[r-stack].presumed_offset))) {
1502 } while (r++, --count);
1503 urelocs += ARRAY_SIZE(stack);
1506 reloc_cache_reset(&eb->reloc_cache);
1511 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1513 const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma);
1514 struct drm_i915_gem_relocation_entry *relocs =
1515 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1519 for (i = 0; i < entry->relocation_count; i++) {
1520 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1522 if ((s64)offset < 0) {
1529 reloc_cache_reset(&eb->reloc_cache);
1533 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1535 const char __user *addr, *end;
1537 char __maybe_unused c;
1539 size = entry->relocation_count;
1543 if (size > N_RELOC(ULONG_MAX))
1546 addr = u64_to_user_ptr(entry->relocs_ptr);
1547 size *= sizeof(struct drm_i915_gem_relocation_entry);
1548 if (!access_ok(addr, size))
1552 for (; addr < end; addr += PAGE_SIZE) {
1553 int err = __get_user(c, addr);
1557 return __get_user(c, end - 1);
1560 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1562 struct drm_i915_gem_relocation_entry *relocs;
1563 const unsigned int count = eb->buffer_count;
1567 for (i = 0; i < count; i++) {
1568 const unsigned int nreloc = eb->exec[i].relocation_count;
1569 struct drm_i915_gem_relocation_entry __user *urelocs;
1571 unsigned long copied;
1576 err = check_relocations(&eb->exec[i]);
1580 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1581 size = nreloc * sizeof(*relocs);
1583 relocs = kvmalloc_array(size, 1, GFP_KERNEL);
1589 /* copy_from_user is limited to < 4GiB */
1593 min_t(u64, BIT_ULL(31), size - copied);
1595 if (__copy_from_user((char *)relocs + copied,
1596 (char __user *)urelocs + copied,
1601 } while (copied < size);
1604 * As we do not update the known relocation offsets after
1605 * relocating (due to the complexities in lock handling),
1606 * we need to mark them as invalid now so that we force the
1607 * relocation processing next time. Just in case the target
1608 * object is evicted and then rebound into its old
1609 * presumed_offset before the next execbuffer - if that
1610 * happened we would make the mistake of assuming that the
1611 * relocations were valid.
1613 if (!user_access_begin(urelocs, size))
1616 for (copied = 0; copied < nreloc; copied++)
1618 &urelocs[copied].presumed_offset,
1622 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1634 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1635 if (eb->exec[i].relocation_count)
1641 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1643 const unsigned int count = eb->buffer_count;
1646 if (unlikely(i915_modparams.prefault_disable))
1649 for (i = 0; i < count; i++) {
1652 err = check_relocations(&eb->exec[i]);
1660 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1662 struct drm_device *dev = &eb->i915->drm;
1663 bool have_copy = false;
1664 struct i915_vma *vma;
1668 if (signal_pending(current)) {
1673 /* We may process another execbuffer during the unlock... */
1675 mutex_unlock(&dev->struct_mutex);
1678 * We take 3 passes through the slowpatch.
1680 * 1 - we try to just prefault all the user relocation entries and
1681 * then attempt to reuse the atomic pagefault disabled fast path again.
1683 * 2 - we copy the user entries to a local buffer here outside of the
1684 * local and allow ourselves to wait upon any rendering before
1687 * 3 - we already have a local copy of the relocation entries, but
1688 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1691 err = eb_prefault_relocations(eb);
1692 } else if (!have_copy) {
1693 err = eb_copy_relocations(eb);
1694 have_copy = err == 0;
1700 mutex_lock(&dev->struct_mutex);
1704 /* A frequent cause for EAGAIN are currently unavailable client pages */
1705 flush_workqueue(eb->i915->mm.userptr_wq);
1707 err = i915_mutex_lock_interruptible(dev);
1709 mutex_lock(&dev->struct_mutex);
1713 /* reacquire the objects */
1714 err = eb_lookup_vmas(eb);
1718 GEM_BUG_ON(!eb->batch);
1720 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1722 pagefault_disable();
1723 err = eb_relocate_vma(eb, vma);
1728 err = eb_relocate_vma_slow(eb, vma);
1735 * Leave the user relocations as are, this is the painfully slow path,
1736 * and we want to avoid the complication of dropping the lock whilst
1737 * having buffers reserved in the aperture and so causing spurious
1738 * ENOSPC for random operations.
1747 const unsigned int count = eb->buffer_count;
1750 for (i = 0; i < count; i++) {
1751 const struct drm_i915_gem_exec_object2 *entry =
1753 struct drm_i915_gem_relocation_entry *relocs;
1755 if (!entry->relocation_count)
1758 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1766 static int eb_relocate(struct i915_execbuffer *eb)
1768 if (eb_lookup_vmas(eb))
1771 /* The objects are in their final locations, apply the relocations. */
1772 if (eb->args->flags & __EXEC_HAS_RELOC) {
1773 struct i915_vma *vma;
1775 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1776 if (eb_relocate_vma(eb, vma))
1784 return eb_relocate_slow(eb);
1787 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1789 const unsigned int count = eb->buffer_count;
1790 struct ww_acquire_ctx acquire;
1794 ww_acquire_init(&acquire, &reservation_ww_class);
1796 for (i = 0; i < count; i++) {
1797 struct i915_vma *vma = eb->vma[i];
1799 err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire);
1803 GEM_BUG_ON(err == -EALREADY); /* No duplicate vma */
1805 if (err == -EDEADLK) {
1810 ww_mutex_unlock(&eb->vma[j]->resv->lock);
1812 swap(eb->flags[i], eb->flags[j]);
1813 swap(eb->vma[i], eb->vma[j]);
1814 eb->vma[i]->exec_flags = &eb->flags[i];
1816 GEM_BUG_ON(vma != eb->vma[0]);
1817 vma->exec_flags = &eb->flags[0];
1819 err = ww_mutex_lock_slow_interruptible(&vma->resv->lock,
1825 ww_acquire_done(&acquire);
1828 unsigned int flags = eb->flags[i];
1829 struct i915_vma *vma = eb->vma[i];
1830 struct drm_i915_gem_object *obj = vma->obj;
1832 assert_vma_held(vma);
1834 if (flags & EXEC_OBJECT_CAPTURE) {
1835 struct i915_capture_list *capture;
1837 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1839 capture->next = eb->request->capture_list;
1841 eb->request->capture_list = capture;
1846 * If the GPU is not _reading_ through the CPU cache, we need
1847 * to make sure that any writes (both previous GPU writes from
1848 * before a change in snooping levels and normal CPU writes)
1849 * caught in that cache are flushed to main memory.
1852 * obj->cache_dirty &&
1853 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1854 * but gcc's optimiser doesn't handle that as well and emits
1855 * two jumps instead of one. Maybe one day...
1857 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1858 if (i915_gem_clflush_object(obj, 0))
1859 flags &= ~EXEC_OBJECT_ASYNC;
1862 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
1863 err = i915_request_await_object
1864 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1868 err = i915_vma_move_to_active(vma, eb->request, flags);
1870 i915_vma_unlock(vma);
1872 __eb_unreserve_vma(vma, flags);
1873 vma->exec_flags = NULL;
1875 if (unlikely(flags & __EXEC_OBJECT_HAS_REF))
1878 ww_acquire_fini(&acquire);
1885 /* Unconditionally flush any chipset caches (for streaming writes). */
1886 intel_gt_chipset_flush(eb->engine->gt);
1890 i915_request_skip(eb->request, err);
1894 static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1896 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1899 /* Kernel clipping was a DRI1 misfeature */
1900 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1901 if (exec->num_cliprects || exec->cliprects_ptr)
1905 if (exec->DR4 == 0xffffffff) {
1906 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1909 if (exec->DR1 || exec->DR4)
1912 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1918 static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
1923 if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) {
1924 DRM_DEBUG("sol reset is gen7/rcs only\n");
1928 cs = intel_ring_begin(rq, 4 * 2 + 2);
1932 *cs++ = MI_LOAD_REGISTER_IMM(4);
1933 for (i = 0; i < 4; i++) {
1934 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1938 intel_ring_advance(rq, cs);
1943 static struct i915_vma *
1944 shadow_batch_pin(struct drm_i915_gem_object *obj,
1945 struct i915_address_space *vm,
1948 struct i915_vma *vma;
1951 vma = i915_vma_instance(obj, vm, NULL);
1955 err = i915_vma_pin(vma, 0, 0, flags);
1957 return ERR_PTR(err);
1962 struct eb_parse_work {
1963 struct dma_fence_work base;
1964 struct intel_engine_cs *engine;
1965 struct i915_vma *batch;
1966 struct i915_vma *shadow;
1967 struct i915_vma *trampoline;
1968 unsigned int batch_offset;
1969 unsigned int batch_length;
1972 static int __eb_parse(struct dma_fence_work *work)
1974 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
1976 return intel_engine_cmd_parser(pw->engine,
1984 static void __eb_parse_release(struct dma_fence_work *work)
1986 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
1989 i915_active_release(&pw->trampoline->active);
1990 i915_active_release(&pw->shadow->active);
1991 i915_active_release(&pw->batch->active);
1994 static const struct dma_fence_work_ops eb_parse_ops = {
1997 .release = __eb_parse_release,
2000 static int eb_parse_pipeline(struct i915_execbuffer *eb,
2001 struct i915_vma *shadow,
2002 struct i915_vma *trampoline)
2004 struct eb_parse_work *pw;
2007 pw = kzalloc(sizeof(*pw), GFP_KERNEL);
2011 err = i915_active_acquire(&eb->batch->active);
2015 err = i915_active_acquire(&shadow->active);
2020 err = i915_active_acquire(&trampoline->active);
2025 dma_fence_work_init(&pw->base, &eb_parse_ops);
2027 pw->engine = eb->engine;
2028 pw->batch = eb->batch;
2029 pw->batch_offset = eb->batch_start_offset;
2030 pw->batch_length = eb->batch_len;
2031 pw->shadow = shadow;
2032 pw->trampoline = trampoline;
2034 err = dma_resv_lock_interruptible(pw->batch->resv, NULL);
2036 goto err_trampoline;
2038 err = dma_resv_reserve_shared(pw->batch->resv, 1);
2040 goto err_batch_unlock;
2042 /* Wait for all writes (and relocs) into the batch to complete */
2043 err = i915_sw_fence_await_reservation(&pw->base.chain,
2044 pw->batch->resv, NULL, false,
2047 goto err_batch_unlock;
2049 /* Keep the batch alive and unwritten as we parse */
2050 dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma);
2052 dma_resv_unlock(pw->batch->resv);
2054 /* Force execution to wait for completion of the parser */
2055 dma_resv_lock(shadow->resv, NULL);
2056 dma_resv_add_excl_fence(shadow->resv, &pw->base.dma);
2057 dma_resv_unlock(shadow->resv);
2059 dma_fence_work_commit(&pw->base);
2063 dma_resv_unlock(pw->batch->resv);
2066 i915_active_release(&trampoline->active);
2068 i915_active_release(&shadow->active);
2070 i915_active_release(&eb->batch->active);
2076 static int eb_parse(struct i915_execbuffer *eb)
2078 struct intel_engine_pool_node *pool;
2079 struct i915_vma *shadow, *trampoline;
2083 if (!eb_use_cmdparser(eb))
2086 len = eb->batch_len;
2087 if (!CMDPARSER_USES_GGTT(eb->i915)) {
2089 * ppGTT backed shadow buffers must be mapped RO, to prevent
2090 * post-scan tampering
2092 if (!eb->context->vm->has_read_only) {
2093 DRM_DEBUG("Cannot prevent post-scan tampering without RO capable vm\n");
2097 len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2100 pool = intel_engine_get_pool(eb->engine, len);
2102 return PTR_ERR(pool);
2104 shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER);
2105 if (IS_ERR(shadow)) {
2106 err = PTR_ERR(shadow);
2109 i915_gem_object_set_readonly(shadow->obj);
2112 if (CMDPARSER_USES_GGTT(eb->i915)) {
2113 trampoline = shadow;
2115 shadow = shadow_batch_pin(pool->obj,
2116 &eb->engine->gt->ggtt->vm,
2118 if (IS_ERR(shadow)) {
2119 err = PTR_ERR(shadow);
2120 shadow = trampoline;
2124 eb->batch_flags |= I915_DISPATCH_SECURE;
2127 err = eb_parse_pipeline(eb, shadow, trampoline);
2129 goto err_trampoline;
2131 eb->vma[eb->buffer_count] = i915_vma_get(shadow);
2132 eb->flags[eb->buffer_count] =
2133 __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF;
2134 shadow->exec_flags = &eb->flags[eb->buffer_count];
2137 eb->trampoline = trampoline;
2138 eb->batch_start_offset = 0;
2141 shadow->private = pool;
2146 i915_vma_unpin(trampoline);
2148 i915_vma_unpin(shadow);
2150 intel_engine_pool_put(pool);
2155 add_to_client(struct i915_request *rq, struct drm_file *file)
2157 struct drm_i915_file_private *file_priv = file->driver_priv;
2159 rq->file_priv = file_priv;
2161 spin_lock(&file_priv->mm.lock);
2162 list_add_tail(&rq->client_link, &file_priv->mm.request_list);
2163 spin_unlock(&file_priv->mm.lock);
2166 static int eb_submit(struct i915_execbuffer *eb)
2170 err = eb_move_to_gpu(eb);
2174 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2175 err = i915_reset_gen7_sol_offsets(eb->request);
2181 * After we completed waiting for other engines (using HW semaphores)
2182 * then we can signal that this request/batch is ready to run. This
2183 * allows us to determine if the batch is still waiting on the GPU
2184 * or actually running by checking the breadcrumb.
2186 if (eb->engine->emit_init_breadcrumb) {
2187 err = eb->engine->emit_init_breadcrumb(eb->request);
2192 err = eb->engine->emit_bb_start(eb->request,
2193 eb->batch->node.start +
2194 eb->batch_start_offset,
2200 if (eb->trampoline) {
2201 GEM_BUG_ON(eb->batch_start_offset);
2202 err = eb->engine->emit_bb_start(eb->request,
2203 eb->trampoline->node.start +
2210 if (intel_context_nopreempt(eb->context))
2211 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &eb->request->fence.flags);
2216 static int num_vcs_engines(const struct drm_i915_private *i915)
2218 return hweight64(INTEL_INFO(i915)->engine_mask &
2219 GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0));
2223 * Find one BSD ring to dispatch the corresponding BSD command.
2224 * The engine index is returned.
2227 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2228 struct drm_file *file)
2230 struct drm_i915_file_private *file_priv = file->driver_priv;
2232 /* Check whether the file_priv has already selected one ring. */
2233 if ((int)file_priv->bsd_engine < 0)
2234 file_priv->bsd_engine =
2235 get_random_int() % num_vcs_engines(dev_priv);
2237 return file_priv->bsd_engine;
2240 static const enum intel_engine_id user_ring_map[] = {
2241 [I915_EXEC_DEFAULT] = RCS0,
2242 [I915_EXEC_RENDER] = RCS0,
2243 [I915_EXEC_BLT] = BCS0,
2244 [I915_EXEC_BSD] = VCS0,
2245 [I915_EXEC_VEBOX] = VECS0
2248 static struct i915_request *eb_throttle(struct intel_context *ce)
2250 struct intel_ring *ring = ce->ring;
2251 struct intel_timeline *tl = ce->timeline;
2252 struct i915_request *rq;
2255 * Completely unscientific finger-in-the-air estimates for suitable
2256 * maximum user request size (to avoid blocking) and then backoff.
2258 if (intel_ring_update_space(ring) >= PAGE_SIZE)
2262 * Find a request that after waiting upon, there will be at least half
2263 * the ring available. The hysteresis allows us to compete for the
2264 * shared ring and should mean that we sleep less often prior to
2265 * claiming our resources, but not so long that the ring completely
2266 * drains before we can submit our next request.
2268 list_for_each_entry(rq, &tl->requests, link) {
2269 if (rq->ring != ring)
2272 if (__intel_ring_space(rq->postfix,
2273 ring->emit, ring->size) > ring->size / 2)
2276 if (&rq->link == &tl->requests)
2277 return NULL; /* weird, we will check again later for real */
2279 return i915_request_get(rq);
2282 static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce)
2284 struct intel_timeline *tl;
2285 struct i915_request *rq;
2289 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2290 * EIO if the GPU is already wedged.
2292 err = intel_gt_terminally_wedged(ce->engine->gt);
2296 if (unlikely(intel_context_is_banned(ce)))
2300 * Pinning the contexts may generate requests in order to acquire
2301 * GGTT space, so do this first before we reserve a seqno for
2304 err = intel_context_pin(ce);
2309 * Take a local wakeref for preparing to dispatch the execbuf as
2310 * we expect to access the hardware fairly frequently in the
2311 * process, and require the engine to be kept awake between accesses.
2312 * Upon dispatch, we acquire another prolonged wakeref that we hold
2313 * until the timeline is idle, which in turn releases the wakeref
2314 * taken on the engine, and the parent device.
2316 tl = intel_context_timeline_lock(ce);
2322 intel_context_enter(ce);
2323 rq = eb_throttle(ce);
2325 intel_context_timeline_unlock(tl);
2328 if (i915_request_wait(rq,
2329 I915_WAIT_INTERRUPTIBLE,
2330 MAX_SCHEDULE_TIMEOUT) < 0) {
2331 i915_request_put(rq);
2336 i915_request_put(rq);
2339 eb->engine = ce->engine;
2344 mutex_lock(&tl->mutex);
2345 intel_context_exit(ce);
2346 intel_context_timeline_unlock(tl);
2348 intel_context_unpin(ce);
2352 static void eb_unpin_engine(struct i915_execbuffer *eb)
2354 struct intel_context *ce = eb->context;
2355 struct intel_timeline *tl = ce->timeline;
2357 mutex_lock(&tl->mutex);
2358 intel_context_exit(ce);
2359 mutex_unlock(&tl->mutex);
2361 intel_context_unpin(ce);
2365 eb_select_legacy_ring(struct i915_execbuffer *eb,
2366 struct drm_file *file,
2367 struct drm_i915_gem_execbuffer2 *args)
2369 struct drm_i915_private *i915 = eb->i915;
2370 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2372 if (user_ring_id != I915_EXEC_BSD &&
2373 (args->flags & I915_EXEC_BSD_MASK)) {
2374 DRM_DEBUG("execbuf with non bsd ring but with invalid "
2375 "bsd dispatch flags: %d\n", (int)(args->flags));
2379 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2380 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2382 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2383 bsd_idx = gen8_dispatch_bsd_engine(i915, file);
2384 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2385 bsd_idx <= I915_EXEC_BSD_RING2) {
2386 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2389 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
2394 return _VCS(bsd_idx);
2397 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2398 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
2402 return user_ring_map[user_ring_id];
2406 eb_pin_engine(struct i915_execbuffer *eb,
2407 struct drm_file *file,
2408 struct drm_i915_gem_execbuffer2 *args)
2410 struct intel_context *ce;
2414 if (i915_gem_context_user_engines(eb->gem_context))
2415 idx = args->flags & I915_EXEC_RING_MASK;
2417 idx = eb_select_legacy_ring(eb, file, args);
2419 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2423 err = __eb_pin_engine(eb, ce);
2424 intel_context_put(ce);
2430 __free_fence_array(struct drm_syncobj **fences, unsigned int n)
2433 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2437 static struct drm_syncobj **
2438 get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2439 struct drm_file *file)
2441 const unsigned long nfences = args->num_cliprects;
2442 struct drm_i915_gem_exec_fence __user *user;
2443 struct drm_syncobj **fences;
2447 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2450 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2451 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2452 if (nfences > min_t(unsigned long,
2453 ULONG_MAX / sizeof(*user),
2454 SIZE_MAX / sizeof(*fences)))
2455 return ERR_PTR(-EINVAL);
2457 user = u64_to_user_ptr(args->cliprects_ptr);
2458 if (!access_ok(user, nfences * sizeof(*user)))
2459 return ERR_PTR(-EFAULT);
2461 fences = kvmalloc_array(nfences, sizeof(*fences),
2462 __GFP_NOWARN | GFP_KERNEL);
2464 return ERR_PTR(-ENOMEM);
2466 for (n = 0; n < nfences; n++) {
2467 struct drm_i915_gem_exec_fence fence;
2468 struct drm_syncobj *syncobj;
2470 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2475 if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
2480 syncobj = drm_syncobj_find(file, fence.handle);
2482 DRM_DEBUG("Invalid syncobj handle provided\n");
2487 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2488 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2490 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2496 __free_fence_array(fences, n);
2497 return ERR_PTR(err);
2501 put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2502 struct drm_syncobj **fences)
2505 __free_fence_array(fences, args->num_cliprects);
2509 await_fence_array(struct i915_execbuffer *eb,
2510 struct drm_syncobj **fences)
2512 const unsigned int nfences = eb->args->num_cliprects;
2516 for (n = 0; n < nfences; n++) {
2517 struct drm_syncobj *syncobj;
2518 struct dma_fence *fence;
2521 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2522 if (!(flags & I915_EXEC_FENCE_WAIT))
2525 fence = drm_syncobj_fence_get(syncobj);
2529 err = i915_request_await_dma_fence(eb->request, fence);
2530 dma_fence_put(fence);
2539 signal_fence_array(struct i915_execbuffer *eb,
2540 struct drm_syncobj **fences)
2542 const unsigned int nfences = eb->args->num_cliprects;
2543 struct dma_fence * const fence = &eb->request->fence;
2546 for (n = 0; n < nfences; n++) {
2547 struct drm_syncobj *syncobj;
2550 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2551 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2554 drm_syncobj_replace_fence(syncobj, fence);
2559 i915_gem_do_execbuffer(struct drm_device *dev,
2560 struct drm_file *file,
2561 struct drm_i915_gem_execbuffer2 *args,
2562 struct drm_i915_gem_exec_object2 *exec,
2563 struct drm_syncobj **fences)
2565 struct drm_i915_private *i915 = to_i915(dev);
2566 struct i915_execbuffer eb;
2567 struct dma_fence *in_fence = NULL;
2568 struct dma_fence *exec_fence = NULL;
2569 struct sync_file *out_fence = NULL;
2570 int out_fence_fd = -1;
2573 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
2574 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2575 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2580 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2581 args->flags |= __EXEC_HAS_RELOC;
2584 eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1);
2586 eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
2588 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2589 reloc_cache_init(&eb.reloc_cache, eb.i915);
2591 eb.buffer_count = args->buffer_count;
2592 eb.batch_start_offset = args->batch_start_offset;
2593 eb.batch_len = args->batch_len;
2594 eb.trampoline = NULL;
2597 if (args->flags & I915_EXEC_SECURE) {
2598 if (INTEL_GEN(i915) >= 11)
2601 /* Return -EPERM to trigger fallback code on old binaries. */
2602 if (!HAS_SECURE_BATCHES(i915))
2605 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2608 eb.batch_flags |= I915_DISPATCH_SECURE;
2610 if (args->flags & I915_EXEC_IS_PINNED)
2611 eb.batch_flags |= I915_DISPATCH_PINNED;
2613 if (args->flags & I915_EXEC_FENCE_IN) {
2614 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2619 if (args->flags & I915_EXEC_FENCE_SUBMIT) {
2625 exec_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2632 if (args->flags & I915_EXEC_FENCE_OUT) {
2633 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2634 if (out_fence_fd < 0) {
2636 goto err_exec_fence;
2640 err = eb_create(&eb);
2644 GEM_BUG_ON(!eb.lut_size);
2646 err = eb_select_context(&eb);
2650 err = eb_pin_engine(&eb, file, args);
2654 err = i915_mutex_lock_interruptible(dev);
2658 err = eb_relocate(&eb);
2661 * If the user expects the execobject.offset and
2662 * reloc.presumed_offset to be an exact match,
2663 * as for using NO_RELOC, then we cannot update
2664 * the execobject.offset until we have completed
2667 args->flags &= ~__EXEC_HAS_RELOC;
2671 if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) {
2672 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
2676 if (eb.batch_start_offset > eb.batch->size ||
2677 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
2678 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
2683 if (eb.batch_len == 0)
2684 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2686 err = eb_parse(&eb);
2691 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2692 * batch" bit. Hence we need to pin secure batches into the global gtt.
2693 * hsw should have this fixed, but bdw mucks it up again. */
2694 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2695 struct i915_vma *vma;
2698 * So on first glance it looks freaky that we pin the batch here
2699 * outside of the reservation loop. But:
2700 * - The batch is already pinned into the relevant ppgtt, so we
2701 * already have the backing storage fully allocated.
2702 * - No other BO uses the global gtt (well contexts, but meh),
2703 * so we don't really have issues with multiple objects not
2704 * fitting due to fragmentation.
2705 * So this is actually safe.
2707 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2716 /* All GPU relocation batches must be submitted prior to the user rq */
2717 GEM_BUG_ON(eb.reloc_cache.rq);
2719 /* Allocate a request for this batch buffer nice and early. */
2720 eb.request = i915_request_create(eb.context);
2721 if (IS_ERR(eb.request)) {
2722 err = PTR_ERR(eb.request);
2723 goto err_batch_unpin;
2727 err = i915_request_await_dma_fence(eb.request, in_fence);
2733 err = i915_request_await_execution(eb.request, exec_fence,
2734 eb.engine->bond_execute);
2740 err = await_fence_array(&eb, fences);
2745 if (out_fence_fd != -1) {
2746 out_fence = sync_file_create(&eb.request->fence);
2754 * Whilst this request exists, batch_obj will be on the
2755 * active_list, and so will hold the active reference. Only when this
2756 * request is retired will the the batch_obj be moved onto the
2757 * inactive_list and lose its active reference. Hence we do not need
2758 * to explicitly hold another reference here.
2760 eb.request->batch = eb.batch;
2761 if (eb.batch->private)
2762 intel_engine_pool_mark_active(eb.batch->private, eb.request);
2764 trace_i915_request_queue(eb.request, eb.batch_flags);
2765 err = eb_submit(&eb);
2767 add_to_client(eb.request, file);
2768 i915_request_get(eb.request);
2769 i915_request_add(eb.request);
2772 signal_fence_array(&eb, fences);
2776 fd_install(out_fence_fd, out_fence->file);
2777 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
2778 args->rsvd2 |= (u64)out_fence_fd << 32;
2781 fput(out_fence->file);
2784 i915_request_put(eb.request);
2787 if (eb.batch_flags & I915_DISPATCH_SECURE)
2788 i915_vma_unpin(eb.batch);
2789 if (eb.batch->private)
2790 intel_engine_pool_put(eb.batch->private);
2793 eb_release_vmas(&eb);
2795 i915_vma_unpin(eb.trampoline);
2796 mutex_unlock(&dev->struct_mutex);
2798 eb_unpin_engine(&eb);
2800 i915_gem_context_put(eb.gem_context);
2804 if (out_fence_fd != -1)
2805 put_unused_fd(out_fence_fd);
2807 dma_fence_put(exec_fence);
2809 dma_fence_put(in_fence);
2813 static size_t eb_element_size(void)
2815 return (sizeof(struct drm_i915_gem_exec_object2) +
2816 sizeof(struct i915_vma *) +
2817 sizeof(unsigned int));
2820 static bool check_buffer_count(size_t count)
2822 const size_t sz = eb_element_size();
2825 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
2826 * array size (see eb_create()). Otherwise, we can accept an array as
2827 * large as can be addressed (though use large arrays at your peril)!
2830 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
2834 * Legacy execbuffer just creates an exec2 list from the original exec object
2835 * list array and passes it to the real function.
2838 i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2839 struct drm_file *file)
2841 struct drm_i915_gem_execbuffer *args = data;
2842 struct drm_i915_gem_execbuffer2 exec2;
2843 struct drm_i915_gem_exec_object *exec_list = NULL;
2844 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2845 const size_t count = args->buffer_count;
2849 if (!check_buffer_count(count)) {
2850 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2854 exec2.buffers_ptr = args->buffers_ptr;
2855 exec2.buffer_count = args->buffer_count;
2856 exec2.batch_start_offset = args->batch_start_offset;
2857 exec2.batch_len = args->batch_len;
2858 exec2.DR1 = args->DR1;
2859 exec2.DR4 = args->DR4;
2860 exec2.num_cliprects = args->num_cliprects;
2861 exec2.cliprects_ptr = args->cliprects_ptr;
2862 exec2.flags = I915_EXEC_RENDER;
2863 i915_execbuffer2_set_context_id(exec2, 0);
2865 err = i915_gem_check_execbuffer(&exec2);
2869 /* Copy in the exec list from userland */
2870 exec_list = kvmalloc_array(count, sizeof(*exec_list),
2871 __GFP_NOWARN | GFP_KERNEL);
2872 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2873 __GFP_NOWARN | GFP_KERNEL);
2874 if (exec_list == NULL || exec2_list == NULL) {
2875 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2876 args->buffer_count);
2881 err = copy_from_user(exec_list,
2882 u64_to_user_ptr(args->buffers_ptr),
2883 sizeof(*exec_list) * count);
2885 DRM_DEBUG("copy %d exec entries failed %d\n",
2886 args->buffer_count, err);
2892 for (i = 0; i < args->buffer_count; i++) {
2893 exec2_list[i].handle = exec_list[i].handle;
2894 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2895 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2896 exec2_list[i].alignment = exec_list[i].alignment;
2897 exec2_list[i].offset = exec_list[i].offset;
2898 if (INTEL_GEN(to_i915(dev)) < 4)
2899 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2901 exec2_list[i].flags = 0;
2904 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2905 if (exec2.flags & __EXEC_HAS_RELOC) {
2906 struct drm_i915_gem_exec_object __user *user_exec_list =
2907 u64_to_user_ptr(args->buffers_ptr);
2909 /* Copy the new buffer offsets back to the user's exec list. */
2910 for (i = 0; i < args->buffer_count; i++) {
2911 if (!(exec2_list[i].offset & UPDATE))
2914 exec2_list[i].offset =
2915 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2916 exec2_list[i].offset &= PIN_OFFSET_MASK;
2917 if (__copy_to_user(&user_exec_list[i].offset,
2918 &exec2_list[i].offset,
2919 sizeof(user_exec_list[i].offset)))
2930 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2931 struct drm_file *file)
2933 struct drm_i915_gem_execbuffer2 *args = data;
2934 struct drm_i915_gem_exec_object2 *exec2_list;
2935 struct drm_syncobj **fences = NULL;
2936 const size_t count = args->buffer_count;
2939 if (!check_buffer_count(count)) {
2940 DRM_DEBUG("execbuf2 with %zd buffers\n", count);
2944 err = i915_gem_check_execbuffer(args);
2948 /* Allocate an extra slot for use by the command parser */
2949 exec2_list = kvmalloc_array(count + 1, eb_element_size(),
2950 __GFP_NOWARN | GFP_KERNEL);
2951 if (exec2_list == NULL) {
2952 DRM_DEBUG("Failed to allocate exec list for %zd buffers\n",
2956 if (copy_from_user(exec2_list,
2957 u64_to_user_ptr(args->buffers_ptr),
2958 sizeof(*exec2_list) * count)) {
2959 DRM_DEBUG("copy %zd exec entries failed\n", count);
2964 if (args->flags & I915_EXEC_FENCE_ARRAY) {
2965 fences = get_fence_array(args, file);
2966 if (IS_ERR(fences)) {
2968 return PTR_ERR(fences);
2972 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
2975 * Now that we have begun execution of the batchbuffer, we ignore
2976 * any new error after this point. Also given that we have already
2977 * updated the associated relocations, we try to write out the current
2978 * object locations irrespective of any error.
2980 if (args->flags & __EXEC_HAS_RELOC) {
2981 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2982 u64_to_user_ptr(args->buffers_ptr);
2985 /* Copy the new buffer offsets back to the user's exec list. */
2987 * Note: count * sizeof(*user_exec_list) does not overflow,
2988 * because we checked 'count' in check_buffer_count().
2990 * And this range already got effectively checked earlier
2991 * when we did the "copy_from_user()" above.
2993 if (!user_access_begin(user_exec_list, count * sizeof(*user_exec_list)))
2996 for (i = 0; i < args->buffer_count; i++) {
2997 if (!(exec2_list[i].offset & UPDATE))
3000 exec2_list[i].offset =
3001 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3002 unsafe_put_user(exec2_list[i].offset,
3003 &user_exec_list[i].offset,
3011 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
3012 put_fence_array(args, fences);