drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38
  39 #include "i915_drv.h"
  40 #include "gt/intel_ring.h"
  41 #include "gvt.h"
  42 #include "i915_pvinfo.h"
  43 #include "trace.h"
  44
  45 #define INVALID_OP    (~0U)
  46
  47 #define OP_LEN_MI           9
  48 #define OP_LEN_2D           10
  49 #define OP_LEN_3D_MEDIA     16
  50 #define OP_LEN_MFX_VC       16
  51 #define OP_LEN_VEBOX        16
  52
  53 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  54
  55 struct sub_op_bits {
  56         int hi;
  57         int low;
  58 };
  59 struct decode_info {
  60         const char *name;
  61         int op_len;
  62         int nr_sub_op;
  63         const struct sub_op_bits *sub_op;
  64 };
  65
  66 #define   MAX_CMD_BUDGET                        0x7fffffff
  67 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  68 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  69 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  70
  71 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  72 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  73 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  74
  75 /* Render Command Map */
  76
  77 /* MI_* command Opcode (28:23) */
  78 #define OP_MI_NOOP                          0x0
  79 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  80 #define OP_MI_USER_INTERRUPT                0x2
  81 #define OP_MI_WAIT_FOR_EVENT                0x3
  82 #define OP_MI_FLUSH                         0x4
  83 #define OP_MI_ARB_CHECK                     0x5
  84 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  85 #define OP_MI_REPORT_HEAD                   0x7
  86 #define OP_MI_ARB_ON_OFF                    0x8
  87 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  88 #define OP_MI_BATCH_BUFFER_END              0xA
  89 #define OP_MI_SUSPEND_FLUSH                 0xB
  90 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  91 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  92 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  93 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  94 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  95 #define OP_MI_DISPLAY_FLIP                  0x14
  96 #define OP_MI_SEMAPHORE_MBOX                0x16
  97 #define OP_MI_SET_CONTEXT                   0x18
  98 #define OP_MI_MATH                          0x1A
  99 #define OP_MI_URB_CLEAR                     0x19
 100 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
 101 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 102
 103 #define OP_MI_STORE_DATA_IMM                0x20
 104 #define OP_MI_STORE_DATA_INDEX              0x21
 105 #define OP_MI_LOAD_REGISTER_IMM             0x22
 106 #define OP_MI_UPDATE_GTT                    0x23
 107 #define OP_MI_STORE_REGISTER_MEM            0x24
 108 #define OP_MI_FLUSH_DW                      0x26
 109 #define OP_MI_CLFLUSH                       0x27
 110 #define OP_MI_REPORT_PERF_COUNT             0x28
 111 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 112 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 113 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 114 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 115 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 116 #define OP_MI_2E                            0x2E  /* BDW+ */
 117 #define OP_MI_2F                            0x2F  /* BDW+ */
 118 #define OP_MI_BATCH_BUFFER_START            0x31
 119
 120 /* Bit definition for dword 0 */
 121 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 122
 123 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 124
 125 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 126 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 127 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 128 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 129
 130 /* 2D command: Opcode (28:22) */
 131 #define OP_2D(x)    ((2<<7) | x)
 132
 133 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 134 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 135 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 136 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 137 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 138 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 139 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 140 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 141 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 142 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 143 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 144 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 145 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 146 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 147 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 148 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 149 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 150 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 151 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 152 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 153 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 154 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 155 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 156 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 157
 158 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 159 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 160         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 161
 162 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 163
 164 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 165 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 166 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 167 #define OP_SWTESS_BASE_ADDRESS                  OP_3D_MEDIA(0x0, 0x1, 0x03)
 168
 169 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 170
 171 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 172
 173 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 174 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 175 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 176 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 177 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 178 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 179
 180 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 181 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 182 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 183 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 184
 185 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 186 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 187 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 188 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 189 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 190 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 191 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 192 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 193 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 194 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 195 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 196 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 197 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 198 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 199 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 200 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 201 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 202 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 203 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 204 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 205 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 206 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 207 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 208 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 209 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 210 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 211 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 212 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 213 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 214 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 215 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 216 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 219 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 220 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 221 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 224 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 225 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 226 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 227 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 228 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 229 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 230 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 232 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 233 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 234 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 235 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 238 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 239 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 240 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 241 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 242 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 243 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 244 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 245 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 247 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 248 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 249 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 250 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 251
 252 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 253 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 254 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 255 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 256 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 257 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 258 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 259 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 260 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 261 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 262 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 263
 264 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 265 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 266 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 267 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 268 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 269 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 270 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 271 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 272 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 273 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 274 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 275 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 276 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 277 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 278 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 281 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 282 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 283 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 284 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 285 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 286 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 287 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 288 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 289 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 290 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 291 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 292
 293 /* VCCP Command Parser */
 294
 295 /*
 296  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 297  * git://anongit.freedesktop.org/vaapi/intel-driver
 298  * src/i965_defines.h
 299  *
 300  */
 301
 302 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 303         (3 << 13 | \
 304          (pipeline) << 11 | \
 305          (op) << 8 | \
 306          (sub_opa) << 5 | \
 307          (sub_opb))
 308
 309 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 310 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 311 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 312 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 313 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 314 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 315 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 316 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 317 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 318 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 319 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 320
 321 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 322
 323 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 324 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 325 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 326 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 327 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 328 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 329 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 330 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 331 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 332 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 333 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 334 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 335
 336 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 337 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 338 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 339 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 340 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 341
 342 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 343 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 344 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 345 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 346 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 347
 348 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 349 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 350 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 351
 352 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 353 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 354 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 355
 356 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 357         (3 << 13 | \
 358          (pipeline) << 11 | \
 359          (op) << 8 | \
 360          (sub_opa) << 5 | \
 361          (sub_opb))
 362
 363 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 364 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 365 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 366
 367 struct parser_exec_state;
 368
 369 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 370
 371 #define GVT_CMD_HASH_BITS   7
 372
 373 /* which DWords need address fix */
 374 #define ADDR_FIX_1(x1)                  (1 << (x1))
 375 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 376 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 377 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 378 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 379
 380 #define DWORD_FIELD(dword, end, start) \
 381         FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
 382
 383 #define OP_LENGTH_BIAS 2
 384 #define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
 385
 386 static int gvt_check_valid_cmd_length(int len, int valid_len)
 387 {
 388         if (valid_len != len) {
 389                 gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 390                         len, valid_len);
 391                 return -EFAULT;
 392         }
 393         return 0;
 394 }
 395
 396 struct cmd_info {
 397         const char *name;
 398         u32 opcode;
 399
 400 #define F_LEN_MASK      3U
 401 #define F_LEN_CONST  1U
 402 #define F_LEN_VAR    0U
 403 /* value is const although LEN maybe variable */
 404 #define F_LEN_VAR_FIXED    (1<<1)
 405
 406 /*
 407  * command has its own ip advance logic
 408  * e.g. MI_BATCH_START, MI_BATCH_END
 409  */
 410 #define F_IP_ADVANCE_CUSTOM (1<<2)
 411         u32 flag;
 412
 413 #define R_RCS   BIT(RCS0)
 414 #define R_VCS1  BIT(VCS0)
 415 #define R_VCS2  BIT(VCS1)
 416 #define R_VCS   (R_VCS1 | R_VCS2)
 417 #define R_BCS   BIT(BCS0)
 418 #define R_VECS  BIT(VECS0)
 419 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 420         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 421         u16 rings;
 422
 423         /* devices that support this cmd: SNB/IVB/HSW/... */
 424         u16 devices;
 425
 426         /* which DWords are address that need fix up.
 427          * bit 0 means a 32-bit non address operand in command
 428          * bit 1 means address operand, which could be 32-bit
 429          * or 64-bit depending on different architectures.(
 430          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 431          * No matter the address length, each address only takes
 432          * one bit in the bitmap.
 433          */
 434         u16 addr_bitmap;
 435
 436         /* flag == F_LEN_CONST : command length
 437          * flag == F_LEN_VAR : length bias bits
 438          * Note: length is in DWord
 439          */
 440         u32 len;
 441
 442         parser_cmd_handler handler;
 443
 444         /* valid length in DWord */
 445         u32 valid_len;
 446 };
 447
 448 struct cmd_entry {
 449         struct hlist_node hlist;
 450         const struct cmd_info *info;
 451 };
 452
 453 enum {
 454         RING_BUFFER_INSTRUCTION,
 455         BATCH_BUFFER_INSTRUCTION,
 456         BATCH_BUFFER_2ND_LEVEL,
 457 };
 458
 459 enum {
 460         GTT_BUFFER,
 461         PPGTT_BUFFER
 462 };
 463
 464 struct parser_exec_state {
 465         struct intel_vgpu *vgpu;
 466         const struct intel_engine_cs *engine;
 467
 468         int buf_type;
 469
 470         /* batch buffer address type */
 471         int buf_addr_type;
 472
 473         /* graphics memory address of ring buffer start */
 474         unsigned long ring_start;
 475         unsigned long ring_size;
 476         unsigned long ring_head;
 477         unsigned long ring_tail;
 478
 479         /* instruction graphics memory address */
 480         unsigned long ip_gma;
 481
 482         /* mapped va of the instr_gma */
 483         void *ip_va;
 484         void *rb_va;
 485
 486         void *ret_bb_va;
 487         /* next instruction when return from  batch buffer to ring buffer */
 488         unsigned long ret_ip_gma_ring;
 489
 490         /* next instruction when return from 2nd batch buffer to batch buffer */
 491         unsigned long ret_ip_gma_bb;
 492
 493         /* batch buffer address type (GTT or PPGTT)
 494          * used when ret from 2nd level batch buffer
 495          */
 496         int saved_buf_addr_type;
 497         bool is_ctx_wa;
 498
 499         const struct cmd_info *info;
 500
 501         struct intel_vgpu_workload *workload;
 502 };
 503
 504 #define gmadr_dw_number(s)      \
 505         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 506
 507 static unsigned long bypass_scan_mask = 0;
 508
 509 /* ring ALL, type = 0 */
 510 static const struct sub_op_bits sub_op_mi[] = {
 511         {31, 29},
 512         {28, 23},
 513 };
 514
 515 static const struct decode_info decode_info_mi = {
 516         "MI",
 517         OP_LEN_MI,
 518         ARRAY_SIZE(sub_op_mi),
 519         sub_op_mi,
 520 };
 521
 522 /* ring RCS, command type 2 */
 523 static const struct sub_op_bits sub_op_2d[] = {
 524         {31, 29},
 525         {28, 22},
 526 };
 527
 528 static const struct decode_info decode_info_2d = {
 529         "2D",
 530         OP_LEN_2D,
 531         ARRAY_SIZE(sub_op_2d),
 532         sub_op_2d,
 533 };
 534
 535 /* ring RCS, command type 3 */
 536 static const struct sub_op_bits sub_op_3d_media[] = {
 537         {31, 29},
 538         {28, 27},
 539         {26, 24},
 540         {23, 16},
 541 };
 542
 543 static const struct decode_info decode_info_3d_media = {
 544         "3D_Media",
 545         OP_LEN_3D_MEDIA,
 546         ARRAY_SIZE(sub_op_3d_media),
 547         sub_op_3d_media,
 548 };
 549
 550 /* ring VCS, command type 3 */
 551 static const struct sub_op_bits sub_op_mfx_vc[] = {
 552         {31, 29},
 553         {28, 27},
 554         {26, 24},
 555         {23, 21},
 556         {20, 16},
 557 };
 558
 559 static const struct decode_info decode_info_mfx_vc = {
 560         "MFX_VC",
 561         OP_LEN_MFX_VC,
 562         ARRAY_SIZE(sub_op_mfx_vc),
 563         sub_op_mfx_vc,
 564 };
 565
 566 /* ring VECS, command type 3 */
 567 static const struct sub_op_bits sub_op_vebox[] = {
 568         {31, 29},
 569         {28, 27},
 570         {26, 24},
 571         {23, 21},
 572         {20, 16},
 573 };
 574
 575 static const struct decode_info decode_info_vebox = {
 576         "VEBOX",
 577         OP_LEN_VEBOX,
 578         ARRAY_SIZE(sub_op_vebox),
 579         sub_op_vebox,
 580 };
 581
 582 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 583         [RCS0] = {
 584                 &decode_info_mi,
 585                 NULL,
 586                 NULL,
 587                 &decode_info_3d_media,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591                 NULL,
 592         },
 593
 594         [VCS0] = {
 595                 &decode_info_mi,
 596                 NULL,
 597                 NULL,
 598                 &decode_info_mfx_vc,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602                 NULL,
 603         },
 604
 605         [BCS0] = {
 606                 &decode_info_mi,
 607                 NULL,
 608                 &decode_info_2d,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613                 NULL,
 614         },
 615
 616         [VECS0] = {
 617                 &decode_info_mi,
 618                 NULL,
 619                 NULL,
 620                 &decode_info_vebox,
 621                 NULL,
 622                 NULL,
 623                 NULL,
 624                 NULL,
 625         },
 626
 627         [VCS1] = {
 628                 &decode_info_mi,
 629                 NULL,
 630                 NULL,
 631                 &decode_info_mfx_vc,
 632                 NULL,
 633                 NULL,
 634                 NULL,
 635                 NULL,
 636         },
 637 };
 638
 639 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
 640 {
 641         const struct decode_info *d_info;
 642
 643         d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 644         if (d_info == NULL)
 645                 return INVALID_OP;
 646
 647         return cmd >> (32 - d_info->op_len);
 648 }
 649
 650 static inline const struct cmd_info *
 651 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
 652                const struct intel_engine_cs *engine)
 653 {
 654         struct cmd_entry *e;
 655
 656         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 657                 if (opcode == e->info->opcode &&
 658                     e->info->rings & engine->mask)
 659                         return e->info;
 660         }
 661         return NULL;
 662 }
 663
 664 static inline const struct cmd_info *
 665 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
 666              const struct intel_engine_cs *engine)
 667 {
 668         u32 opcode;
 669
 670         opcode = get_opcode(cmd, engine);
 671         if (opcode == INVALID_OP)
 672                 return NULL;
 673
 674         return find_cmd_entry(gvt, opcode, engine);
 675 }
 676
 677 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 678 {
 679         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 680 }
 681
 682 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
 683 {
 684         const struct decode_info *d_info;
 685         int i;
 686
 687         d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 688         if (d_info == NULL)
 689                 return;
 690
 691         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 692                         cmd >> (32 - d_info->op_len), d_info->name);
 693
 694         for (i = 0; i < d_info->nr_sub_op; i++)
 695                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 696                                         d_info->sub_op[i].low));
 697
 698         pr_err("\n");
 699 }
 700
 701 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 702 {
 703         return s->ip_va + (index << 2);
 704 }
 705
 706 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 707 {
 708         return *cmd_ptr(s, index);
 709 }
 710
 711 static void parser_exec_state_dump(struct parser_exec_state *s)
 712 {
 713         int cnt = 0;
 714         int i;
 715
 716         gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
 717                     " ring_head(%08lx) ring_tail(%08lx)\n",
 718                     s->vgpu->id, s->engine->name,
 719                     s->ring_start, s->ring_start + s->ring_size,
 720                     s->ring_head, s->ring_tail);
 721
 722         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 723                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 724                         "RING_BUFFER" : "BATCH_BUFFER",
 725                         s->buf_addr_type == GTT_BUFFER ?
 726                         "GTT" : "PPGTT", s->ip_gma);
 727
 728         if (s->ip_va == NULL) {
 729                 gvt_dbg_cmd(" ip_va(NULL)");
 730                 return;
 731         }
 732
 733         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 734                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 735                         cmd_val(s, 2), cmd_val(s, 3));
 736
 737         print_opcode(cmd_val(s, 0), s->engine);
 738
 739         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 740
 741         while (cnt < 1024) {
 742                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 743                 for (i = 0; i < 8; i++)
 744                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 745                 gvt_dbg_cmd("\n");
 746
 747                 s->ip_va += 8 * sizeof(u32);
 748                 cnt += 8;
 749         }
 750 }
 751
 752 static inline void update_ip_va(struct parser_exec_state *s)
 753 {
 754         unsigned long len = 0;
 755
 756         if (WARN_ON(s->ring_head == s->ring_tail))
 757                 return;
 758
 759         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 760                 unsigned long ring_top = s->ring_start + s->ring_size;
 761
 762                 if (s->ring_head > s->ring_tail) {
 763                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 764                                 len = (s->ip_gma - s->ring_head);
 765                         else if (s->ip_gma >= s->ring_start &&
 766                                         s->ip_gma <= s->ring_tail)
 767                                 len = (ring_top - s->ring_head) +
 768                                         (s->ip_gma - s->ring_start);
 769                 } else
 770                         len = (s->ip_gma - s->ring_head);
 771
 772                 s->ip_va = s->rb_va + len;
 773         } else {/* shadow batch buffer */
 774                 s->ip_va = s->ret_bb_va;
 775         }
 776 }
 777
 778 static inline int ip_gma_set(struct parser_exec_state *s,
 779                 unsigned long ip_gma)
 780 {
 781         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 782
 783         s->ip_gma = ip_gma;
 784         update_ip_va(s);
 785         return 0;
 786 }
 787
 788 static inline int ip_gma_advance(struct parser_exec_state *s,
 789                 unsigned int dw_len)
 790 {
 791         s->ip_gma += (dw_len << 2);
 792
 793         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 794                 if (s->ip_gma >= s->ring_start + s->ring_size)
 795                         s->ip_gma -= s->ring_size;
 796                 update_ip_va(s);
 797         } else {
 798                 s->ip_va += (dw_len << 2);
 799         }
 800
 801         return 0;
 802 }
 803
 804 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 805 {
 806         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 807                 return info->len;
 808         else
 809                 return (cmd & ((1U << info->len) - 1)) + 2;
 810         return 0;
 811 }
 812
 813 static inline int cmd_length(struct parser_exec_state *s)
 814 {
 815         return get_cmd_length(s->info, cmd_val(s, 0));
 816 }
 817
 818 /* do not remove this, some platform may need clflush here */
 819 #define patch_value(s, addr, val) do { \
 820         *addr = val; \
 821 } while (0)
 822
 823 static bool is_shadowed_mmio(unsigned int offset)
 824 {
 825         bool ret = false;
 826
 827         if ((offset == 0x2168) || /*BB current head register UDW */
 828             (offset == 0x2140) || /*BB current header register */
 829             (offset == 0x211c) || /*second BB header register UDW */
 830             (offset == 0x2114)) { /*second BB header register UDW */
 831                 ret = true;
 832         }
 833         return ret;
 834 }
 835
 836 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 837 {
 838         return (offset >= 0x24d0 && offset < 0x2500);
 839 }
 840
 841 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 842                 unsigned int offset, unsigned int index, char *cmd)
 843 {
 844         struct intel_gvt *gvt = s->vgpu->gvt;
 845         unsigned int data;
 846         u32 ring_base;
 847         u32 nopid;
 848
 849         if (!strcmp(cmd, "lri"))
 850                 data = cmd_val(s, index + 1);
 851         else {
 852                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
 853                         offset, cmd);
 854                 return -EINVAL;
 855         }
 856
 857         ring_base = s->engine->mmio_base;
 858         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 859
 860         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
 861                         data != nopid) {
 862                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 863                         offset, data);
 864                 patch_value(s, cmd_ptr(s, index), nopid);
 865                 return 0;
 866         }
 867         return 0;
 868 }
 869
 870 static inline bool is_mocs_mmio(unsigned int offset)
 871 {
 872         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 873                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 874 }
 875
 876 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 877                                 unsigned int offset, unsigned int index)
 878 {
 879         if (!is_mocs_mmio(offset))
 880                 return -EINVAL;
 881         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 882         return 0;
 883 }
 884
 885 static int cmd_reg_handler(struct parser_exec_state *s,
 886         unsigned int offset, unsigned int index, char *cmd)
 887 {
 888         struct intel_vgpu *vgpu = s->vgpu;
 889         struct intel_gvt *gvt = vgpu->gvt;
 890         u32 ctx_sr_ctl;
 891
 892         if (offset + 4 > gvt->device_info.mmio_size) {
 893                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 894                                 cmd, offset);
 895                 return -EFAULT;
 896         }
 897
 898         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 899                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 900                                 cmd, offset);
 901                 return -EBADRQC;
 902         }
 903
 904         if (is_shadowed_mmio(offset)) {
 905                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 906                 return 0;
 907         }
 908
 909         if (is_mocs_mmio(offset) &&
 910             mocs_cmd_reg_handler(s, offset, index))
 911                 return -EINVAL;
 912
 913         if (is_force_nonpriv_mmio(offset) &&
 914                 force_nonpriv_reg_handler(s, offset, index, cmd))
 915                 return -EPERM;
 916
 917         if (offset == i915_mmio_reg_offset(DERRMR) ||
 918                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 919                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 920                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 921         }
 922
 923         /* TODO
 924          * In order to let workload with inhibit context to generate
 925          * correct image data into memory, vregs values will be loaded to
 926          * hw via LRIs in the workload with inhibit context. But as
 927          * indirect context is loaded prior to LRIs in workload, we don't
 928          * want reg values specified in indirect context overwritten by
 929          * LRIs in workloads. So, when scanning an indirect context, we
 930          * update reg values in it into vregs, so LRIs in workload with
 931          * inhibit context will restore with correct values
 932          */
 933         if (IS_GEN(s->engine->i915, 9) &&
 934             intel_gvt_mmio_is_in_ctx(gvt, offset) &&
 935             !strncmp(cmd, "lri", 3)) {
 936                 intel_gvt_hypervisor_read_gpa(s->vgpu,
 937                         s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
 938                 /* check inhibit context */
 939                 if (ctx_sr_ctl & 1) {
 940                         u32 data = cmd_val(s, index + 1);
 941
 942                         if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
 943                                 intel_vgpu_mask_mmio_write(vgpu,
 944                                                         offset, &data, 4);
 945                         else
 946                                 vgpu_vreg(vgpu, offset) = data;
 947                 }
 948         }
 949
 950         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 951         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 952         return 0;
 953 }
 954
 955 #define cmd_reg(s, i) \
 956         (cmd_val(s, i) & GENMASK(22, 2))
 957
 958 #define cmd_reg_inhibit(s, i) \
 959         (cmd_val(s, i) & GENMASK(22, 18))
 960
 961 #define cmd_gma(s, i) \
 962         (cmd_val(s, i) & GENMASK(31, 2))
 963
 964 #define cmd_gma_hi(s, i) \
 965         (cmd_val(s, i) & GENMASK(15, 0))
 966
 967 static int cmd_handler_lri(struct parser_exec_state *s)
 968 {
 969         int i, ret = 0;
 970         int cmd_len = cmd_length(s);
 971
 972         for (i = 1; i < cmd_len; i += 2) {
 973                 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
 974                         if (s->engine->id == BCS0 &&
 975                             cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
 976                                 ret |= 0;
 977                         else
 978                                 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
 979                 }
 980                 if (ret)
 981                         break;
 982                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 983                 if (ret)
 984                         break;
 985         }
 986         return ret;
 987 }
 988
 989 static int cmd_handler_lrr(struct parser_exec_state *s)
 990 {
 991         int i, ret = 0;
 992         int cmd_len = cmd_length(s);
 993
 994         for (i = 1; i < cmd_len; i += 2) {
 995                 if (IS_BROADWELL(s->engine->i915))
 996                         ret |= ((cmd_reg_inhibit(s, i) ||
 997                                  (cmd_reg_inhibit(s, i + 1)))) ?
 998                                 -EBADRQC : 0;
 999                 if (ret)
1000                         break;
1001                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1002                 if (ret)
1003                         break;
1004                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1005                 if (ret)
1006                         break;
1007         }
1008         return ret;
1009 }
1010
1011 static inline int cmd_address_audit(struct parser_exec_state *s,
1012                 unsigned long guest_gma, int op_size, bool index_mode);
1013
1014 static int cmd_handler_lrm(struct parser_exec_state *s)
1015 {
1016         struct intel_gvt *gvt = s->vgpu->gvt;
1017         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1018         unsigned long gma;
1019         int i, ret = 0;
1020         int cmd_len = cmd_length(s);
1021
1022         for (i = 1; i < cmd_len;) {
1023                 if (IS_BROADWELL(s->engine->i915))
1024                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1025                 if (ret)
1026                         break;
1027                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1028                 if (ret)
1029                         break;
1030                 if (cmd_val(s, 0) & (1 << 22)) {
1031                         gma = cmd_gma(s, i + 1);
1032                         if (gmadr_bytes == 8)
1033                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1034                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1035                         if (ret)
1036                                 break;
1037                 }
1038                 i += gmadr_dw_number(s) + 1;
1039         }
1040         return ret;
1041 }
1042
1043 static int cmd_handler_srm(struct parser_exec_state *s)
1044 {
1045         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1046         unsigned long gma;
1047         int i, ret = 0;
1048         int cmd_len = cmd_length(s);
1049
1050         for (i = 1; i < cmd_len;) {
1051                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1052                 if (ret)
1053                         break;
1054                 if (cmd_val(s, 0) & (1 << 22)) {
1055                         gma = cmd_gma(s, i + 1);
1056                         if (gmadr_bytes == 8)
1057                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1058                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1059                         if (ret)
1060                                 break;
1061                 }
1062                 i += gmadr_dw_number(s) + 1;
1063         }
1064         return ret;
1065 }
1066
1067 struct cmd_interrupt_event {
1068         int pipe_control_notify;
1069         int mi_flush_dw;
1070         int mi_user_interrupt;
1071 };
1072
1073 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1074         [RCS0] = {
1075                 .pipe_control_notify = RCS_PIPE_CONTROL,
1076                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1077                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1078         },
1079         [BCS0] = {
1080                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1081                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1082                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1083         },
1084         [VCS0] = {
1085                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1086                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1087                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1088         },
1089         [VCS1] = {
1090                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1091                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1092                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1093         },
1094         [VECS0] = {
1095                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1096                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1097                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1098         },
1099 };
1100
1101 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1102 {
1103         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1104         unsigned long gma;
1105         bool index_mode = false;
1106         unsigned int post_sync;
1107         int ret = 0;
1108         u32 hws_pga, val;
1109
1110         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1111
1112         /* LRI post sync */
1113         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1114                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1115         /* post sync */
1116         else if (post_sync) {
1117                 if (post_sync == 2)
1118                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1119                 else if (post_sync == 3)
1120                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1121                 else if (post_sync == 1) {
1122                         /* check ggtt*/
1123                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1124                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1125                                 if (gmadr_bytes == 8)
1126                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1127                                 /* Store Data Index */
1128                                 if (cmd_val(s, 1) & (1 << 21))
1129                                         index_mode = true;
1130                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1131                                                 index_mode);
1132                                 if (ret)
1133                                         return ret;
1134                                 if (index_mode) {
1135                                         hws_pga = s->vgpu->hws_pga[s->engine->id];
1136                                         gma = hws_pga + gma;
1137                                         patch_value(s, cmd_ptr(s, 2), gma);
1138                                         val = cmd_val(s, 1) & (~(1 << 21));
1139                                         patch_value(s, cmd_ptr(s, 1), val);
1140                                 }
1141                         }
1142                 }
1143         }
1144
1145         if (ret)
1146                 return ret;
1147
1148         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1149                 set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1150                         s->workload->pending_events);
1151         return 0;
1152 }
1153
1154 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1155 {
1156         set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1157                 s->workload->pending_events);
1158         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1159         return 0;
1160 }
1161
1162 static int cmd_advance_default(struct parser_exec_state *s)
1163 {
1164         return ip_gma_advance(s, cmd_length(s));
1165 }
1166
1167 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1168 {
1169         int ret;
1170
1171         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1172                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1173                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1174                 s->buf_addr_type = s->saved_buf_addr_type;
1175         } else {
1176                 s->buf_type = RING_BUFFER_INSTRUCTION;
1177                 s->buf_addr_type = GTT_BUFFER;
1178                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1179                         s->ret_ip_gma_ring -= s->ring_size;
1180                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1181         }
1182         return ret;
1183 }
1184
1185 struct mi_display_flip_command_info {
1186         int pipe;
1187         int plane;
1188         int event;
1189         i915_reg_t stride_reg;
1190         i915_reg_t ctrl_reg;
1191         i915_reg_t surf_reg;
1192         u64 stride_val;
1193         u64 tile_val;
1194         u64 surf_val;
1195         bool async_flip;
1196 };
1197
1198 struct plane_code_mapping {
1199         int pipe;
1200         int plane;
1201         int event;
1202 };
1203
1204 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1205                 struct mi_display_flip_command_info *info)
1206 {
1207         struct drm_i915_private *dev_priv = s->engine->i915;
1208         struct plane_code_mapping gen8_plane_code[] = {
1209                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1210                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1211                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1212                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1213                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1214                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1215         };
1216         u32 dword0, dword1, dword2;
1217         u32 v;
1218
1219         dword0 = cmd_val(s, 0);
1220         dword1 = cmd_val(s, 1);
1221         dword2 = cmd_val(s, 2);
1222
1223         v = (dword0 & GENMASK(21, 19)) >> 19;
1224         if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1225                 return -EBADRQC;
1226
1227         info->pipe = gen8_plane_code[v].pipe;
1228         info->plane = gen8_plane_code[v].plane;
1229         info->event = gen8_plane_code[v].event;
1230         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1231         info->tile_val = (dword1 & 0x1);
1232         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1233         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1234
1235         if (info->plane == PLANE_A) {
1236                 info->ctrl_reg = DSPCNTR(info->pipe);
1237                 info->stride_reg = DSPSTRIDE(info->pipe);
1238                 info->surf_reg = DSPSURF(info->pipe);
1239         } else if (info->plane == PLANE_B) {
1240                 info->ctrl_reg = SPRCTL(info->pipe);
1241                 info->stride_reg = SPRSTRIDE(info->pipe);
1242                 info->surf_reg = SPRSURF(info->pipe);
1243         } else {
1244                 drm_WARN_ON(&dev_priv->drm, 1);
1245                 return -EBADRQC;
1246         }
1247         return 0;
1248 }
1249
1250 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1251                 struct mi_display_flip_command_info *info)
1252 {
1253         struct drm_i915_private *dev_priv = s->engine->i915;
1254         struct intel_vgpu *vgpu = s->vgpu;
1255         u32 dword0 = cmd_val(s, 0);
1256         u32 dword1 = cmd_val(s, 1);
1257         u32 dword2 = cmd_val(s, 2);
1258         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1259
1260         info->plane = PRIMARY_PLANE;
1261
1262         switch (plane) {
1263         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1264                 info->pipe = PIPE_A;
1265                 info->event = PRIMARY_A_FLIP_DONE;
1266                 break;
1267         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1268                 info->pipe = PIPE_B;
1269                 info->event = PRIMARY_B_FLIP_DONE;
1270                 break;
1271         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1272                 info->pipe = PIPE_C;
1273                 info->event = PRIMARY_C_FLIP_DONE;
1274                 break;
1275
1276         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1277                 info->pipe = PIPE_A;
1278                 info->event = SPRITE_A_FLIP_DONE;
1279                 info->plane = SPRITE_PLANE;
1280                 break;
1281         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1282                 info->pipe = PIPE_B;
1283                 info->event = SPRITE_B_FLIP_DONE;
1284                 info->plane = SPRITE_PLANE;
1285                 break;
1286         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1287                 info->pipe = PIPE_C;
1288                 info->event = SPRITE_C_FLIP_DONE;
1289                 info->plane = SPRITE_PLANE;
1290                 break;
1291
1292         default:
1293                 gvt_vgpu_err("unknown plane code %d\n", plane);
1294                 return -EBADRQC;
1295         }
1296
1297         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1298         info->tile_val = (dword1 & GENMASK(2, 0));
1299         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1300         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1301
1302         info->ctrl_reg = DSPCNTR(info->pipe);
1303         info->stride_reg = DSPSTRIDE(info->pipe);
1304         info->surf_reg = DSPSURF(info->pipe);
1305
1306         return 0;
1307 }
1308
1309 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1310                 struct mi_display_flip_command_info *info)
1311 {
1312         u32 stride, tile;
1313
1314         if (!info->async_flip)
1315                 return 0;
1316
1317         if (INTEL_GEN(s->engine->i915) >= 9) {
1318                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1319                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1320                                 GENMASK(12, 10)) >> 10;
1321         } else {
1322                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1323                                 GENMASK(15, 6)) >> 6;
1324                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1325         }
1326
1327         if (stride != info->stride_val)
1328                 gvt_dbg_cmd("cannot change stride during async flip\n");
1329
1330         if (tile != info->tile_val)
1331                 gvt_dbg_cmd("cannot change tile during async flip\n");
1332
1333         return 0;
1334 }
1335
1336 static int gen8_update_plane_mmio_from_mi_display_flip(
1337                 struct parser_exec_state *s,
1338                 struct mi_display_flip_command_info *info)
1339 {
1340         struct drm_i915_private *dev_priv = s->engine->i915;
1341         struct intel_vgpu *vgpu = s->vgpu;
1342
1343         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1344                       info->surf_val << 12);
1345         if (INTEL_GEN(dev_priv) >= 9) {
1346                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1347                               info->stride_val);
1348                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1349                               info->tile_val << 10);
1350         } else {
1351                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1352                               info->stride_val << 6);
1353                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1354                               info->tile_val << 10);
1355         }
1356
1357         if (info->plane == PLANE_PRIMARY)
1358                 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1359
1360         if (info->async_flip)
1361                 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1362         else
1363                 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1364
1365         return 0;
1366 }
1367
1368 static int decode_mi_display_flip(struct parser_exec_state *s,
1369                 struct mi_display_flip_command_info *info)
1370 {
1371         if (IS_BROADWELL(s->engine->i915))
1372                 return gen8_decode_mi_display_flip(s, info);
1373         if (INTEL_GEN(s->engine->i915) >= 9)
1374                 return skl_decode_mi_display_flip(s, info);
1375
1376         return -ENODEV;
1377 }
1378
1379 static int check_mi_display_flip(struct parser_exec_state *s,
1380                 struct mi_display_flip_command_info *info)
1381 {
1382         return gen8_check_mi_display_flip(s, info);
1383 }
1384
1385 static int update_plane_mmio_from_mi_display_flip(
1386                 struct parser_exec_state *s,
1387                 struct mi_display_flip_command_info *info)
1388 {
1389         return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1390 }
1391
1392 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1393 {
1394         struct mi_display_flip_command_info info;
1395         struct intel_vgpu *vgpu = s->vgpu;
1396         int ret;
1397         int i;
1398         int len = cmd_length(s);
1399         u32 valid_len = CMD_LEN(1);
1400
1401         /* Flip Type == Stereo 3D Flip */
1402         if (DWORD_FIELD(2, 1, 0) == 2)
1403                 valid_len++;
1404         ret = gvt_check_valid_cmd_length(cmd_length(s),
1405                         valid_len);
1406         if (ret)
1407                 return ret;
1408
1409         ret = decode_mi_display_flip(s, &info);
1410         if (ret) {
1411                 gvt_vgpu_err("fail to decode MI display flip command\n");
1412                 return ret;
1413         }
1414
1415         ret = check_mi_display_flip(s, &info);
1416         if (ret) {
1417                 gvt_vgpu_err("invalid MI display flip command\n");
1418                 return ret;
1419         }
1420
1421         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1422         if (ret) {
1423                 gvt_vgpu_err("fail to update plane mmio\n");
1424                 return ret;
1425         }
1426
1427         for (i = 0; i < len; i++)
1428                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1429         return 0;
1430 }
1431
1432 static bool is_wait_for_flip_pending(u32 cmd)
1433 {
1434         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1435                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1436                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1437                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1438                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1439                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1440 }
1441
1442 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1443 {
1444         u32 cmd = cmd_val(s, 0);
1445
1446         if (!is_wait_for_flip_pending(cmd))
1447                 return 0;
1448
1449         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1450         return 0;
1451 }
1452
1453 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1454 {
1455         unsigned long addr;
1456         unsigned long gma_high, gma_low;
1457         struct intel_vgpu *vgpu = s->vgpu;
1458         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1459
1460         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1461                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1462                 return INTEL_GVT_INVALID_ADDR;
1463         }
1464
1465         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1466         if (gmadr_bytes == 4) {
1467                 addr = gma_low;
1468         } else {
1469                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1470                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1471         }
1472         return addr;
1473 }
1474
1475 static inline int cmd_address_audit(struct parser_exec_state *s,
1476                 unsigned long guest_gma, int op_size, bool index_mode)
1477 {
1478         struct intel_vgpu *vgpu = s->vgpu;
1479         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1480         int i;
1481         int ret;
1482
1483         if (op_size > max_surface_size) {
1484                 gvt_vgpu_err("command address audit fail name %s\n",
1485                         s->info->name);
1486                 return -EFAULT;
1487         }
1488
1489         if (index_mode) {
1490                 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1491                         ret = -EFAULT;
1492                         goto err;
1493                 }
1494         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1495                 ret = -EFAULT;
1496                 goto err;
1497         }
1498
1499         return 0;
1500
1501 err:
1502         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1503                         s->info->name, guest_gma, op_size);
1504
1505         pr_err("cmd dump: ");
1506         for (i = 0; i < cmd_length(s); i++) {
1507                 if (!(i % 4))
1508                         pr_err("\n%08x ", cmd_val(s, i));
1509                 else
1510                         pr_err("%08x ", cmd_val(s, i));
1511         }
1512         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1513                         vgpu->id,
1514                         vgpu_aperture_gmadr_base(vgpu),
1515                         vgpu_aperture_gmadr_end(vgpu),
1516                         vgpu_hidden_gmadr_base(vgpu),
1517                         vgpu_hidden_gmadr_end(vgpu));
1518         return ret;
1519 }
1520
1521 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1522 {
1523         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1524         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1525         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1526         unsigned long gma, gma_low, gma_high;
1527         u32 valid_len = CMD_LEN(2);
1528         int ret = 0;
1529
1530         /* check ppggt */
1531         if (!(cmd_val(s, 0) & (1 << 22)))
1532                 return 0;
1533
1534         /* check if QWORD */
1535         if (DWORD_FIELD(0, 21, 21))
1536                 valid_len++;
1537         ret = gvt_check_valid_cmd_length(cmd_length(s),
1538                         valid_len);
1539         if (ret)
1540                 return ret;
1541
1542         gma = cmd_val(s, 2) & GENMASK(31, 2);
1543
1544         if (gmadr_bytes == 8) {
1545                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1546                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1547                 gma = (gma_high << 32) | gma_low;
1548                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1549         }
1550         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1551         return ret;
1552 }
1553
1554 static inline int unexpected_cmd(struct parser_exec_state *s)
1555 {
1556         struct intel_vgpu *vgpu = s->vgpu;
1557
1558         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1559
1560         return -EBADRQC;
1561 }
1562
1563 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1564 {
1565         return unexpected_cmd(s);
1566 }
1567
1568 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1569 {
1570         return unexpected_cmd(s);
1571 }
1572
1573 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1574 {
1575         return unexpected_cmd(s);
1576 }
1577
1578 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1579 {
1580         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1581         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1582                         sizeof(u32);
1583         unsigned long gma, gma_high;
1584         u32 valid_len = CMD_LEN(1);
1585         int ret = 0;
1586
1587         if (!(cmd_val(s, 0) & (1 << 22)))
1588                 return ret;
1589
1590         /* check inline data */
1591         if (cmd_val(s, 0) & BIT(18))
1592                 valid_len = CMD_LEN(9);
1593         ret = gvt_check_valid_cmd_length(cmd_length(s),
1594                         valid_len);
1595         if (ret)
1596                 return ret;
1597
1598         gma = cmd_val(s, 1) & GENMASK(31, 2);
1599         if (gmadr_bytes == 8) {
1600                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1601                 gma = (gma_high << 32) | gma;
1602         }
1603         ret = cmd_address_audit(s, gma, op_size, false);
1604         return ret;
1605 }
1606
1607 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1608 {
1609         return unexpected_cmd(s);
1610 }
1611
1612 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1613 {
1614         return unexpected_cmd(s);
1615 }
1616
1617 static int cmd_handler_mi_conditional_batch_buffer_end(
1618                 struct parser_exec_state *s)
1619 {
1620         return unexpected_cmd(s);
1621 }
1622
1623 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1624 {
1625         return unexpected_cmd(s);
1626 }
1627
1628 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1629 {
1630         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1631         unsigned long gma;
1632         bool index_mode = false;
1633         int ret = 0;
1634         u32 hws_pga, val;
1635         u32 valid_len = CMD_LEN(2);
1636
1637         ret = gvt_check_valid_cmd_length(cmd_length(s),
1638                         valid_len);
1639         if (ret) {
1640                 /* Check again for Qword */
1641                 ret = gvt_check_valid_cmd_length(cmd_length(s),
1642                         ++valid_len);
1643                 return ret;
1644         }
1645
1646         /* Check post-sync and ppgtt bit */
1647         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1648                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1649                 if (gmadr_bytes == 8)
1650                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1651                 /* Store Data Index */
1652                 if (cmd_val(s, 0) & (1 << 21))
1653                         index_mode = true;
1654                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1655                 if (ret)
1656                         return ret;
1657                 if (index_mode) {
1658                         hws_pga = s->vgpu->hws_pga[s->engine->id];
1659                         gma = hws_pga + gma;
1660                         patch_value(s, cmd_ptr(s, 1), gma);
1661                         val = cmd_val(s, 0) & (~(1 << 21));
1662                         patch_value(s, cmd_ptr(s, 0), val);
1663                 }
1664         }
1665         /* Check notify bit */
1666         if ((cmd_val(s, 0) & (1 << 8)))
1667                 set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1668                         s->workload->pending_events);
1669         return ret;
1670 }
1671
1672 static void addr_type_update_snb(struct parser_exec_state *s)
1673 {
1674         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1675                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1676                 s->buf_addr_type = PPGTT_BUFFER;
1677         }
1678 }
1679
1680
1681 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1682                 unsigned long gma, unsigned long end_gma, void *va)
1683 {
1684         unsigned long copy_len, offset;
1685         unsigned long len = 0;
1686         unsigned long gpa;
1687
1688         while (gma != end_gma) {
1689                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1690                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1691                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1692                         return -EFAULT;
1693                 }
1694
1695                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1696
1697                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1698                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1699
1700                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1701
1702                 len += copy_len;
1703                 gma += copy_len;
1704         }
1705         return len;
1706 }
1707
1708
1709 /*
1710  * Check whether a batch buffer needs to be scanned. Currently
1711  * the only criteria is based on privilege.
1712  */
1713 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1714 {
1715         /* Decide privilege based on address space */
1716         if (cmd_val(s, 0) & BIT(8) &&
1717             !(s->vgpu->scan_nonprivbb & s->engine->mask))
1718                 return 0;
1719
1720         return 1;
1721 }
1722
1723 static const char *repr_addr_type(unsigned int type)
1724 {
1725         return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1726 }
1727
1728 static int find_bb_size(struct parser_exec_state *s,
1729                         unsigned long *bb_size,
1730                         unsigned long *bb_end_cmd_offset)
1731 {
1732         unsigned long gma = 0;
1733         const struct cmd_info *info;
1734         u32 cmd_len = 0;
1735         bool bb_end = false;
1736         struct intel_vgpu *vgpu = s->vgpu;
1737         u32 cmd;
1738         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1739                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1740
1741         *bb_size = 0;
1742         *bb_end_cmd_offset = 0;
1743
1744         /* get the start gm address of the batch buffer */
1745         gma = get_gma_bb_from_cmd(s, 1);
1746         if (gma == INTEL_GVT_INVALID_ADDR)
1747                 return -EFAULT;
1748
1749         cmd = cmd_val(s, 0);
1750         info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1751         if (info == NULL) {
1752                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1753                              cmd, get_opcode(cmd, s->engine),
1754                              repr_addr_type(s->buf_addr_type),
1755                              s->engine->name, s->workload);
1756                 return -EBADRQC;
1757         }
1758         do {
1759                 if (copy_gma_to_hva(s->vgpu, mm,
1760                                     gma, gma + 4, &cmd) < 0)
1761                         return -EFAULT;
1762                 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1763                 if (info == NULL) {
1764                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1765                                      cmd, get_opcode(cmd, s->engine),
1766                                      repr_addr_type(s->buf_addr_type),
1767                                      s->engine->name, s->workload);
1768                         return -EBADRQC;
1769                 }
1770
1771                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1772                         bb_end = true;
1773                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1774                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1775                                 /* chained batch buffer */
1776                                 bb_end = true;
1777                 }
1778
1779                 if (bb_end)
1780                         *bb_end_cmd_offset = *bb_size;
1781
1782                 cmd_len = get_cmd_length(info, cmd) << 2;
1783                 *bb_size += cmd_len;
1784                 gma += cmd_len;
1785         } while (!bb_end);
1786
1787         return 0;
1788 }
1789
1790 static int audit_bb_end(struct parser_exec_state *s, void *va)
1791 {
1792         struct intel_vgpu *vgpu = s->vgpu;
1793         u32 cmd = *(u32 *)va;
1794         const struct cmd_info *info;
1795
1796         info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1797         if (info == NULL) {
1798                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1799                              cmd, get_opcode(cmd, s->engine),
1800                              repr_addr_type(s->buf_addr_type),
1801                              s->engine->name, s->workload);
1802                 return -EBADRQC;
1803         }
1804
1805         if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1806             ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1807              (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1808                 return 0;
1809
1810         return -EBADRQC;
1811 }
1812
1813 static int perform_bb_shadow(struct parser_exec_state *s)
1814 {
1815         struct intel_vgpu *vgpu = s->vgpu;
1816         struct intel_vgpu_shadow_bb *bb;
1817         unsigned long gma = 0;
1818         unsigned long bb_size;
1819         unsigned long bb_end_cmd_offset;
1820         int ret = 0;
1821         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1822                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1823         unsigned long start_offset = 0;
1824
1825         /* get the start gm address of the batch buffer */
1826         gma = get_gma_bb_from_cmd(s, 1);
1827         if (gma == INTEL_GVT_INVALID_ADDR)
1828                 return -EFAULT;
1829
1830         ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1831         if (ret)
1832                 return ret;
1833
1834         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1835         if (!bb)
1836                 return -ENOMEM;
1837
1838         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1839
1840         /* the start_offset stores the batch buffer's start gma's
1841          * offset relative to page boundary. so for non-privileged batch
1842          * buffer, the shadowed gem object holds exactly the same page
1843          * layout as original gem object. This is for the convience of
1844          * replacing the whole non-privilged batch buffer page to this
1845          * shadowed one in PPGTT at the same gma address. (this replacing
1846          * action is not implemented yet now, but may be necessary in
1847          * future).
1848          * for prileged batch buffer, we just change start gma address to
1849          * that of shadowed page.
1850          */
1851         if (bb->ppgtt)
1852                 start_offset = gma & ~I915_GTT_PAGE_MASK;
1853
1854         bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1855                                                round_up(bb_size + start_offset,
1856                                                         PAGE_SIZE));
1857         if (IS_ERR(bb->obj)) {
1858                 ret = PTR_ERR(bb->obj);
1859                 goto err_free_bb;
1860         }
1861
1862         ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush);
1863         if (ret)
1864                 goto err_free_obj;
1865
1866         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1867         if (IS_ERR(bb->va)) {
1868                 ret = PTR_ERR(bb->va);
1869                 goto err_finish_shmem_access;
1870         }
1871
1872         if (bb->clflush & CLFLUSH_BEFORE) {
1873                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1874                 bb->clflush &= ~CLFLUSH_BEFORE;
1875         }
1876
1877         ret = copy_gma_to_hva(s->vgpu, mm,
1878                               gma, gma + bb_size,
1879                               bb->va + start_offset);
1880         if (ret < 0) {
1881                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1882                 ret = -EFAULT;
1883                 goto err_unmap;
1884         }
1885
1886         ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1887         if (ret)
1888                 goto err_unmap;
1889
1890         INIT_LIST_HEAD(&bb->list);
1891         list_add(&bb->list, &s->workload->shadow_bb);
1892
1893         bb->accessing = true;
1894         bb->bb_start_cmd_va = s->ip_va;
1895
1896         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1897                 bb->bb_offset = s->ip_va - s->rb_va;
1898         else
1899                 bb->bb_offset = 0;
1900
1901         /*
1902          * ip_va saves the virtual address of the shadow batch buffer, while
1903          * ip_gma saves the graphics address of the original batch buffer.
1904          * As the shadow batch buffer is just a copy from the originial one,
1905          * it should be right to use shadow batch buffer'va and original batch
1906          * buffer's gma in pair. After all, we don't want to pin the shadow
1907          * buffer here (too early).
1908          */
1909         s->ip_va = bb->va + start_offset;
1910         s->ip_gma = gma;
1911         return 0;
1912 err_unmap:
1913         i915_gem_object_unpin_map(bb->obj);
1914 err_finish_shmem_access:
1915         i915_gem_object_finish_access(bb->obj);
1916 err_free_obj:
1917         i915_gem_object_put(bb->obj);
1918 err_free_bb:
1919         kfree(bb);
1920         return ret;
1921 }
1922
1923 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1924 {
1925         bool second_level;
1926         int ret = 0;
1927         struct intel_vgpu *vgpu = s->vgpu;
1928
1929         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1930                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1931                 return -EFAULT;
1932         }
1933
1934         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1935         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1936                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1937                 return -EFAULT;
1938         }
1939
1940         s->saved_buf_addr_type = s->buf_addr_type;
1941         addr_type_update_snb(s);
1942         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1943                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1944                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1945         } else if (second_level) {
1946                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1947                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1948                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1949         }
1950
1951         if (batch_buffer_needs_scan(s)) {
1952                 ret = perform_bb_shadow(s);
1953                 if (ret < 0)
1954                         gvt_vgpu_err("invalid shadow batch buffer\n");
1955         } else {
1956                 /* emulate a batch buffer end to do return right */
1957                 ret = cmd_handler_mi_batch_buffer_end(s);
1958                 if (ret < 0)
1959                         return ret;
1960         }
1961         return ret;
1962 }
1963
1964 static int mi_noop_index;
1965
1966 static const struct cmd_info cmd_info[] = {
1967         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1968
1969         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1970                 0, 1, NULL},
1971
1972         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1973                 0, 1, cmd_handler_mi_user_interrupt},
1974
1975         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1976                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1977
1978         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1979
1980         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1981                 NULL},
1982
1983         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1984                 NULL},
1985
1986         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1987                 NULL},
1988
1989         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1990                 NULL},
1991
1992         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1993                 D_ALL, 0, 1, NULL},
1994
1995         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1996                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1997                 cmd_handler_mi_batch_buffer_end},
1998
1999         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2000                 0, 1, NULL},
2001
2002         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2003                 NULL},
2004
2005         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2006                 D_ALL, 0, 1, NULL},
2007
2008         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2009                 NULL},
2010
2011         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2012                 NULL},
2013
2014         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2015                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2016
2017         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2018                 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2019
2020         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2021
2022         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2023                 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2024
2025         {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2026                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2027                 NULL, CMD_LEN(0)},
2028
2029         {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2030                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2031                 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2032
2033         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2034                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2035
2036         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2037                 0, 8, cmd_handler_mi_store_data_index},
2038
2039         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2040                 D_ALL, 0, 8, cmd_handler_lri},
2041
2042         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2043                 cmd_handler_mi_update_gtt},
2044
2045         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2046                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2047                 cmd_handler_srm, CMD_LEN(2)},
2048
2049         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2050                 cmd_handler_mi_flush_dw},
2051
2052         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2053                 10, cmd_handler_mi_clflush},
2054
2055         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2056                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2057                 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2058
2059         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2060                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2061                 cmd_handler_lrm, CMD_LEN(2)},
2062
2063         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2064                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2065                 cmd_handler_lrr, CMD_LEN(1)},
2066
2067         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2068                 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2069                 8, NULL, CMD_LEN(2)},
2070
2071         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2072                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2073
2074         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2075                 ADDR_FIX_1(2), 8, NULL},
2076
2077         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2078                 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2079
2080         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2081                 8, cmd_handler_mi_op_2f},
2082
2083         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2084                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2085                 cmd_handler_mi_batch_buffer_start},
2086
2087         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2088                 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2089                 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2090
2091         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2092                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2093
2094         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2095                 ADDR_FIX_2(4, 7), 8, NULL},
2096
2097         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2098                 0, 8, NULL},
2099
2100         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2101                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2102
2103         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2104
2105         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2106                 0, 8, NULL},
2107
2108         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2109                 ADDR_FIX_1(3), 8, NULL},
2110
2111         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2112                 D_ALL, 0, 8, NULL},
2113
2114         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2115                 ADDR_FIX_1(4), 8, NULL},
2116
2117         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2118                 ADDR_FIX_2(4, 5), 8, NULL},
2119
2120         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2121                 ADDR_FIX_1(4), 8, NULL},
2122
2123         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2124                 ADDR_FIX_2(4, 7), 8, NULL},
2125
2126         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2127                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2128
2129         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2130
2131         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2132                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2133
2134         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2135                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2136
2137         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2138                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2139                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2140
2141         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2142                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2143
2144         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2145                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2146
2147         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2148                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2149
2150         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2151                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2152
2153         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2154                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2155
2156         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2157                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2158                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2159
2160         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2161                 ADDR_FIX_2(4, 5), 8, NULL},
2162
2163         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2164                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2165
2166         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2167                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2168                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2169
2170         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2171                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2172                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2173
2174         {"3DSTATE_BLEND_STATE_POINTERS",
2175                 OP_3DSTATE_BLEND_STATE_POINTERS,
2176                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2177
2178         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2179                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2180                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2181
2182         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2183                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2184                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2185
2186         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2187                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2188                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2189
2190         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2191                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2192                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2193
2194         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2195                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2196                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2197
2198         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2199                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2200                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2201
2202         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2203                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2204                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2205
2206         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2207                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2208                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2209
2210         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2211                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2212                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2213
2214         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2215                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2216                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2217
2218         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2219                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2220                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2221
2222         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2223                 0, 8, NULL},
2224
2225         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2226                 0, 8, NULL},
2227
2228         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2229                 0, 8, NULL},
2230
2231         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2232                 0, 8, NULL},
2233
2234         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2235                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2236
2237         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2238                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2241                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2242
2243         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2244                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2247                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2248
2249         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2250                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2251
2252         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2253                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2254
2255         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2256                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2257
2258         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2259                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2260
2261         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2262                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2263
2264         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2265                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2266
2267         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2268                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2271                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2272
2273         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2274                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2275
2276         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2277                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2278
2279         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2280                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2281
2282         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2283                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2284
2285         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2286                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2287
2288         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2289                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2290
2291         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2292                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2293
2294         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2295                 D_BDW_PLUS, 0, 8, NULL},
2296
2297         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2298                 NULL},
2299
2300         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2301                 D_BDW_PLUS, 0, 8, NULL},
2302
2303         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2304                 D_BDW_PLUS, 0, 8, NULL},
2305
2306         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2307                 8, NULL},
2308
2309         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2310                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2311
2312         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2313                 8, NULL},
2314
2315         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2316                 NULL},
2317
2318         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2319                 NULL},
2320
2321         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2322                 NULL},
2323
2324         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2325                 D_BDW_PLUS, 0, 8, NULL},
2326
2327         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2328                 R_RCS, D_ALL, 0, 8, NULL},
2329
2330         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2331                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2332
2333         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2334                 R_RCS, D_ALL, 0, 1, NULL},
2335
2336         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2337
2338         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2339                 R_RCS, D_ALL, 0, 8, NULL},
2340
2341         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2342                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2343
2344         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2345
2346         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2347
2348         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349
2350         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2351                 D_BDW_PLUS, 0, 8, NULL},
2352
2353         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2354                 D_BDW_PLUS, 0, 8, NULL},
2355
2356         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2357                 D_ALL, 0, 8, NULL},
2358
2359         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2360                 D_BDW_PLUS, 0, 8, NULL},
2361
2362         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2363                 D_BDW_PLUS, 0, 8, NULL},
2364
2365         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2366
2367         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2368
2369         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2370
2371         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2372                 D_ALL, 0, 8, NULL},
2373
2374         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2375
2376         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2377
2378         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2379                 R_RCS, D_ALL, 0, 8, NULL},
2380
2381         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2382                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2383
2384         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2385                 0, 8, NULL},
2386
2387         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2388                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2389
2390         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2391                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2392
2393         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2394                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2395
2396         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2397                 D_ALL, 0, 8, NULL},
2398
2399         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2400                 D_ALL, 0, 8, NULL},
2401
2402         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2403                 D_ALL, 0, 8, NULL},
2404
2405         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2406                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2407
2408         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2409                 D_BDW_PLUS, 0, 8, NULL},
2410
2411         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2412                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2413
2414         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2415                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2416
2417         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2418                 R_RCS, D_ALL, 0, 8, NULL},
2419
2420         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2421                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2422
2423         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2424                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2425
2426         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2427                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2428
2429         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2430                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2431
2432         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2433                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2434
2435         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2436                 R_RCS, D_ALL, 0, 8, NULL},
2437
2438         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2439                 D_ALL, 0, 9, NULL},
2440
2441         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2442                 ADDR_FIX_2(2, 4), 8, NULL},
2443
2444         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2445                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2446                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2447
2448         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2449                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2450
2451         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2452                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2453                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2454
2455         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2456                 D_BDW_PLUS, 0, 8, NULL},
2457
2458         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2459                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2460
2461         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2462
2463         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2464                 1, NULL},
2465
2466         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2467                 ADDR_FIX_1(1), 8, NULL},
2468
2469         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2470
2471         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2472                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2473
2474         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2475                 ADDR_FIX_1(1), 8, NULL},
2476
2477         {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2478                 F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2479
2480         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2481
2482         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2483
2484         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2485                 0, 8, NULL},
2486
2487         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2488                 D_SKL_PLUS, 0, 8, NULL},
2489
2490         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2491                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2492
2493         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2494                 0, 16, NULL},
2495
2496         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2497                 0, 16, NULL},
2498
2499         {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2500                 0, 16, NULL},
2501
2502         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2503
2504         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2505                 0, 16, NULL},
2506
2507         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2508                 0, 16, NULL},
2509
2510         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2511                 0, 16, NULL},
2512
2513         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2514                 0, 8, NULL},
2515
2516         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2517                 NULL},
2518
2519         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2520                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2521
2522         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2523                 R_VCS, D_ALL, 0, 12, NULL},
2524
2525         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2526                 R_VCS, D_ALL, 0, 12, NULL},
2527
2528         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2529                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2530
2531         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2532                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2533
2534         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2535                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2536
2537         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2538
2539         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2540                 R_VCS, D_ALL, 0, 12, NULL},
2541
2542         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2543                 R_VCS, D_ALL, 0, 12, NULL},
2544
2545         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2546                 R_VCS, D_ALL, 0, 12, NULL},
2547
2548         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2549                 R_VCS, D_ALL, 0, 12, NULL},
2550
2551         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2552                 R_VCS, D_ALL, 0, 12, NULL},
2553
2554         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2555                 R_VCS, D_ALL, 0, 12, NULL},
2556
2557         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2558                 R_VCS, D_ALL, 0, 6, NULL},
2559
2560         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2561                 R_VCS, D_ALL, 0, 12, NULL},
2562
2563         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2564                 R_VCS, D_ALL, 0, 12, NULL},
2565
2566         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2567                 R_VCS, D_ALL, 0, 12, NULL},
2568
2569         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2570                 R_VCS, D_ALL, 0, 12, NULL},
2571
2572         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2573                 R_VCS, D_ALL, 0, 12, NULL},
2574
2575         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2576                 R_VCS, D_ALL, 0, 12, NULL},
2577
2578         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2579                 R_VCS, D_ALL, 0, 12, NULL},
2580         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2581                 R_VCS, D_ALL, 0, 12, NULL},
2582
2583         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2584                 R_VCS, D_ALL, 0, 12, NULL},
2585
2586         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2587                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2588
2589         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2590                 R_VCS, D_ALL, 0, 12, NULL},
2591
2592         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2593                 R_VCS, D_ALL, 0, 12, NULL},
2594
2595         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2596                 R_VCS, D_ALL, 0, 12, NULL},
2597
2598         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2599                 R_VCS, D_ALL, 0, 12, NULL},
2600
2601         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2602                 R_VCS, D_ALL, 0, 12, NULL},
2603
2604         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2605                 R_VCS, D_ALL, 0, 12, NULL},
2606
2607         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2608                 R_VCS, D_ALL, 0, 12, NULL},
2609
2610         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2611                 R_VCS, D_ALL, 0, 12, NULL},
2612
2613         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2614                 R_VCS, D_ALL, 0, 12, NULL},
2615
2616         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2617                 R_VCS, D_ALL, 0, 12, NULL},
2618
2619         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2620                 R_VCS, D_ALL, 0, 12, NULL},
2621
2622         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2623                 0, 16, NULL},
2624
2625         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2626
2627         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2628
2629         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2630                 R_VCS, D_ALL, 0, 12, NULL},
2631
2632         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2633                 R_VCS, D_ALL, 0, 12, NULL},
2634
2635         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2636                 R_VCS, D_ALL, 0, 12, NULL},
2637
2638         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2639
2640         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2641                 0, 12, NULL},
2642
2643         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2644                 0, 12, NULL},
2645 };
2646
2647 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2648 {
2649         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2650 }
2651
2652 /* call the cmd handler, and advance ip */
2653 static int cmd_parser_exec(struct parser_exec_state *s)
2654 {
2655         struct intel_vgpu *vgpu = s->vgpu;
2656         const struct cmd_info *info;
2657         u32 cmd;
2658         int ret = 0;
2659
2660         cmd = cmd_val(s, 0);
2661
2662         /* fastpath for MI_NOOP */
2663         if (cmd == MI_NOOP)
2664                 info = &cmd_info[mi_noop_index];
2665         else
2666                 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2667
2668         if (info == NULL) {
2669                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2670                              cmd, get_opcode(cmd, s->engine),
2671                              repr_addr_type(s->buf_addr_type),
2672                              s->engine->name, s->workload);
2673                 return -EBADRQC;
2674         }
2675
2676         s->info = info;
2677
2678         trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2679                           cmd_length(s), s->buf_type, s->buf_addr_type,
2680                           s->workload, info->name);
2681
2682         if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2683                 ret = gvt_check_valid_cmd_length(cmd_length(s),
2684                                                  info->valid_len);
2685                 if (ret)
2686                         return ret;
2687         }
2688
2689         if (info->handler) {
2690                 ret = info->handler(s);
2691                 if (ret < 0) {
2692                         gvt_vgpu_err("%s handler error\n", info->name);
2693                         return ret;
2694                 }
2695         }
2696
2697         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2698                 ret = cmd_advance_default(s);
2699                 if (ret) {
2700                         gvt_vgpu_err("%s IP advance error\n", info->name);
2701                         return ret;
2702                 }
2703         }
2704         return 0;
2705 }
2706
2707 static inline bool gma_out_of_range(unsigned long gma,
2708                 unsigned long gma_head, unsigned int gma_tail)
2709 {
2710         if (gma_tail >= gma_head)
2711                 return (gma < gma_head) || (gma > gma_tail);
2712         else
2713                 return (gma > gma_tail) && (gma < gma_head);
2714 }
2715
2716 /* Keep the consistent return type, e.g EBADRQC for unknown
2717  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2718  * works as the input of VM healthy status.
2719  */
2720 static int command_scan(struct parser_exec_state *s,
2721                 unsigned long rb_head, unsigned long rb_tail,
2722                 unsigned long rb_start, unsigned long rb_len)
2723 {
2724
2725         unsigned long gma_head, gma_tail, gma_bottom;
2726         int ret = 0;
2727         struct intel_vgpu *vgpu = s->vgpu;
2728
2729         gma_head = rb_start + rb_head;
2730         gma_tail = rb_start + rb_tail;
2731         gma_bottom = rb_start +  rb_len;
2732
2733         while (s->ip_gma != gma_tail) {
2734                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2735                         if (!(s->ip_gma >= rb_start) ||
2736                                 !(s->ip_gma < gma_bottom)) {
2737                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2738                                         "(base:0x%lx, bottom: 0x%lx)\n",
2739                                         s->ip_gma, rb_start,
2740                                         gma_bottom);
2741                                 parser_exec_state_dump(s);
2742                                 return -EFAULT;
2743                         }
2744                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2745                                 gvt_vgpu_err("ip_gma %lx out of range."
2746                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2747                                         s->ip_gma, rb_start,
2748                                         rb_head, rb_tail);
2749                                 parser_exec_state_dump(s);
2750                                 break;
2751                         }
2752                 }
2753                 ret = cmd_parser_exec(s);
2754                 if (ret) {
2755                         gvt_vgpu_err("cmd parser error\n");
2756                         parser_exec_state_dump(s);
2757                         break;
2758                 }
2759         }
2760
2761         return ret;
2762 }
2763
2764 static int scan_workload(struct intel_vgpu_workload *workload)
2765 {
2766         unsigned long gma_head, gma_tail, gma_bottom;
2767         struct parser_exec_state s;
2768         int ret = 0;
2769
2770         /* ring base is page aligned */
2771         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2772                 return -EINVAL;
2773
2774         gma_head = workload->rb_start + workload->rb_head;
2775         gma_tail = workload->rb_start + workload->rb_tail;
2776         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2777
2778         s.buf_type = RING_BUFFER_INSTRUCTION;
2779         s.buf_addr_type = GTT_BUFFER;
2780         s.vgpu = workload->vgpu;
2781         s.engine = workload->engine;
2782         s.ring_start = workload->rb_start;
2783         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2784         s.ring_head = gma_head;
2785         s.ring_tail = gma_tail;
2786         s.rb_va = workload->shadow_ring_buffer_va;
2787         s.workload = workload;
2788         s.is_ctx_wa = false;
2789
2790         if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2791                 return 0;
2792
2793         ret = ip_gma_set(&s, gma_head);
2794         if (ret)
2795                 goto out;
2796
2797         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2798                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2799
2800 out:
2801         return ret;
2802 }
2803
2804 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2805 {
2806
2807         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2808         struct parser_exec_state s;
2809         int ret = 0;
2810         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2811                                 struct intel_vgpu_workload,
2812                                 wa_ctx);
2813
2814         /* ring base is page aligned */
2815         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2816                                         I915_GTT_PAGE_SIZE)))
2817                 return -EINVAL;
2818
2819         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2820         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2821                         PAGE_SIZE);
2822         gma_head = wa_ctx->indirect_ctx.guest_gma;
2823         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2824         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2825
2826         s.buf_type = RING_BUFFER_INSTRUCTION;
2827         s.buf_addr_type = GTT_BUFFER;
2828         s.vgpu = workload->vgpu;
2829         s.engine = workload->engine;
2830         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2831         s.ring_size = ring_size;
2832         s.ring_head = gma_head;
2833         s.ring_tail = gma_tail;
2834         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2835         s.workload = workload;
2836         s.is_ctx_wa = true;
2837
2838         ret = ip_gma_set(&s, gma_head);
2839         if (ret)
2840                 goto out;
2841
2842         ret = command_scan(&s, 0, ring_tail,
2843                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2844 out:
2845         return ret;
2846 }
2847
2848 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2849 {
2850         struct intel_vgpu *vgpu = workload->vgpu;
2851         struct intel_vgpu_submission *s = &vgpu->submission;
2852         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2853         void *shadow_ring_buffer_va;
2854         int ret;
2855
2856         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2857
2858         /* calculate workload ring buffer size */
2859         workload->rb_len = (workload->rb_tail + guest_rb_size -
2860                         workload->rb_head) % guest_rb_size;
2861
2862         gma_head = workload->rb_start + workload->rb_head;
2863         gma_tail = workload->rb_start + workload->rb_tail;
2864         gma_top = workload->rb_start + guest_rb_size;
2865
2866         if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2867                 void *p;
2868
2869                 /* realloc the new ring buffer if needed */
2870                 p = krealloc(s->ring_scan_buffer[workload->engine->id],
2871                              workload->rb_len, GFP_KERNEL);
2872                 if (!p) {
2873                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2874                         return -ENOMEM;
2875                 }
2876                 s->ring_scan_buffer[workload->engine->id] = p;
2877                 s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2878         }
2879
2880         shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2881
2882         /* get shadow ring buffer va */
2883         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2884
2885         /* head > tail --> copy head <-> top */
2886         if (gma_head > gma_tail) {
2887                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2888                                       gma_head, gma_top, shadow_ring_buffer_va);
2889                 if (ret < 0) {
2890                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2891                         return ret;
2892                 }
2893                 shadow_ring_buffer_va += ret;
2894                 gma_head = workload->rb_start;
2895         }
2896
2897         /* copy head or start <-> tail */
2898         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2899                                 shadow_ring_buffer_va);
2900         if (ret < 0) {
2901                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2902                 return ret;
2903         }
2904         return 0;
2905 }
2906
2907 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2908 {
2909         int ret;
2910         struct intel_vgpu *vgpu = workload->vgpu;
2911
2912         ret = shadow_workload_ring_buffer(workload);
2913         if (ret) {
2914                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2915                 return ret;
2916         }
2917
2918         ret = scan_workload(workload);
2919         if (ret) {
2920                 gvt_vgpu_err("scan workload error\n");
2921                 return ret;
2922         }
2923         return 0;
2924 }
2925
2926 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2927 {
2928         int ctx_size = wa_ctx->indirect_ctx.size;
2929         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2930         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2931                                         struct intel_vgpu_workload,
2932                                         wa_ctx);
2933         struct intel_vgpu *vgpu = workload->vgpu;
2934         struct drm_i915_gem_object *obj;
2935         int ret = 0;
2936         void *map;
2937
2938         obj = i915_gem_object_create_shmem(workload->engine->i915,
2939                                            roundup(ctx_size + CACHELINE_BYTES,
2940                                                    PAGE_SIZE));
2941         if (IS_ERR(obj))
2942                 return PTR_ERR(obj);
2943
2944         /* get the va of the shadow batch buffer */
2945         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2946         if (IS_ERR(map)) {
2947                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2948                 ret = PTR_ERR(map);
2949                 goto put_obj;
2950         }
2951
2952         i915_gem_object_lock(obj);
2953         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2954         i915_gem_object_unlock(obj);
2955         if (ret) {
2956                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2957                 goto unmap_src;
2958         }
2959
2960         ret = copy_gma_to_hva(workload->vgpu,
2961                                 workload->vgpu->gtt.ggtt_mm,
2962                                 guest_gma, guest_gma + ctx_size,
2963                                 map);
2964         if (ret < 0) {
2965                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2966                 goto unmap_src;
2967         }
2968
2969         wa_ctx->indirect_ctx.obj = obj;
2970         wa_ctx->indirect_ctx.shadow_va = map;
2971         return 0;
2972
2973 unmap_src:
2974         i915_gem_object_unpin_map(obj);
2975 put_obj:
2976         i915_gem_object_put(obj);
2977         return ret;
2978 }
2979
2980 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2981 {
2982         u32 per_ctx_start[CACHELINE_DWORDS] = {0};
2983         unsigned char *bb_start_sva;
2984
2985         if (!wa_ctx->per_ctx.valid)
2986                 return 0;
2987
2988         per_ctx_start[0] = 0x18800001;
2989         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2990
2991         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2992                                 wa_ctx->indirect_ctx.size;
2993
2994         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2995
2996         return 0;
2997 }
2998
2999 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3000 {
3001         int ret;
3002         struct intel_vgpu_workload *workload = container_of(wa_ctx,
3003                                         struct intel_vgpu_workload,
3004                                         wa_ctx);
3005         struct intel_vgpu *vgpu = workload->vgpu;
3006
3007         if (wa_ctx->indirect_ctx.size == 0)
3008                 return 0;
3009
3010         ret = shadow_indirect_ctx(wa_ctx);
3011         if (ret) {
3012                 gvt_vgpu_err("fail to shadow indirect ctx\n");
3013                 return ret;
3014         }
3015
3016         combine_wa_ctx(wa_ctx);
3017
3018         ret = scan_wa_ctx(wa_ctx);
3019         if (ret) {
3020                 gvt_vgpu_err("scan wa ctx error\n");
3021                 return ret;
3022         }
3023
3024         return 0;
3025 }
3026
3027 static int init_cmd_table(struct intel_gvt *gvt)
3028 {
3029         unsigned int gen_type = intel_gvt_get_device_type(gvt);
3030         int i;
3031
3032         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3033                 struct cmd_entry *e;
3034
3035                 if (!(cmd_info[i].devices & gen_type))
3036                         continue;
3037
3038                 e = kzalloc(sizeof(*e), GFP_KERNEL);
3039                 if (!e)
3040                         return -ENOMEM;
3041
3042                 e->info = &cmd_info[i];
3043                 if (cmd_info[i].opcode == OP_MI_NOOP)
3044                         mi_noop_index = i;
3045
3046                 INIT_HLIST_NODE(&e->hlist);
3047                 add_cmd_entry(gvt, e);
3048                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3049                             e->info->name, e->info->opcode, e->info->flag,
3050                             e->info->devices, e->info->rings);
3051         }
3052
3053         return 0;
3054 }
3055
3056 static void clean_cmd_table(struct intel_gvt *gvt)
3057 {
3058         struct hlist_node *tmp;
3059         struct cmd_entry *e;
3060         int i;
3061
3062         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3063                 kfree(e);
3064
3065         hash_init(gvt->cmd_table);
3066 }
3067
3068 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3069 {
3070         clean_cmd_table(gvt);
3071 }
3072
3073 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3074 {
3075         int ret;
3076
3077         ret = init_cmd_table(gvt);
3078         if (ret) {
3079                 intel_gvt_clean_cmd_parser(gvt);
3080                 return ret;
3081         }
3082         return 0;
3083 }