2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
29 * Tina Zhang <tina.zhang@intel.com>
30 * Min He <min.he@intel.com>
31 * Niu Bing <bing.niu@intel.com>
32 * Zhi Wang <zhi.a.wang@intel.com>
40 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
44 * Zero on success, negative error code if failed
46 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
48 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
49 return gpa - gttmmio_gpa;
52 #define reg_is_mmio(gvt, reg) \
53 (reg >= 0 && reg < gvt->device_info.mmio_size)
55 #define reg_is_gtt(gvt, reg) \
56 (reg >= gvt->device_info.gtt_start_offset \
57 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
59 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
60 void *p_data, unsigned int bytes, bool read)
62 struct intel_gvt *gvt = NULL;
64 unsigned int offset = 0;
70 mutex_lock(&gvt->lock);
71 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
72 if (reg_is_mmio(gvt, offset)) {
74 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
77 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
79 } else if (reg_is_gtt(gvt, offset)) {
80 offset -= gvt->device_info.gtt_start_offset;
81 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
83 memcpy(p_data, pt, bytes);
85 memcpy(pt, p_data, bytes);
88 mutex_unlock(&gvt->lock);
92 * intel_vgpu_emulate_mmio_read - emulate MMIO read
94 * @pa: guest physical address
95 * @p_data: data return buffer
96 * @bytes: access data length
99 * Zero on success, negative error code if failed
101 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
102 void *p_data, unsigned int bytes)
104 struct intel_gvt *gvt = vgpu->gvt;
105 unsigned int offset = 0;
108 if (vgpu->failsafe) {
109 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
112 mutex_lock(&gvt->lock);
114 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
116 if (WARN_ON(bytes > 8))
119 if (reg_is_gtt(gvt, offset)) {
120 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
122 if (WARN_ON(bytes != 4 && bytes != 8))
124 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
127 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
134 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
135 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
139 if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
142 if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
143 if (WARN_ON(!IS_ALIGNED(offset, bytes)))
147 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
151 intel_gvt_mmio_set_accessed(gvt, offset);
156 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
159 mutex_unlock(&gvt->lock);
164 * intel_vgpu_emulate_mmio_write - emulate MMIO write
166 * @pa: guest physical address
167 * @p_data: write data buffer
168 * @bytes: access data length
171 * Zero on success, negative error code if failed
173 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
174 void *p_data, unsigned int bytes)
176 struct intel_gvt *gvt = vgpu->gvt;
177 unsigned int offset = 0;
180 if (vgpu->failsafe) {
181 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
185 mutex_lock(&gvt->lock);
187 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
189 if (WARN_ON(bytes > 8))
192 if (reg_is_gtt(gvt, offset)) {
193 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
195 if (WARN_ON(bytes != 4 && bytes != 8))
197 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
200 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
207 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
208 ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
212 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
216 intel_gvt_mmio_set_accessed(gvt, offset);
220 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
223 mutex_unlock(&gvt->lock);
229 * intel_vgpu_reset_mmio - reset virtual MMIO space
233 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
235 struct intel_gvt *gvt = vgpu->gvt;
236 const struct intel_gvt_device_info *info = &gvt->device_info;
237 void *mmio = gvt->firmware.mmio;
240 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
241 memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
243 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
245 /* set the bit 0:2(Core C-State ) to C0 */
246 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
248 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
249 /* only reset the engine related, so starting with 0x44200
250 * interrupt include DE,display mmio related will not be
253 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
254 memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
260 * intel_vgpu_init_mmio - init MMIO space
264 * Zero on success, negative error code if failed
266 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
268 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
270 vgpu->mmio.vreg = vzalloc(info->mmio_size * 2);
271 if (!vgpu->mmio.vreg)
274 vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
276 intel_vgpu_reset_mmio(vgpu, true);
282 * intel_vgpu_clean_mmio - clean MMIO space
286 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
288 vfree(vgpu->mmio.vreg);
289 vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;