drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include <linux/sched/mm.h>
  32 #include "intel_drv.h"
  33 #include "i915_guc_submission.h"
  34
  35 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  36 {
  37         return to_i915(node->minor->dev);
  38 }
  39
  40 static __always_inline void seq_print_param(struct seq_file *m,
  41                                             const char *name,
  42                                             const char *type,
  43                                             const void *x)
  44 {
  45         if (!__builtin_strcmp(type, "bool"))
  46                 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
  47         else if (!__builtin_strcmp(type, "int"))
  48                 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
  49         else if (!__builtin_strcmp(type, "unsigned int"))
  50                 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
  51         else if (!__builtin_strcmp(type, "char *"))
  52                 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
  53         else
  54                 BUILD_BUG();
  55 }
  56
  57 static int i915_capabilities(struct seq_file *m, void *data)
  58 {
  59         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  60         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  61
  62         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  63         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  64         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  65
  66 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  67         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  68 #undef PRINT_FLAG
  69
  70         kernel_param_lock(THIS_MODULE);
  71 #define PRINT_PARAM(T, x, ...) seq_print_param(m, #x, #T, &i915_modparams.x);
  72         I915_PARAMS_FOR_EACH(PRINT_PARAM);
  73 #undef PRINT_PARAM
  74         kernel_param_unlock(THIS_MODULE);
  75
  76         return 0;
  77 }
  78
  79 static char get_active_flag(struct drm_i915_gem_object *obj)
  80 {
  81         return i915_gem_object_is_active(obj) ? '*' : ' ';
  82 }
  83
  84 static char get_pin_flag(struct drm_i915_gem_object *obj)
  85 {
  86         return obj->pin_global ? 'p' : ' ';
  87 }
  88
  89 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  90 {
  91         switch (i915_gem_object_get_tiling(obj)) {
  92         default:
  93         case I915_TILING_NONE: return ' ';
  94         case I915_TILING_X: return 'X';
  95         case I915_TILING_Y: return 'Y';
  96         }
  97 }
  98
  99 static char get_global_flag(struct drm_i915_gem_object *obj)
 100 {
 101         return obj->userfault_count ? 'g' : ' ';
 102 }
 103
 104 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 105 {
 106         return obj->mm.mapping ? 'M' : ' ';
 107 }
 108
 109 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 110 {
 111         u64 size = 0;
 112         struct i915_vma *vma;
 113
 114         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 115                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 116                         size += vma->node.size;
 117         }
 118
 119         return size;
 120 }
 121
 122 static const char *
 123 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
 124 {
 125         size_t x = 0;
 126
 127         switch (page_sizes) {
 128         case 0:
 129                 return "";
 130         case I915_GTT_PAGE_SIZE_4K:
 131                 return "4K";
 132         case I915_GTT_PAGE_SIZE_64K:
 133                 return "64K";
 134         case I915_GTT_PAGE_SIZE_2M:
 135                 return "2M";
 136         default:
 137                 if (!buf)
 138                         return "M";
 139
 140                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 141                         x += snprintf(buf + x, len - x, "2M, ");
 142                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 143                         x += snprintf(buf + x, len - x, "64K, ");
 144                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 145                         x += snprintf(buf + x, len - x, "4K, ");
 146                 buf[x-2] = '\0';
 147
 148                 return buf;
 149         }
 150 }
 151
 152 static void
 153 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 154 {
 155         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 156         struct intel_engine_cs *engine;
 157         struct i915_vma *vma;
 158         unsigned int frontbuffer_bits;
 159         int pin_count = 0;
 160
 161         lockdep_assert_held(&obj->base.dev->struct_mutex);
 162
 163         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 164                    &obj->base,
 165                    get_active_flag(obj),
 166                    get_pin_flag(obj),
 167                    get_tiling_flag(obj),
 168                    get_global_flag(obj),
 169                    get_pin_mapped_flag(obj),
 170                    obj->base.size / 1024,
 171                    obj->base.read_domains,
 172                    obj->base.write_domain,
 173                    i915_cache_level_str(dev_priv, obj->cache_level),
 174                    obj->mm.dirty ? " dirty" : "",
 175                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 176         if (obj->base.name)
 177                 seq_printf(m, " (name: %d)", obj->base.name);
 178         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 179                 if (i915_vma_is_pinned(vma))
 180                         pin_count++;
 181         }
 182         seq_printf(m, " (pinned x %d)", pin_count);
 183         if (obj->pin_global)
 184                 seq_printf(m, " (global)");
 185         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 186                 if (!drm_mm_node_allocated(&vma->node))
 187                         continue;
 188
 189                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 190                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 191                            vma->node.start, vma->node.size,
 192                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 193                 if (i915_vma_is_ggtt(vma)) {
 194                         switch (vma->ggtt_view.type) {
 195                         case I915_GGTT_VIEW_NORMAL:
 196                                 seq_puts(m, ", normal");
 197                                 break;
 198
 199                         case I915_GGTT_VIEW_PARTIAL:
 200                                 seq_printf(m, ", partial [%08llx+%x]",
 201                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 202                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 203                                 break;
 204
 205                         case I915_GGTT_VIEW_ROTATED:
 206                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 207                                            vma->ggtt_view.rotated.plane[0].width,
 208                                            vma->ggtt_view.rotated.plane[0].height,
 209                                            vma->ggtt_view.rotated.plane[0].stride,
 210                                            vma->ggtt_view.rotated.plane[0].offset,
 211                                            vma->ggtt_view.rotated.plane[1].width,
 212                                            vma->ggtt_view.rotated.plane[1].height,
 213                                            vma->ggtt_view.rotated.plane[1].stride,
 214                                            vma->ggtt_view.rotated.plane[1].offset);
 215                                 break;
 216
 217                         default:
 218                                 MISSING_CASE(vma->ggtt_view.type);
 219                                 break;
 220                         }
 221                 }
 222                 if (vma->fence)
 223                         seq_printf(m, " , fence: %d%s",
 224                                    vma->fence->id,
 225                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 226                 seq_puts(m, ")");
 227         }
 228         if (obj->stolen)
 229                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 230
 231         engine = i915_gem_object_last_write_engine(obj);
 232         if (engine)
 233                 seq_printf(m, " (%s)", engine->name);
 234
 235         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 236         if (frontbuffer_bits)
 237                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 238 }
 239
 240 static int obj_rank_by_stolen(const void *A, const void *B)
 241 {
 242         const struct drm_i915_gem_object *a =
 243                 *(const struct drm_i915_gem_object **)A;
 244         const struct drm_i915_gem_object *b =
 245                 *(const struct drm_i915_gem_object **)B;
 246
 247         if (a->stolen->start < b->stolen->start)
 248                 return -1;
 249         if (a->stolen->start > b->stolen->start)
 250                 return 1;
 251         return 0;
 252 }
 253
 254 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 255 {
 256         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 257         struct drm_device *dev = &dev_priv->drm;
 258         struct drm_i915_gem_object **objects;
 259         struct drm_i915_gem_object *obj;
 260         u64 total_obj_size, total_gtt_size;
 261         unsigned long total, count, n;
 262         int ret;
 263
 264         total = READ_ONCE(dev_priv->mm.object_count);
 265         objects = kvmalloc_array(total, sizeof(*objects), GFP_KERNEL);
 266         if (!objects)
 267                 return -ENOMEM;
 268
 269         ret = mutex_lock_interruptible(&dev->struct_mutex);
 270         if (ret)
 271                 goto out;
 272
 273         total_obj_size = total_gtt_size = count = 0;
 274         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 275                 if (count == total)
 276                         break;
 277
 278                 if (obj->stolen == NULL)
 279                         continue;
 280
 281                 objects[count++] = obj;
 282                 total_obj_size += obj->base.size;
 283                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 284
 285         }
 286         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 287                 if (count == total)
 288                         break;
 289
 290                 if (obj->stolen == NULL)
 291                         continue;
 292
 293                 objects[count++] = obj;
 294                 total_obj_size += obj->base.size;
 295         }
 296
 297         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 298
 299         seq_puts(m, "Stolen:\n");
 300         for (n = 0; n < count; n++) {
 301                 seq_puts(m, "   ");
 302                 describe_obj(m, objects[n]);
 303                 seq_putc(m, '\n');
 304         }
 305         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 306                    count, total_obj_size, total_gtt_size);
 307
 308         mutex_unlock(&dev->struct_mutex);
 309 out:
 310         kvfree(objects);
 311         return ret;
 312 }
 313
 314 struct file_stats {
 315         struct drm_i915_file_private *file_priv;
 316         unsigned long count;
 317         u64 total, unbound;
 318         u64 global, shared;
 319         u64 active, inactive;
 320 };
 321
 322 static int per_file_stats(int id, void *ptr, void *data)
 323 {
 324         struct drm_i915_gem_object *obj = ptr;
 325         struct file_stats *stats = data;
 326         struct i915_vma *vma;
 327
 328         lockdep_assert_held(&obj->base.dev->struct_mutex);
 329
 330         stats->count++;
 331         stats->total += obj->base.size;
 332         if (!obj->bind_count)
 333                 stats->unbound += obj->base.size;
 334         if (obj->base.name || obj->base.dma_buf)
 335                 stats->shared += obj->base.size;
 336
 337         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 338                 if (!drm_mm_node_allocated(&vma->node))
 339                         continue;
 340
 341                 if (i915_vma_is_ggtt(vma)) {
 342                         stats->global += vma->node.size;
 343                 } else {
 344                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 345
 346                         if (ppgtt->base.file != stats->file_priv)
 347                                 continue;
 348                 }
 349
 350                 if (i915_vma_is_active(vma))
 351                         stats->active += vma->node.size;
 352                 else
 353                         stats->inactive += vma->node.size;
 354         }
 355
 356         return 0;
 357 }
 358
 359 #define print_file_stats(m, name, stats) do { \
 360         if (stats.count) \
 361                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 362                            name, \
 363                            stats.count, \
 364                            stats.total, \
 365                            stats.active, \
 366                            stats.inactive, \
 367                            stats.global, \
 368                            stats.shared, \
 369                            stats.unbound); \
 370 } while (0)
 371
 372 static void print_batch_pool_stats(struct seq_file *m,
 373                                    struct drm_i915_private *dev_priv)
 374 {
 375         struct drm_i915_gem_object *obj;
 376         struct file_stats stats;
 377         struct intel_engine_cs *engine;
 378         enum intel_engine_id id;
 379         int j;
 380
 381         memset(&stats, 0, sizeof(stats));
 382
 383         for_each_engine(engine, dev_priv, id) {
 384                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 385                         list_for_each_entry(obj,
 386                                             &engine->batch_pool.cache_list[j],
 387                                             batch_pool_link)
 388                                 per_file_stats(0, obj, &stats);
 389                 }
 390         }
 391
 392         print_file_stats(m, "[k]batch pool", stats);
 393 }
 394
 395 static int per_file_ctx_stats(int id, void *ptr, void *data)
 396 {
 397         struct i915_gem_context *ctx = ptr;
 398         int n;
 399
 400         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 401                 if (ctx->engine[n].state)
 402                         per_file_stats(0, ctx->engine[n].state->obj, data);
 403                 if (ctx->engine[n].ring)
 404                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 405         }
 406
 407         return 0;
 408 }
 409
 410 static void print_context_stats(struct seq_file *m,
 411                                 struct drm_i915_private *dev_priv)
 412 {
 413         struct drm_device *dev = &dev_priv->drm;
 414         struct file_stats stats;
 415         struct drm_file *file;
 416
 417         memset(&stats, 0, sizeof(stats));
 418
 419         mutex_lock(&dev->struct_mutex);
 420         if (dev_priv->kernel_context)
 421                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 422
 423         list_for_each_entry(file, &dev->filelist, lhead) {
 424                 struct drm_i915_file_private *fpriv = file->driver_priv;
 425                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 426         }
 427         mutex_unlock(&dev->struct_mutex);
 428
 429         print_file_stats(m, "[k]contexts", stats);
 430 }
 431
 432 static int i915_gem_object_info(struct seq_file *m, void *data)
 433 {
 434         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 435         struct drm_device *dev = &dev_priv->drm;
 436         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 437         u32 count, mapped_count, purgeable_count, dpy_count, huge_count;
 438         u64 size, mapped_size, purgeable_size, dpy_size, huge_size;
 439         struct drm_i915_gem_object *obj;
 440         unsigned int page_sizes = 0;
 441         struct drm_file *file;
 442         char buf[80];
 443         int ret;
 444
 445         ret = mutex_lock_interruptible(&dev->struct_mutex);
 446         if (ret)
 447                 return ret;
 448
 449         seq_printf(m, "%u objects, %llu bytes\n",
 450                    dev_priv->mm.object_count,
 451                    dev_priv->mm.object_memory);
 452
 453         size = count = 0;
 454         mapped_size = mapped_count = 0;
 455         purgeable_size = purgeable_count = 0;
 456         huge_size = huge_count = 0;
 457         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 458                 size += obj->base.size;
 459                 ++count;
 460
 461                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 462                         purgeable_size += obj->base.size;
 463                         ++purgeable_count;
 464                 }
 465
 466                 if (obj->mm.mapping) {
 467                         mapped_count++;
 468                         mapped_size += obj->base.size;
 469                 }
 470
 471                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 472                         huge_count++;
 473                         huge_size += obj->base.size;
 474                         page_sizes |= obj->mm.page_sizes.sg;
 475                 }
 476         }
 477         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 478
 479         size = count = dpy_size = dpy_count = 0;
 480         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 481                 size += obj->base.size;
 482                 ++count;
 483
 484                 if (obj->pin_global) {
 485                         dpy_size += obj->base.size;
 486                         ++dpy_count;
 487                 }
 488
 489                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 490                         purgeable_size += obj->base.size;
 491                         ++purgeable_count;
 492                 }
 493
 494                 if (obj->mm.mapping) {
 495                         mapped_count++;
 496                         mapped_size += obj->base.size;
 497                 }
 498
 499                 if (obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) {
 500                         huge_count++;
 501                         huge_size += obj->base.size;
 502                         page_sizes |= obj->mm.page_sizes.sg;
 503                 }
 504         }
 505         seq_printf(m, "%u bound objects, %llu bytes\n",
 506                    count, size);
 507         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 508                    purgeable_count, purgeable_size);
 509         seq_printf(m, "%u mapped objects, %llu bytes\n",
 510                    mapped_count, mapped_size);
 511         seq_printf(m, "%u huge-paged objects (%s) %llu bytes\n",
 512                    huge_count,
 513                    stringify_page_sizes(page_sizes, buf, sizeof(buf)),
 514                    huge_size);
 515         seq_printf(m, "%u display objects (globally pinned), %llu bytes\n",
 516                    dpy_count, dpy_size);
 517
 518         seq_printf(m, "%llu [%llu] gtt total\n",
 519                    ggtt->base.total, ggtt->mappable_end);
 520         seq_printf(m, "Supported page sizes: %s\n",
 521                    stringify_page_sizes(INTEL_INFO(dev_priv)->page_sizes,
 522                                         buf, sizeof(buf)));
 523
 524         seq_putc(m, '\n');
 525         print_batch_pool_stats(m, dev_priv);
 526         mutex_unlock(&dev->struct_mutex);
 527
 528         mutex_lock(&dev->filelist_mutex);
 529         print_context_stats(m, dev_priv);
 530         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 531                 struct file_stats stats;
 532                 struct drm_i915_file_private *file_priv = file->driver_priv;
 533                 struct drm_i915_gem_request *request;
 534                 struct task_struct *task;
 535
 536                 mutex_lock(&dev->struct_mutex);
 537
 538                 memset(&stats, 0, sizeof(stats));
 539                 stats.file_priv = file->driver_priv;
 540                 spin_lock(&file->table_lock);
 541                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 542                 spin_unlock(&file->table_lock);
 543                 /*
 544                  * Although we have a valid reference on file->pid, that does
 545                  * not guarantee that the task_struct who called get_pid() is
 546                  * still alive (e.g. get_pid(current) => fork() => exit()).
 547                  * Therefore, we need to protect this ->comm access using RCU.
 548                  */
 549                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 550                                                    struct drm_i915_gem_request,
 551                                                    client_link);
 552                 rcu_read_lock();
 553                 task = pid_task(request && request->ctx->pid ?
 554                                 request->ctx->pid : file->pid,
 555                                 PIDTYPE_PID);
 556                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 557                 rcu_read_unlock();
 558
 559                 mutex_unlock(&dev->struct_mutex);
 560         }
 561         mutex_unlock(&dev->filelist_mutex);
 562
 563         return 0;
 564 }
 565
 566 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 567 {
 568         struct drm_info_node *node = m->private;
 569         struct drm_i915_private *dev_priv = node_to_i915(node);
 570         struct drm_device *dev = &dev_priv->drm;
 571         struct drm_i915_gem_object *obj;
 572         u64 total_obj_size, total_gtt_size;
 573         int count, ret;
 574
 575         ret = mutex_lock_interruptible(&dev->struct_mutex);
 576         if (ret)
 577                 return ret;
 578
 579         total_obj_size = total_gtt_size = count = 0;
 580         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 581                 seq_puts(m, "   ");
 582                 describe_obj(m, obj);
 583                 seq_putc(m, '\n');
 584                 total_obj_size += obj->base.size;
 585                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 586                 count++;
 587         }
 588
 589         mutex_unlock(&dev->struct_mutex);
 590
 591         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 592                    count, total_obj_size, total_gtt_size);
 593
 594         return 0;
 595 }
 596
 597 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 598 {
 599         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 600         struct drm_device *dev = &dev_priv->drm;
 601         struct drm_i915_gem_object *obj;
 602         struct intel_engine_cs *engine;
 603         enum intel_engine_id id;
 604         int total = 0;
 605         int ret, j;
 606
 607         ret = mutex_lock_interruptible(&dev->struct_mutex);
 608         if (ret)
 609                 return ret;
 610
 611         for_each_engine(engine, dev_priv, id) {
 612                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 613                         int count;
 614
 615                         count = 0;
 616                         list_for_each_entry(obj,
 617                                             &engine->batch_pool.cache_list[j],
 618                                             batch_pool_link)
 619                                 count++;
 620                         seq_printf(m, "%s cache[%d]: %d objects\n",
 621                                    engine->name, j, count);
 622
 623                         list_for_each_entry(obj,
 624                                             &engine->batch_pool.cache_list[j],
 625                                             batch_pool_link) {
 626                                 seq_puts(m, "   ");
 627                                 describe_obj(m, obj);
 628                                 seq_putc(m, '\n');
 629                         }
 630
 631                         total += count;
 632                 }
 633         }
 634
 635         seq_printf(m, "total: %d\n", total);
 636
 637         mutex_unlock(&dev->struct_mutex);
 638
 639         return 0;
 640 }
 641
 642 static void print_request(struct seq_file *m,
 643                           struct drm_i915_gem_request *rq,
 644                           const char *prefix)
 645 {
 646         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 647                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 648                    rq->priotree.priority,
 649                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 650                    rq->timeline->common->name);
 651 }
 652
 653 static int i915_gem_request_info(struct seq_file *m, void *data)
 654 {
 655         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 656         struct drm_device *dev = &dev_priv->drm;
 657         struct drm_i915_gem_request *req;
 658         struct intel_engine_cs *engine;
 659         enum intel_engine_id id;
 660         int ret, any;
 661
 662         ret = mutex_lock_interruptible(&dev->struct_mutex);
 663         if (ret)
 664                 return ret;
 665
 666         any = 0;
 667         for_each_engine(engine, dev_priv, id) {
 668                 int count;
 669
 670                 count = 0;
 671                 list_for_each_entry(req, &engine->timeline->requests, link)
 672                         count++;
 673                 if (count == 0)
 674                         continue;
 675
 676                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 677                 list_for_each_entry(req, &engine->timeline->requests, link)
 678                         print_request(m, req, "    ");
 679
 680                 any++;
 681         }
 682         mutex_unlock(&dev->struct_mutex);
 683
 684         if (any == 0)
 685                 seq_puts(m, "No requests\n");
 686
 687         return 0;
 688 }
 689
 690 static void i915_ring_seqno_info(struct seq_file *m,
 691                                  struct intel_engine_cs *engine)
 692 {
 693         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 694         struct rb_node *rb;
 695
 696         seq_printf(m, "Current sequence (%s): %x\n",
 697                    engine->name, intel_engine_get_seqno(engine));
 698
 699         spin_lock_irq(&b->rb_lock);
 700         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 701                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 702
 703                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 704                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 705         }
 706         spin_unlock_irq(&b->rb_lock);
 707 }
 708
 709 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 710 {
 711         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 712         struct intel_engine_cs *engine;
 713         enum intel_engine_id id;
 714
 715         for_each_engine(engine, dev_priv, id)
 716                 i915_ring_seqno_info(m, engine);
 717
 718         return 0;
 719 }
 720
 721
 722 static int i915_interrupt_info(struct seq_file *m, void *data)
 723 {
 724         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 725         struct intel_engine_cs *engine;
 726         enum intel_engine_id id;
 727         int i, pipe;
 728
 729         intel_runtime_pm_get(dev_priv);
 730
 731         if (IS_CHERRYVIEW(dev_priv)) {
 732                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 733                            I915_READ(GEN8_MASTER_IRQ));
 734
 735                 seq_printf(m, "Display IER:\t%08x\n",
 736                            I915_READ(VLV_IER));
 737                 seq_printf(m, "Display IIR:\t%08x\n",
 738                            I915_READ(VLV_IIR));
 739                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 740                            I915_READ(VLV_IIR_RW));
 741                 seq_printf(m, "Display IMR:\t%08x\n",
 742                            I915_READ(VLV_IMR));
 743                 for_each_pipe(dev_priv, pipe) {
 744                         enum intel_display_power_domain power_domain;
 745
 746                         power_domain = POWER_DOMAIN_PIPE(pipe);
 747                         if (!intel_display_power_get_if_enabled(dev_priv,
 748                                                                 power_domain)) {
 749                                 seq_printf(m, "Pipe %c power disabled\n",
 750                                            pipe_name(pipe));
 751                                 continue;
 752                         }
 753
 754                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 755                                    pipe_name(pipe),
 756                                    I915_READ(PIPESTAT(pipe)));
 757
 758                         intel_display_power_put(dev_priv, power_domain);
 759                 }
 760
 761                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 762                 seq_printf(m, "Port hotplug:\t%08x\n",
 763                            I915_READ(PORT_HOTPLUG_EN));
 764                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 765                            I915_READ(VLV_DPFLIPSTAT));
 766                 seq_printf(m, "DPINVGTT:\t%08x\n",
 767                            I915_READ(DPINVGTT));
 768                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 769
 770                 for (i = 0; i < 4; i++) {
 771                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 772                                    i, I915_READ(GEN8_GT_IMR(i)));
 773                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 774                                    i, I915_READ(GEN8_GT_IIR(i)));
 775                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 776                                    i, I915_READ(GEN8_GT_IER(i)));
 777                 }
 778
 779                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 780                            I915_READ(GEN8_PCU_IMR));
 781                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 782                            I915_READ(GEN8_PCU_IIR));
 783                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 784                            I915_READ(GEN8_PCU_IER));
 785         } else if (INTEL_GEN(dev_priv) >= 8) {
 786                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 787                            I915_READ(GEN8_MASTER_IRQ));
 788
 789                 for (i = 0; i < 4; i++) {
 790                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 791                                    i, I915_READ(GEN8_GT_IMR(i)));
 792                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 793                                    i, I915_READ(GEN8_GT_IIR(i)));
 794                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 795                                    i, I915_READ(GEN8_GT_IER(i)));
 796                 }
 797
 798                 for_each_pipe(dev_priv, pipe) {
 799                         enum intel_display_power_domain power_domain;
 800
 801                         power_domain = POWER_DOMAIN_PIPE(pipe);
 802                         if (!intel_display_power_get_if_enabled(dev_priv,
 803                                                                 power_domain)) {
 804                                 seq_printf(m, "Pipe %c power disabled\n",
 805                                            pipe_name(pipe));
 806                                 continue;
 807                         }
 808                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 809                                    pipe_name(pipe),
 810                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 811                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 812                                    pipe_name(pipe),
 813                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 814                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 815                                    pipe_name(pipe),
 816                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 817
 818                         intel_display_power_put(dev_priv, power_domain);
 819                 }
 820
 821                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 822                            I915_READ(GEN8_DE_PORT_IMR));
 823                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 824                            I915_READ(GEN8_DE_PORT_IIR));
 825                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 826                            I915_READ(GEN8_DE_PORT_IER));
 827
 828                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 829                            I915_READ(GEN8_DE_MISC_IMR));
 830                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 831                            I915_READ(GEN8_DE_MISC_IIR));
 832                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 833                            I915_READ(GEN8_DE_MISC_IER));
 834
 835                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 836                            I915_READ(GEN8_PCU_IMR));
 837                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 838                            I915_READ(GEN8_PCU_IIR));
 839                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 840                            I915_READ(GEN8_PCU_IER));
 841         } else if (IS_VALLEYVIEW(dev_priv)) {
 842                 seq_printf(m, "Display IER:\t%08x\n",
 843                            I915_READ(VLV_IER));
 844                 seq_printf(m, "Display IIR:\t%08x\n",
 845                            I915_READ(VLV_IIR));
 846                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 847                            I915_READ(VLV_IIR_RW));
 848                 seq_printf(m, "Display IMR:\t%08x\n",
 849                            I915_READ(VLV_IMR));
 850                 for_each_pipe(dev_priv, pipe) {
 851                         enum intel_display_power_domain power_domain;
 852
 853                         power_domain = POWER_DOMAIN_PIPE(pipe);
 854                         if (!intel_display_power_get_if_enabled(dev_priv,
 855                                                                 power_domain)) {
 856                                 seq_printf(m, "Pipe %c power disabled\n",
 857                                            pipe_name(pipe));
 858                                 continue;
 859                         }
 860
 861                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 862                                    pipe_name(pipe),
 863                                    I915_READ(PIPESTAT(pipe)));
 864                         intel_display_power_put(dev_priv, power_domain);
 865                 }
 866
 867                 seq_printf(m, "Master IER:\t%08x\n",
 868                            I915_READ(VLV_MASTER_IER));
 869
 870                 seq_printf(m, "Render IER:\t%08x\n",
 871                            I915_READ(GTIER));
 872                 seq_printf(m, "Render IIR:\t%08x\n",
 873                            I915_READ(GTIIR));
 874                 seq_printf(m, "Render IMR:\t%08x\n",
 875                            I915_READ(GTIMR));
 876
 877                 seq_printf(m, "PM IER:\t\t%08x\n",
 878                            I915_READ(GEN6_PMIER));
 879                 seq_printf(m, "PM IIR:\t\t%08x\n",
 880                            I915_READ(GEN6_PMIIR));
 881                 seq_printf(m, "PM IMR:\t\t%08x\n",
 882                            I915_READ(GEN6_PMIMR));
 883
 884                 seq_printf(m, "Port hotplug:\t%08x\n",
 885                            I915_READ(PORT_HOTPLUG_EN));
 886                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 887                            I915_READ(VLV_DPFLIPSTAT));
 888                 seq_printf(m, "DPINVGTT:\t%08x\n",
 889                            I915_READ(DPINVGTT));
 890
 891         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 892                 seq_printf(m, "Interrupt enable:    %08x\n",
 893                            I915_READ(IER));
 894                 seq_printf(m, "Interrupt identity:  %08x\n",
 895                            I915_READ(IIR));
 896                 seq_printf(m, "Interrupt mask:      %08x\n",
 897                            I915_READ(IMR));
 898                 for_each_pipe(dev_priv, pipe)
 899                         seq_printf(m, "Pipe %c stat:         %08x\n",
 900                                    pipe_name(pipe),
 901                                    I915_READ(PIPESTAT(pipe)));
 902         } else {
 903                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 904                            I915_READ(DEIER));
 905                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 906                            I915_READ(DEIIR));
 907                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 908                            I915_READ(DEIMR));
 909                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 910                            I915_READ(SDEIER));
 911                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 912                            I915_READ(SDEIIR));
 913                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 914                            I915_READ(SDEIMR));
 915                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 916                            I915_READ(GTIER));
 917                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 918                            I915_READ(GTIIR));
 919                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 920                            I915_READ(GTIMR));
 921         }
 922         for_each_engine(engine, dev_priv, id) {
 923                 if (INTEL_GEN(dev_priv) >= 6) {
 924                         seq_printf(m,
 925                                    "Graphics Interrupt mask (%s):       %08x\n",
 926                                    engine->name, I915_READ_IMR(engine));
 927                 }
 928                 i915_ring_seqno_info(m, engine);
 929         }
 930         intel_runtime_pm_put(dev_priv);
 931
 932         return 0;
 933 }
 934
 935 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 936 {
 937         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 938         struct drm_device *dev = &dev_priv->drm;
 939         int i, ret;
 940
 941         ret = mutex_lock_interruptible(&dev->struct_mutex);
 942         if (ret)
 943                 return ret;
 944
 945         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 946         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 947                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 948
 949                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 950                            i, dev_priv->fence_regs[i].pin_count);
 951                 if (!vma)
 952                         seq_puts(m, "unused");
 953                 else
 954                         describe_obj(m, vma->obj);
 955                 seq_putc(m, '\n');
 956         }
 957
 958         mutex_unlock(&dev->struct_mutex);
 959         return 0;
 960 }
 961
 962 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 963 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 964                               size_t count, loff_t *pos)
 965 {
 966         struct i915_gpu_state *error = file->private_data;
 967         struct drm_i915_error_state_buf str;
 968         ssize_t ret;
 969         loff_t tmp;
 970
 971         if (!error)
 972                 return 0;
 973
 974         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 975         if (ret)
 976                 return ret;
 977
 978         ret = i915_error_state_to_str(&str, error);
 979         if (ret)
 980                 goto out;
 981
 982         tmp = 0;
 983         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
 984         if (ret < 0)
 985                 goto out;
 986
 987         *pos = str.start + ret;
 988 out:
 989         i915_error_state_buf_release(&str);
 990         return ret;
 991 }
 992
 993 static int gpu_state_release(struct inode *inode, struct file *file)
 994 {
 995         i915_gpu_state_put(file->private_data);
 996         return 0;
 997 }
 998
 999 static int i915_gpu_info_open(struct inode *inode, struct file *file)
1000 {
1001         struct drm_i915_private *i915 = inode->i_private;
1002         struct i915_gpu_state *gpu;
1003
1004         intel_runtime_pm_get(i915);
1005         gpu = i915_capture_gpu_state(i915);
1006         intel_runtime_pm_put(i915);
1007         if (!gpu)
1008                 return -ENOMEM;
1009
1010         file->private_data = gpu;
1011         return 0;
1012 }
1013
1014 static const struct file_operations i915_gpu_info_fops = {
1015         .owner = THIS_MODULE,
1016         .open = i915_gpu_info_open,
1017         .read = gpu_state_read,
1018         .llseek = default_llseek,
1019         .release = gpu_state_release,
1020 };
1021
1022 static ssize_t
1023 i915_error_state_write(struct file *filp,
1024                        const char __user *ubuf,
1025                        size_t cnt,
1026                        loff_t *ppos)
1027 {
1028         struct i915_gpu_state *error = filp->private_data;
1029
1030         if (!error)
1031                 return 0;
1032
1033         DRM_DEBUG_DRIVER("Resetting error state\n");
1034         i915_reset_error_state(error->i915);
1035
1036         return cnt;
1037 }
1038
1039 static int i915_error_state_open(struct inode *inode, struct file *file)
1040 {
1041         file->private_data = i915_first_error_state(inode->i_private);
1042         return 0;
1043 }
1044
1045 static const struct file_operations i915_error_state_fops = {
1046         .owner = THIS_MODULE,
1047         .open = i915_error_state_open,
1048         .read = gpu_state_read,
1049         .write = i915_error_state_write,
1050         .llseek = default_llseek,
1051         .release = gpu_state_release,
1052 };
1053 #endif
1054
1055 static int
1056 i915_next_seqno_set(void *data, u64 val)
1057 {
1058         struct drm_i915_private *dev_priv = data;
1059         struct drm_device *dev = &dev_priv->drm;
1060         int ret;
1061
1062         ret = mutex_lock_interruptible(&dev->struct_mutex);
1063         if (ret)
1064                 return ret;
1065
1066         ret = i915_gem_set_global_seqno(dev, val);
1067         mutex_unlock(&dev->struct_mutex);
1068
1069         return ret;
1070 }
1071
1072 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1073                         NULL, i915_next_seqno_set,
1074                         "0x%llx\n");
1075
1076 static int i915_frequency_info(struct seq_file *m, void *unused)
1077 {
1078         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1079         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1080         int ret = 0;
1081
1082         intel_runtime_pm_get(dev_priv);
1083
1084         if (IS_GEN5(dev_priv)) {
1085                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1086                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1087
1088                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1089                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1090                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1091                            MEMSTAT_VID_SHIFT);
1092                 seq_printf(m, "Current P-state: %d\n",
1093                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1094         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1095                 u32 rpmodectl, freq_sts;
1096
1097                 mutex_lock(&dev_priv->pcu_lock);
1098
1099                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1100                 seq_printf(m, "Video Turbo Mode: %s\n",
1101                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1102                 seq_printf(m, "HW control enabled: %s\n",
1103                            yesno(rpmodectl & GEN6_RP_ENABLE));
1104                 seq_printf(m, "SW control enabled: %s\n",
1105                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1106                                   GEN6_RP_MEDIA_SW_MODE));
1107
1108                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1109                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1110                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1111
1112                 seq_printf(m, "actual GPU freq: %d MHz\n",
1113                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1114
1115                 seq_printf(m, "current GPU freq: %d MHz\n",
1116                            intel_gpu_freq(dev_priv, rps->cur_freq));
1117
1118                 seq_printf(m, "max GPU freq: %d MHz\n",
1119                            intel_gpu_freq(dev_priv, rps->max_freq));
1120
1121                 seq_printf(m, "min GPU freq: %d MHz\n",
1122                            intel_gpu_freq(dev_priv, rps->min_freq));
1123
1124                 seq_printf(m, "idle GPU freq: %d MHz\n",
1125                            intel_gpu_freq(dev_priv, rps->idle_freq));
1126
1127                 seq_printf(m,
1128                            "efficient (RPe) frequency: %d MHz\n",
1129                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1130                 mutex_unlock(&dev_priv->pcu_lock);
1131         } else if (INTEL_GEN(dev_priv) >= 6) {
1132                 u32 rp_state_limits;
1133                 u32 gt_perf_status;
1134                 u32 rp_state_cap;
1135                 u32 rpmodectl, rpinclimit, rpdeclimit;
1136                 u32 rpstat, cagf, reqf;
1137                 u32 rpupei, rpcurup, rpprevup;
1138                 u32 rpdownei, rpcurdown, rpprevdown;
1139                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1140                 int max_freq;
1141
1142                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1143                 if (IS_GEN9_LP(dev_priv)) {
1144                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1145                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1146                 } else {
1147                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1148                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1149                 }
1150
1151                 /* RPSTAT1 is in the GT power well */
1152                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1153
1154                 reqf = I915_READ(GEN6_RPNSWREQ);
1155                 if (INTEL_GEN(dev_priv) >= 9)
1156                         reqf >>= 23;
1157                 else {
1158                         reqf &= ~GEN6_TURBO_DISABLE;
1159                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1160                                 reqf >>= 24;
1161                         else
1162                                 reqf >>= 25;
1163                 }
1164                 reqf = intel_gpu_freq(dev_priv, reqf);
1165
1166                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1167                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1168                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1169
1170                 rpstat = I915_READ(GEN6_RPSTAT1);
1171                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1172                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1173                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1174                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1175                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1176                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1177                 if (INTEL_GEN(dev_priv) >= 9)
1178                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1179                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1180                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1181                 else
1182                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1183                 cagf = intel_gpu_freq(dev_priv, cagf);
1184
1185                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1186
1187                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1188                         pm_ier = I915_READ(GEN6_PMIER);
1189                         pm_imr = I915_READ(GEN6_PMIMR);
1190                         pm_isr = I915_READ(GEN6_PMISR);
1191                         pm_iir = I915_READ(GEN6_PMIIR);
1192                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1193                 } else {
1194                         pm_ier = I915_READ(GEN8_GT_IER(2));
1195                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1196                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1197                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1198                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1199                 }
1200                 seq_printf(m, "Video Turbo Mode: %s\n",
1201                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
1202                 seq_printf(m, "HW control enabled: %s\n",
1203                            yesno(rpmodectl & GEN6_RP_ENABLE));
1204                 seq_printf(m, "SW control enabled: %s\n",
1205                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
1206                                   GEN6_RP_MEDIA_SW_MODE));
1207                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1208                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1209                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1210                            rps->pm_intrmsk_mbz);
1211                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1212                 seq_printf(m, "Render p-state ratio: %d\n",
1213                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
1214                 seq_printf(m, "Render p-state VID: %d\n",
1215                            gt_perf_status & 0xff);
1216                 seq_printf(m, "Render p-state limit: %d\n",
1217                            rp_state_limits & 0xff);
1218                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1219                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1220                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1221                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1222                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1223                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1224                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1225                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1226                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1227                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1228                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1229                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1230                 seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
1231
1232                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1233                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1234                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1235                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1236                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1237                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1238                 seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);
1239
1240                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1241                             rp_state_cap >> 16) & 0xff;
1242                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1243                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1244                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1245                            intel_gpu_freq(dev_priv, max_freq));
1246
1247                 max_freq = (rp_state_cap & 0xff00) >> 8;
1248                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1249                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1250                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1251                            intel_gpu_freq(dev_priv, max_freq));
1252
1253                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1254                             rp_state_cap >> 0) & 0xff;
1255                 max_freq *= (IS_GEN9_BC(dev_priv) ||
1256                              IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
1257                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1258                            intel_gpu_freq(dev_priv, max_freq));
1259                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1260                            intel_gpu_freq(dev_priv, rps->max_freq));
1261
1262                 seq_printf(m, "Current freq: %d MHz\n",
1263                            intel_gpu_freq(dev_priv, rps->cur_freq));
1264                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1265                 seq_printf(m, "Idle freq: %d MHz\n",
1266                            intel_gpu_freq(dev_priv, rps->idle_freq));
1267                 seq_printf(m, "Min freq: %d MHz\n",
1268                            intel_gpu_freq(dev_priv, rps->min_freq));
1269                 seq_printf(m, "Boost freq: %d MHz\n",
1270                            intel_gpu_freq(dev_priv, rps->boost_freq));
1271                 seq_printf(m, "Max freq: %d MHz\n",
1272                            intel_gpu_freq(dev_priv, rps->max_freq));
1273                 seq_printf(m,
1274                            "efficient (RPe) frequency: %d MHz\n",
1275                            intel_gpu_freq(dev_priv, rps->efficient_freq));
1276         } else {
1277                 seq_puts(m, "no P-state info available\n");
1278         }
1279
1280         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1281         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1282         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1283
1284         intel_runtime_pm_put(dev_priv);
1285         return ret;
1286 }
1287
1288 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1289                                struct seq_file *m,
1290                                struct intel_instdone *instdone)
1291 {
1292         int slice;
1293         int subslice;
1294
1295         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1296                    instdone->instdone);
1297
1298         if (INTEL_GEN(dev_priv) <= 3)
1299                 return;
1300
1301         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1302                    instdone->slice_common);
1303
1304         if (INTEL_GEN(dev_priv) <= 6)
1305                 return;
1306
1307         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1308                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1309                            slice, subslice, instdone->sampler[slice][subslice]);
1310
1311         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1312                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1313                            slice, subslice, instdone->row[slice][subslice]);
1314 }
1315
1316 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1317 {
1318         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1319         struct intel_engine_cs *engine;
1320         u64 acthd[I915_NUM_ENGINES];
1321         u32 seqno[I915_NUM_ENGINES];
1322         struct intel_instdone instdone;
1323         enum intel_engine_id id;
1324
1325         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1326                 seq_puts(m, "Wedged\n");
1327         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1328                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1329         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1330                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1331         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1332                 seq_puts(m, "Waiter holding struct mutex\n");
1333         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1334                 seq_puts(m, "struct_mutex blocked for reset\n");
1335
1336         if (!i915_modparams.enable_hangcheck) {
1337                 seq_puts(m, "Hangcheck disabled\n");
1338                 return 0;
1339         }
1340
1341         intel_runtime_pm_get(dev_priv);
1342
1343         for_each_engine(engine, dev_priv, id) {
1344                 acthd[id] = intel_engine_get_active_head(engine);
1345                 seqno[id] = intel_engine_get_seqno(engine);
1346         }
1347
1348         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1349
1350         intel_runtime_pm_put(dev_priv);
1351
1352         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1353                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1354                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1355                                             jiffies));
1356         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1357                 seq_puts(m, "Hangcheck active, work pending\n");
1358         else
1359                 seq_puts(m, "Hangcheck inactive\n");
1360
1361         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1362
1363         for_each_engine(engine, dev_priv, id) {
1364                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1365                 struct rb_node *rb;
1366
1367                 seq_printf(m, "%s:\n", engine->name);
1368                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1369                            engine->hangcheck.seqno, seqno[id],
1370                            intel_engine_last_submit(engine),
1371                            engine->timeline->inflight_seqnos);
1372                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1373                            yesno(intel_engine_has_waiter(engine)),
1374                            yesno(test_bit(engine->id,
1375                                           &dev_priv->gpu_error.missed_irq_rings)),
1376                            yesno(engine->hangcheck.stalled));
1377
1378                 spin_lock_irq(&b->rb_lock);
1379                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1380                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1381
1382                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1383                                    w->tsk->comm, w->tsk->pid, w->seqno);
1384                 }
1385                 spin_unlock_irq(&b->rb_lock);
1386
1387                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1388                            (long long)engine->hangcheck.acthd,
1389                            (long long)acthd[id]);
1390                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1391                            hangcheck_action_to_str(engine->hangcheck.action),
1392                            engine->hangcheck.action,
1393                            jiffies_to_msecs(jiffies -
1394                                             engine->hangcheck.action_timestamp));
1395
1396                 if (engine->id == RCS) {
1397                         seq_puts(m, "\tinstdone read =\n");
1398
1399                         i915_instdone_info(dev_priv, m, &instdone);
1400
1401                         seq_puts(m, "\tinstdone accu =\n");
1402
1403                         i915_instdone_info(dev_priv, m,
1404                                            &engine->hangcheck.instdone);
1405                 }
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int i915_reset_info(struct seq_file *m, void *unused)
1412 {
1413         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1414         struct i915_gpu_error *error = &dev_priv->gpu_error;
1415         struct intel_engine_cs *engine;
1416         enum intel_engine_id id;
1417
1418         seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
1419
1420         for_each_engine(engine, dev_priv, id) {
1421                 seq_printf(m, "%s = %u\n", engine->name,
1422                            i915_reset_engine_count(error, engine));
1423         }
1424
1425         return 0;
1426 }
1427
1428 static int ironlake_drpc_info(struct seq_file *m)
1429 {
1430         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1431         u32 rgvmodectl, rstdbyctl;
1432         u16 crstandvid;
1433
1434         rgvmodectl = I915_READ(MEMMODECTL);
1435         rstdbyctl = I915_READ(RSTDBYCTL);
1436         crstandvid = I915_READ16(CRSTANDVID);
1437
1438         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1439         seq_printf(m, "Boost freq: %d\n",
1440                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1441                    MEMMODE_BOOST_FREQ_SHIFT);
1442         seq_printf(m, "HW control enabled: %s\n",
1443                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1444         seq_printf(m, "SW control enabled: %s\n",
1445                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1446         seq_printf(m, "Gated voltage change: %s\n",
1447                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1448         seq_printf(m, "Starting frequency: P%d\n",
1449                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1450         seq_printf(m, "Max P-state: P%d\n",
1451                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1452         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1453         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1454         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1455         seq_printf(m, "Render standby enabled: %s\n",
1456                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1457         seq_puts(m, "Current RS state: ");
1458         switch (rstdbyctl & RSX_STATUS_MASK) {
1459         case RSX_STATUS_ON:
1460                 seq_puts(m, "on\n");
1461                 break;
1462         case RSX_STATUS_RC1:
1463                 seq_puts(m, "RC1\n");
1464                 break;
1465         case RSX_STATUS_RC1E:
1466                 seq_puts(m, "RC1E\n");
1467                 break;
1468         case RSX_STATUS_RS1:
1469                 seq_puts(m, "RS1\n");
1470                 break;
1471         case RSX_STATUS_RS2:
1472                 seq_puts(m, "RS2 (RC6)\n");
1473                 break;
1474         case RSX_STATUS_RS3:
1475                 seq_puts(m, "RC3 (RC6+)\n");
1476                 break;
1477         default:
1478                 seq_puts(m, "unknown\n");
1479                 break;
1480         }
1481
1482         return 0;
1483 }
1484
1485 static int i915_forcewake_domains(struct seq_file *m, void *data)
1486 {
1487         struct drm_i915_private *i915 = node_to_i915(m->private);
1488         struct intel_uncore_forcewake_domain *fw_domain;
1489         unsigned int tmp;
1490
1491         seq_printf(m, "user.bypass_count = %u\n",
1492                    i915->uncore.user_forcewake.count);
1493
1494         for_each_fw_domain(fw_domain, i915, tmp)
1495                 seq_printf(m, "%s.wake_count = %u\n",
1496                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1497                            READ_ONCE(fw_domain->wake_count));
1498
1499         return 0;
1500 }
1501
1502 static void print_rc6_res(struct seq_file *m,
1503                           const char *title,
1504                           const i915_reg_t reg)
1505 {
1506         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1507
1508         seq_printf(m, "%s %u (%llu us)\n",
1509                    title, I915_READ(reg),
1510                    intel_rc6_residency_us(dev_priv, reg));
1511 }
1512
1513 static int vlv_drpc_info(struct seq_file *m)
1514 {
1515         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1516         u32 rcctl1, pw_status;
1517
1518         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1519         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1520
1521         seq_printf(m, "RC6 Enabled: %s\n",
1522                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1523                                         GEN6_RC_CTL_EI_MODE(1))));
1524         seq_printf(m, "Render Power Well: %s\n",
1525                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1526         seq_printf(m, "Media Power Well: %s\n",
1527                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1528
1529         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1530         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1531
1532         return i915_forcewake_domains(m, NULL);
1533 }
1534
1535 static int gen6_drpc_info(struct seq_file *m)
1536 {
1537         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1538         u32 gt_core_status, rcctl1, rc6vids = 0;
1539         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1540         unsigned forcewake_count;
1541         int count = 0;
1542
1543         forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1544         if (forcewake_count) {
1545                 seq_puts(m, "RC information inaccurate because somebody "
1546                             "holds a forcewake reference \n");
1547         } else {
1548                 /* NB: we cannot use forcewake, else we read the wrong values */
1549                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1550                         udelay(10);
1551                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1552         }
1553
1554         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1555         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1556
1557         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1558         if (INTEL_GEN(dev_priv) >= 9) {
1559                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1560                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1561         }
1562
1563         mutex_lock(&dev_priv->pcu_lock);
1564         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1565         mutex_unlock(&dev_priv->pcu_lock);
1566
1567         seq_printf(m, "RC1e Enabled: %s\n",
1568                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1569         seq_printf(m, "RC6 Enabled: %s\n",
1570                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1571         if (INTEL_GEN(dev_priv) >= 9) {
1572                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1573                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1574                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1575                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1576         }
1577         seq_printf(m, "Deep RC6 Enabled: %s\n",
1578                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1579         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1580                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1581         seq_puts(m, "Current RC state: ");
1582         switch (gt_core_status & GEN6_RCn_MASK) {
1583         case GEN6_RC0:
1584                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1585                         seq_puts(m, "Core Power Down\n");
1586                 else
1587                         seq_puts(m, "on\n");
1588                 break;
1589         case GEN6_RC3:
1590                 seq_puts(m, "RC3\n");
1591                 break;
1592         case GEN6_RC6:
1593                 seq_puts(m, "RC6\n");
1594                 break;
1595         case GEN6_RC7:
1596                 seq_puts(m, "RC7\n");
1597                 break;
1598         default:
1599                 seq_puts(m, "Unknown\n");
1600                 break;
1601         }
1602
1603         seq_printf(m, "Core Power Down: %s\n",
1604                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1605         if (INTEL_GEN(dev_priv) >= 9) {
1606                 seq_printf(m, "Render Power Well: %s\n",
1607                         (gen9_powergate_status &
1608                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1609                 seq_printf(m, "Media Power Well: %s\n",
1610                         (gen9_powergate_status &
1611                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1612         }
1613
1614         /* Not exactly sure what this is */
1615         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1616                       GEN6_GT_GFX_RC6_LOCKED);
1617         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1618         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1619         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1620
1621         seq_printf(m, "RC6   voltage: %dmV\n",
1622                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1623         seq_printf(m, "RC6+  voltage: %dmV\n",
1624                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1625         seq_printf(m, "RC6++ voltage: %dmV\n",
1626                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1627         return i915_forcewake_domains(m, NULL);
1628 }
1629
1630 static int i915_drpc_info(struct seq_file *m, void *unused)
1631 {
1632         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1633         int err;
1634
1635         intel_runtime_pm_get(dev_priv);
1636
1637         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1638                 err = vlv_drpc_info(m);
1639         else if (INTEL_GEN(dev_priv) >= 6)
1640                 err = gen6_drpc_info(m);
1641         else
1642                 err = ironlake_drpc_info(m);
1643
1644         intel_runtime_pm_put(dev_priv);
1645
1646         return err;
1647 }
1648
1649 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1650 {
1651         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1652
1653         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1654                    dev_priv->fb_tracking.busy_bits);
1655
1656         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1657                    dev_priv->fb_tracking.flip_bits);
1658
1659         return 0;
1660 }
1661
1662 static int i915_fbc_status(struct seq_file *m, void *unused)
1663 {
1664         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1665
1666         if (!HAS_FBC(dev_priv)) {
1667                 seq_puts(m, "FBC unsupported on this chipset\n");
1668                 return 0;
1669         }
1670
1671         intel_runtime_pm_get(dev_priv);
1672         mutex_lock(&dev_priv->fbc.lock);
1673
1674         if (intel_fbc_is_active(dev_priv))
1675                 seq_puts(m, "FBC enabled\n");
1676         else
1677                 seq_printf(m, "FBC disabled: %s\n",
1678                            dev_priv->fbc.no_fbc_reason);
1679
1680         if (intel_fbc_is_active(dev_priv)) {
1681                 u32 mask;
1682
1683                 if (INTEL_GEN(dev_priv) >= 8)
1684                         mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
1685                 else if (INTEL_GEN(dev_priv) >= 7)
1686                         mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
1687                 else if (INTEL_GEN(dev_priv) >= 5)
1688                         mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
1689                 else if (IS_G4X(dev_priv))
1690                         mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
1691                 else
1692                         mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING |
1693                                                         FBC_STAT_COMPRESSED);
1694
1695                 seq_printf(m, "Compressing: %s\n", yesno(mask));
1696         }
1697
1698         mutex_unlock(&dev_priv->fbc.lock);
1699         intel_runtime_pm_put(dev_priv);
1700
1701         return 0;
1702 }
1703
1704 static int i915_fbc_false_color_get(void *data, u64 *val)
1705 {
1706         struct drm_i915_private *dev_priv = data;
1707
1708         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1709                 return -ENODEV;
1710
1711         *val = dev_priv->fbc.false_color;
1712
1713         return 0;
1714 }
1715
1716 static int i915_fbc_false_color_set(void *data, u64 val)
1717 {
1718         struct drm_i915_private *dev_priv = data;
1719         u32 reg;
1720
1721         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1722                 return -ENODEV;
1723
1724         mutex_lock(&dev_priv->fbc.lock);
1725
1726         reg = I915_READ(ILK_DPFC_CONTROL);
1727         dev_priv->fbc.false_color = val;
1728
1729         I915_WRITE(ILK_DPFC_CONTROL, val ?
1730                    (reg | FBC_CTL_FALSE_COLOR) :
1731                    (reg & ~FBC_CTL_FALSE_COLOR));
1732
1733         mutex_unlock(&dev_priv->fbc.lock);
1734         return 0;
1735 }
1736
1737 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
1738                         i915_fbc_false_color_get, i915_fbc_false_color_set,
1739                         "%llu\n");
1740
1741 static int i915_ips_status(struct seq_file *m, void *unused)
1742 {
1743         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1744
1745         if (!HAS_IPS(dev_priv)) {
1746                 seq_puts(m, "not supported\n");
1747                 return 0;
1748         }
1749
1750         intel_runtime_pm_get(dev_priv);
1751
1752         seq_printf(m, "Enabled by kernel parameter: %s\n",
1753                    yesno(i915_modparams.enable_ips));
1754
1755         if (INTEL_GEN(dev_priv) >= 8) {
1756                 seq_puts(m, "Currently: unknown\n");
1757         } else {
1758                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1759                         seq_puts(m, "Currently: enabled\n");
1760                 else
1761                         seq_puts(m, "Currently: disabled\n");
1762         }
1763
1764         intel_runtime_pm_put(dev_priv);
1765
1766         return 0;
1767 }
1768
1769 static int i915_sr_status(struct seq_file *m, void *unused)
1770 {
1771         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1772         bool sr_enabled = false;
1773
1774         intel_runtime_pm_get(dev_priv);
1775         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1776
1777         if (INTEL_GEN(dev_priv) >= 9)
1778                 /* no global SR status; inspect per-plane WM */;
1779         else if (HAS_PCH_SPLIT(dev_priv))
1780                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1781         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1782                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1783                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1784         else if (IS_I915GM(dev_priv))
1785                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1786         else if (IS_PINEVIEW(dev_priv))
1787                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1788         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1789                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1790
1791         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1792         intel_runtime_pm_put(dev_priv);
1793
1794         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1795
1796         return 0;
1797 }
1798
1799 static int i915_emon_status(struct seq_file *m, void *unused)
1800 {
1801         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1802         struct drm_device *dev = &dev_priv->drm;
1803         unsigned long temp, chipset, gfx;
1804         int ret;
1805
1806         if (!IS_GEN5(dev_priv))
1807                 return -ENODEV;
1808
1809         ret = mutex_lock_interruptible(&dev->struct_mutex);
1810         if (ret)
1811                 return ret;
1812
1813         temp = i915_mch_val(dev_priv);
1814         chipset = i915_chipset_val(dev_priv);
1815         gfx = i915_gfx_val(dev_priv);
1816         mutex_unlock(&dev->struct_mutex);
1817
1818         seq_printf(m, "GMCH temp: %ld\n", temp);
1819         seq_printf(m, "Chipset power: %ld\n", chipset);
1820         seq_printf(m, "GFX power: %ld\n", gfx);
1821         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1822
1823         return 0;
1824 }
1825
1826 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1827 {
1828         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1829         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1830         int ret = 0;
1831         int gpu_freq, ia_freq;
1832         unsigned int max_gpu_freq, min_gpu_freq;
1833
1834         if (!HAS_LLC(dev_priv)) {
1835                 seq_puts(m, "unsupported on this chipset\n");
1836                 return 0;
1837         }
1838
1839         intel_runtime_pm_get(dev_priv);
1840
1841         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
1842         if (ret)
1843                 goto out;
1844
1845         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
1846                 /* Convert GT frequency to 50 HZ units */
1847                 min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
1848                 max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
1849         } else {
1850                 min_gpu_freq = rps->min_freq_softlimit;
1851                 max_gpu_freq = rps->max_freq_softlimit;
1852         }
1853
1854         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1855
1856         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1857                 ia_freq = gpu_freq;
1858                 sandybridge_pcode_read(dev_priv,
1859                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1860                                        &ia_freq);
1861                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1862                            intel_gpu_freq(dev_priv, (gpu_freq *
1863                                                      (IS_GEN9_BC(dev_priv) ||
1864                                                       IS_CANNONLAKE(dev_priv) ?
1865                                                       GEN9_FREQ_SCALER : 1))),
1866                            ((ia_freq >> 0) & 0xff) * 100,
1867                            ((ia_freq >> 8) & 0xff) * 100);
1868         }
1869
1870         mutex_unlock(&dev_priv->pcu_lock);
1871
1872 out:
1873         intel_runtime_pm_put(dev_priv);
1874         return ret;
1875 }
1876
1877 static int i915_opregion(struct seq_file *m, void *unused)
1878 {
1879         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1880         struct drm_device *dev = &dev_priv->drm;
1881         struct intel_opregion *opregion = &dev_priv->opregion;
1882         int ret;
1883
1884         ret = mutex_lock_interruptible(&dev->struct_mutex);
1885         if (ret)
1886                 goto out;
1887
1888         if (opregion->header)
1889                 seq_write(m, opregion->header, OPREGION_SIZE);
1890
1891         mutex_unlock(&dev->struct_mutex);
1892
1893 out:
1894         return 0;
1895 }
1896
1897 static int i915_vbt(struct seq_file *m, void *unused)
1898 {
1899         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1900
1901         if (opregion->vbt)
1902                 seq_write(m, opregion->vbt, opregion->vbt_size);
1903
1904         return 0;
1905 }
1906
1907 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1908 {
1909         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1910         struct drm_device *dev = &dev_priv->drm;
1911         struct intel_framebuffer *fbdev_fb = NULL;
1912         struct drm_framebuffer *drm_fb;
1913         int ret;
1914
1915         ret = mutex_lock_interruptible(&dev->struct_mutex);
1916         if (ret)
1917                 return ret;
1918
1919 #ifdef CONFIG_DRM_FBDEV_EMULATION
1920         if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
1921                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1922
1923                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1924                            fbdev_fb->base.width,
1925                            fbdev_fb->base.height,
1926                            fbdev_fb->base.format->depth,
1927                            fbdev_fb->base.format->cpp[0] * 8,
1928                            fbdev_fb->base.modifier,
1929                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1930                 describe_obj(m, fbdev_fb->obj);
1931                 seq_putc(m, '\n');
1932         }
1933 #endif
1934
1935         mutex_lock(&dev->mode_config.fb_lock);
1936         drm_for_each_fb(drm_fb, dev) {
1937                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1938                 if (fb == fbdev_fb)
1939                         continue;
1940
1941                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1942                            fb->base.width,
1943                            fb->base.height,
1944                            fb->base.format->depth,
1945                            fb->base.format->cpp[0] * 8,
1946                            fb->base.modifier,
1947                            drm_framebuffer_read_refcount(&fb->base));
1948                 describe_obj(m, fb->obj);
1949                 seq_putc(m, '\n');
1950         }
1951         mutex_unlock(&dev->mode_config.fb_lock);
1952         mutex_unlock(&dev->struct_mutex);
1953
1954         return 0;
1955 }
1956
1957 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1958 {
1959         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1960                    ring->space, ring->head, ring->tail);
1961 }
1962
1963 static int i915_context_status(struct seq_file *m, void *unused)
1964 {
1965         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1966         struct drm_device *dev = &dev_priv->drm;
1967         struct intel_engine_cs *engine;
1968         struct i915_gem_context *ctx;
1969         enum intel_engine_id id;
1970         int ret;
1971
1972         ret = mutex_lock_interruptible(&dev->struct_mutex);
1973         if (ret)
1974                 return ret;
1975
1976         list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
1977                 seq_printf(m, "HW context %u ", ctx->hw_id);
1978                 if (ctx->pid) {
1979                         struct task_struct *task;
1980
1981                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1982                         if (task) {
1983                                 seq_printf(m, "(%s [%d]) ",
1984                                            task->comm, task->pid);
1985                                 put_task_struct(task);
1986                         }
1987                 } else if (IS_ERR(ctx->file_priv)) {
1988                         seq_puts(m, "(deleted) ");
1989                 } else {
1990                         seq_puts(m, "(kernel) ");
1991                 }
1992
1993                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1994                 seq_putc(m, '\n');
1995
1996                 for_each_engine(engine, dev_priv, id) {
1997                         struct intel_context *ce = &ctx->engine[engine->id];
1998
1999                         seq_printf(m, "%s: ", engine->name);
2000                         seq_putc(m, ce->initialised ? 'I' : 'i');
2001                         if (ce->state)
2002                                 describe_obj(m, ce->state->obj);
2003                         if (ce->ring)
2004                                 describe_ctx_ring(m, ce->ring);
2005                         seq_putc(m, '\n');
2006                 }
2007
2008                 seq_putc(m, '\n');
2009         }
2010
2011         mutex_unlock(&dev->struct_mutex);
2012
2013         return 0;
2014 }
2015
2016 static void i915_dump_lrc_obj(struct seq_file *m,
2017                               struct i915_gem_context *ctx,
2018                               struct intel_engine_cs *engine)
2019 {
2020         struct i915_vma *vma = ctx->engine[engine->id].state;
2021         struct page *page;
2022         int j;
2023
2024         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2025
2026         if (!vma) {
2027                 seq_puts(m, "\tFake context\n");
2028                 return;
2029         }
2030
2031         if (vma->flags & I915_VMA_GLOBAL_BIND)
2032                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2033                            i915_ggtt_offset(vma));
2034
2035         if (i915_gem_object_pin_pages(vma->obj)) {
2036                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2037                 return;
2038         }
2039
2040         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2041         if (page) {
2042                 u32 *reg_state = kmap_atomic(page);
2043
2044                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2045                         seq_printf(m,
2046                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2047                                    j * 4,
2048                                    reg_state[j], reg_state[j + 1],
2049                                    reg_state[j + 2], reg_state[j + 3]);
2050                 }
2051                 kunmap_atomic(reg_state);
2052         }
2053
2054         i915_gem_object_unpin_pages(vma->obj);
2055         seq_putc(m, '\n');
2056 }
2057
2058 static int i915_dump_lrc(struct seq_file *m, void *unused)
2059 {
2060         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2061         struct drm_device *dev = &dev_priv->drm;
2062         struct intel_engine_cs *engine;
2063         struct i915_gem_context *ctx;
2064         enum intel_engine_id id;
2065         int ret;
2066
2067         if (!i915_modparams.enable_execlists) {
2068                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2069                 return 0;
2070         }
2071
2072         ret = mutex_lock_interruptible(&dev->struct_mutex);
2073         if (ret)
2074                 return ret;
2075
2076         list_for_each_entry(ctx, &dev_priv->contexts.list, link)
2077                 for_each_engine(engine, dev_priv, id)
2078                         i915_dump_lrc_obj(m, ctx, engine);
2079
2080         mutex_unlock(&dev->struct_mutex);
2081
2082         return 0;
2083 }
2084
2085 static const char *swizzle_string(unsigned swizzle)
2086 {
2087         switch (swizzle) {
2088         case I915_BIT_6_SWIZZLE_NONE:
2089                 return "none";
2090         case I915_BIT_6_SWIZZLE_9:
2091                 return "bit9";
2092         case I915_BIT_6_SWIZZLE_9_10:
2093                 return "bit9/bit10";
2094         case I915_BIT_6_SWIZZLE_9_11:
2095                 return "bit9/bit11";
2096         case I915_BIT_6_SWIZZLE_9_10_11:
2097                 return "bit9/bit10/bit11";
2098         case I915_BIT_6_SWIZZLE_9_17:
2099                 return "bit9/bit17";
2100         case I915_BIT_6_SWIZZLE_9_10_17:
2101                 return "bit9/bit10/bit17";
2102         case I915_BIT_6_SWIZZLE_UNKNOWN:
2103                 return "unknown";
2104         }
2105
2106         return "bug";
2107 }
2108
2109 static int i915_swizzle_info(struct seq_file *m, void *data)
2110 {
2111         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2112
2113         intel_runtime_pm_get(dev_priv);
2114
2115         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2116                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2117         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2118                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2119
2120         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2121                 seq_printf(m, "DDC = 0x%08x\n",
2122                            I915_READ(DCC));
2123                 seq_printf(m, "DDC2 = 0x%08x\n",
2124                            I915_READ(DCC2));
2125                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2126                            I915_READ16(C0DRB3));
2127                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2128                            I915_READ16(C1DRB3));
2129         } else if (INTEL_GEN(dev_priv) >= 6) {
2130                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2131                            I915_READ(MAD_DIMM_C0));
2132                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2133                            I915_READ(MAD_DIMM_C1));
2134                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2135                            I915_READ(MAD_DIMM_C2));
2136                 seq_printf(m, "TILECTL = 0x%08x\n",
2137                            I915_READ(TILECTL));
2138                 if (INTEL_GEN(dev_priv) >= 8)
2139                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2140                                    I915_READ(GAMTARBMODE));
2141                 else
2142                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2143                                    I915_READ(ARB_MODE));
2144                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2145                            I915_READ(DISP_ARB_CTL));
2146         }
2147
2148         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2149                 seq_puts(m, "L-shaped memory detected\n");
2150
2151         intel_runtime_pm_put(dev_priv);
2152
2153         return 0;
2154 }
2155
2156 static int per_file_ctx(int id, void *ptr, void *data)
2157 {
2158         struct i915_gem_context *ctx = ptr;
2159         struct seq_file *m = data;
2160         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2161
2162         if (!ppgtt) {
2163                 seq_printf(m, "  no ppgtt for context %d\n",
2164                            ctx->user_handle);
2165                 return 0;
2166         }
2167
2168         if (i915_gem_context_is_default(ctx))
2169                 seq_puts(m, "  default context:\n");
2170         else
2171                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2172         ppgtt->debug_dump(ppgtt, m);
2173
2174         return 0;
2175 }
2176
2177 static void gen8_ppgtt_info(struct seq_file *m,
2178                             struct drm_i915_private *dev_priv)
2179 {
2180         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2181         struct intel_engine_cs *engine;
2182         enum intel_engine_id id;
2183         int i;
2184
2185         if (!ppgtt)
2186                 return;
2187
2188         for_each_engine(engine, dev_priv, id) {
2189                 seq_printf(m, "%s\n", engine->name);
2190                 for (i = 0; i < 4; i++) {
2191                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2192                         pdp <<= 32;
2193                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2194                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2195                 }
2196         }
2197 }
2198
2199 static void gen6_ppgtt_info(struct seq_file *m,
2200                             struct drm_i915_private *dev_priv)
2201 {
2202         struct intel_engine_cs *engine;
2203         enum intel_engine_id id;
2204
2205         if (IS_GEN6(dev_priv))
2206                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2207
2208         for_each_engine(engine, dev_priv, id) {
2209                 seq_printf(m, "%s\n", engine->name);
2210                 if (IS_GEN7(dev_priv))
2211                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2212                                    I915_READ(RING_MODE_GEN7(engine)));
2213                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2214                            I915_READ(RING_PP_DIR_BASE(engine)));
2215                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2216                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2217                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2218                            I915_READ(RING_PP_DIR_DCLV(engine)));
2219         }
2220         if (dev_priv->mm.aliasing_ppgtt) {
2221                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2222
2223                 seq_puts(m, "aliasing PPGTT:\n");
2224                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2225
2226                 ppgtt->debug_dump(ppgtt, m);
2227         }
2228
2229         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2230 }
2231
2232 static int i915_ppgtt_info(struct seq_file *m, void *data)
2233 {
2234         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2235         struct drm_device *dev = &dev_priv->drm;
2236         struct drm_file *file;
2237         int ret;
2238
2239         mutex_lock(&dev->filelist_mutex);
2240         ret = mutex_lock_interruptible(&dev->struct_mutex);
2241         if (ret)
2242                 goto out_unlock;
2243
2244         intel_runtime_pm_get(dev_priv);
2245
2246         if (INTEL_GEN(dev_priv) >= 8)
2247                 gen8_ppgtt_info(m, dev_priv);
2248         else if (INTEL_GEN(dev_priv) >= 6)
2249                 gen6_ppgtt_info(m, dev_priv);
2250
2251         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2252                 struct drm_i915_file_private *file_priv = file->driver_priv;
2253                 struct task_struct *task;
2254
2255                 task = get_pid_task(file->pid, PIDTYPE_PID);
2256                 if (!task) {
2257                         ret = -ESRCH;
2258                         goto out_rpm;
2259                 }
2260                 seq_printf(m, "\nproc: %s\n", task->comm);
2261                 put_task_struct(task);
2262                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2263                              (void *)(unsigned long)m);
2264         }
2265
2266 out_rpm:
2267         intel_runtime_pm_put(dev_priv);
2268         mutex_unlock(&dev->struct_mutex);
2269 out_unlock:
2270         mutex_unlock(&dev->filelist_mutex);
2271         return ret;
2272 }
2273
2274 static int count_irq_waiters(struct drm_i915_private *i915)
2275 {
2276         struct intel_engine_cs *engine;
2277         enum intel_engine_id id;
2278         int count = 0;
2279
2280         for_each_engine(engine, i915, id)
2281                 count += intel_engine_has_waiter(engine);
2282
2283         return count;
2284 }
2285
2286 static const char *rps_power_to_str(unsigned int power)
2287 {
2288         static const char * const strings[] = {
2289                 [LOW_POWER] = "low power",
2290                 [BETWEEN] = "mixed",
2291                 [HIGH_POWER] = "high power",
2292         };
2293
2294         if (power >= ARRAY_SIZE(strings) || !strings[power])
2295                 return "unknown";
2296
2297         return strings[power];
2298 }
2299
2300 static int i915_rps_boost_info(struct seq_file *m, void *data)
2301 {
2302         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2303         struct drm_device *dev = &dev_priv->drm;
2304         struct intel_rps *rps = &dev_priv->gt_pm.rps;
2305         struct drm_file *file;
2306
2307         seq_printf(m, "RPS enabled? %d\n", rps->enabled);
2308         seq_printf(m, "GPU busy? %s [%d requests]\n",
2309                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2310         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2311         seq_printf(m, "Boosts outstanding? %d\n",
2312                    atomic_read(&rps->num_waiters));
2313         seq_printf(m, "Frequency requested %d\n",
2314                    intel_gpu_freq(dev_priv, rps->cur_freq));
2315         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2316                    intel_gpu_freq(dev_priv, rps->min_freq),
2317                    intel_gpu_freq(dev_priv, rps->min_freq_softlimit),
2318                    intel_gpu_freq(dev_priv, rps->max_freq_softlimit),
2319                    intel_gpu_freq(dev_priv, rps->max_freq));
2320         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2321                    intel_gpu_freq(dev_priv, rps->idle_freq),
2322                    intel_gpu_freq(dev_priv, rps->efficient_freq),
2323                    intel_gpu_freq(dev_priv, rps->boost_freq));
2324
2325         mutex_lock(&dev->filelist_mutex);
2326         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2327                 struct drm_i915_file_private *file_priv = file->driver_priv;
2328                 struct task_struct *task;
2329
2330                 rcu_read_lock();
2331                 task = pid_task(file->pid, PIDTYPE_PID);
2332                 seq_printf(m, "%s [%d]: %d boosts\n",
2333                            task ? task->comm : "<unknown>",
2334                            task ? task->pid : -1,
2335                            atomic_read(&file_priv->rps_client.boosts));
2336                 rcu_read_unlock();
2337         }
2338         seq_printf(m, "Kernel (anonymous) boosts: %d\n",
2339                    atomic_read(&rps->boosts));
2340         mutex_unlock(&dev->filelist_mutex);
2341
2342         if (INTEL_GEN(dev_priv) >= 6 &&
2343             rps->enabled &&
2344             dev_priv->gt.active_requests) {
2345                 u32 rpup, rpupei;
2346                 u32 rpdown, rpdownei;
2347
2348                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2349                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2350                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2351                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2352                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2353                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2354
2355                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2356                            rps_power_to_str(rps->power));
2357                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2358                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2359                            rps->up_threshold);
2360                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2361                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2362                            rps->down_threshold);
2363         } else {
2364                 seq_puts(m, "\nRPS Autotuning inactive\n");
2365         }
2366
2367         return 0;
2368 }
2369
2370 static int i915_llc(struct seq_file *m, void *data)
2371 {
2372         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2373         const bool edram = INTEL_GEN(dev_priv) > 8;
2374
2375         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2376         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2377                    intel_uncore_edram_size(dev_priv)/1024/1024);
2378
2379         return 0;
2380 }
2381
2382 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2383 {
2384         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2385         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2386
2387         if (!HAS_HUC_UCODE(dev_priv))
2388                 return 0;
2389
2390         seq_puts(m, "HuC firmware status:\n");
2391         seq_printf(m, "\tpath: %s\n", huc_fw->path);
2392         seq_printf(m, "\tfetch: %s\n",
2393                 intel_uc_fw_status_repr(huc_fw->fetch_status));
2394         seq_printf(m, "\tload: %s\n",
2395                 intel_uc_fw_status_repr(huc_fw->load_status));
2396         seq_printf(m, "\tversion wanted: %d.%d\n",
2397                 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2398         seq_printf(m, "\tversion found: %d.%d\n",
2399                 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2400         seq_printf(m, "\theader: offset is %d; size = %d\n",
2401                 huc_fw->header_offset, huc_fw->header_size);
2402         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2403                 huc_fw->ucode_offset, huc_fw->ucode_size);
2404         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2405                 huc_fw->rsa_offset, huc_fw->rsa_size);
2406
2407         intel_runtime_pm_get(dev_priv);
2408         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2409         intel_runtime_pm_put(dev_priv);
2410
2411         return 0;
2412 }
2413
2414 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2415 {
2416         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2417         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2418         u32 tmp, i;
2419
2420         if (!HAS_GUC_UCODE(dev_priv))
2421                 return 0;
2422
2423         seq_printf(m, "GuC firmware status:\n");
2424         seq_printf(m, "\tpath: %s\n",
2425                 guc_fw->path);
2426         seq_printf(m, "\tfetch: %s\n",
2427                 intel_uc_fw_status_repr(guc_fw->fetch_status));
2428         seq_printf(m, "\tload: %s\n",
2429                 intel_uc_fw_status_repr(guc_fw->load_status));
2430         seq_printf(m, "\tversion wanted: %d.%d\n",
2431                 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2432         seq_printf(m, "\tversion found: %d.%d\n",
2433                 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2434         seq_printf(m, "\theader: offset is %d; size = %d\n",
2435                 guc_fw->header_offset, guc_fw->header_size);
2436         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2437                 guc_fw->ucode_offset, guc_fw->ucode_size);
2438         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2439                 guc_fw->rsa_offset, guc_fw->rsa_size);
2440
2441         intel_runtime_pm_get(dev_priv);
2442
2443         tmp = I915_READ(GUC_STATUS);
2444
2445         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2446         seq_printf(m, "\tBootrom status = 0x%x\n",
2447                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2448         seq_printf(m, "\tuKernel status = 0x%x\n",
2449                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2450         seq_printf(m, "\tMIA Core status = 0x%x\n",
2451                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2452         seq_puts(m, "\nScratch registers:\n");
2453         for (i = 0; i < 16; i++)
2454                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2455
2456         intel_runtime_pm_put(dev_priv);
2457
2458         return 0;
2459 }
2460
2461 static void i915_guc_log_info(struct seq_file *m,
2462                               struct drm_i915_private *dev_priv)
2463 {
2464         struct intel_guc *guc = &dev_priv->guc;
2465
2466         seq_puts(m, "\nGuC logging stats:\n");
2467
2468         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2469                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2470                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2471
2472         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2473                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2474                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2475
2476         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2477                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2478                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2479
2480         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2481                    guc->log.flush_interrupt_count);
2482
2483         seq_printf(m, "\tCapture miss count: %u\n",
2484                    guc->log.capture_miss_count);
2485 }
2486
2487 static void i915_guc_client_info(struct seq_file *m,
2488                                  struct drm_i915_private *dev_priv,
2489                                  struct i915_guc_client *client)
2490 {
2491         struct intel_engine_cs *engine;
2492         enum intel_engine_id id;
2493         uint64_t tot = 0;
2494
2495         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2496                 client->priority, client->stage_id, client->proc_desc_offset);
2497         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n",
2498                 client->doorbell_id, client->doorbell_offset);
2499
2500         for_each_engine(engine, dev_priv, id) {
2501                 u64 submissions = client->submissions[id];
2502                 tot += submissions;
2503                 seq_printf(m, "\tSubmissions: %llu %s\n",
2504                                 submissions, engine->name);
2505         }
2506         seq_printf(m, "\tTotal: %llu\n", tot);
2507 }
2508
2509 static bool check_guc_submission(struct seq_file *m)
2510 {
2511         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2512         const struct intel_guc *guc = &dev_priv->guc;
2513
2514         if (!guc->execbuf_client) {
2515                 seq_printf(m, "GuC submission %s\n",
2516                            HAS_GUC_SCHED(dev_priv) ?
2517                            "disabled" :
2518                            "not supported");
2519                 return false;
2520         }
2521
2522         return true;
2523 }
2524
2525 static int i915_guc_info(struct seq_file *m, void *data)
2526 {
2527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2528         const struct intel_guc *guc = &dev_priv->guc;
2529
2530         if (!check_guc_submission(m))
2531                 return 0;
2532
2533         seq_printf(m, "Doorbell map:\n");
2534         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2535         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2536
2537         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2538         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2539
2540         i915_guc_log_info(m, dev_priv);
2541
2542         /* Add more as required ... */
2543
2544         return 0;
2545 }
2546
2547 static int i915_guc_stage_pool(struct seq_file *m, void *data)
2548 {
2549         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2550         const struct intel_guc *guc = &dev_priv->guc;
2551         struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
2552         struct i915_guc_client *client = guc->execbuf_client;
2553         unsigned int tmp;
2554         int index;
2555
2556         if (!check_guc_submission(m))
2557                 return 0;
2558
2559         for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
2560                 struct intel_engine_cs *engine;
2561
2562                 if (!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE))
2563                         continue;
2564
2565                 seq_printf(m, "GuC stage descriptor %u:\n", index);
2566                 seq_printf(m, "\tIndex: %u\n", desc->stage_id);
2567                 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute);
2568                 seq_printf(m, "\tPriority: %d\n", desc->priority);
2569                 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id);
2570                 seq_printf(m, "\tEngines used: 0x%x\n",
2571                            desc->engines_used);
2572                 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n",
2573                            desc->db_trigger_phy,
2574                            desc->db_trigger_cpu,
2575                            desc->db_trigger_uk);
2576                 seq_printf(m, "\tProcess descriptor: 0x%x\n",
2577                            desc->process_desc);
2578                 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n",
2579                            desc->wq_addr, desc->wq_size);
2580                 seq_putc(m, '\n');
2581
2582                 for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
2583                         u32 guc_engine_id = engine->guc_id;
2584                         struct guc_execlist_context *lrc =
2585                                                 &desc->lrc[guc_engine_id];
2586
2587                         seq_printf(m, "\t%s LRC:\n", engine->name);
2588                         seq_printf(m, "\t\tContext desc: 0x%x\n",
2589                                    lrc->context_desc);
2590                         seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id);
2591                         seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca);
2592                         seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin);
2593                         seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end);
2594                         seq_putc(m, '\n');
2595                 }
2596         }
2597
2598         return 0;
2599 }
2600
2601 static int i915_guc_log_dump(struct seq_file *m, void *data)
2602 {
2603         struct drm_info_node *node = m->private;
2604         struct drm_i915_private *dev_priv = node_to_i915(node);
2605         bool dump_load_err = !!node->info_ent->data;
2606         struct drm_i915_gem_object *obj = NULL;
2607         u32 *log;
2608         int i = 0;
2609
2610         if (dump_load_err)
2611                 obj = dev_priv->guc.load_err_log;
2612         else if (dev_priv->guc.log.vma)
2613                 obj = dev_priv->guc.log.vma->obj;
2614
2615         if (!obj)
2616                 return 0;
2617
2618         log = i915_gem_object_pin_map(obj, I915_MAP_WC);
2619         if (IS_ERR(log)) {
2620                 DRM_DEBUG("Failed to pin object\n");
2621                 seq_puts(m, "(log data unaccessible)\n");
2622                 return PTR_ERR(log);
2623         }
2624
2625         for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
2626                 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2627                            *(log + i), *(log + i + 1),
2628                            *(log + i + 2), *(log + i + 3));
2629
2630         seq_putc(m, '\n');
2631
2632         i915_gem_object_unpin_map(obj);
2633
2634         return 0;
2635 }
2636
2637 static int i915_guc_log_control_get(void *data, u64 *val)
2638 {
2639         struct drm_i915_private *dev_priv = data;
2640
2641         if (!dev_priv->guc.log.vma)
2642                 return -EINVAL;
2643
2644         *val = i915_modparams.guc_log_level;
2645
2646         return 0;
2647 }
2648
2649 static int i915_guc_log_control_set(void *data, u64 val)
2650 {
2651         struct drm_i915_private *dev_priv = data;
2652         int ret;
2653
2654         if (!dev_priv->guc.log.vma)
2655                 return -EINVAL;
2656
2657         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
2658         if (ret)
2659                 return ret;
2660
2661         intel_runtime_pm_get(dev_priv);
2662         ret = i915_guc_log_control(dev_priv, val);
2663         intel_runtime_pm_put(dev_priv);
2664
2665         mutex_unlock(&dev_priv->drm.struct_mutex);
2666         return ret;
2667 }
2668
2669 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2670                         i915_guc_log_control_get, i915_guc_log_control_set,
2671                         "%lld\n");
2672
2673 static const char *psr2_live_status(u32 val)
2674 {
2675         static const char * const live_status[] = {
2676                 "IDLE",
2677                 "CAPTURE",
2678                 "CAPTURE_FS",
2679                 "SLEEP",
2680                 "BUFON_FW",
2681                 "ML_UP",
2682                 "SU_STANDBY",
2683                 "FAST_SLEEP",
2684                 "DEEP_SLEEP",
2685                 "BUF_ON",
2686                 "TG_ON"
2687         };
2688
2689         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2690         if (val < ARRAY_SIZE(live_status))
2691                 return live_status[val];
2692
2693         return "unknown";
2694 }
2695
2696 static int i915_edp_psr_status(struct seq_file *m, void *data)
2697 {
2698         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2699         u32 psrperf = 0;
2700         u32 stat[3];
2701         enum pipe pipe;
2702         bool enabled = false;
2703
2704         if (!HAS_PSR(dev_priv)) {
2705                 seq_puts(m, "PSR not supported\n");
2706                 return 0;
2707         }
2708
2709         intel_runtime_pm_get(dev_priv);
2710
2711         mutex_lock(&dev_priv->psr.lock);
2712         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2713         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2714         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2715         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2716         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2717                    dev_priv->psr.busy_frontbuffer_bits);
2718         seq_printf(m, "Re-enable work scheduled: %s\n",
2719                    yesno(work_busy(&dev_priv->psr.work.work)));
2720
2721         if (HAS_DDI(dev_priv)) {
2722                 if (dev_priv->psr.psr2_support)
2723                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2724                 else
2725                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2726         } else {
2727                 for_each_pipe(dev_priv, pipe) {
2728                         enum transcoder cpu_transcoder =
2729                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2730                         enum intel_display_power_domain power_domain;
2731
2732                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2733                         if (!intel_display_power_get_if_enabled(dev_priv,
2734                                                                 power_domain))
2735                                 continue;
2736
2737                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2738                                 VLV_EDP_PSR_CURR_STATE_MASK;
2739                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2740                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2741                                 enabled = true;
2742
2743                         intel_display_power_put(dev_priv, power_domain);
2744                 }
2745         }
2746
2747         seq_printf(m, "Main link in standby mode: %s\n",
2748                    yesno(dev_priv->psr.link_standby));
2749
2750         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2751
2752         if (!HAS_DDI(dev_priv))
2753                 for_each_pipe(dev_priv, pipe) {
2754                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2755                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2756                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2757                 }
2758         seq_puts(m, "\n");
2759
2760         /*
2761          * VLV/CHV PSR has no kind of performance counter
2762          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2763          */
2764         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2765                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2766                         EDP_PSR_PERF_CNT_MASK;
2767
2768                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2769         }
2770         if (dev_priv->psr.psr2_support) {
2771                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2772
2773                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2774                            psr2, psr2_live_status(psr2));
2775         }
2776         mutex_unlock(&dev_priv->psr.lock);
2777
2778         intel_runtime_pm_put(dev_priv);
2779         return 0;
2780 }
2781
2782 static int i915_sink_crc(struct seq_file *m, void *data)
2783 {
2784         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2785         struct drm_device *dev = &dev_priv->drm;
2786         struct intel_connector *connector;
2787         struct drm_connector_list_iter conn_iter;
2788         struct intel_dp *intel_dp = NULL;
2789         int ret;
2790         u8 crc[6];
2791
2792         drm_modeset_lock_all(dev);
2793         drm_connector_list_iter_begin(dev, &conn_iter);
2794         for_each_intel_connector_iter(connector, &conn_iter) {
2795                 struct drm_crtc *crtc;
2796
2797                 if (!connector->base.state->best_encoder)
2798                         continue;
2799
2800                 crtc = connector->base.state->crtc;
2801                 if (!crtc->state->active)
2802                         continue;
2803
2804                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2805                         continue;
2806
2807                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2808
2809                 ret = intel_dp_sink_crc(intel_dp, crc);
2810                 if (ret)
2811                         goto out;
2812
2813                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2814                            crc[0], crc[1], crc[2],
2815                            crc[3], crc[4], crc[5]);
2816                 goto out;
2817         }
2818         ret = -ENODEV;
2819 out:
2820         drm_connector_list_iter_end(&conn_iter);
2821         drm_modeset_unlock_all(dev);
2822         return ret;
2823 }
2824
2825 static int i915_energy_uJ(struct seq_file *m, void *data)
2826 {
2827         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2828         unsigned long long power;
2829         u32 units;
2830
2831         if (INTEL_GEN(dev_priv) < 6)
2832                 return -ENODEV;
2833
2834         intel_runtime_pm_get(dev_priv);
2835
2836         if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) {
2837                 intel_runtime_pm_put(dev_priv);
2838                 return -ENODEV;
2839         }
2840
2841         units = (power & 0x1f00) >> 8;
2842         power = I915_READ(MCH_SECP_NRG_STTS);
2843         power = (1000000 * power) >> units; /* convert to uJ */
2844
2845         intel_runtime_pm_put(dev_priv);
2846
2847         seq_printf(m, "%llu", power);
2848
2849         return 0;
2850 }
2851
2852 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2853 {
2854         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2855         struct pci_dev *pdev = dev_priv->drm.pdev;
2856
2857         if (!HAS_RUNTIME_PM(dev_priv))
2858                 seq_puts(m, "Runtime power management not supported\n");
2859
2860         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2861         seq_printf(m, "IRQs disabled: %s\n",
2862                    yesno(!intel_irqs_enabled(dev_priv)));
2863 #ifdef CONFIG_PM
2864         seq_printf(m, "Usage count: %d\n",
2865                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2866 #else
2867         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2868 #endif
2869         seq_printf(m, "PCI device power state: %s [%d]\n",
2870                    pci_power_name(pdev->current_state),
2871                    pdev->current_state);
2872
2873         return 0;
2874 }
2875
2876 static int i915_power_domain_info(struct seq_file *m, void *unused)
2877 {
2878         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2879         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2880         int i;
2881
2882         mutex_lock(&power_domains->lock);
2883
2884         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2885         for (i = 0; i < power_domains->power_well_count; i++) {
2886                 struct i915_power_well *power_well;
2887                 enum intel_display_power_domain power_domain;
2888
2889                 power_well = &power_domains->power_wells[i];
2890                 seq_printf(m, "%-25s %d\n", power_well->name,
2891                            power_well->count);
2892
2893                 for_each_power_domain(power_domain, power_well->domains)
2894                         seq_printf(m, "  %-23s %d\n",
2895                                  intel_display_power_domain_str(power_domain),
2896                                  power_domains->domain_use_count[power_domain]);
2897         }
2898
2899         mutex_unlock(&power_domains->lock);
2900
2901         return 0;
2902 }
2903
2904 static int i915_dmc_info(struct seq_file *m, void *unused)
2905 {
2906         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2907         struct intel_csr *csr;
2908
2909         if (!HAS_CSR(dev_priv)) {
2910                 seq_puts(m, "not supported\n");
2911                 return 0;
2912         }
2913
2914         csr = &dev_priv->csr;
2915
2916         intel_runtime_pm_get(dev_priv);
2917
2918         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2919         seq_printf(m, "path: %s\n", csr->fw_path);
2920
2921         if (!csr->dmc_payload)
2922                 goto out;
2923
2924         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2925                    CSR_VERSION_MINOR(csr->version));
2926
2927         if (IS_KABYLAKE(dev_priv) ||
2928             (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
2929                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2930                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2931                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2932                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2933         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2934                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2935                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2936         }
2937
2938 out:
2939         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2940         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2941         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2942
2943         intel_runtime_pm_put(dev_priv);
2944
2945         return 0;
2946 }
2947
2948 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2949                                  struct drm_display_mode *mode)
2950 {
2951         int i;
2952
2953         for (i = 0; i < tabs; i++)
2954                 seq_putc(m, '\t');
2955
2956         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2957                    mode->base.id, mode->name,
2958                    mode->vrefresh, mode->clock,
2959                    mode->hdisplay, mode->hsync_start,
2960                    mode->hsync_end, mode->htotal,
2961                    mode->vdisplay, mode->vsync_start,
2962                    mode->vsync_end, mode->vtotal,
2963                    mode->type, mode->flags);
2964 }
2965
2966 static void intel_encoder_info(struct seq_file *m,
2967                                struct intel_crtc *intel_crtc,
2968                                struct intel_encoder *intel_encoder)
2969 {
2970         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2971         struct drm_device *dev = &dev_priv->drm;
2972         struct drm_crtc *crtc = &intel_crtc->base;
2973         struct intel_connector *intel_connector;
2974         struct drm_encoder *encoder;
2975
2976         encoder = &intel_encoder->base;
2977         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2978                    encoder->base.id, encoder->name);
2979         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2980                 struct drm_connector *connector = &intel_connector->base;
2981                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2982                            connector->base.id,
2983                            connector->name,
2984                            drm_get_connector_status_name(connector->status));
2985                 if (connector->status == connector_status_connected) {
2986                         struct drm_display_mode *mode = &crtc->mode;
2987                         seq_printf(m, ", mode:\n");
2988                         intel_seq_print_mode(m, 2, mode);
2989                 } else {
2990                         seq_putc(m, '\n');
2991                 }
2992         }
2993 }
2994
2995 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2996 {
2997         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2998         struct drm_device *dev = &dev_priv->drm;
2999         struct drm_crtc *crtc = &intel_crtc->base;
3000         struct intel_encoder *intel_encoder;
3001         struct drm_plane_state *plane_state = crtc->primary->state;
3002         struct drm_framebuffer *fb = plane_state->fb;
3003
3004         if (fb)
3005                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
3006                            fb->base.id, plane_state->src_x >> 16,
3007                            plane_state->src_y >> 16, fb->width, fb->height);
3008         else
3009                 seq_puts(m, "\tprimary plane disabled\n");
3010         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3011                 intel_encoder_info(m, intel_crtc, intel_encoder);
3012 }
3013
3014 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
3015 {
3016         struct drm_display_mode *mode = panel->fixed_mode;
3017
3018         seq_printf(m, "\tfixed mode:\n");
3019         intel_seq_print_mode(m, 2, mode);
3020 }
3021
3022 static void intel_dp_info(struct seq_file *m,
3023                           struct intel_connector *intel_connector)
3024 {
3025         struct intel_encoder *intel_encoder = intel_connector->encoder;
3026         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3027
3028         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
3029         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
3030         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
3031                 intel_panel_info(m, &intel_connector->panel);
3032
3033         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
3034                                 &intel_dp->aux);
3035 }
3036
3037 static void intel_dp_mst_info(struct seq_file *m,
3038                           struct intel_connector *intel_connector)
3039 {
3040         struct intel_encoder *intel_encoder = intel_connector->encoder;
3041         struct intel_dp_mst_encoder *intel_mst =
3042                 enc_to_mst(&intel_encoder->base);
3043         struct intel_digital_port *intel_dig_port = intel_mst->primary;
3044         struct intel_dp *intel_dp = &intel_dig_port->dp;
3045         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
3046                                         intel_connector->port);
3047
3048         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
3049 }
3050
3051 static void intel_hdmi_info(struct seq_file *m,
3052                             struct intel_connector *intel_connector)
3053 {
3054         struct intel_encoder *intel_encoder = intel_connector->encoder;
3055         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
3056
3057         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
3058 }
3059
3060 static void intel_lvds_info(struct seq_file *m,
3061                             struct intel_connector *intel_connector)
3062 {
3063         intel_panel_info(m, &intel_connector->panel);
3064 }
3065
3066 static void intel_connector_info(struct seq_file *m,
3067                                  struct drm_connector *connector)
3068 {
3069         struct intel_connector *intel_connector = to_intel_connector(connector);
3070         struct intel_encoder *intel_encoder = intel_connector->encoder;
3071         struct drm_display_mode *mode;
3072
3073         seq_printf(m, "connector %d: type %s, status: %s\n",
3074                    connector->base.id, connector->name,
3075                    drm_get_connector_status_name(connector->status));
3076         if (connector->status == connector_status_connected) {
3077                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3078                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3079                            connector->display_info.width_mm,
3080                            connector->display_info.height_mm);
3081                 seq_printf(m, "\tsubpixel order: %s\n",
3082                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3083                 seq_printf(m, "\tCEA rev: %d\n",
3084                            connector->display_info.cea_rev);
3085         }
3086
3087         if (!intel_encoder)
3088                 return;
3089
3090         switch (connector->connector_type) {
3091         case DRM_MODE_CONNECTOR_DisplayPort:
3092         case DRM_MODE_CONNECTOR_eDP:
3093                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3094                         intel_dp_mst_info(m, intel_connector);
3095                 else
3096                         intel_dp_info(m, intel_connector);
3097                 break;
3098         case DRM_MODE_CONNECTOR_LVDS:
3099                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3100                         intel_lvds_info(m, intel_connector);
3101                 break;
3102         case DRM_MODE_CONNECTOR_HDMIA:
3103                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3104                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3105                         intel_hdmi_info(m, intel_connector);
3106                 break;
3107         default:
3108                 break;
3109         }
3110
3111         seq_printf(m, "\tmodes:\n");
3112         list_for_each_entry(mode, &connector->modes, head)
3113                 intel_seq_print_mode(m, 2, mode);
3114 }
3115
3116 static const char *plane_type(enum drm_plane_type type)
3117 {
3118         switch (type) {
3119         case DRM_PLANE_TYPE_OVERLAY:
3120                 return "OVL";
3121         case DRM_PLANE_TYPE_PRIMARY:
3122                 return "PRI";
3123         case DRM_PLANE_TYPE_CURSOR:
3124                 return "CUR";
3125         /*
3126          * Deliberately omitting default: to generate compiler warnings
3127          * when a new drm_plane_type gets added.
3128          */
3129         }
3130
3131         return "unknown";
3132 }
3133
3134 static const char *plane_rotation(unsigned int rotation)
3135 {
3136         static char buf[48];
3137         /*
3138          * According to doc only one DRM_MODE_ROTATE_ is allowed but this
3139          * will print them all to visualize if the values are misused
3140          */
3141         snprintf(buf, sizeof(buf),
3142                  "%s%s%s%s%s%s(0x%08x)",
3143                  (rotation & DRM_MODE_ROTATE_0) ? "0 " : "",
3144                  (rotation & DRM_MODE_ROTATE_90) ? "90 " : "",
3145                  (rotation & DRM_MODE_ROTATE_180) ? "180 " : "",
3146                  (rotation & DRM_MODE_ROTATE_270) ? "270 " : "",
3147                  (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "",
3148                  (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "",
3149                  rotation);
3150
3151         return buf;
3152 }
3153
3154 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3155 {
3156         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3157         struct drm_device *dev = &dev_priv->drm;
3158         struct intel_plane *intel_plane;
3159
3160         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3161                 struct drm_plane_state *state;
3162                 struct drm_plane *plane = &intel_plane->base;
3163                 struct drm_format_name_buf format_name;
3164
3165                 if (!plane->state) {
3166                         seq_puts(m, "plane->state is NULL!\n");
3167                         continue;
3168                 }
3169
3170                 state = plane->state;
3171
3172                 if (state->fb) {
3173                         drm_get_format_name(state->fb->format->format,
3174                                             &format_name);
3175                 } else {
3176                         sprintf(format_name.str, "N/A");
3177                 }
3178
3179                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3180                            plane->base.id,
3181                            plane_type(intel_plane->base.type),
3182                            state->crtc_x, state->crtc_y,
3183                            state->crtc_w, state->crtc_h,
3184                            (state->src_x >> 16),
3185                            ((state->src_x & 0xffff) * 15625) >> 10,
3186                            (state->src_y >> 16),
3187                            ((state->src_y & 0xffff) * 15625) >> 10,
3188                            (state->src_w >> 16),
3189                            ((state->src_w & 0xffff) * 15625) >> 10,
3190                            (state->src_h >> 16),
3191                            ((state->src_h & 0xffff) * 15625) >> 10,
3192                            format_name.str,
3193                            plane_rotation(state->rotation));
3194         }
3195 }
3196
3197 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3198 {
3199         struct intel_crtc_state *pipe_config;
3200         int num_scalers = intel_crtc->num_scalers;
3201         int i;
3202
3203         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3204
3205         /* Not all platformas have a scaler */
3206         if (num_scalers) {
3207                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3208                            num_scalers,
3209                            pipe_config->scaler_state.scaler_users,
3210                            pipe_config->scaler_state.scaler_id);
3211
3212                 for (i = 0; i < num_scalers; i++) {
3213                         struct intel_scaler *sc =
3214                                         &pipe_config->scaler_state.scalers[i];
3215
3216                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3217                                    i, yesno(sc->in_use), sc->mode);
3218                 }
3219                 seq_puts(m, "\n");
3220         } else {
3221                 seq_puts(m, "\tNo scalers available on this platform\n");
3222         }
3223 }
3224
3225 static int i915_display_info(struct seq_file *m, void *unused)
3226 {
3227         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3228         struct drm_device *dev = &dev_priv->drm;
3229         struct intel_crtc *crtc;
3230         struct drm_connector *connector;
3231         struct drm_connector_list_iter conn_iter;
3232
3233         intel_runtime_pm_get(dev_priv);
3234         seq_printf(m, "CRTC info\n");
3235         seq_printf(m, "---------\n");
3236         for_each_intel_crtc(dev, crtc) {
3237                 struct intel_crtc_state *pipe_config;
3238
3239                 drm_modeset_lock(&crtc->base.mutex, NULL);
3240                 pipe_config = to_intel_crtc_state(crtc->base.state);
3241
3242                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3243                            crtc->base.base.id, pipe_name(crtc->pipe),
3244                            yesno(pipe_config->base.active),
3245                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3246                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3247
3248                 if (pipe_config->base.active) {
3249                         struct intel_plane *cursor =
3250                                 to_intel_plane(crtc->base.cursor);
3251
3252                         intel_crtc_info(m, crtc);
3253
3254                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n",
3255                                    yesno(cursor->base.state->visible),
3256                                    cursor->base.state->crtc_x,
3257                                    cursor->base.state->crtc_y,
3258                                    cursor->base.state->crtc_w,
3259                                    cursor->base.state->crtc_h,
3260                                    cursor->cursor.base);
3261                         intel_scaler_info(m, crtc);
3262                         intel_plane_info(m, crtc);
3263                 }
3264
3265                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3266                            yesno(!crtc->cpu_fifo_underrun_disabled),
3267                            yesno(!crtc->pch_fifo_underrun_disabled));
3268                 drm_modeset_unlock(&crtc->base.mutex);
3269         }
3270
3271         seq_printf(m, "\n");
3272         seq_printf(m, "Connector info\n");
3273         seq_printf(m, "--------------\n");
3274         mutex_lock(&dev->mode_config.mutex);
3275         drm_connector_list_iter_begin(dev, &conn_iter);
3276         drm_for_each_connector_iter(connector, &conn_iter)
3277                 intel_connector_info(m, connector);
3278         drm_connector_list_iter_end(&conn_iter);
3279         mutex_unlock(&dev->mode_config.mutex);
3280
3281         intel_runtime_pm_put(dev_priv);
3282
3283         return 0;
3284 }
3285
3286 static int i915_engine_info(struct seq_file *m, void *unused)
3287 {
3288         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3289         struct intel_engine_cs *engine;
3290         enum intel_engine_id id;
3291         struct drm_printer p;
3292
3293         intel_runtime_pm_get(dev_priv);
3294
3295         seq_printf(m, "GT awake? %s\n",
3296                    yesno(dev_priv->gt.awake));
3297         seq_printf(m, "Global active requests: %d\n",
3298                    dev_priv->gt.active_requests);
3299
3300         p = drm_seq_file_printer(m);
3301         for_each_engine(engine, dev_priv, id)
3302                 intel_engine_dump(engine, &p);
3303
3304         intel_runtime_pm_put(dev_priv);
3305
3306         return 0;
3307 }
3308
3309 static int i915_semaphore_status(struct seq_file *m, void *unused)
3310 {
3311         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3312         struct drm_device *dev = &dev_priv->drm;
3313         struct intel_engine_cs *engine;
3314         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3315         enum intel_engine_id id;
3316         int j, ret;
3317
3318         if (!i915_modparams.semaphores) {
3319                 seq_puts(m, "Semaphores are disabled\n");
3320                 return 0;
3321         }
3322
3323         ret = mutex_lock_interruptible(&dev->struct_mutex);
3324         if (ret)
3325                 return ret;
3326         intel_runtime_pm_get(dev_priv);
3327
3328         if (IS_BROADWELL(dev_priv)) {
3329                 struct page *page;
3330                 uint64_t *seqno;
3331
3332                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3333
3334                 seqno = (uint64_t *)kmap_atomic(page);
3335                 for_each_engine(engine, dev_priv, id) {
3336                         uint64_t offset;
3337
3338                         seq_printf(m, "%s\n", engine->name);
3339
3340                         seq_puts(m, "  Last signal:");
3341                         for (j = 0; j < num_rings; j++) {
3342                                 offset = id * I915_NUM_ENGINES + j;
3343                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3344                                            seqno[offset], offset * 8);
3345                         }
3346                         seq_putc(m, '\n');
3347
3348                         seq_puts(m, "  Last wait:  ");
3349                         for (j = 0; j < num_rings; j++) {
3350                                 offset = id + (j * I915_NUM_ENGINES);
3351                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3352                                            seqno[offset], offset * 8);
3353                         }
3354                         seq_putc(m, '\n');
3355
3356                 }
3357                 kunmap_atomic(seqno);
3358         } else {
3359                 seq_puts(m, "  Last signal:");
3360                 for_each_engine(engine, dev_priv, id)
3361                         for (j = 0; j < num_rings; j++)
3362                                 seq_printf(m, "0x%08x\n",
3363                                            I915_READ(engine->semaphore.mbox.signal[j]));
3364                 seq_putc(m, '\n');
3365         }
3366
3367         intel_runtime_pm_put(dev_priv);
3368         mutex_unlock(&dev->struct_mutex);
3369         return 0;
3370 }
3371
3372 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3373 {
3374         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3375         struct drm_device *dev = &dev_priv->drm;
3376         int i;
3377
3378         drm_modeset_lock_all(dev);
3379         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3380                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3381
3382                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3383                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3384                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3385                 seq_printf(m, " tracked hardware state:\n");
3386                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3387                 seq_printf(m, " dpll_md: 0x%08x\n",
3388                            pll->state.hw_state.dpll_md);
3389                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3390                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3391                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3392         }
3393         drm_modeset_unlock_all(dev);
3394
3395         return 0;
3396 }
3397
3398 static int i915_wa_registers(struct seq_file *m, void *unused)
3399 {
3400         int i;
3401         int ret;
3402         struct intel_engine_cs *engine;
3403         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3404         struct drm_device *dev = &dev_priv->drm;
3405         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3406         enum intel_engine_id id;
3407
3408         ret = mutex_lock_interruptible(&dev->struct_mutex);
3409         if (ret)
3410                 return ret;
3411
3412         intel_runtime_pm_get(dev_priv);
3413
3414         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3415         for_each_engine(engine, dev_priv, id)
3416                 seq_printf(m, "HW whitelist count for %s: %d\n",
3417                            engine->name, workarounds->hw_whitelist_count[id]);
3418         for (i = 0; i < workarounds->count; ++i) {
3419                 i915_reg_t addr;
3420                 u32 mask, value, read;
3421                 bool ok;
3422
3423                 addr = workarounds->reg[i].addr;
3424                 mask = workarounds->reg[i].mask;
3425                 value = workarounds->reg[i].value;
3426                 read = I915_READ(addr);
3427                 ok = (value & mask) == (read & mask);
3428                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3429                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3430         }
3431
3432         intel_runtime_pm_put(dev_priv);
3433         mutex_unlock(&dev->struct_mutex);
3434
3435         return 0;
3436 }
3437
3438 static int i915_ipc_status_show(struct seq_file *m, void *data)
3439 {
3440         struct drm_i915_private *dev_priv = m->private;
3441
3442         seq_printf(m, "Isochronous Priority Control: %s\n",
3443                         yesno(dev_priv->ipc_enabled));
3444         return 0;
3445 }
3446
3447 static int i915_ipc_status_open(struct inode *inode, struct file *file)
3448 {
3449         struct drm_i915_private *dev_priv = inode->i_private;
3450
3451         if (!HAS_IPC(dev_priv))
3452                 return -ENODEV;
3453
3454         return single_open(file, i915_ipc_status_show, dev_priv);
3455 }
3456
3457 static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf,
3458                                      size_t len, loff_t *offp)
3459 {
3460         struct seq_file *m = file->private_data;
3461         struct drm_i915_private *dev_priv = m->private;
3462         int ret;
3463         bool enable;
3464
3465         ret = kstrtobool_from_user(ubuf, len, &enable);
3466         if (ret < 0)
3467                 return ret;
3468
3469         intel_runtime_pm_get(dev_priv);
3470         if (!dev_priv->ipc_enabled && enable)
3471                 DRM_INFO("Enabling IPC: WM will be proper only after next commit\n");
3472         dev_priv->wm.distrust_bios_wm = true;
3473         dev_priv->ipc_enabled = enable;
3474         intel_enable_ipc(dev_priv);
3475         intel_runtime_pm_put(dev_priv);
3476
3477         return len;
3478 }
3479
3480 static const struct file_operations i915_ipc_status_fops = {
3481         .owner = THIS_MODULE,
3482         .open = i915_ipc_status_open,
3483         .read = seq_read,
3484         .llseek = seq_lseek,
3485         .release = single_release,
3486         .write = i915_ipc_status_write
3487 };
3488
3489 static int i915_ddb_info(struct seq_file *m, void *unused)
3490 {
3491         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3492         struct drm_device *dev = &dev_priv->drm;
3493         struct skl_ddb_allocation *ddb;
3494         struct skl_ddb_entry *entry;
3495         enum pipe pipe;
3496         int plane;
3497
3498         if (INTEL_GEN(dev_priv) < 9)
3499                 return 0;
3500
3501         drm_modeset_lock_all(dev);
3502
3503         ddb = &dev_priv->wm.skl_hw.ddb;
3504
3505         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3506
3507         for_each_pipe(dev_priv, pipe) {
3508                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3509
3510                 for_each_universal_plane(dev_priv, pipe, plane) {
3511                         entry = &ddb->plane[pipe][plane];
3512                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3513                                    entry->start, entry->end,
3514                                    skl_ddb_entry_size(entry));
3515                 }
3516
3517                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3518                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3519                            entry->end, skl_ddb_entry_size(entry));
3520         }
3521
3522         drm_modeset_unlock_all(dev);
3523
3524         return 0;
3525 }
3526
3527 static void drrs_status_per_crtc(struct seq_file *m,
3528                                  struct drm_device *dev,
3529                                  struct intel_crtc *intel_crtc)
3530 {
3531         struct drm_i915_private *dev_priv = to_i915(dev);
3532         struct i915_drrs *drrs = &dev_priv->drrs;
3533         int vrefresh = 0;
3534         struct drm_connector *connector;
3535         struct drm_connector_list_iter conn_iter;
3536
3537         drm_connector_list_iter_begin(dev, &conn_iter);
3538         drm_for_each_connector_iter(connector, &conn_iter) {
3539                 if (connector->state->crtc != &intel_crtc->base)
3540                         continue;
3541
3542                 seq_printf(m, "%s:\n", connector->name);
3543         }
3544         drm_connector_list_iter_end(&conn_iter);
3545
3546         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3547                 seq_puts(m, "\tVBT: DRRS_type: Static");
3548         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3549                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3550         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3551                 seq_puts(m, "\tVBT: DRRS_type: None");
3552         else
3553                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3554
3555         seq_puts(m, "\n\n");
3556
3557         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3558                 struct intel_panel *panel;
3559
3560                 mutex_lock(&drrs->mutex);
3561                 /* DRRS Supported */
3562                 seq_puts(m, "\tDRRS Supported: Yes\n");
3563
3564                 /* disable_drrs() will make drrs->dp NULL */
3565                 if (!drrs->dp) {
3566                         seq_puts(m, "Idleness DRRS: Disabled");
3567                         mutex_unlock(&drrs->mutex);
3568                         return;
3569                 }
3570
3571                 panel = &drrs->dp->attached_connector->panel;
3572                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3573                                         drrs->busy_frontbuffer_bits);
3574
3575                 seq_puts(m, "\n\t\t");
3576                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3577                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3578                         vrefresh = panel->fixed_mode->vrefresh;
3579                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3580                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3581                         vrefresh = panel->downclock_mode->vrefresh;
3582                 } else {
3583                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3584                                                 drrs->refresh_rate_type);
3585                         mutex_unlock(&drrs->mutex);
3586                         return;
3587                 }
3588                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3589
3590                 seq_puts(m, "\n\t\t");
3591                 mutex_unlock(&drrs->mutex);
3592         } else {
3593                 /* DRRS not supported. Print the VBT parameter*/
3594                 seq_puts(m, "\tDRRS Supported : No");
3595         }
3596         seq_puts(m, "\n");
3597 }
3598
3599 static int i915_drrs_status(struct seq_file *m, void *unused)
3600 {
3601         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3602         struct drm_device *dev = &dev_priv->drm;
3603         struct intel_crtc *intel_crtc;
3604         int active_crtc_cnt = 0;
3605
3606         drm_modeset_lock_all(dev);
3607         for_each_intel_crtc(dev, intel_crtc) {
3608                 if (intel_crtc->base.state->active) {
3609                         active_crtc_cnt++;
3610                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3611
3612                         drrs_status_per_crtc(m, dev, intel_crtc);
3613                 }
3614         }
3615         drm_modeset_unlock_all(dev);
3616
3617         if (!active_crtc_cnt)
3618                 seq_puts(m, "No active crtc found\n");
3619
3620         return 0;
3621 }
3622
3623 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3624 {
3625         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3626         struct drm_device *dev = &dev_priv->drm;
3627         struct intel_encoder *intel_encoder;
3628         struct intel_digital_port *intel_dig_port;
3629         struct drm_connector *connector;
3630         struct drm_connector_list_iter conn_iter;
3631
3632         drm_connector_list_iter_begin(dev, &conn_iter);
3633         drm_for_each_connector_iter(connector, &conn_iter) {
3634                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3635                         continue;
3636
3637                 intel_encoder = intel_attached_encoder(connector);
3638                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3639                         continue;
3640
3641                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3642                 if (!intel_dig_port->dp.can_mst)
3643                         continue;
3644
3645                 seq_printf(m, "MST Source Port %c\n",
3646                            port_name(intel_dig_port->port));
3647                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3648         }
3649         drm_connector_list_iter_end(&conn_iter);
3650
3651         return 0;
3652 }
3653
3654 static ssize_t i915_displayport_test_active_write(struct file *file,
3655                                                   const char __user *ubuf,
3656                                                   size_t len, loff_t *offp)
3657 {
3658         char *input_buffer;
3659         int status = 0;
3660         struct drm_device *dev;
3661         struct drm_connector *connector;
3662         struct drm_connector_list_iter conn_iter;
3663         struct intel_dp *intel_dp;
3664         int val = 0;
3665
3666         dev = ((struct seq_file *)file->private_data)->private;
3667
3668         if (len == 0)
3669                 return 0;
3670
3671         input_buffer = memdup_user_nul(ubuf, len);
3672         if (IS_ERR(input_buffer))
3673                 return PTR_ERR(input_buffer);
3674
3675         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3676
3677         drm_connector_list_iter_begin(dev, &conn_iter);
3678         drm_for_each_connector_iter(connector, &conn_iter) {
3679                 struct intel_encoder *encoder;
3680
3681                 if (connector->connector_type !=
3682                     DRM_MODE_CONNECTOR_DisplayPort)
3683                         continue;
3684
3685                 encoder = to_intel_encoder(connector->encoder);
3686                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3687                         continue;
3688
3689                 if (encoder && connector->status == connector_status_connected) {
3690                         intel_dp = enc_to_intel_dp(&encoder->base);
3691                         status = kstrtoint(input_buffer, 10, &val);
3692                         if (status < 0)
3693                                 break;
3694                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3695                         /* To prevent erroneous activation of the compliance
3696                          * testing code, only accept an actual value of 1 here
3697                          */
3698                         if (val == 1)
3699                                 intel_dp->compliance.test_active = 1;
3700                         else
3701                                 intel_dp->compliance.test_active = 0;
3702                 }
3703         }
3704         drm_connector_list_iter_end(&conn_iter);
3705         kfree(input_buffer);
3706         if (status < 0)
3707                 return status;
3708
3709         *offp += len;
3710         return len;
3711 }
3712
3713 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3714 {
3715         struct drm_device *dev = m->private;
3716         struct drm_connector *connector;
3717         struct drm_connector_list_iter conn_iter;
3718         struct intel_dp *intel_dp;
3719
3720         drm_connector_list_iter_begin(dev, &conn_iter);
3721         drm_for_each_connector_iter(connector, &conn_iter) {
3722                 struct intel_encoder *encoder;
3723
3724                 if (connector->connector_type !=
3725                     DRM_MODE_CONNECTOR_DisplayPort)
3726                         continue;
3727
3728                 encoder = to_intel_encoder(connector->encoder);
3729                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3730                         continue;
3731
3732                 if (encoder && connector->status == connector_status_connected) {
3733                         intel_dp = enc_to_intel_dp(&encoder->base);
3734                         if (intel_dp->compliance.test_active)
3735                                 seq_puts(m, "1");
3736                         else
3737                                 seq_puts(m, "0");
3738                 } else
3739                         seq_puts(m, "0");
3740         }
3741         drm_connector_list_iter_end(&conn_iter);
3742
3743         return 0;
3744 }
3745
3746 static int i915_displayport_test_active_open(struct inode *inode,
3747                                              struct file *file)
3748 {
3749         struct drm_i915_private *dev_priv = inode->i_private;
3750
3751         return single_open(file, i915_displayport_test_active_show,
3752                            &dev_priv->drm);
3753 }
3754
3755 static const struct file_operations i915_displayport_test_active_fops = {
3756         .owner = THIS_MODULE,
3757         .open = i915_displayport_test_active_open,
3758         .read = seq_read,
3759         .llseek = seq_lseek,
3760         .release = single_release,
3761         .write = i915_displayport_test_active_write
3762 };
3763
3764 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3765 {
3766         struct drm_device *dev = m->private;
3767         struct drm_connector *connector;
3768         struct drm_connector_list_iter conn_iter;
3769         struct intel_dp *intel_dp;
3770
3771         drm_connector_list_iter_begin(dev, &conn_iter);
3772         drm_for_each_connector_iter(connector, &conn_iter) {
3773                 struct intel_encoder *encoder;
3774
3775                 if (connector->connector_type !=
3776                     DRM_MODE_CONNECTOR_DisplayPort)
3777                         continue;
3778
3779                 encoder = to_intel_encoder(connector->encoder);
3780                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3781                         continue;
3782
3783                 if (encoder && connector->status == connector_status_connected) {
3784                         intel_dp = enc_to_intel_dp(&encoder->base);
3785                         if (intel_dp->compliance.test_type ==
3786                             DP_TEST_LINK_EDID_READ)
3787                                 seq_printf(m, "%lx",
3788                                            intel_dp->compliance.test_data.edid);
3789                         else if (intel_dp->compliance.test_type ==
3790                                  DP_TEST_LINK_VIDEO_PATTERN) {
3791                                 seq_printf(m, "hdisplay: %d\n",
3792                                            intel_dp->compliance.test_data.hdisplay);
3793                                 seq_printf(m, "vdisplay: %d\n",
3794                                            intel_dp->compliance.test_data.vdisplay);
3795                                 seq_printf(m, "bpc: %u\n",
3796                                            intel_dp->compliance.test_data.bpc);
3797                         }
3798                 } else
3799                         seq_puts(m, "0");
3800         }
3801         drm_connector_list_iter_end(&conn_iter);
3802
3803         return 0;
3804 }
3805 static int i915_displayport_test_data_open(struct inode *inode,
3806                                            struct file *file)
3807 {
3808         struct drm_i915_private *dev_priv = inode->i_private;
3809
3810         return single_open(file, i915_displayport_test_data_show,
3811                            &dev_priv->drm);
3812 }
3813
3814 static const struct file_operations i915_displayport_test_data_fops = {
3815         .owner = THIS_MODULE,
3816         .open = i915_displayport_test_data_open,
3817         .read = seq_read,
3818         .llseek = seq_lseek,
3819         .release = single_release
3820 };
3821
3822 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3823 {
3824         struct drm_device *dev = m->private;
3825         struct drm_connector *connector;
3826         struct drm_connector_list_iter conn_iter;
3827         struct intel_dp *intel_dp;
3828
3829         drm_connector_list_iter_begin(dev, &conn_iter);
3830         drm_for_each_connector_iter(connector, &conn_iter) {
3831                 struct intel_encoder *encoder;
3832
3833                 if (connector->connector_type !=
3834                     DRM_MODE_CONNECTOR_DisplayPort)
3835                         continue;
3836
3837                 encoder = to_intel_encoder(connector->encoder);
3838                 if (encoder && encoder->type == INTEL_OUTPUT_DP_MST)
3839                         continue;
3840
3841                 if (encoder && connector->status == connector_status_connected) {
3842                         intel_dp = enc_to_intel_dp(&encoder->base);
3843                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3844                 } else
3845                         seq_puts(m, "0");
3846         }
3847         drm_connector_list_iter_end(&conn_iter);
3848
3849         return 0;
3850 }
3851
3852 static int i915_displayport_test_type_open(struct inode *inode,
3853                                        struct file *file)
3854 {
3855         struct drm_i915_private *dev_priv = inode->i_private;
3856
3857         return single_open(file, i915_displayport_test_type_show,
3858                            &dev_priv->drm);
3859 }
3860
3861 static const struct file_operations i915_displayport_test_type_fops = {
3862         .owner = THIS_MODULE,
3863         .open = i915_displayport_test_type_open,
3864         .read = seq_read,
3865         .llseek = seq_lseek,
3866         .release = single_release
3867 };
3868
3869 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3870 {
3871         struct drm_i915_private *dev_priv = m->private;
3872         struct drm_device *dev = &dev_priv->drm;
3873         int level;
3874         int num_levels;
3875
3876         if (IS_CHERRYVIEW(dev_priv))
3877                 num_levels = 3;
3878         else if (IS_VALLEYVIEW(dev_priv))
3879                 num_levels = 1;
3880         else if (IS_G4X(dev_priv))
3881                 num_levels = 3;
3882         else
3883                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3884
3885         drm_modeset_lock_all(dev);
3886
3887         for (level = 0; level < num_levels; level++) {
3888                 unsigned int latency = wm[level];
3889
3890                 /*
3891                  * - WM1+ latency values in 0.5us units
3892                  * - latencies are in us on gen9/vlv/chv
3893                  */
3894                 if (INTEL_GEN(dev_priv) >= 9 ||
3895                     IS_VALLEYVIEW(dev_priv) ||
3896                     IS_CHERRYVIEW(dev_priv) ||
3897                     IS_G4X(dev_priv))
3898                         latency *= 10;
3899                 else if (level > 0)
3900                         latency *= 5;
3901
3902                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3903                            level, wm[level], latency / 10, latency % 10);
3904         }
3905
3906         drm_modeset_unlock_all(dev);
3907 }
3908
3909 static int pri_wm_latency_show(struct seq_file *m, void *data)
3910 {
3911         struct drm_i915_private *dev_priv = m->private;
3912         const uint16_t *latencies;
3913
3914         if (INTEL_GEN(dev_priv) >= 9)
3915                 latencies = dev_priv->wm.skl_latency;
3916         else
3917                 latencies = dev_priv->wm.pri_latency;
3918
3919         wm_latency_show(m, latencies);
3920
3921         return 0;
3922 }
3923
3924 static int spr_wm_latency_show(struct seq_file *m, void *data)
3925 {
3926         struct drm_i915_private *dev_priv = m->private;
3927         const uint16_t *latencies;
3928
3929         if (INTEL_GEN(dev_priv) >= 9)
3930                 latencies = dev_priv->wm.skl_latency;
3931         else
3932                 latencies = dev_priv->wm.spr_latency;
3933
3934         wm_latency_show(m, latencies);
3935
3936         return 0;
3937 }
3938
3939 static int cur_wm_latency_show(struct seq_file *m, void *data)
3940 {
3941         struct drm_i915_private *dev_priv = m->private;
3942         const uint16_t *latencies;
3943
3944         if (INTEL_GEN(dev_priv) >= 9)
3945                 latencies = dev_priv->wm.skl_latency;
3946         else
3947                 latencies = dev_priv->wm.cur_latency;
3948
3949         wm_latency_show(m, latencies);
3950
3951         return 0;
3952 }
3953
3954 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3955 {
3956         struct drm_i915_private *dev_priv = inode->i_private;
3957
3958         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
3959                 return -ENODEV;
3960
3961         return single_open(file, pri_wm_latency_show, dev_priv);
3962 }
3963
3964 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3965 {
3966         struct drm_i915_private *dev_priv = inode->i_private;
3967
3968         if (HAS_GMCH_DISPLAY(dev_priv))
3969                 return -ENODEV;
3970
3971         return single_open(file, spr_wm_latency_show, dev_priv);
3972 }
3973
3974 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3975 {
3976         struct drm_i915_private *dev_priv = inode->i_private;
3977
3978         if (HAS_GMCH_DISPLAY(dev_priv))
3979                 return -ENODEV;
3980
3981         return single_open(file, cur_wm_latency_show, dev_priv);
3982 }
3983
3984 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3985                                 size_t len, loff_t *offp, uint16_t wm[8])
3986 {
3987         struct seq_file *m = file->private_data;
3988         struct drm_i915_private *dev_priv = m->private;
3989         struct drm_device *dev = &dev_priv->drm;
3990         uint16_t new[8] = { 0 };
3991         int num_levels;
3992         int level;
3993         int ret;
3994         char tmp[32];
3995
3996         if (IS_CHERRYVIEW(dev_priv))
3997                 num_levels = 3;
3998         else if (IS_VALLEYVIEW(dev_priv))
3999                 num_levels = 1;
4000         else if (IS_G4X(dev_priv))
4001                 num_levels = 3;
4002         else
4003                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4004
4005         if (len >= sizeof(tmp))
4006                 return -EINVAL;
4007
4008         if (copy_from_user(tmp, ubuf, len))
4009                 return -EFAULT;
4010
4011         tmp[len] = '\0';
4012
4013         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4014                      &new[0], &new[1], &new[2], &new[3],
4015                      &new[4], &new[5], &new[6], &new[7]);
4016         if (ret != num_levels)
4017                 return -EINVAL;
4018
4019         drm_modeset_lock_all(dev);
4020
4021         for (level = 0; level < num_levels; level++)
4022                 wm[level] = new[level];
4023
4024         drm_modeset_unlock_all(dev);
4025
4026         return len;
4027 }
4028
4029
4030 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4031                                     size_t len, loff_t *offp)
4032 {
4033         struct seq_file *m = file->private_data;
4034         struct drm_i915_private *dev_priv = m->private;
4035         uint16_t *latencies;
4036
4037         if (INTEL_GEN(dev_priv) >= 9)
4038                 latencies = dev_priv->wm.skl_latency;
4039         else
4040                 latencies = dev_priv->wm.pri_latency;
4041
4042         return wm_latency_write(file, ubuf, len, offp, latencies);
4043 }
4044
4045 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4046                                     size_t len, loff_t *offp)
4047 {
4048         struct seq_file *m = file->private_data;
4049         struct drm_i915_private *dev_priv = m->private;
4050         uint16_t *latencies;
4051
4052         if (INTEL_GEN(dev_priv) >= 9)
4053                 latencies = dev_priv->wm.skl_latency;
4054         else
4055                 latencies = dev_priv->wm.spr_latency;
4056
4057         return wm_latency_write(file, ubuf, len, offp, latencies);
4058 }
4059
4060 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4061                                     size_t len, loff_t *offp)
4062 {
4063         struct seq_file *m = file->private_data;
4064         struct drm_i915_private *dev_priv = m->private;
4065         uint16_t *latencies;
4066
4067         if (INTEL_GEN(dev_priv) >= 9)
4068                 latencies = dev_priv->wm.skl_latency;
4069         else
4070                 latencies = dev_priv->wm.cur_latency;
4071
4072         return wm_latency_write(file, ubuf, len, offp, latencies);
4073 }
4074
4075 static const struct file_operations i915_pri_wm_latency_fops = {
4076         .owner = THIS_MODULE,
4077         .open = pri_wm_latency_open,
4078         .read = seq_read,
4079         .llseek = seq_lseek,
4080         .release = single_release,
4081         .write = pri_wm_latency_write
4082 };
4083
4084 static const struct file_operations i915_spr_wm_latency_fops = {
4085         .owner = THIS_MODULE,
4086         .open = spr_wm_latency_open,
4087         .read = seq_read,
4088         .llseek = seq_lseek,
4089         .release = single_release,
4090         .write = spr_wm_latency_write
4091 };
4092
4093 static const struct file_operations i915_cur_wm_latency_fops = {
4094         .owner = THIS_MODULE,
4095         .open = cur_wm_latency_open,
4096         .read = seq_read,
4097         .llseek = seq_lseek,
4098         .release = single_release,
4099         .write = cur_wm_latency_write
4100 };
4101
4102 static int
4103 i915_wedged_get(void *data, u64 *val)
4104 {
4105         struct drm_i915_private *dev_priv = data;
4106
4107         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4108
4109         return 0;
4110 }
4111
4112 static int
4113 i915_wedged_set(void *data, u64 val)
4114 {
4115         struct drm_i915_private *i915 = data;
4116         struct intel_engine_cs *engine;
4117         unsigned int tmp;
4118
4119         /*
4120          * There is no safeguard against this debugfs entry colliding
4121          * with the hangcheck calling same i915_handle_error() in
4122          * parallel, causing an explosion. For now we assume that the
4123          * test harness is responsible enough not to inject gpu hangs
4124          * while it is writing to 'i915_wedged'
4125          */
4126
4127         if (i915_reset_backoff(&i915->gpu_error))
4128                 return -EAGAIN;
4129
4130         for_each_engine_masked(engine, i915, val, tmp) {
4131                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4132                 engine->hangcheck.stalled = true;
4133         }
4134
4135         i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4136
4137         wait_on_bit(&i915->gpu_error.flags,
4138                     I915_RESET_HANDOFF,
4139                     TASK_UNINTERRUPTIBLE);
4140
4141         return 0;
4142 }
4143
4144 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4145                         i915_wedged_get, i915_wedged_set,
4146                         "%llu\n");
4147
4148 static int
4149 fault_irq_set(struct drm_i915_private *i915,
4150               unsigned long *irq,
4151               unsigned long val)
4152 {
4153         int err;
4154
4155         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4156         if (err)
4157                 return err;
4158
4159         err = i915_gem_wait_for_idle(i915,
4160                                      I915_WAIT_LOCKED |
4161                                      I915_WAIT_INTERRUPTIBLE);
4162         if (err)
4163                 goto err_unlock;
4164
4165         *irq = val;
4166         mutex_unlock(&i915->drm.struct_mutex);
4167
4168         /* Flush idle worker to disarm irq */
4169         drain_delayed_work(&i915->gt.idle_work);
4170
4171         return 0;
4172
4173 err_unlock:
4174         mutex_unlock(&i915->drm.struct_mutex);
4175         return err;
4176 }
4177
4178 static int
4179 i915_ring_missed_irq_get(void *data, u64 *val)
4180 {
4181         struct drm_i915_private *dev_priv = data;
4182
4183         *val = dev_priv->gpu_error.missed_irq_rings;
4184         return 0;
4185 }
4186
4187 static int
4188 i915_ring_missed_irq_set(void *data, u64 val)
4189 {
4190         struct drm_i915_private *i915 = data;
4191
4192         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4193 }
4194
4195 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4196                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4197                         "0x%08llx\n");
4198
4199 static int
4200 i915_ring_test_irq_get(void *data, u64 *val)
4201 {
4202         struct drm_i915_private *dev_priv = data;
4203
4204         *val = dev_priv->gpu_error.test_irq_rings;
4205
4206         return 0;
4207 }
4208
4209 static int
4210 i915_ring_test_irq_set(void *data, u64 val)
4211 {
4212         struct drm_i915_private *i915 = data;
4213
4214         val &= INTEL_INFO(i915)->ring_mask;
4215         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4216
4217         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4218 }
4219
4220 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4221                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4222                         "0x%08llx\n");
4223
4224 #define DROP_UNBOUND 0x1
4225 #define DROP_BOUND 0x2
4226 #define DROP_RETIRE 0x4
4227 #define DROP_ACTIVE 0x8
4228 #define DROP_FREED 0x10
4229 #define DROP_SHRINK_ALL 0x20
4230 #define DROP_ALL (DROP_UNBOUND  | \
4231                   DROP_BOUND    | \
4232                   DROP_RETIRE   | \
4233                   DROP_ACTIVE   | \
4234                   DROP_FREED    | \
4235                   DROP_SHRINK_ALL)
4236 static int
4237 i915_drop_caches_get(void *data, u64 *val)
4238 {
4239         *val = DROP_ALL;
4240
4241         return 0;
4242 }
4243
4244 static int
4245 i915_drop_caches_set(void *data, u64 val)
4246 {
4247         struct drm_i915_private *dev_priv = data;
4248         struct drm_device *dev = &dev_priv->drm;
4249         int ret = 0;
4250
4251         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4252
4253         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4254          * on ioctls on -EAGAIN. */
4255         if (val & (DROP_ACTIVE | DROP_RETIRE)) {
4256                 ret = mutex_lock_interruptible(&dev->struct_mutex);
4257                 if (ret)
4258                         return ret;
4259
4260                 if (val & DROP_ACTIVE)
4261                         ret = i915_gem_wait_for_idle(dev_priv,
4262                                                      I915_WAIT_INTERRUPTIBLE |
4263                                                      I915_WAIT_LOCKED);
4264
4265                 if (val & DROP_RETIRE)
4266                         i915_gem_retire_requests(dev_priv);
4267
4268                 mutex_unlock(&dev->struct_mutex);
4269         }
4270
4271         fs_reclaim_acquire(GFP_KERNEL);
4272         if (val & DROP_BOUND)
4273                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_BOUND);
4274
4275         if (val & DROP_UNBOUND)
4276                 i915_gem_shrink(dev_priv, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
4277
4278         if (val & DROP_SHRINK_ALL)
4279                 i915_gem_shrink_all(dev_priv);
4280         fs_reclaim_release(GFP_KERNEL);
4281
4282         if (val & DROP_FREED) {
4283                 synchronize_rcu();
4284                 i915_gem_drain_freed_objects(dev_priv);
4285         }
4286
4287         return ret;
4288 }
4289
4290 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4291                         i915_drop_caches_get, i915_drop_caches_set,
4292                         "0x%08llx\n");
4293
4294 static int
4295 i915_max_freq_get(void *data, u64 *val)
4296 {
4297         struct drm_i915_private *dev_priv = data;
4298
4299         if (INTEL_GEN(dev_priv) < 6)
4300                 return -ENODEV;
4301
4302         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
4303         return 0;
4304 }
4305
4306 static int
4307 i915_max_freq_set(void *data, u64 val)
4308 {
4309         struct drm_i915_private *dev_priv = data;
4310         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4311         u32 hw_max, hw_min;
4312         int ret;
4313
4314         if (INTEL_GEN(dev_priv) < 6)
4315                 return -ENODEV;
4316
4317         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4318
4319         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4320         if (ret)
4321                 return ret;
4322
4323         /*
4324          * Turbo will still be enabled, but won't go above the set value.
4325          */
4326         val = intel_freq_opcode(dev_priv, val);
4327
4328         hw_max = rps->max_freq;
4329         hw_min = rps->min_freq;
4330
4331         if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
4332                 mutex_unlock(&dev_priv->pcu_lock);
4333                 return -EINVAL;
4334         }
4335
4336         rps->max_freq_softlimit = val;
4337
4338         if (intel_set_rps(dev_priv, val))
4339                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4340
4341         mutex_unlock(&dev_priv->pcu_lock);
4342
4343         return 0;
4344 }
4345
4346 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4347                         i915_max_freq_get, i915_max_freq_set,
4348                         "%llu\n");
4349
4350 static int
4351 i915_min_freq_get(void *data, u64 *val)
4352 {
4353         struct drm_i915_private *dev_priv = data;
4354
4355         if (INTEL_GEN(dev_priv) < 6)
4356                 return -ENODEV;
4357
4358         *val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
4359         return 0;
4360 }
4361
4362 static int
4363 i915_min_freq_set(void *data, u64 val)
4364 {
4365         struct drm_i915_private *dev_priv = data;
4366         struct intel_rps *rps = &dev_priv->gt_pm.rps;
4367         u32 hw_max, hw_min;
4368         int ret;
4369
4370         if (INTEL_GEN(dev_priv) < 6)
4371                 return -ENODEV;
4372
4373         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4374
4375         ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
4376         if (ret)
4377                 return ret;
4378
4379         /*
4380          * Turbo will still be enabled, but won't go below the set value.
4381          */
4382         val = intel_freq_opcode(dev_priv, val);
4383
4384         hw_max = rps->max_freq;
4385         hw_min = rps->min_freq;
4386
4387         if (val < hw_min ||
4388             val > hw_max || val > rps->max_freq_softlimit) {
4389                 mutex_unlock(&dev_priv->pcu_lock);
4390                 return -EINVAL;
4391         }
4392
4393         rps->min_freq_softlimit = val;
4394
4395         if (intel_set_rps(dev_priv, val))
4396                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4397
4398         mutex_unlock(&dev_priv->pcu_lock);
4399
4400         return 0;
4401 }
4402
4403 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4404                         i915_min_freq_get, i915_min_freq_set,
4405                         "%llu\n");
4406
4407 static int
4408 i915_cache_sharing_get(void *data, u64 *val)
4409 {
4410         struct drm_i915_private *dev_priv = data;
4411         u32 snpcr;
4412
4413         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4414                 return -ENODEV;
4415
4416         intel_runtime_pm_get(dev_priv);
4417
4418         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4419
4420         intel_runtime_pm_put(dev_priv);
4421
4422         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4423
4424         return 0;
4425 }
4426
4427 static int
4428 i915_cache_sharing_set(void *data, u64 val)
4429 {
4430         struct drm_i915_private *dev_priv = data;
4431         u32 snpcr;
4432
4433         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4434                 return -ENODEV;
4435
4436         if (val > 3)
4437                 return -EINVAL;
4438
4439         intel_runtime_pm_get(dev_priv);
4440         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4441
4442         /* Update the cache sharing policy here as well */
4443         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4444         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4445         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4446         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4447
4448         intel_runtime_pm_put(dev_priv);
4449         return 0;
4450 }
4451
4452 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4453                         i915_cache_sharing_get, i915_cache_sharing_set,
4454                         "%llu\n");
4455
4456 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4457                                           struct sseu_dev_info *sseu)
4458 {
4459         int ss_max = 2;
4460         int ss;
4461         u32 sig1[ss_max], sig2[ss_max];
4462
4463         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4464         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4465         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4466         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4467
4468         for (ss = 0; ss < ss_max; ss++) {
4469                 unsigned int eu_cnt;
4470
4471                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4472                         /* skip disabled subslice */
4473                         continue;
4474
4475                 sseu->slice_mask = BIT(0);
4476                 sseu->subslice_mask |= BIT(ss);
4477                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4478                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4479                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4480                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4481                 sseu->eu_total += eu_cnt;
4482                 sseu->eu_per_subslice = max_t(unsigned int,
4483                                               sseu->eu_per_subslice, eu_cnt);
4484         }
4485 }
4486
4487 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4488                                     struct sseu_dev_info *sseu)
4489 {
4490         int s_max = 3, ss_max = 4;
4491         int s, ss;
4492         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4493
4494         /* BXT has a single slice and at most 3 subslices. */
4495         if (IS_GEN9_LP(dev_priv)) {
4496                 s_max = 1;
4497                 ss_max = 3;
4498         }
4499
4500         for (s = 0; s < s_max; s++) {
4501                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4502                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4503                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4504         }
4505
4506         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4507                      GEN9_PGCTL_SSA_EU19_ACK |
4508                      GEN9_PGCTL_SSA_EU210_ACK |
4509                      GEN9_PGCTL_SSA_EU311_ACK;
4510         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4511                      GEN9_PGCTL_SSB_EU19_ACK |
4512                      GEN9_PGCTL_SSB_EU210_ACK |
4513                      GEN9_PGCTL_SSB_EU311_ACK;
4514
4515         for (s = 0; s < s_max; s++) {
4516                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4517                         /* skip disabled slice */
4518                         continue;
4519
4520                 sseu->slice_mask |= BIT(s);
4521
4522                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
4523                         sseu->subslice_mask =
4524                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4525
4526                 for (ss = 0; ss < ss_max; ss++) {
4527                         unsigned int eu_cnt;
4528
4529                         if (IS_GEN9_LP(dev_priv)) {
4530                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4531                                         /* skip disabled subslice */
4532                                         continue;
4533
4534                                 sseu->subslice_mask |= BIT(ss);
4535                         }
4536
4537                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4538                                                eu_mask[ss%2]);
4539                         sseu->eu_total += eu_cnt;
4540                         sseu->eu_per_subslice = max_t(unsigned int,
4541                                                       sseu->eu_per_subslice,
4542                                                       eu_cnt);
4543                 }
4544         }
4545 }
4546
4547 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4548                                          struct sseu_dev_info *sseu)
4549 {
4550         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4551         int s;
4552
4553         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4554
4555         if (sseu->slice_mask) {
4556                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4557                 sseu->eu_per_subslice =
4558                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4559                 sseu->eu_total = sseu->eu_per_subslice *
4560                                  sseu_subslice_total(sseu);
4561
4562                 /* subtract fused off EU(s) from enabled slice(s) */
4563                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4564                         u8 subslice_7eu =
4565                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4566
4567                         sseu->eu_total -= hweight8(subslice_7eu);
4568                 }
4569         }
4570 }
4571
4572 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4573                                  const struct sseu_dev_info *sseu)
4574 {
4575         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4576         const char *type = is_available_info ? "Available" : "Enabled";
4577
4578         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4579                    sseu->slice_mask);
4580         seq_printf(m, "  %s Slice Total: %u\n", type,
4581                    hweight8(sseu->slice_mask));
4582         seq_printf(m, "  %s Subslice Total: %u\n", type,
4583                    sseu_subslice_total(sseu));
4584         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4585                    sseu->subslice_mask);
4586         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4587                    hweight8(sseu->subslice_mask));
4588         seq_printf(m, "  %s EU Total: %u\n", type,
4589                    sseu->eu_total);
4590         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4591                    sseu->eu_per_subslice);
4592
4593         if (!is_available_info)
4594                 return;
4595
4596         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4597         if (HAS_POOLED_EU(dev_priv))
4598                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4599
4600         seq_printf(m, "  Has Slice Power Gating: %s\n",
4601                    yesno(sseu->has_slice_pg));
4602         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4603                    yesno(sseu->has_subslice_pg));
4604         seq_printf(m, "  Has EU Power Gating: %s\n",
4605                    yesno(sseu->has_eu_pg));
4606 }
4607
4608 static int i915_sseu_status(struct seq_file *m, void *unused)
4609 {
4610         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4611         struct sseu_dev_info sseu;
4612
4613         if (INTEL_GEN(dev_priv) < 8)
4614                 return -ENODEV;
4615
4616         seq_puts(m, "SSEU Device Info\n");
4617         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4618
4619         seq_puts(m, "SSEU Device Status\n");
4620         memset(&sseu, 0, sizeof(sseu));
4621
4622         intel_runtime_pm_get(dev_priv);
4623
4624         if (IS_CHERRYVIEW(dev_priv)) {
4625                 cherryview_sseu_device_status(dev_priv, &sseu);
4626         } else if (IS_BROADWELL(dev_priv)) {
4627                 broadwell_sseu_device_status(dev_priv, &sseu);
4628         } else if (INTEL_GEN(dev_priv) >= 9) {
4629                 gen9_sseu_device_status(dev_priv, &sseu);
4630         }
4631
4632         intel_runtime_pm_put(dev_priv);
4633
4634         i915_print_sseu_info(m, false, &sseu);
4635
4636         return 0;
4637 }
4638
4639 static int i915_forcewake_open(struct inode *inode, struct file *file)
4640 {
4641         struct drm_i915_private *i915 = inode->i_private;
4642
4643         if (INTEL_GEN(i915) < 6)
4644                 return 0;
4645
4646         intel_runtime_pm_get(i915);
4647         intel_uncore_forcewake_user_get(i915);
4648
4649         return 0;
4650 }
4651
4652 static int i915_forcewake_release(struct inode *inode, struct file *file)
4653 {
4654         struct drm_i915_private *i915 = inode->i_private;
4655
4656         if (INTEL_GEN(i915) < 6)
4657                 return 0;
4658
4659         intel_uncore_forcewake_user_put(i915);
4660         intel_runtime_pm_put(i915);
4661
4662         return 0;
4663 }
4664
4665 static const struct file_operations i915_forcewake_fops = {
4666         .owner = THIS_MODULE,
4667         .open = i915_forcewake_open,
4668         .release = i915_forcewake_release,
4669 };
4670
4671 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4672 {
4673         struct drm_i915_private *dev_priv = m->private;
4674         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4675
4676         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4677         seq_printf(m, "Detected: %s\n",
4678                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4679
4680         return 0;
4681 }
4682
4683 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4684                                         const char __user *ubuf, size_t len,
4685                                         loff_t *offp)
4686 {
4687         struct seq_file *m = file->private_data;
4688         struct drm_i915_private *dev_priv = m->private;
4689         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4690         unsigned int new_threshold;
4691         int i;
4692         char *newline;
4693         char tmp[16];
4694
4695         if (len >= sizeof(tmp))
4696                 return -EINVAL;
4697
4698         if (copy_from_user(tmp, ubuf, len))
4699                 return -EFAULT;
4700
4701         tmp[len] = '\0';
4702
4703         /* Strip newline, if any */
4704         newline = strchr(tmp, '\n');
4705         if (newline)
4706                 *newline = '\0';
4707
4708         if (strcmp(tmp, "reset") == 0)
4709                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4710         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4711                 return -EINVAL;
4712
4713         if (new_threshold > 0)
4714                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4715                               new_threshold);
4716         else
4717                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4718
4719         spin_lock_irq(&dev_priv->irq_lock);
4720         hotplug->hpd_storm_threshold = new_threshold;
4721         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4722         for_each_hpd_pin(i)
4723                 hotplug->stats[i].count = 0;
4724         spin_unlock_irq(&dev_priv->irq_lock);
4725
4726         /* Re-enable hpd immediately if we were in an irq storm */
4727         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4728
4729         return len;
4730 }
4731
4732 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4733 {
4734         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4735 }
4736
4737 static const struct file_operations i915_hpd_storm_ctl_fops = {
4738         .owner = THIS_MODULE,
4739         .open = i915_hpd_storm_ctl_open,
4740         .read = seq_read,
4741         .llseek = seq_lseek,
4742         .release = single_release,
4743         .write = i915_hpd_storm_ctl_write
4744 };
4745
4746 static const struct drm_info_list i915_debugfs_list[] = {
4747         {"i915_capabilities", i915_capabilities, 0},
4748         {"i915_gem_objects", i915_gem_object_info, 0},
4749         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4750         {"i915_gem_stolen", i915_gem_stolen_list_info },
4751         {"i915_gem_request", i915_gem_request_info, 0},
4752         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4753         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4754         {"i915_gem_interrupt", i915_interrupt_info, 0},
4755         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4756         {"i915_guc_info", i915_guc_info, 0},
4757         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4758         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4759         {"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
4760         {"i915_guc_stage_pool", i915_guc_stage_pool, 0},
4761         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4762         {"i915_frequency_info", i915_frequency_info, 0},
4763         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4764         {"i915_reset_info", i915_reset_info, 0},
4765         {"i915_drpc_info", i915_drpc_info, 0},
4766         {"i915_emon_status", i915_emon_status, 0},
4767         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4768         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4769         {"i915_fbc_status", i915_fbc_status, 0},
4770         {"i915_ips_status", i915_ips_status, 0},
4771         {"i915_sr_status", i915_sr_status, 0},
4772         {"i915_opregion", i915_opregion, 0},
4773         {"i915_vbt", i915_vbt, 0},
4774         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4775         {"i915_context_status", i915_context_status, 0},
4776         {"i915_dump_lrc", i915_dump_lrc, 0},
4777         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4778         {"i915_swizzle_info", i915_swizzle_info, 0},
4779         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4780         {"i915_llc", i915_llc, 0},
4781         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4782         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4783         {"i915_energy_uJ", i915_energy_uJ, 0},
4784         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4785         {"i915_power_domain_info", i915_power_domain_info, 0},
4786         {"i915_dmc_info", i915_dmc_info, 0},
4787         {"i915_display_info", i915_display_info, 0},
4788         {"i915_engine_info", i915_engine_info, 0},
4789         {"i915_semaphore_status", i915_semaphore_status, 0},
4790         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4791         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4792         {"i915_wa_registers", i915_wa_registers, 0},
4793         {"i915_ddb_info", i915_ddb_info, 0},
4794         {"i915_sseu_status", i915_sseu_status, 0},
4795         {"i915_drrs_status", i915_drrs_status, 0},
4796         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4797 };
4798 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4799
4800 static const struct i915_debugfs_files {
4801         const char *name;
4802         const struct file_operations *fops;
4803 } i915_debugfs_files[] = {
4804         {"i915_wedged", &i915_wedged_fops},
4805         {"i915_max_freq", &i915_max_freq_fops},
4806         {"i915_min_freq", &i915_min_freq_fops},
4807         {"i915_cache_sharing", &i915_cache_sharing_fops},
4808         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4809         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4810         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4811 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4812         {"i915_error_state", &i915_error_state_fops},
4813         {"i915_gpu_info", &i915_gpu_info_fops},
4814 #endif
4815         {"i915_next_seqno", &i915_next_seqno_fops},
4816         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4817         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4818         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4819         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4820         {"i915_fbc_false_color", &i915_fbc_false_color_fops},
4821         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4822         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4823         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4824         {"i915_guc_log_control", &i915_guc_log_control_fops},
4825         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
4826         {"i915_ipc_status", &i915_ipc_status_fops}
4827 };
4828
4829 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4830 {
4831         struct drm_minor *minor = dev_priv->drm.primary;
4832         struct dentry *ent;
4833         int ret, i;
4834
4835         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4836                                   minor->debugfs_root, to_i915(minor->dev),
4837                                   &i915_forcewake_fops);
4838         if (!ent)
4839                 return -ENOMEM;
4840
4841         ret = intel_pipe_crc_create(minor);
4842         if (ret)
4843                 return ret;
4844
4845         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4846                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4847                                           S_IRUGO | S_IWUSR,
4848                                           minor->debugfs_root,
4849                                           to_i915(minor->dev),
4850                                           i915_debugfs_files[i].fops);
4851                 if (!ent)
4852                         return -ENOMEM;
4853         }
4854
4855         return drm_debugfs_create_files(i915_debugfs_list,
4856                                         I915_DEBUGFS_ENTRIES,
4857                                         minor->debugfs_root, minor);
4858 }
4859
4860 struct dpcd_block {
4861         /* DPCD dump start address. */
4862         unsigned int offset;
4863         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4864         unsigned int end;
4865         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4866         size_t size;
4867         /* Only valid for eDP. */
4868         bool edp;
4869 };
4870
4871 static const struct dpcd_block i915_dpcd_debug[] = {
4872         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4873         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4874         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4875         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4876         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4877         { .offset = DP_SET_POWER },
4878         { .offset = DP_EDP_DPCD_REV },
4879         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4880         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4881         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4882 };
4883
4884 static int i915_dpcd_show(struct seq_file *m, void *data)
4885 {
4886         struct drm_connector *connector = m->private;
4887         struct intel_dp *intel_dp =
4888                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4889         uint8_t buf[16];
4890         ssize_t err;
4891         int i;
4892
4893         if (connector->status != connector_status_connected)
4894                 return -ENODEV;
4895
4896         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4897                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4898                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4899
4900                 if (b->edp &&
4901                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4902                         continue;
4903
4904                 /* low tech for now */
4905                 if (WARN_ON(size > sizeof(buf)))
4906                         continue;
4907
4908                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4909                 if (err <= 0) {
4910                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4911                                   size, b->offset, err);
4912                         continue;
4913                 }
4914
4915                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4916         }
4917
4918         return 0;
4919 }
4920
4921 static int i915_dpcd_open(struct inode *inode, struct file *file)
4922 {
4923         return single_open(file, i915_dpcd_show, inode->i_private);
4924 }
4925
4926 static const struct file_operations i915_dpcd_fops = {
4927         .owner = THIS_MODULE,
4928         .open = i915_dpcd_open,
4929         .read = seq_read,
4930         .llseek = seq_lseek,
4931         .release = single_release,
4932 };
4933
4934 static int i915_panel_show(struct seq_file *m, void *data)
4935 {
4936         struct drm_connector *connector = m->private;
4937         struct intel_dp *intel_dp =
4938                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4939
4940         if (connector->status != connector_status_connected)
4941                 return -ENODEV;
4942
4943         seq_printf(m, "Panel power up delay: %d\n",
4944                    intel_dp->panel_power_up_delay);
4945         seq_printf(m, "Panel power down delay: %d\n",
4946                    intel_dp->panel_power_down_delay);
4947         seq_printf(m, "Backlight on delay: %d\n",
4948                    intel_dp->backlight_on_delay);
4949         seq_printf(m, "Backlight off delay: %d\n",
4950                    intel_dp->backlight_off_delay);
4951
4952         return 0;
4953 }
4954
4955 static int i915_panel_open(struct inode *inode, struct file *file)
4956 {
4957         return single_open(file, i915_panel_show, inode->i_private);
4958 }
4959
4960 static const struct file_operations i915_panel_fops = {
4961         .owner = THIS_MODULE,
4962         .open = i915_panel_open,
4963         .read = seq_read,
4964         .llseek = seq_lseek,
4965         .release = single_release,
4966 };
4967
4968 /**
4969  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4970  * @connector: pointer to a registered drm_connector
4971  *
4972  * Cleanup will be done by drm_connector_unregister() through a call to
4973  * drm_debugfs_connector_remove().
4974  *
4975  * Returns 0 on success, negative error codes on error.
4976  */
4977 int i915_debugfs_connector_add(struct drm_connector *connector)
4978 {
4979         struct dentry *root = connector->debugfs_entry;
4980
4981         /* The connector must have been registered beforehands. */
4982         if (!root)
4983                 return -ENODEV;
4984
4985         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4986             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4987                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
4988                                     connector, &i915_dpcd_fops);
4989
4990         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4991                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
4992                                     connector, &i915_panel_fops);
4993
4994         return 0;
4995 }