2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v)
51 return v ? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor *minor,
61 struct drm_info_node *node;
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
71 node->info_ent = (void *) key;
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
80 static int i915_capabilities(struct seq_file *m, void *data)
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
99 if (obj->user_pin_count > 0)
101 else if (i915_gem_obj_is_pinned(obj))
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
109 switch (obj->tiling_mode) {
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
119 return obj->has_global_gtt_mapping ? "g" : " ";
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
125 struct i915_vma *vma;
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
164 if (obj->pin_mappable)
166 if (obj->fault_mappable)
169 seq_printf(m, " (%s mappable)", s);
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
179 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
186 struct drm_info_node *node = m->private;
187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
189 struct drm_device *dev = node->minor->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
192 struct i915_vma *vma;
193 size_t total_obj_size, total_gtt_size;
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
200 /* FIXME: the user of this interface might want more than just GGTT */
203 seq_puts(m, "Active:\n");
204 head = &vm->active_list;
207 seq_puts(m, "Inactive:\n");
208 head = &vm->inactive_list;
211 mutex_unlock(&dev->struct_mutex);
215 total_obj_size = total_gtt_size = count = 0;
216 list_for_each_entry(vma, head, mm_list) {
218 describe_obj(m, vma->obj);
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
224 mutex_unlock(&dev->struct_mutex);
226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
231 static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
234 struct drm_i915_gem_object *a =
235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
236 struct drm_i915_gem_object *b =
237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
239 return a->stolen->start - b->stolen->start;
242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244 struct drm_info_node *node = m->private;
245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
261 list_add(&obj->obj_exec_link, &stolen);
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
271 list_add(&obj->obj_exec_link, &stolen);
273 total_obj_size += obj->base.size;
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
281 describe_obj(m, obj);
283 list_del_init(&obj->obj_exec_link);
285 mutex_unlock(&dev->struct_mutex);
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
304 struct drm_i915_file_private *file_priv;
306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
311 static int per_file_stats(int id, void *ptr, void *data)
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
315 struct i915_vma *vma;
318 stats->total += obj->base.size;
320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
327 if (!drm_mm_node_allocated(&vma->node))
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
342 stats->inactive += obj->base.size;
347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
350 stats->active += obj->base.size;
352 stats->inactive += obj->base.size;
357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
363 #define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
374 static int i915_gem_object_info(struct seq_file *m, void* data)
376 struct drm_info_node *node = m->private;
377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
381 struct drm_i915_gem_object *obj;
382 struct i915_address_space *vm = &dev_priv->gtt.base;
383 struct drm_file *file;
384 struct i915_vma *vma;
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
395 size = count = mappable_size = mappable_count = 0;
396 count_objects(&dev_priv->mm.bound_list, global_list);
397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
400 size = count = mappable_size = mappable_count = 0;
401 count_vmas(&vm->active_list, mm_list);
402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
405 size = count = mappable_size = mappable_count = 0;
406 count_vmas(&vm->inactive_list, mm_list);
407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
410 size = count = purgeable_size = purgeable_count = 0;
411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
412 size += obj->base.size, ++count;
413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
418 size = count = mappable_size = mappable_count = 0;
419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
420 if (obj->fault_mappable) {
421 size += i915_gem_obj_ggtt_size(obj);
424 if (obj->pin_mappable) {
425 mappable_size += i915_gem_obj_ggtt_size(obj);
428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
440 seq_printf(m, "%zu [%lu] gtt total\n",
441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
447 struct task_struct *task;
449 memset(&stats, 0, sizeof(stats));
450 stats.file_priv = file->driver_priv;
451 spin_lock(&file->table_lock);
452 idr_for_each(&file->object_idr, per_file_stats, &stats);
453 spin_unlock(&file->table_lock);
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
461 task = pid_task(file->pid, PIDTYPE_PID);
462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
463 task ? task->comm : "<unknown>",
474 mutex_unlock(&dev->struct_mutex);
479 static int i915_gem_gtt_info(struct seq_file *m, void *data)
481 struct drm_info_node *node = m->private;
482 struct drm_device *dev = node->minor->dev;
483 uintptr_t list = (uintptr_t) node->info_ent->data;
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
493 total_obj_size = total_gtt_size = count = 0;
494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
499 describe_obj(m, obj);
501 total_obj_size += obj->base.size;
502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
506 mutex_unlock(&dev->struct_mutex);
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
514 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
516 struct drm_info_node *node = m->private;
517 struct drm_device *dev = node->minor->dev;
519 struct intel_crtc *crtc;
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
526 for_each_intel_crtc(dev, crtc) {
527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
529 struct intel_unpin_work *work;
531 spin_lock_irqsave(&dev->event_lock, flags);
532 work = crtc->unpin_work;
534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
544 if (work->enable_stall_check)
545 seq_puts(m, "Stall check enabled, ");
547 seq_puts(m, "Stall check waiting for page flip ioctl, ");
548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
550 if (work->old_fb_obj) {
551 struct drm_i915_gem_object *obj = work->old_fb_obj;
553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj));
556 if (work->pending_flip_obj) {
557 struct drm_i915_gem_object *obj = work->pending_flip_obj;
559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
563 spin_unlock_irqrestore(&dev->event_lock, flags);
566 mutex_unlock(&dev->struct_mutex);
571 static int i915_gem_request_info(struct seq_file *m, void *data)
573 struct drm_info_node *node = m->private;
574 struct drm_device *dev = node->minor->dev;
575 struct drm_i915_private *dev_priv = dev->dev_private;
576 struct intel_engine_cs *ring;
577 struct drm_i915_gem_request *gem_request;
580 ret = mutex_lock_interruptible(&dev->struct_mutex);
585 for_each_ring(ring, dev_priv, i) {
586 if (list_empty(&ring->request_list))
589 seq_printf(m, "%s requests:\n", ring->name);
590 list_for_each_entry(gem_request,
593 seq_printf(m, " %d @ %d\n",
595 (int) (jiffies - gem_request->emitted_jiffies));
599 mutex_unlock(&dev->struct_mutex);
602 seq_puts(m, "No requests\n");
607 static void i915_ring_seqno_info(struct seq_file *m,
608 struct intel_engine_cs *ring)
610 if (ring->get_seqno) {
611 seq_printf(m, "Current sequence (%s): %u\n",
612 ring->name, ring->get_seqno(ring, false));
616 static int i915_gem_seqno_info(struct seq_file *m, void *data)
618 struct drm_info_node *node = m->private;
619 struct drm_device *dev = node->minor->dev;
620 struct drm_i915_private *dev_priv = dev->dev_private;
621 struct intel_engine_cs *ring;
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
627 intel_runtime_pm_get(dev_priv);
629 for_each_ring(ring, dev_priv, i)
630 i915_ring_seqno_info(m, ring);
632 intel_runtime_pm_put(dev_priv);
633 mutex_unlock(&dev->struct_mutex);
639 static int i915_interrupt_info(struct seq_file *m, void *data)
641 struct drm_info_node *node = m->private;
642 struct drm_device *dev = node->minor->dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 struct intel_engine_cs *ring;
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 intel_runtime_pm_get(dev_priv);
652 if (IS_CHERRYVIEW(dev)) {
654 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ));
657 seq_printf(m, "Display IER:\t%08x\n",
659 seq_printf(m, "Display IIR:\t%08x\n",
661 seq_printf(m, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n",
666 seq_printf(m, "Pipe %c stat:\t%08x\n",
668 I915_READ(PIPESTAT(pipe)));
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
677 for (i = 0; i < 4; i++) {
678 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IMR(i)));
680 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
681 i, I915_READ(GEN8_GT_IIR(i)));
682 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
683 i, I915_READ(GEN8_GT_IER(i)));
686 seq_printf(m, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR));
688 seq_printf(m, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR));
690 seq_printf(m, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER));
692 } else if (INTEL_INFO(dev)->gen >= 8) {
693 seq_printf(m, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ));
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
705 for_each_pipe(pipe) {
706 seq_printf(m, "Pipe %c IMR:\t%08x\n",
708 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
709 seq_printf(m, "Pipe %c IIR:\t%08x\n",
711 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
712 seq_printf(m, "Pipe %c IER:\t%08x\n",
714 I915_READ(GEN8_DE_PIPE_IER(pipe)));
717 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IMR));
719 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
720 I915_READ(GEN8_DE_PORT_IIR));
721 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
722 I915_READ(GEN8_DE_PORT_IER));
724 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IMR));
726 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
727 I915_READ(GEN8_DE_MISC_IIR));
728 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
729 I915_READ(GEN8_DE_MISC_IER));
731 seq_printf(m, "PCU interrupt mask:\t%08x\n",
732 I915_READ(GEN8_PCU_IMR));
733 seq_printf(m, "PCU interrupt identity:\t%08x\n",
734 I915_READ(GEN8_PCU_IIR));
735 seq_printf(m, "PCU interrupt enable:\t%08x\n",
736 I915_READ(GEN8_PCU_IER));
737 } else if (IS_VALLEYVIEW(dev)) {
738 seq_printf(m, "Display IER:\t%08x\n",
740 seq_printf(m, "Display IIR:\t%08x\n",
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
747 seq_printf(m, "Pipe %c stat:\t%08x\n",
749 I915_READ(PIPESTAT(pipe)));
751 seq_printf(m, "Master IER:\t%08x\n",
752 I915_READ(VLV_MASTER_IER));
754 seq_printf(m, "Render IER:\t%08x\n",
756 seq_printf(m, "Render IIR:\t%08x\n",
758 seq_printf(m, "Render IMR:\t%08x\n",
761 seq_printf(m, "PM IER:\t\t%08x\n",
762 I915_READ(GEN6_PMIER));
763 seq_printf(m, "PM IIR:\t\t%08x\n",
764 I915_READ(GEN6_PMIIR));
765 seq_printf(m, "PM IMR:\t\t%08x\n",
766 I915_READ(GEN6_PMIMR));
768 seq_printf(m, "Port hotplug:\t%08x\n",
769 I915_READ(PORT_HOTPLUG_EN));
770 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
771 I915_READ(VLV_DPFLIPSTAT));
772 seq_printf(m, "DPINVGTT:\t%08x\n",
773 I915_READ(DPINVGTT));
775 } else if (!HAS_PCH_SPLIT(dev)) {
776 seq_printf(m, "Interrupt enable: %08x\n",
778 seq_printf(m, "Interrupt identity: %08x\n",
780 seq_printf(m, "Interrupt mask: %08x\n",
783 seq_printf(m, "Pipe %c stat: %08x\n",
785 I915_READ(PIPESTAT(pipe)));
787 seq_printf(m, "North Display Interrupt enable: %08x\n",
789 seq_printf(m, "North Display Interrupt identity: %08x\n",
791 seq_printf(m, "North Display Interrupt mask: %08x\n",
793 seq_printf(m, "South Display Interrupt enable: %08x\n",
795 seq_printf(m, "South Display Interrupt identity: %08x\n",
797 seq_printf(m, "South Display Interrupt mask: %08x\n",
799 seq_printf(m, "Graphics Interrupt enable: %08x\n",
801 seq_printf(m, "Graphics Interrupt identity: %08x\n",
803 seq_printf(m, "Graphics Interrupt mask: %08x\n",
806 for_each_ring(ring, dev_priv, i) {
807 if (INTEL_INFO(dev)->gen >= 6) {
809 "Graphics Interrupt mask (%s): %08x\n",
810 ring->name, I915_READ_IMR(ring));
812 i915_ring_seqno_info(m, ring);
814 intel_runtime_pm_put(dev_priv);
815 mutex_unlock(&dev->struct_mutex);
820 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
822 struct drm_info_node *node = m->private;
823 struct drm_device *dev = node->minor->dev;
824 struct drm_i915_private *dev_priv = dev->dev_private;
827 ret = mutex_lock_interruptible(&dev->struct_mutex);
831 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
832 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
834 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
836 seq_printf(m, "Fence %d, pin count = %d, object = ",
837 i, dev_priv->fence_regs[i].pin_count);
839 seq_puts(m, "unused");
841 describe_obj(m, obj);
845 mutex_unlock(&dev->struct_mutex);
849 static int i915_hws_info(struct seq_file *m, void *data)
851 struct drm_info_node *node = m->private;
852 struct drm_device *dev = node->minor->dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
854 struct intel_engine_cs *ring;
858 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
859 hws = ring->status_page.page_addr;
863 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
864 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
866 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
872 i915_error_state_write(struct file *filp,
873 const char __user *ubuf,
877 struct i915_error_state_file_priv *error_priv = filp->private_data;
878 struct drm_device *dev = error_priv->dev;
881 DRM_DEBUG_DRIVER("Resetting error state\n");
883 ret = mutex_lock_interruptible(&dev->struct_mutex);
887 i915_destroy_error_state(dev);
888 mutex_unlock(&dev->struct_mutex);
893 static int i915_error_state_open(struct inode *inode, struct file *file)
895 struct drm_device *dev = inode->i_private;
896 struct i915_error_state_file_priv *error_priv;
898 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
902 error_priv->dev = dev;
904 i915_error_state_get(dev, error_priv);
906 file->private_data = error_priv;
911 static int i915_error_state_release(struct inode *inode, struct file *file)
913 struct i915_error_state_file_priv *error_priv = file->private_data;
915 i915_error_state_put(error_priv);
921 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
922 size_t count, loff_t *pos)
924 struct i915_error_state_file_priv *error_priv = file->private_data;
925 struct drm_i915_error_state_buf error_str;
927 ssize_t ret_count = 0;
930 ret = i915_error_state_buf_init(&error_str, count, *pos);
934 ret = i915_error_state_to_str(&error_str, error_priv);
938 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
945 *pos = error_str.start + ret_count;
947 i915_error_state_buf_release(&error_str);
948 return ret ?: ret_count;
951 static const struct file_operations i915_error_state_fops = {
952 .owner = THIS_MODULE,
953 .open = i915_error_state_open,
954 .read = i915_error_state_read,
955 .write = i915_error_state_write,
956 .llseek = default_llseek,
957 .release = i915_error_state_release,
961 i915_next_seqno_get(void *data, u64 *val)
963 struct drm_device *dev = data;
964 struct drm_i915_private *dev_priv = dev->dev_private;
967 ret = mutex_lock_interruptible(&dev->struct_mutex);
971 *val = dev_priv->next_seqno;
972 mutex_unlock(&dev->struct_mutex);
978 i915_next_seqno_set(void *data, u64 val)
980 struct drm_device *dev = data;
983 ret = mutex_lock_interruptible(&dev->struct_mutex);
987 ret = i915_gem_set_seqno(dev, val);
988 mutex_unlock(&dev->struct_mutex);
993 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
994 i915_next_seqno_get, i915_next_seqno_set,
997 static int i915_rstdby_delays(struct seq_file *m, void *unused)
999 struct drm_info_node *node = m->private;
1000 struct drm_device *dev = node->minor->dev;
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1005 ret = mutex_lock_interruptible(&dev->struct_mutex);
1008 intel_runtime_pm_get(dev_priv);
1010 crstanddelay = I915_READ16(CRSTANDVID);
1012 intel_runtime_pm_put(dev_priv);
1013 mutex_unlock(&dev->struct_mutex);
1015 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1020 static int i915_frequency_info(struct seq_file *m, void *unused)
1022 struct drm_info_node *node = m->private;
1023 struct drm_device *dev = node->minor->dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1027 intel_runtime_pm_get(dev_priv);
1029 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1032 u16 rgvswctl = I915_READ16(MEMSWCTL);
1033 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1035 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1036 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1037 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1039 seq_printf(m, "Current P-state: %d\n",
1040 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1041 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1042 IS_BROADWELL(dev)) {
1043 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1044 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1045 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1046 u32 rpmodectl, rpinclimit, rpdeclimit;
1047 u32 rpstat, cagf, reqf;
1048 u32 rpupei, rpcurup, rpprevup;
1049 u32 rpdownei, rpcurdown, rpprevdown;
1052 /* RPSTAT1 is in the GT power well */
1053 ret = mutex_lock_interruptible(&dev->struct_mutex);
1057 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1059 reqf = I915_READ(GEN6_RPNSWREQ);
1060 reqf &= ~GEN6_TURBO_DISABLE;
1061 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1065 reqf *= GT_FREQUENCY_MULTIPLIER;
1067 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1068 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1069 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1071 rpstat = I915_READ(GEN6_RPSTAT1);
1072 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1073 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1074 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1075 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1076 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1077 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1078 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1079 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1081 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1082 cagf *= GT_FREQUENCY_MULTIPLIER;
1084 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1085 mutex_unlock(&dev->struct_mutex);
1087 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1088 I915_READ(GEN6_PMIER),
1089 I915_READ(GEN6_PMIMR),
1090 I915_READ(GEN6_PMISR),
1091 I915_READ(GEN6_PMIIR),
1092 I915_READ(GEN6_PMINTRMSK));
1093 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1094 seq_printf(m, "Render p-state ratio: %d\n",
1095 (gt_perf_status & 0xff00) >> 8);
1096 seq_printf(m, "Render p-state VID: %d\n",
1097 gt_perf_status & 0xff);
1098 seq_printf(m, "Render p-state limit: %d\n",
1099 rp_state_limits & 0xff);
1100 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1101 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1102 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1103 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1104 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1105 seq_printf(m, "CAGF: %dMHz\n", cagf);
1106 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1107 GEN6_CURICONT_MASK);
1108 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1109 GEN6_CURBSYTAVG_MASK);
1110 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1111 GEN6_CURBSYTAVG_MASK);
1112 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1114 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1117 GEN6_CURBSYTAVG_MASK);
1119 max_freq = (rp_state_cap & 0xff0000) >> 16;
1120 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1121 max_freq * GT_FREQUENCY_MULTIPLIER);
1123 max_freq = (rp_state_cap & 0xff00) >> 8;
1124 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1125 max_freq * GT_FREQUENCY_MULTIPLIER);
1127 max_freq = rp_state_cap & 0xff;
1128 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1129 max_freq * GT_FREQUENCY_MULTIPLIER);
1131 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1132 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1133 } else if (IS_VALLEYVIEW(dev)) {
1136 mutex_lock(&dev_priv->rps.hw_lock);
1137 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1138 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1139 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1141 val = valleyview_rps_max_freq(dev_priv);
1142 seq_printf(m, "max GPU freq: %d MHz\n",
1143 vlv_gpu_freq(dev_priv, val));
1145 val = valleyview_rps_min_freq(dev_priv);
1146 seq_printf(m, "min GPU freq: %d MHz\n",
1147 vlv_gpu_freq(dev_priv, val));
1149 seq_printf(m, "current GPU freq: %d MHz\n",
1150 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1151 mutex_unlock(&dev_priv->rps.hw_lock);
1153 seq_puts(m, "no P-state info available\n");
1157 intel_runtime_pm_put(dev_priv);
1161 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1163 struct drm_info_node *node = m->private;
1164 struct drm_device *dev = node->minor->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1172 intel_runtime_pm_get(dev_priv);
1174 for (i = 0; i < 16; i++) {
1175 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1176 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1177 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1180 intel_runtime_pm_put(dev_priv);
1182 mutex_unlock(&dev->struct_mutex);
1187 static inline int MAP_TO_MV(int map)
1189 return 1250 - (map * 25);
1192 static int i915_inttoext_table(struct seq_file *m, void *unused)
1194 struct drm_info_node *node = m->private;
1195 struct drm_device *dev = node->minor->dev;
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1200 ret = mutex_lock_interruptible(&dev->struct_mutex);
1203 intel_runtime_pm_get(dev_priv);
1205 for (i = 1; i <= 32; i++) {
1206 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1207 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1210 intel_runtime_pm_put(dev_priv);
1211 mutex_unlock(&dev->struct_mutex);
1216 static int ironlake_drpc_info(struct seq_file *m)
1218 struct drm_info_node *node = m->private;
1219 struct drm_device *dev = node->minor->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 u32 rgvmodectl, rstdbyctl;
1225 ret = mutex_lock_interruptible(&dev->struct_mutex);
1228 intel_runtime_pm_get(dev_priv);
1230 rgvmodectl = I915_READ(MEMMODECTL);
1231 rstdbyctl = I915_READ(RSTDBYCTL);
1232 crstandvid = I915_READ16(CRSTANDVID);
1234 intel_runtime_pm_put(dev_priv);
1235 mutex_unlock(&dev->struct_mutex);
1237 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1239 seq_printf(m, "Boost freq: %d\n",
1240 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1241 MEMMODE_BOOST_FREQ_SHIFT);
1242 seq_printf(m, "HW control enabled: %s\n",
1243 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1244 seq_printf(m, "SW control enabled: %s\n",
1245 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1246 seq_printf(m, "Gated voltage change: %s\n",
1247 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1248 seq_printf(m, "Starting frequency: P%d\n",
1249 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1250 seq_printf(m, "Max P-state: P%d\n",
1251 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1252 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1253 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1254 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1255 seq_printf(m, "Render standby enabled: %s\n",
1256 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1257 seq_puts(m, "Current RS state: ");
1258 switch (rstdbyctl & RSX_STATUS_MASK) {
1260 seq_puts(m, "on\n");
1262 case RSX_STATUS_RC1:
1263 seq_puts(m, "RC1\n");
1265 case RSX_STATUS_RC1E:
1266 seq_puts(m, "RC1E\n");
1268 case RSX_STATUS_RS1:
1269 seq_puts(m, "RS1\n");
1271 case RSX_STATUS_RS2:
1272 seq_puts(m, "RS2 (RC6)\n");
1274 case RSX_STATUS_RS3:
1275 seq_puts(m, "RC3 (RC6+)\n");
1278 seq_puts(m, "unknown\n");
1285 static int vlv_drpc_info(struct seq_file *m)
1288 struct drm_info_node *node = m->private;
1289 struct drm_device *dev = node->minor->dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 u32 rpmodectl1, rcctl1;
1292 unsigned fw_rendercount = 0, fw_mediacount = 0;
1294 intel_runtime_pm_get(dev_priv);
1296 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1297 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1299 intel_runtime_pm_put(dev_priv);
1301 seq_printf(m, "Video Turbo Mode: %s\n",
1302 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1303 seq_printf(m, "Turbo enabled: %s\n",
1304 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1305 seq_printf(m, "HW control enabled: %s\n",
1306 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1307 seq_printf(m, "SW control enabled: %s\n",
1308 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1309 GEN6_RP_MEDIA_SW_MODE));
1310 seq_printf(m, "RC6 Enabled: %s\n",
1311 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1312 GEN6_RC_CTL_EI_MODE(1))));
1313 seq_printf(m, "Render Power Well: %s\n",
1314 (I915_READ(VLV_GTLC_PW_STATUS) &
1315 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1316 seq_printf(m, "Media Power Well: %s\n",
1317 (I915_READ(VLV_GTLC_PW_STATUS) &
1318 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1320 seq_printf(m, "Render RC6 residency since boot: %u\n",
1321 I915_READ(VLV_GT_RENDER_RC6));
1322 seq_printf(m, "Media RC6 residency since boot: %u\n",
1323 I915_READ(VLV_GT_MEDIA_RC6));
1325 spin_lock_irq(&dev_priv->uncore.lock);
1326 fw_rendercount = dev_priv->uncore.fw_rendercount;
1327 fw_mediacount = dev_priv->uncore.fw_mediacount;
1328 spin_unlock_irq(&dev_priv->uncore.lock);
1330 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1331 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1338 static int gen6_drpc_info(struct seq_file *m)
1341 struct drm_info_node *node = m->private;
1342 struct drm_device *dev = node->minor->dev;
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1345 unsigned forcewake_count;
1348 ret = mutex_lock_interruptible(&dev->struct_mutex);
1351 intel_runtime_pm_get(dev_priv);
1353 spin_lock_irq(&dev_priv->uncore.lock);
1354 forcewake_count = dev_priv->uncore.forcewake_count;
1355 spin_unlock_irq(&dev_priv->uncore.lock);
1357 if (forcewake_count) {
1358 seq_puts(m, "RC information inaccurate because somebody "
1359 "holds a forcewake reference \n");
1361 /* NB: we cannot use forcewake, else we read the wrong values */
1362 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1364 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1367 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1368 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1370 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1371 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1372 mutex_unlock(&dev->struct_mutex);
1373 mutex_lock(&dev_priv->rps.hw_lock);
1374 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1375 mutex_unlock(&dev_priv->rps.hw_lock);
1377 intel_runtime_pm_put(dev_priv);
1379 seq_printf(m, "Video Turbo Mode: %s\n",
1380 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1381 seq_printf(m, "HW control enabled: %s\n",
1382 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1383 seq_printf(m, "SW control enabled: %s\n",
1384 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1385 GEN6_RP_MEDIA_SW_MODE));
1386 seq_printf(m, "RC1e Enabled: %s\n",
1387 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1388 seq_printf(m, "RC6 Enabled: %s\n",
1389 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1390 seq_printf(m, "Deep RC6 Enabled: %s\n",
1391 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1392 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1393 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1394 seq_puts(m, "Current RC state: ");
1395 switch (gt_core_status & GEN6_RCn_MASK) {
1397 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1398 seq_puts(m, "Core Power Down\n");
1400 seq_puts(m, "on\n");
1403 seq_puts(m, "RC3\n");
1406 seq_puts(m, "RC6\n");
1409 seq_puts(m, "RC7\n");
1412 seq_puts(m, "Unknown\n");
1416 seq_printf(m, "Core Power Down: %s\n",
1417 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1419 /* Not exactly sure what this is */
1420 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1421 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1422 seq_printf(m, "RC6 residency since boot: %u\n",
1423 I915_READ(GEN6_GT_GFX_RC6));
1424 seq_printf(m, "RC6+ residency since boot: %u\n",
1425 I915_READ(GEN6_GT_GFX_RC6p));
1426 seq_printf(m, "RC6++ residency since boot: %u\n",
1427 I915_READ(GEN6_GT_GFX_RC6pp));
1429 seq_printf(m, "RC6 voltage: %dmV\n",
1430 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1431 seq_printf(m, "RC6+ voltage: %dmV\n",
1432 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1433 seq_printf(m, "RC6++ voltage: %dmV\n",
1434 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1438 static int i915_drpc_info(struct seq_file *m, void *unused)
1440 struct drm_info_node *node = m->private;
1441 struct drm_device *dev = node->minor->dev;
1443 if (IS_VALLEYVIEW(dev))
1444 return vlv_drpc_info(m);
1445 else if (IS_GEN6(dev) || IS_GEN7(dev))
1446 return gen6_drpc_info(m);
1448 return ironlake_drpc_info(m);
1451 static int i915_fbc_status(struct seq_file *m, void *unused)
1453 struct drm_info_node *node = m->private;
1454 struct drm_device *dev = node->minor->dev;
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1457 if (!HAS_FBC(dev)) {
1458 seq_puts(m, "FBC unsupported on this chipset\n");
1462 intel_runtime_pm_get(dev_priv);
1464 if (intel_fbc_enabled(dev)) {
1465 seq_puts(m, "FBC enabled\n");
1467 seq_puts(m, "FBC disabled: ");
1468 switch (dev_priv->fbc.no_fbc_reason) {
1470 seq_puts(m, "FBC actived, but currently disabled in hardware");
1472 case FBC_UNSUPPORTED:
1473 seq_puts(m, "unsupported by this chipset");
1476 seq_puts(m, "no outputs");
1478 case FBC_STOLEN_TOO_SMALL:
1479 seq_puts(m, "not enough stolen memory");
1481 case FBC_UNSUPPORTED_MODE:
1482 seq_puts(m, "mode not supported");
1484 case FBC_MODE_TOO_LARGE:
1485 seq_puts(m, "mode too large");
1488 seq_puts(m, "FBC unsupported on plane");
1491 seq_puts(m, "scanout buffer not tiled");
1493 case FBC_MULTIPLE_PIPES:
1494 seq_puts(m, "multiple pipes are enabled");
1496 case FBC_MODULE_PARAM:
1497 seq_puts(m, "disabled per module param (default off)");
1499 case FBC_CHIP_DEFAULT:
1500 seq_puts(m, "disabled per chip default");
1503 seq_puts(m, "unknown reason");
1508 intel_runtime_pm_put(dev_priv);
1513 static int i915_ips_status(struct seq_file *m, void *unused)
1515 struct drm_info_node *node = m->private;
1516 struct drm_device *dev = node->minor->dev;
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1519 if (!HAS_IPS(dev)) {
1520 seq_puts(m, "not supported\n");
1524 intel_runtime_pm_get(dev_priv);
1526 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1527 seq_puts(m, "enabled\n");
1529 seq_puts(m, "disabled\n");
1531 intel_runtime_pm_put(dev_priv);
1536 static int i915_sr_status(struct seq_file *m, void *unused)
1538 struct drm_info_node *node = m->private;
1539 struct drm_device *dev = node->minor->dev;
1540 struct drm_i915_private *dev_priv = dev->dev_private;
1541 bool sr_enabled = false;
1543 intel_runtime_pm_get(dev_priv);
1545 if (HAS_PCH_SPLIT(dev))
1546 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1547 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1548 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1549 else if (IS_I915GM(dev))
1550 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1551 else if (IS_PINEVIEW(dev))
1552 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1554 intel_runtime_pm_put(dev_priv);
1556 seq_printf(m, "self-refresh: %s\n",
1557 sr_enabled ? "enabled" : "disabled");
1562 static int i915_emon_status(struct seq_file *m, void *unused)
1564 struct drm_info_node *node = m->private;
1565 struct drm_device *dev = node->minor->dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 unsigned long temp, chipset, gfx;
1573 ret = mutex_lock_interruptible(&dev->struct_mutex);
1577 temp = i915_mch_val(dev_priv);
1578 chipset = i915_chipset_val(dev_priv);
1579 gfx = i915_gfx_val(dev_priv);
1580 mutex_unlock(&dev->struct_mutex);
1582 seq_printf(m, "GMCH temp: %ld\n", temp);
1583 seq_printf(m, "Chipset power: %ld\n", chipset);
1584 seq_printf(m, "GFX power: %ld\n", gfx);
1585 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1590 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1592 struct drm_info_node *node = m->private;
1593 struct drm_device *dev = node->minor->dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1596 int gpu_freq, ia_freq;
1598 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1599 seq_puts(m, "unsupported on this chipset\n");
1603 intel_runtime_pm_get(dev_priv);
1605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1607 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1611 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1613 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1614 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1617 sandybridge_pcode_read(dev_priv,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1620 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1622 ((ia_freq >> 0) & 0xff) * 100,
1623 ((ia_freq >> 8) & 0xff) * 100);
1626 mutex_unlock(&dev_priv->rps.hw_lock);
1629 intel_runtime_pm_put(dev_priv);
1633 static int i915_gfxec(struct seq_file *m, void *unused)
1635 struct drm_info_node *node = m->private;
1636 struct drm_device *dev = node->minor->dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1640 ret = mutex_lock_interruptible(&dev->struct_mutex);
1643 intel_runtime_pm_get(dev_priv);
1645 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1646 intel_runtime_pm_put(dev_priv);
1648 mutex_unlock(&dev->struct_mutex);
1653 static int i915_opregion(struct seq_file *m, void *unused)
1655 struct drm_info_node *node = m->private;
1656 struct drm_device *dev = node->minor->dev;
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 struct intel_opregion *opregion = &dev_priv->opregion;
1659 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1665 ret = mutex_lock_interruptible(&dev->struct_mutex);
1669 if (opregion->header) {
1670 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1671 seq_write(m, data, OPREGION_SIZE);
1674 mutex_unlock(&dev->struct_mutex);
1681 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1683 struct drm_info_node *node = m->private;
1684 struct drm_device *dev = node->minor->dev;
1685 struct intel_fbdev *ifbdev = NULL;
1686 struct intel_framebuffer *fb;
1688 #ifdef CONFIG_DRM_I915_FBDEV
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1691 ifbdev = dev_priv->fbdev;
1692 fb = to_intel_framebuffer(ifbdev->helper.fb);
1694 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1698 fb->base.bits_per_pixel,
1699 atomic_read(&fb->base.refcount.refcount));
1700 describe_obj(m, fb->obj);
1704 mutex_lock(&dev->mode_config.fb_lock);
1705 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1706 if (ifbdev && &fb->base == ifbdev->helper.fb)
1709 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1713 fb->base.bits_per_pixel,
1714 atomic_read(&fb->base.refcount.refcount));
1715 describe_obj(m, fb->obj);
1718 mutex_unlock(&dev->mode_config.fb_lock);
1723 static int i915_context_status(struct seq_file *m, void *unused)
1725 struct drm_info_node *node = m->private;
1726 struct drm_device *dev = node->minor->dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 struct intel_engine_cs *ring;
1729 struct intel_context *ctx;
1732 ret = mutex_lock_interruptible(&dev->struct_mutex);
1736 if (dev_priv->ips.pwrctx) {
1737 seq_puts(m, "power context ");
1738 describe_obj(m, dev_priv->ips.pwrctx);
1742 if (dev_priv->ips.renderctx) {
1743 seq_puts(m, "render context ");
1744 describe_obj(m, dev_priv->ips.renderctx);
1748 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1749 if (ctx->obj == NULL)
1752 seq_puts(m, "HW context ");
1753 describe_ctx(m, ctx);
1754 for_each_ring(ring, dev_priv, i)
1755 if (ring->default_context == ctx)
1756 seq_printf(m, "(default context %s) ", ring->name);
1758 describe_obj(m, ctx->obj);
1762 mutex_unlock(&dev->struct_mutex);
1767 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1769 struct drm_info_node *node = m->private;
1770 struct drm_device *dev = node->minor->dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1774 spin_lock_irq(&dev_priv->uncore.lock);
1775 if (IS_VALLEYVIEW(dev)) {
1776 fw_rendercount = dev_priv->uncore.fw_rendercount;
1777 fw_mediacount = dev_priv->uncore.fw_mediacount;
1779 forcewake_count = dev_priv->uncore.forcewake_count;
1780 spin_unlock_irq(&dev_priv->uncore.lock);
1782 if (IS_VALLEYVIEW(dev)) {
1783 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1784 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1786 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1791 static const char *swizzle_string(unsigned swizzle)
1794 case I915_BIT_6_SWIZZLE_NONE:
1796 case I915_BIT_6_SWIZZLE_9:
1798 case I915_BIT_6_SWIZZLE_9_10:
1799 return "bit9/bit10";
1800 case I915_BIT_6_SWIZZLE_9_11:
1801 return "bit9/bit11";
1802 case I915_BIT_6_SWIZZLE_9_10_11:
1803 return "bit9/bit10/bit11";
1804 case I915_BIT_6_SWIZZLE_9_17:
1805 return "bit9/bit17";
1806 case I915_BIT_6_SWIZZLE_9_10_17:
1807 return "bit9/bit10/bit17";
1808 case I915_BIT_6_SWIZZLE_UNKNOWN:
1815 static int i915_swizzle_info(struct seq_file *m, void *data)
1817 struct drm_info_node *node = m->private;
1818 struct drm_device *dev = node->minor->dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1822 ret = mutex_lock_interruptible(&dev->struct_mutex);
1825 intel_runtime_pm_get(dev_priv);
1827 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1828 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1829 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1830 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1832 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1833 seq_printf(m, "DDC = 0x%08x\n",
1835 seq_printf(m, "C0DRB3 = 0x%04x\n",
1836 I915_READ16(C0DRB3));
1837 seq_printf(m, "C1DRB3 = 0x%04x\n",
1838 I915_READ16(C1DRB3));
1839 } else if (INTEL_INFO(dev)->gen >= 6) {
1840 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1841 I915_READ(MAD_DIMM_C0));
1842 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1843 I915_READ(MAD_DIMM_C1));
1844 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1845 I915_READ(MAD_DIMM_C2));
1846 seq_printf(m, "TILECTL = 0x%08x\n",
1847 I915_READ(TILECTL));
1849 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1850 I915_READ(GAMTARBMODE));
1852 seq_printf(m, "ARB_MODE = 0x%08x\n",
1853 I915_READ(ARB_MODE));
1854 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1855 I915_READ(DISP_ARB_CTL));
1857 intel_runtime_pm_put(dev_priv);
1858 mutex_unlock(&dev->struct_mutex);
1863 static int per_file_ctx(int id, void *ptr, void *data)
1865 struct intel_context *ctx = ptr;
1866 struct seq_file *m = data;
1867 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1869 if (i915_gem_context_is_default(ctx))
1870 seq_puts(m, " default context:\n");
1872 seq_printf(m, " context %d:\n", ctx->id);
1873 ppgtt->debug_dump(ppgtt, m);
1878 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 struct intel_engine_cs *ring;
1882 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1888 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1889 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1890 for_each_ring(ring, dev_priv, unused) {
1891 seq_printf(m, "%s\n", ring->name);
1892 for (i = 0; i < 4; i++) {
1893 u32 offset = 0x270 + i * 8;
1894 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1896 pdp |= I915_READ(ring->mmio_base + offset);
1897 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1902 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 struct intel_engine_cs *ring;
1906 struct drm_file *file;
1909 if (INTEL_INFO(dev)->gen == 6)
1910 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1912 for_each_ring(ring, dev_priv, i) {
1913 seq_printf(m, "%s\n", ring->name);
1914 if (INTEL_INFO(dev)->gen == 7)
1915 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1916 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1917 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1918 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1920 if (dev_priv->mm.aliasing_ppgtt) {
1921 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1923 seq_puts(m, "aliasing PPGTT:\n");
1924 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1926 ppgtt->debug_dump(ppgtt, m);
1930 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1931 struct drm_i915_file_private *file_priv = file->driver_priv;
1933 seq_printf(m, "proc: %s\n",
1934 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1935 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1937 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1940 static int i915_ppgtt_info(struct seq_file *m, void *data)
1942 struct drm_info_node *node = m->private;
1943 struct drm_device *dev = node->minor->dev;
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1946 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1949 intel_runtime_pm_get(dev_priv);
1951 if (INTEL_INFO(dev)->gen >= 8)
1952 gen8_ppgtt_info(m, dev);
1953 else if (INTEL_INFO(dev)->gen >= 6)
1954 gen6_ppgtt_info(m, dev);
1956 intel_runtime_pm_put(dev_priv);
1957 mutex_unlock(&dev->struct_mutex);
1962 static int i915_llc(struct seq_file *m, void *data)
1964 struct drm_info_node *node = m->private;
1965 struct drm_device *dev = node->minor->dev;
1966 struct drm_i915_private *dev_priv = dev->dev_private;
1968 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1969 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1970 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1975 static int i915_edp_psr_status(struct seq_file *m, void *data)
1977 struct drm_info_node *node = m->private;
1978 struct drm_device *dev = node->minor->dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1981 bool enabled = false;
1983 intel_runtime_pm_get(dev_priv);
1985 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1986 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1987 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1988 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
1990 enabled = HAS_PSR(dev) &&
1991 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1992 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
1995 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1996 EDP_PSR_PERF_CNT_MASK;
1997 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1999 intel_runtime_pm_put(dev_priv);
2003 static int i915_sink_crc(struct seq_file *m, void *data)
2005 struct drm_info_node *node = m->private;
2006 struct drm_device *dev = node->minor->dev;
2007 struct intel_encoder *encoder;
2008 struct intel_connector *connector;
2009 struct intel_dp *intel_dp = NULL;
2013 drm_modeset_lock_all(dev);
2014 list_for_each_entry(connector, &dev->mode_config.connector_list,
2017 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2020 if (!connector->base.encoder)
2023 encoder = to_intel_encoder(connector->base.encoder);
2024 if (encoder->type != INTEL_OUTPUT_EDP)
2027 intel_dp = enc_to_intel_dp(&encoder->base);
2029 ret = intel_dp_sink_crc(intel_dp, crc);
2033 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2034 crc[0], crc[1], crc[2],
2035 crc[3], crc[4], crc[5]);
2040 drm_modeset_unlock_all(dev);
2044 static int i915_energy_uJ(struct seq_file *m, void *data)
2046 struct drm_info_node *node = m->private;
2047 struct drm_device *dev = node->minor->dev;
2048 struct drm_i915_private *dev_priv = dev->dev_private;
2052 if (INTEL_INFO(dev)->gen < 6)
2055 intel_runtime_pm_get(dev_priv);
2057 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2058 power = (power & 0x1f00) >> 8;
2059 units = 1000000 / (1 << power); /* convert to uJ */
2060 power = I915_READ(MCH_SECP_NRG_STTS);
2063 intel_runtime_pm_put(dev_priv);
2065 seq_printf(m, "%llu", (long long unsigned)power);
2070 static int i915_pc8_status(struct seq_file *m, void *unused)
2072 struct drm_info_node *node = m->private;
2073 struct drm_device *dev = node->minor->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2076 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2077 seq_puts(m, "not supported\n");
2081 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2082 seq_printf(m, "IRQs disabled: %s\n",
2083 yesno(dev_priv->pm.irqs_disabled));
2088 static const char *power_domain_str(enum intel_display_power_domain domain)
2091 case POWER_DOMAIN_PIPE_A:
2093 case POWER_DOMAIN_PIPE_B:
2095 case POWER_DOMAIN_PIPE_C:
2097 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2098 return "PIPE_A_PANEL_FITTER";
2099 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2100 return "PIPE_B_PANEL_FITTER";
2101 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2102 return "PIPE_C_PANEL_FITTER";
2103 case POWER_DOMAIN_TRANSCODER_A:
2104 return "TRANSCODER_A";
2105 case POWER_DOMAIN_TRANSCODER_B:
2106 return "TRANSCODER_B";
2107 case POWER_DOMAIN_TRANSCODER_C:
2108 return "TRANSCODER_C";
2109 case POWER_DOMAIN_TRANSCODER_EDP:
2110 return "TRANSCODER_EDP";
2111 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2112 return "PORT_DDI_A_2_LANES";
2113 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2114 return "PORT_DDI_A_4_LANES";
2115 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2116 return "PORT_DDI_B_2_LANES";
2117 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2118 return "PORT_DDI_B_4_LANES";
2119 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2120 return "PORT_DDI_C_2_LANES";
2121 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2122 return "PORT_DDI_C_4_LANES";
2123 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2124 return "PORT_DDI_D_2_LANES";
2125 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2126 return "PORT_DDI_D_4_LANES";
2127 case POWER_DOMAIN_PORT_DSI:
2129 case POWER_DOMAIN_PORT_CRT:
2131 case POWER_DOMAIN_PORT_OTHER:
2132 return "PORT_OTHER";
2133 case POWER_DOMAIN_VGA:
2135 case POWER_DOMAIN_AUDIO:
2137 case POWER_DOMAIN_INIT:
2145 static int i915_power_domain_info(struct seq_file *m, void *unused)
2147 struct drm_info_node *node = m->private;
2148 struct drm_device *dev = node->minor->dev;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2153 mutex_lock(&power_domains->lock);
2155 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2156 for (i = 0; i < power_domains->power_well_count; i++) {
2157 struct i915_power_well *power_well;
2158 enum intel_display_power_domain power_domain;
2160 power_well = &power_domains->power_wells[i];
2161 seq_printf(m, "%-25s %d\n", power_well->name,
2164 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2166 if (!(BIT(power_domain) & power_well->domains))
2169 seq_printf(m, " %-23s %d\n",
2170 power_domain_str(power_domain),
2171 power_domains->domain_use_count[power_domain]);
2175 mutex_unlock(&power_domains->lock);
2180 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2181 struct drm_display_mode *mode)
2185 for (i = 0; i < tabs; i++)
2188 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2189 mode->base.id, mode->name,
2190 mode->vrefresh, mode->clock,
2191 mode->hdisplay, mode->hsync_start,
2192 mode->hsync_end, mode->htotal,
2193 mode->vdisplay, mode->vsync_start,
2194 mode->vsync_end, mode->vtotal,
2195 mode->type, mode->flags);
2198 static void intel_encoder_info(struct seq_file *m,
2199 struct intel_crtc *intel_crtc,
2200 struct intel_encoder *intel_encoder)
2202 struct drm_info_node *node = m->private;
2203 struct drm_device *dev = node->minor->dev;
2204 struct drm_crtc *crtc = &intel_crtc->base;
2205 struct intel_connector *intel_connector;
2206 struct drm_encoder *encoder;
2208 encoder = &intel_encoder->base;
2209 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2210 encoder->base.id, encoder->name);
2211 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2212 struct drm_connector *connector = &intel_connector->base;
2213 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2216 drm_get_connector_status_name(connector->status));
2217 if (connector->status == connector_status_connected) {
2218 struct drm_display_mode *mode = &crtc->mode;
2219 seq_printf(m, ", mode:\n");
2220 intel_seq_print_mode(m, 2, mode);
2227 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2229 struct drm_info_node *node = m->private;
2230 struct drm_device *dev = node->minor->dev;
2231 struct drm_crtc *crtc = &intel_crtc->base;
2232 struct intel_encoder *intel_encoder;
2234 if (crtc->primary->fb)
2235 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2236 crtc->primary->fb->base.id, crtc->x, crtc->y,
2237 crtc->primary->fb->width, crtc->primary->fb->height);
2239 seq_puts(m, "\tprimary plane disabled\n");
2240 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2241 intel_encoder_info(m, intel_crtc, intel_encoder);
2244 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2246 struct drm_display_mode *mode = panel->fixed_mode;
2248 seq_printf(m, "\tfixed mode:\n");
2249 intel_seq_print_mode(m, 2, mode);
2252 static void intel_dp_info(struct seq_file *m,
2253 struct intel_connector *intel_connector)
2255 struct intel_encoder *intel_encoder = intel_connector->encoder;
2256 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2258 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2259 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2261 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2262 intel_panel_info(m, &intel_connector->panel);
2265 static void intel_hdmi_info(struct seq_file *m,
2266 struct intel_connector *intel_connector)
2268 struct intel_encoder *intel_encoder = intel_connector->encoder;
2269 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2271 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2275 static void intel_lvds_info(struct seq_file *m,
2276 struct intel_connector *intel_connector)
2278 intel_panel_info(m, &intel_connector->panel);
2281 static void intel_connector_info(struct seq_file *m,
2282 struct drm_connector *connector)
2284 struct intel_connector *intel_connector = to_intel_connector(connector);
2285 struct intel_encoder *intel_encoder = intel_connector->encoder;
2286 struct drm_display_mode *mode;
2288 seq_printf(m, "connector %d: type %s, status: %s\n",
2289 connector->base.id, connector->name,
2290 drm_get_connector_status_name(connector->status));
2291 if (connector->status == connector_status_connected) {
2292 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2293 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2294 connector->display_info.width_mm,
2295 connector->display_info.height_mm);
2296 seq_printf(m, "\tsubpixel order: %s\n",
2297 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2298 seq_printf(m, "\tCEA rev: %d\n",
2299 connector->display_info.cea_rev);
2301 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2302 intel_encoder->type == INTEL_OUTPUT_EDP)
2303 intel_dp_info(m, intel_connector);
2304 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2305 intel_hdmi_info(m, intel_connector);
2306 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2307 intel_lvds_info(m, intel_connector);
2309 seq_printf(m, "\tmodes:\n");
2310 list_for_each_entry(mode, &connector->modes, head)
2311 intel_seq_print_mode(m, 2, mode);
2314 static bool cursor_active(struct drm_device *dev, int pipe)
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2319 if (IS_845G(dev) || IS_I865G(dev))
2320 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2322 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2327 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2332 pos = I915_READ(CURPOS(pipe));
2334 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2335 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2338 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2339 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2342 return cursor_active(dev, pipe);
2345 static int i915_display_info(struct seq_file *m, void *unused)
2347 struct drm_info_node *node = m->private;
2348 struct drm_device *dev = node->minor->dev;
2349 struct drm_i915_private *dev_priv = dev->dev_private;
2350 struct intel_crtc *crtc;
2351 struct drm_connector *connector;
2353 intel_runtime_pm_get(dev_priv);
2354 drm_modeset_lock_all(dev);
2355 seq_printf(m, "CRTC info\n");
2356 seq_printf(m, "---------\n");
2357 for_each_intel_crtc(dev, crtc) {
2361 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2362 crtc->base.base.id, pipe_name(crtc->pipe),
2363 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2365 intel_crtc_info(m, crtc);
2367 active = cursor_position(dev, crtc->pipe, &x, &y);
2368 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2369 yesno(crtc->cursor_base),
2370 x, y, crtc->cursor_width, crtc->cursor_height,
2371 crtc->cursor_addr, yesno(active));
2374 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2375 yesno(!crtc->cpu_fifo_underrun_disabled),
2376 yesno(!crtc->pch_fifo_underrun_disabled));
2379 seq_printf(m, "\n");
2380 seq_printf(m, "Connector info\n");
2381 seq_printf(m, "--------------\n");
2382 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2383 intel_connector_info(m, connector);
2385 drm_modeset_unlock_all(dev);
2386 intel_runtime_pm_put(dev_priv);
2391 struct pipe_crc_info {
2393 struct drm_device *dev;
2397 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2399 struct pipe_crc_info *info = inode->i_private;
2400 struct drm_i915_private *dev_priv = info->dev->dev_private;
2401 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2403 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2406 spin_lock_irq(&pipe_crc->lock);
2408 if (pipe_crc->opened) {
2409 spin_unlock_irq(&pipe_crc->lock);
2410 return -EBUSY; /* already open */
2413 pipe_crc->opened = true;
2414 filep->private_data = inode->i_private;
2416 spin_unlock_irq(&pipe_crc->lock);
2421 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2423 struct pipe_crc_info *info = inode->i_private;
2424 struct drm_i915_private *dev_priv = info->dev->dev_private;
2425 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2427 spin_lock_irq(&pipe_crc->lock);
2428 pipe_crc->opened = false;
2429 spin_unlock_irq(&pipe_crc->lock);
2434 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2435 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2436 /* account for \'0' */
2437 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2439 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2441 assert_spin_locked(&pipe_crc->lock);
2442 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2443 INTEL_PIPE_CRC_ENTRIES_NR);
2447 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2450 struct pipe_crc_info *info = filep->private_data;
2451 struct drm_device *dev = info->dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2454 char buf[PIPE_CRC_BUFFER_LEN];
2455 int head, tail, n_entries, n;
2459 * Don't allow user space to provide buffers not big enough to hold
2462 if (count < PIPE_CRC_LINE_LEN)
2465 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2468 /* nothing to read */
2469 spin_lock_irq(&pipe_crc->lock);
2470 while (pipe_crc_data_count(pipe_crc) == 0) {
2473 if (filep->f_flags & O_NONBLOCK) {
2474 spin_unlock_irq(&pipe_crc->lock);
2478 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2479 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2481 spin_unlock_irq(&pipe_crc->lock);
2486 /* We now have one or more entries to read */
2487 head = pipe_crc->head;
2488 tail = pipe_crc->tail;
2489 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2490 count / PIPE_CRC_LINE_LEN);
2491 spin_unlock_irq(&pipe_crc->lock);
2496 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2499 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2500 "%8u %8x %8x %8x %8x %8x\n",
2501 entry->frame, entry->crc[0],
2502 entry->crc[1], entry->crc[2],
2503 entry->crc[3], entry->crc[4]);
2505 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2506 buf, PIPE_CRC_LINE_LEN);
2507 if (ret == PIPE_CRC_LINE_LEN)
2510 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2511 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2513 } while (--n_entries);
2515 spin_lock_irq(&pipe_crc->lock);
2516 pipe_crc->tail = tail;
2517 spin_unlock_irq(&pipe_crc->lock);
2522 static const struct file_operations i915_pipe_crc_fops = {
2523 .owner = THIS_MODULE,
2524 .open = i915_pipe_crc_open,
2525 .read = i915_pipe_crc_read,
2526 .release = i915_pipe_crc_release,
2529 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2531 .name = "i915_pipe_A_crc",
2535 .name = "i915_pipe_B_crc",
2539 .name = "i915_pipe_C_crc",
2544 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2547 struct drm_device *dev = minor->dev;
2549 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2552 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2553 &i915_pipe_crc_fops);
2557 return drm_add_fake_info_node(minor, ent, info);
2560 static const char * const pipe_crc_sources[] = {
2573 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2575 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2576 return pipe_crc_sources[source];
2579 static int display_crc_ctl_show(struct seq_file *m, void *data)
2581 struct drm_device *dev = m->private;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2585 for (i = 0; i < I915_MAX_PIPES; i++)
2586 seq_printf(m, "%c %s\n", pipe_name(i),
2587 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2592 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2594 struct drm_device *dev = inode->i_private;
2596 return single_open(file, display_crc_ctl_show, dev);
2599 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2602 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2603 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2606 case INTEL_PIPE_CRC_SOURCE_PIPE:
2607 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2609 case INTEL_PIPE_CRC_SOURCE_NONE:
2619 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2620 enum intel_pipe_crc_source *source)
2622 struct intel_encoder *encoder;
2623 struct intel_crtc *crtc;
2624 struct intel_digital_port *dig_port;
2627 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2629 drm_modeset_lock_all(dev);
2630 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2632 if (!encoder->base.crtc)
2635 crtc = to_intel_crtc(encoder->base.crtc);
2637 if (crtc->pipe != pipe)
2640 switch (encoder->type) {
2641 case INTEL_OUTPUT_TVOUT:
2642 *source = INTEL_PIPE_CRC_SOURCE_TV;
2644 case INTEL_OUTPUT_DISPLAYPORT:
2645 case INTEL_OUTPUT_EDP:
2646 dig_port = enc_to_dig_port(&encoder->base);
2647 switch (dig_port->port) {
2649 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2652 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2655 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2658 WARN(1, "nonexisting DP port %c\n",
2659 port_name(dig_port->port));
2665 drm_modeset_unlock_all(dev);
2670 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2672 enum intel_pipe_crc_source *source,
2675 struct drm_i915_private *dev_priv = dev->dev_private;
2676 bool need_stable_symbols = false;
2678 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2679 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2685 case INTEL_PIPE_CRC_SOURCE_PIPE:
2686 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2688 case INTEL_PIPE_CRC_SOURCE_DP_B:
2689 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2690 need_stable_symbols = true;
2692 case INTEL_PIPE_CRC_SOURCE_DP_C:
2693 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2694 need_stable_symbols = true;
2696 case INTEL_PIPE_CRC_SOURCE_NONE:
2704 * When the pipe CRC tap point is after the transcoders we need
2705 * to tweak symbol-level features to produce a deterministic series of
2706 * symbols for a given frame. We need to reset those features only once
2707 * a frame (instead of every nth symbol):
2708 * - DC-balance: used to ensure a better clock recovery from the data
2710 * - DisplayPort scrambling: used for EMI reduction
2712 if (need_stable_symbols) {
2713 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2715 tmp |= DC_BALANCE_RESET_VLV;
2717 tmp |= PIPE_A_SCRAMBLE_RESET;
2719 tmp |= PIPE_B_SCRAMBLE_RESET;
2721 I915_WRITE(PORT_DFT2_G4X, tmp);
2727 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2729 enum intel_pipe_crc_source *source,
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 bool need_stable_symbols = false;
2735 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2736 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2742 case INTEL_PIPE_CRC_SOURCE_PIPE:
2743 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2745 case INTEL_PIPE_CRC_SOURCE_TV:
2746 if (!SUPPORTS_TV(dev))
2748 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2750 case INTEL_PIPE_CRC_SOURCE_DP_B:
2753 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2754 need_stable_symbols = true;
2756 case INTEL_PIPE_CRC_SOURCE_DP_C:
2759 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2760 need_stable_symbols = true;
2762 case INTEL_PIPE_CRC_SOURCE_DP_D:
2765 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2766 need_stable_symbols = true;
2768 case INTEL_PIPE_CRC_SOURCE_NONE:
2776 * When the pipe CRC tap point is after the transcoders we need
2777 * to tweak symbol-level features to produce a deterministic series of
2778 * symbols for a given frame. We need to reset those features only once
2779 * a frame (instead of every nth symbol):
2780 * - DC-balance: used to ensure a better clock recovery from the data
2782 * - DisplayPort scrambling: used for EMI reduction
2784 if (need_stable_symbols) {
2785 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2787 WARN_ON(!IS_G4X(dev));
2789 I915_WRITE(PORT_DFT_I9XX,
2790 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2793 tmp |= PIPE_A_SCRAMBLE_RESET;
2795 tmp |= PIPE_B_SCRAMBLE_RESET;
2797 I915_WRITE(PORT_DFT2_G4X, tmp);
2803 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2810 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2812 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2813 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2814 tmp &= ~DC_BALANCE_RESET_VLV;
2815 I915_WRITE(PORT_DFT2_G4X, tmp);
2819 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2826 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2828 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2829 I915_WRITE(PORT_DFT2_G4X, tmp);
2831 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2832 I915_WRITE(PORT_DFT_I9XX,
2833 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2837 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2840 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2841 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2844 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2845 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2847 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2848 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2850 case INTEL_PIPE_CRC_SOURCE_PIPE:
2851 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2853 case INTEL_PIPE_CRC_SOURCE_NONE:
2863 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2866 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2867 *source = INTEL_PIPE_CRC_SOURCE_PF;
2870 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2871 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2873 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2874 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2876 case INTEL_PIPE_CRC_SOURCE_PF:
2877 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2879 case INTEL_PIPE_CRC_SOURCE_NONE:
2889 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2890 enum intel_pipe_crc_source source)
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2894 u32 val = 0; /* shut up gcc */
2897 if (pipe_crc->source == source)
2900 /* forbid changing the source without going back to 'none' */
2901 if (pipe_crc->source && source)
2905 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2906 else if (INTEL_INFO(dev)->gen < 5)
2907 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2908 else if (IS_VALLEYVIEW(dev))
2909 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2910 else if (IS_GEN5(dev) || IS_GEN6(dev))
2911 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2913 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2918 /* none -> real source transition */
2920 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2921 pipe_name(pipe), pipe_crc_source_name(source));
2923 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2924 INTEL_PIPE_CRC_ENTRIES_NR,
2926 if (!pipe_crc->entries)
2929 spin_lock_irq(&pipe_crc->lock);
2932 spin_unlock_irq(&pipe_crc->lock);
2935 pipe_crc->source = source;
2937 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2938 POSTING_READ(PIPE_CRC_CTL(pipe));
2940 /* real source -> none transition */
2941 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2942 struct intel_pipe_crc_entry *entries;
2943 struct intel_crtc *crtc =
2944 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2946 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2949 drm_modeset_lock(&crtc->base.mutex, NULL);
2951 intel_wait_for_vblank(dev, pipe);
2952 drm_modeset_unlock(&crtc->base.mutex);
2954 spin_lock_irq(&pipe_crc->lock);
2955 entries = pipe_crc->entries;
2956 pipe_crc->entries = NULL;
2957 spin_unlock_irq(&pipe_crc->lock);
2962 g4x_undo_pipe_scramble_reset(dev, pipe);
2963 else if (IS_VALLEYVIEW(dev))
2964 vlv_undo_pipe_scramble_reset(dev, pipe);
2971 * Parse pipe CRC command strings:
2972 * command: wsp* object wsp+ name wsp+ source wsp*
2975 * source: (none | plane1 | plane2 | pf)
2976 * wsp: (#0x20 | #0x9 | #0xA)+
2979 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2980 * "pipe A none" -> Stop CRC
2982 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2989 /* skip leading white space */
2990 buf = skip_spaces(buf);
2992 break; /* end of buffer */
2994 /* find end of word */
2995 for (end = buf; *end && !isspace(*end); end++)
2998 if (n_words == max_words) {
2999 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3001 return -EINVAL; /* ran out of words[] before bytes */
3006 words[n_words++] = buf;
3013 enum intel_pipe_crc_object {
3014 PIPE_CRC_OBJECT_PIPE,
3017 static const char * const pipe_crc_objects[] = {
3022 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3026 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3027 if (!strcmp(buf, pipe_crc_objects[i])) {
3035 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3037 const char name = buf[0];
3039 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3048 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3052 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3053 if (!strcmp(buf, pipe_crc_sources[i])) {
3061 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3065 char *words[N_WORDS];
3067 enum intel_pipe_crc_object object;
3068 enum intel_pipe_crc_source source;
3070 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3071 if (n_words != N_WORDS) {
3072 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3077 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3078 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3082 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3083 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3087 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3088 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3092 return pipe_crc_set_source(dev, pipe, source);
3095 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3096 size_t len, loff_t *offp)
3098 struct seq_file *m = file->private_data;
3099 struct drm_device *dev = m->private;
3106 if (len > PAGE_SIZE - 1) {
3107 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3112 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3116 if (copy_from_user(tmpbuf, ubuf, len)) {
3122 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3133 static const struct file_operations i915_display_crc_ctl_fops = {
3134 .owner = THIS_MODULE,
3135 .open = display_crc_ctl_open,
3137 .llseek = seq_lseek,
3138 .release = single_release,
3139 .write = display_crc_ctl_write
3142 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3144 struct drm_device *dev = m->private;
3145 int num_levels = ilk_wm_max_level(dev) + 1;
3148 drm_modeset_lock_all(dev);
3150 for (level = 0; level < num_levels; level++) {
3151 unsigned int latency = wm[level];
3153 /* WM1+ latency values in 0.5us units */
3157 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3159 latency / 10, latency % 10);
3162 drm_modeset_unlock_all(dev);
3165 static int pri_wm_latency_show(struct seq_file *m, void *data)
3167 struct drm_device *dev = m->private;
3169 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3174 static int spr_wm_latency_show(struct seq_file *m, void *data)
3176 struct drm_device *dev = m->private;
3178 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3183 static int cur_wm_latency_show(struct seq_file *m, void *data)
3185 struct drm_device *dev = m->private;
3187 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3192 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3194 struct drm_device *dev = inode->i_private;
3196 if (!HAS_PCH_SPLIT(dev))
3199 return single_open(file, pri_wm_latency_show, dev);
3202 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3204 struct drm_device *dev = inode->i_private;
3206 if (!HAS_PCH_SPLIT(dev))
3209 return single_open(file, spr_wm_latency_show, dev);
3212 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3214 struct drm_device *dev = inode->i_private;
3216 if (!HAS_PCH_SPLIT(dev))
3219 return single_open(file, cur_wm_latency_show, dev);
3222 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3223 size_t len, loff_t *offp, uint16_t wm[5])
3225 struct seq_file *m = file->private_data;
3226 struct drm_device *dev = m->private;
3227 uint16_t new[5] = { 0 };
3228 int num_levels = ilk_wm_max_level(dev) + 1;
3233 if (len >= sizeof(tmp))
3236 if (copy_from_user(tmp, ubuf, len))
3241 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3242 if (ret != num_levels)
3245 drm_modeset_lock_all(dev);
3247 for (level = 0; level < num_levels; level++)
3248 wm[level] = new[level];
3250 drm_modeset_unlock_all(dev);
3256 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3257 size_t len, loff_t *offp)
3259 struct seq_file *m = file->private_data;
3260 struct drm_device *dev = m->private;
3262 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3265 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3266 size_t len, loff_t *offp)
3268 struct seq_file *m = file->private_data;
3269 struct drm_device *dev = m->private;
3271 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3274 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3275 size_t len, loff_t *offp)
3277 struct seq_file *m = file->private_data;
3278 struct drm_device *dev = m->private;
3280 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3283 static const struct file_operations i915_pri_wm_latency_fops = {
3284 .owner = THIS_MODULE,
3285 .open = pri_wm_latency_open,
3287 .llseek = seq_lseek,
3288 .release = single_release,
3289 .write = pri_wm_latency_write
3292 static const struct file_operations i915_spr_wm_latency_fops = {
3293 .owner = THIS_MODULE,
3294 .open = spr_wm_latency_open,
3296 .llseek = seq_lseek,
3297 .release = single_release,
3298 .write = spr_wm_latency_write
3301 static const struct file_operations i915_cur_wm_latency_fops = {
3302 .owner = THIS_MODULE,
3303 .open = cur_wm_latency_open,
3305 .llseek = seq_lseek,
3306 .release = single_release,
3307 .write = cur_wm_latency_write
3311 i915_wedged_get(void *data, u64 *val)
3313 struct drm_device *dev = data;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3316 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3322 i915_wedged_set(void *data, u64 val)
3324 struct drm_device *dev = data;
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3327 intel_runtime_pm_get(dev_priv);
3329 i915_handle_error(dev, val,
3330 "Manually setting wedged to %llu", val);
3332 intel_runtime_pm_put(dev_priv);
3337 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3338 i915_wedged_get, i915_wedged_set,
3342 i915_ring_stop_get(void *data, u64 *val)
3344 struct drm_device *dev = data;
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3347 *val = dev_priv->gpu_error.stop_rings;
3353 i915_ring_stop_set(void *data, u64 val)
3355 struct drm_device *dev = data;
3356 struct drm_i915_private *dev_priv = dev->dev_private;
3359 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3361 ret = mutex_lock_interruptible(&dev->struct_mutex);
3365 dev_priv->gpu_error.stop_rings = val;
3366 mutex_unlock(&dev->struct_mutex);
3371 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3372 i915_ring_stop_get, i915_ring_stop_set,
3376 i915_ring_missed_irq_get(void *data, u64 *val)
3378 struct drm_device *dev = data;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3381 *val = dev_priv->gpu_error.missed_irq_rings;
3386 i915_ring_missed_irq_set(void *data, u64 val)
3388 struct drm_device *dev = data;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3392 /* Lock against concurrent debugfs callers */
3393 ret = mutex_lock_interruptible(&dev->struct_mutex);
3396 dev_priv->gpu_error.missed_irq_rings = val;
3397 mutex_unlock(&dev->struct_mutex);
3402 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3403 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3407 i915_ring_test_irq_get(void *data, u64 *val)
3409 struct drm_device *dev = data;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3412 *val = dev_priv->gpu_error.test_irq_rings;
3418 i915_ring_test_irq_set(void *data, u64 val)
3420 struct drm_device *dev = data;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3424 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3426 /* Lock against concurrent debugfs callers */
3427 ret = mutex_lock_interruptible(&dev->struct_mutex);
3431 dev_priv->gpu_error.test_irq_rings = val;
3432 mutex_unlock(&dev->struct_mutex);
3437 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3438 i915_ring_test_irq_get, i915_ring_test_irq_set,
3441 #define DROP_UNBOUND 0x1
3442 #define DROP_BOUND 0x2
3443 #define DROP_RETIRE 0x4
3444 #define DROP_ACTIVE 0x8
3445 #define DROP_ALL (DROP_UNBOUND | \
3450 i915_drop_caches_get(void *data, u64 *val)
3458 i915_drop_caches_set(void *data, u64 val)
3460 struct drm_device *dev = data;
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 struct drm_i915_gem_object *obj, *next;
3463 struct i915_address_space *vm;
3464 struct i915_vma *vma, *x;
3467 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3469 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3470 * on ioctls on -EAGAIN. */
3471 ret = mutex_lock_interruptible(&dev->struct_mutex);
3475 if (val & DROP_ACTIVE) {
3476 ret = i915_gpu_idle(dev);
3481 if (val & (DROP_RETIRE | DROP_ACTIVE))
3482 i915_gem_retire_requests(dev);
3484 if (val & DROP_BOUND) {
3485 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3486 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3491 ret = i915_vma_unbind(vma);
3498 if (val & DROP_UNBOUND) {
3499 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3501 if (obj->pages_pin_count == 0) {
3502 ret = i915_gem_object_put_pages(obj);
3509 mutex_unlock(&dev->struct_mutex);
3514 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3515 i915_drop_caches_get, i915_drop_caches_set,
3519 i915_max_freq_get(void *data, u64 *val)
3521 struct drm_device *dev = data;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3525 if (INTEL_INFO(dev)->gen < 6)
3528 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3530 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3534 if (IS_VALLEYVIEW(dev))
3535 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3537 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3538 mutex_unlock(&dev_priv->rps.hw_lock);
3544 i915_max_freq_set(void *data, u64 val)
3546 struct drm_device *dev = data;
3547 struct drm_i915_private *dev_priv = dev->dev_private;
3548 u32 rp_state_cap, hw_max, hw_min;
3551 if (INTEL_INFO(dev)->gen < 6)
3554 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3556 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3558 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3563 * Turbo will still be enabled, but won't go above the set value.
3565 if (IS_VALLEYVIEW(dev)) {
3566 val = vlv_freq_opcode(dev_priv, val);
3568 hw_max = valleyview_rps_max_freq(dev_priv);
3569 hw_min = valleyview_rps_min_freq(dev_priv);
3571 do_div(val, GT_FREQUENCY_MULTIPLIER);
3573 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3574 hw_max = dev_priv->rps.max_freq;
3575 hw_min = (rp_state_cap >> 16) & 0xff;
3578 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3579 mutex_unlock(&dev_priv->rps.hw_lock);
3583 dev_priv->rps.max_freq_softlimit = val;
3585 if (IS_VALLEYVIEW(dev))
3586 valleyview_set_rps(dev, val);
3588 gen6_set_rps(dev, val);
3590 mutex_unlock(&dev_priv->rps.hw_lock);
3595 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3596 i915_max_freq_get, i915_max_freq_set,
3600 i915_min_freq_get(void *data, u64 *val)
3602 struct drm_device *dev = data;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3606 if (INTEL_INFO(dev)->gen < 6)
3609 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3611 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3615 if (IS_VALLEYVIEW(dev))
3616 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3618 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3619 mutex_unlock(&dev_priv->rps.hw_lock);
3625 i915_min_freq_set(void *data, u64 val)
3627 struct drm_device *dev = data;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 u32 rp_state_cap, hw_max, hw_min;
3632 if (INTEL_INFO(dev)->gen < 6)
3635 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3637 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3639 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3644 * Turbo will still be enabled, but won't go below the set value.
3646 if (IS_VALLEYVIEW(dev)) {
3647 val = vlv_freq_opcode(dev_priv, val);
3649 hw_max = valleyview_rps_max_freq(dev_priv);
3650 hw_min = valleyview_rps_min_freq(dev_priv);
3652 do_div(val, GT_FREQUENCY_MULTIPLIER);
3654 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3655 hw_max = dev_priv->rps.max_freq;
3656 hw_min = (rp_state_cap >> 16) & 0xff;
3659 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3660 mutex_unlock(&dev_priv->rps.hw_lock);
3664 dev_priv->rps.min_freq_softlimit = val;
3666 if (IS_VALLEYVIEW(dev))
3667 valleyview_set_rps(dev, val);
3669 gen6_set_rps(dev, val);
3671 mutex_unlock(&dev_priv->rps.hw_lock);
3676 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3677 i915_min_freq_get, i915_min_freq_set,
3681 i915_cache_sharing_get(void *data, u64 *val)
3683 struct drm_device *dev = data;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3688 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3691 ret = mutex_lock_interruptible(&dev->struct_mutex);
3694 intel_runtime_pm_get(dev_priv);
3696 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3698 intel_runtime_pm_put(dev_priv);
3699 mutex_unlock(&dev_priv->dev->struct_mutex);
3701 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3707 i915_cache_sharing_set(void *data, u64 val)
3709 struct drm_device *dev = data;
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3713 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3719 intel_runtime_pm_get(dev_priv);
3720 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3722 /* Update the cache sharing policy here as well */
3723 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3724 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3725 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3726 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3728 intel_runtime_pm_put(dev_priv);
3732 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3733 i915_cache_sharing_get, i915_cache_sharing_set,
3736 static int i915_forcewake_open(struct inode *inode, struct file *file)
3738 struct drm_device *dev = inode->i_private;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3741 if (INTEL_INFO(dev)->gen < 6)
3744 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3749 static int i915_forcewake_release(struct inode *inode, struct file *file)
3751 struct drm_device *dev = inode->i_private;
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3754 if (INTEL_INFO(dev)->gen < 6)
3757 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3762 static const struct file_operations i915_forcewake_fops = {
3763 .owner = THIS_MODULE,
3764 .open = i915_forcewake_open,
3765 .release = i915_forcewake_release,
3768 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3770 struct drm_device *dev = minor->dev;
3773 ent = debugfs_create_file("i915_forcewake_user",
3776 &i915_forcewake_fops);
3780 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3783 static int i915_debugfs_create(struct dentry *root,
3784 struct drm_minor *minor,
3786 const struct file_operations *fops)
3788 struct drm_device *dev = minor->dev;
3791 ent = debugfs_create_file(name,
3798 return drm_add_fake_info_node(minor, ent, fops);
3801 static const struct drm_info_list i915_debugfs_list[] = {
3802 {"i915_capabilities", i915_capabilities, 0},
3803 {"i915_gem_objects", i915_gem_object_info, 0},
3804 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3805 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3806 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3807 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3808 {"i915_gem_stolen", i915_gem_stolen_list_info },
3809 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3810 {"i915_gem_request", i915_gem_request_info, 0},
3811 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3812 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3813 {"i915_gem_interrupt", i915_interrupt_info, 0},
3814 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3815 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3816 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3817 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3818 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3819 {"i915_frequency_info", i915_frequency_info, 0},
3820 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3821 {"i915_inttoext_table", i915_inttoext_table, 0},
3822 {"i915_drpc_info", i915_drpc_info, 0},
3823 {"i915_emon_status", i915_emon_status, 0},
3824 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3825 {"i915_gfxec", i915_gfxec, 0},
3826 {"i915_fbc_status", i915_fbc_status, 0},
3827 {"i915_ips_status", i915_ips_status, 0},
3828 {"i915_sr_status", i915_sr_status, 0},
3829 {"i915_opregion", i915_opregion, 0},
3830 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3831 {"i915_context_status", i915_context_status, 0},
3832 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3833 {"i915_swizzle_info", i915_swizzle_info, 0},
3834 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3835 {"i915_llc", i915_llc, 0},
3836 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3837 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3838 {"i915_energy_uJ", i915_energy_uJ, 0},
3839 {"i915_pc8_status", i915_pc8_status, 0},
3840 {"i915_power_domain_info", i915_power_domain_info, 0},
3841 {"i915_display_info", i915_display_info, 0},
3843 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3845 static const struct i915_debugfs_files {
3847 const struct file_operations *fops;
3848 } i915_debugfs_files[] = {
3849 {"i915_wedged", &i915_wedged_fops},
3850 {"i915_max_freq", &i915_max_freq_fops},
3851 {"i915_min_freq", &i915_min_freq_fops},
3852 {"i915_cache_sharing", &i915_cache_sharing_fops},
3853 {"i915_ring_stop", &i915_ring_stop_fops},
3854 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3855 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3856 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3857 {"i915_error_state", &i915_error_state_fops},
3858 {"i915_next_seqno", &i915_next_seqno_fops},
3859 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3860 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3861 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3862 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3865 void intel_display_crc_init(struct drm_device *dev)
3867 struct drm_i915_private *dev_priv = dev->dev_private;
3870 for_each_pipe(pipe) {
3871 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3873 pipe_crc->opened = false;
3874 spin_lock_init(&pipe_crc->lock);
3875 init_waitqueue_head(&pipe_crc->wq);
3879 int i915_debugfs_init(struct drm_minor *minor)
3883 ret = i915_forcewake_create(minor->debugfs_root, minor);
3887 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3888 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3893 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3894 ret = i915_debugfs_create(minor->debugfs_root, minor,
3895 i915_debugfs_files[i].name,
3896 i915_debugfs_files[i].fops);
3901 return drm_debugfs_create_files(i915_debugfs_list,
3902 I915_DEBUGFS_ENTRIES,
3903 minor->debugfs_root, minor);
3906 void i915_debugfs_cleanup(struct drm_minor *minor)
3910 drm_debugfs_remove_files(i915_debugfs_list,
3911 I915_DEBUGFS_ENTRIES, minor);
3913 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3916 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3917 struct drm_info_list *info_list =
3918 (struct drm_info_list *)&i915_pipe_crc_data[i];
3920 drm_debugfs_remove_files(info_list, 1, minor);
3923 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3924 struct drm_info_list *info_list =
3925 (struct drm_info_list *) i915_debugfs_files[i].fops;
3927 drm_debugfs_remove_files(info_list, 1, minor);