drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
 156                            vma->node.start, vma->node.size,
 157                            vma->ggtt_view.type);
 158         }
 159         if (obj->stolen)
 160                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 161         if (obj->pin_mappable || obj->fault_mappable) {
 162                 char s[3], *t = s;
 163                 if (obj->pin_mappable)
 164                         *t++ = 'p';
 165                 if (obj->fault_mappable)
 166                         *t++ = 'f';
 167                 *t = '\0';
 168                 seq_printf(m, " (%s mappable)", s);
 169         }
 170         if (obj->last_read_req != NULL)
 171                 seq_printf(m, " (%s)",
 172                            i915_gem_request_get_ring(obj->last_read_req)->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->active) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->active)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define print_file_stats(m, name, stats) \
 364         seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 365                    name, \
 366                    stats.count, \
 367                    stats.total, \
 368                    stats.active, \
 369                    stats.inactive, \
 370                    stats.global, \
 371                    stats.shared, \
 372                    stats.unbound)
 373
 374 static void print_batch_pool_stats(struct seq_file *m,
 375                                    struct drm_i915_private *dev_priv)
 376 {
 377         struct drm_i915_gem_object *obj;
 378         struct file_stats stats;
 379
 380         memset(&stats, 0, sizeof(stats));
 381
 382         list_for_each_entry(obj,
 383                             &dev_priv->mm.batch_pool.cache_list,
 384                             batch_pool_list)
 385                 per_file_stats(0, obj, &stats);
 386
 387         print_file_stats(m, "batch pool", stats);
 388 }
 389
 390 #define count_vmas(list, member) do { \
 391         list_for_each_entry(vma, list, member) { \
 392                 size += i915_gem_obj_ggtt_size(vma->obj); \
 393                 ++count; \
 394                 if (vma->obj->map_and_fenceable) { \
 395                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 396                         ++mappable_count; \
 397                 } \
 398         } \
 399 } while (0)
 400
 401 static int i915_gem_object_info(struct seq_file *m, void* data)
 402 {
 403         struct drm_info_node *node = m->private;
 404         struct drm_device *dev = node->minor->dev;
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         u32 count, mappable_count, purgeable_count;
 407         size_t size, mappable_size, purgeable_size;
 408         struct drm_i915_gem_object *obj;
 409         struct i915_address_space *vm = &dev_priv->gtt.base;
 410         struct drm_file *file;
 411         struct i915_vma *vma;
 412         int ret;
 413
 414         ret = mutex_lock_interruptible(&dev->struct_mutex);
 415         if (ret)
 416                 return ret;
 417
 418         seq_printf(m, "%u objects, %zu bytes\n",
 419                    dev_priv->mm.object_count,
 420                    dev_priv->mm.object_memory);
 421
 422         size = count = mappable_size = mappable_count = 0;
 423         count_objects(&dev_priv->mm.bound_list, global_list);
 424         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 425                    count, mappable_count, size, mappable_size);
 426
 427         size = count = mappable_size = mappable_count = 0;
 428         count_vmas(&vm->active_list, mm_list);
 429         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 430                    count, mappable_count, size, mappable_size);
 431
 432         size = count = mappable_size = mappable_count = 0;
 433         count_vmas(&vm->inactive_list, mm_list);
 434         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 435                    count, mappable_count, size, mappable_size);
 436
 437         size = count = purgeable_size = purgeable_count = 0;
 438         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 439                 size += obj->base.size, ++count;
 440                 if (obj->madv == I915_MADV_DONTNEED)
 441                         purgeable_size += obj->base.size, ++purgeable_count;
 442         }
 443         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 444
 445         size = count = mappable_size = mappable_count = 0;
 446         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 447                 if (obj->fault_mappable) {
 448                         size += i915_gem_obj_ggtt_size(obj);
 449                         ++count;
 450                 }
 451                 if (obj->pin_mappable) {
 452                         mappable_size += i915_gem_obj_ggtt_size(obj);
 453                         ++mappable_count;
 454                 }
 455                 if (obj->madv == I915_MADV_DONTNEED) {
 456                         purgeable_size += obj->base.size;
 457                         ++purgeable_count;
 458                 }
 459         }
 460         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 461                    purgeable_count, purgeable_size);
 462         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 463                    mappable_count, mappable_size);
 464         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 465                    count, size);
 466
 467         seq_printf(m, "%zu [%lu] gtt total\n",
 468                    dev_priv->gtt.base.total,
 469                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 470
 471         seq_putc(m, '\n');
 472         print_batch_pool_stats(m, dev_priv);
 473
 474         seq_putc(m, '\n');
 475         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 476                 struct file_stats stats;
 477                 struct task_struct *task;
 478
 479                 memset(&stats, 0, sizeof(stats));
 480                 stats.file_priv = file->driver_priv;
 481                 spin_lock(&file->table_lock);
 482                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 483                 spin_unlock(&file->table_lock);
 484                 /*
 485                  * Although we have a valid reference on file->pid, that does
 486                  * not guarantee that the task_struct who called get_pid() is
 487                  * still alive (e.g. get_pid(current) => fork() => exit()).
 488                  * Therefore, we need to protect this ->comm access using RCU.
 489                  */
 490                 rcu_read_lock();
 491                 task = pid_task(file->pid, PIDTYPE_PID);
 492                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 493                 rcu_read_unlock();
 494         }
 495
 496         mutex_unlock(&dev->struct_mutex);
 497
 498         return 0;
 499 }
 500
 501 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 502 {
 503         struct drm_info_node *node = m->private;
 504         struct drm_device *dev = node->minor->dev;
 505         uintptr_t list = (uintptr_t) node->info_ent->data;
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct drm_i915_gem_object *obj;
 508         size_t total_obj_size, total_gtt_size;
 509         int count, ret;
 510
 511         ret = mutex_lock_interruptible(&dev->struct_mutex);
 512         if (ret)
 513                 return ret;
 514
 515         total_obj_size = total_gtt_size = count = 0;
 516         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 517                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 518                         continue;
 519
 520                 seq_puts(m, "   ");
 521                 describe_obj(m, obj);
 522                 seq_putc(m, '\n');
 523                 total_obj_size += obj->base.size;
 524                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 525                 count++;
 526         }
 527
 528         mutex_unlock(&dev->struct_mutex);
 529
 530         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 531                    count, total_obj_size, total_gtt_size);
 532
 533         return 0;
 534 }
 535
 536 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 537 {
 538         struct drm_info_node *node = m->private;
 539         struct drm_device *dev = node->minor->dev;
 540         struct drm_i915_private *dev_priv = dev->dev_private;
 541         struct intel_crtc *crtc;
 542         int ret;
 543
 544         ret = mutex_lock_interruptible(&dev->struct_mutex);
 545         if (ret)
 546                 return ret;
 547
 548         for_each_intel_crtc(dev, crtc) {
 549                 const char pipe = pipe_name(crtc->pipe);
 550                 const char plane = plane_name(crtc->plane);
 551                 struct intel_unpin_work *work;
 552
 553                 spin_lock_irq(&dev->event_lock);
 554                 work = crtc->unpin_work;
 555                 if (work == NULL) {
 556                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 557                                    pipe, plane);
 558                 } else {
 559                         u32 addr;
 560
 561                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 562                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *ring =
 570                                         i915_gem_request_get_ring(work->flip_queued_req);
 571
 572                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 573                                            ring->name,
 574                                            i915_gem_request_get_seqno(work->flip_queued_req),
 575                                            dev_priv->next_seqno,
 576                                            ring->get_seqno(ring, true),
 577                                            i915_gem_request_completed(work->flip_queued_req, true));
 578                         } else
 579                                 seq_printf(m, "Flip not associated with any ring\n");
 580                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 581                                    work->flip_queued_vblank,
 582                                    work->flip_ready_vblank,
 583                                    drm_vblank_count(dev, crtc->pipe));
 584                         if (work->enable_stall_check)
 585                                 seq_puts(m, "Stall check enabled, ");
 586                         else
 587                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 588                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 589
 590                         if (INTEL_INFO(dev)->gen >= 4)
 591                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 592                         else
 593                                 addr = I915_READ(DSPADDR(crtc->plane));
 594                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 595
 596                         if (work->pending_flip_obj) {
 597                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 598                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 599                         }
 600                 }
 601                 spin_unlock_irq(&dev->event_lock);
 602         }
 603
 604         mutex_unlock(&dev->struct_mutex);
 605
 606         return 0;
 607 }
 608
 609 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 610 {
 611         struct drm_info_node *node = m->private;
 612         struct drm_device *dev = node->minor->dev;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct drm_i915_gem_object *obj;
 615         int count = 0;
 616         int ret;
 617
 618         ret = mutex_lock_interruptible(&dev->struct_mutex);
 619         if (ret)
 620                 return ret;
 621
 622         seq_puts(m, "cache:\n");
 623         list_for_each_entry(obj,
 624                             &dev_priv->mm.batch_pool.cache_list,
 625                             batch_pool_list) {
 626                 seq_puts(m, "   ");
 627                 describe_obj(m, obj);
 628                 seq_putc(m, '\n');
 629                 count++;
 630         }
 631
 632         seq_printf(m, "total: %d\n", count);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static int i915_gem_request_info(struct seq_file *m, void *data)
 640 {
 641         struct drm_info_node *node = m->private;
 642         struct drm_device *dev = node->minor->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_engine_cs *ring;
 645         struct drm_i915_gem_request *gem_request;
 646         int ret, count, i;
 647
 648         ret = mutex_lock_interruptible(&dev->struct_mutex);
 649         if (ret)
 650                 return ret;
 651
 652         count = 0;
 653         for_each_ring(ring, dev_priv, i) {
 654                 if (list_empty(&ring->request_list))
 655                         continue;
 656
 657                 seq_printf(m, "%s requests:\n", ring->name);
 658                 list_for_each_entry(gem_request,
 659                                     &ring->request_list,
 660                                     list) {
 661                         seq_printf(m, "    %x @ %d\n",
 662                                    gem_request->seqno,
 663                                    (int) (jiffies - gem_request->emitted_jiffies));
 664                 }
 665                 count++;
 666         }
 667         mutex_unlock(&dev->struct_mutex);
 668
 669         if (count == 0)
 670                 seq_puts(m, "No requests\n");
 671
 672         return 0;
 673 }
 674
 675 static void i915_ring_seqno_info(struct seq_file *m,
 676                                  struct intel_engine_cs *ring)
 677 {
 678         if (ring->get_seqno) {
 679                 seq_printf(m, "Current sequence (%s): %x\n",
 680                            ring->name, ring->get_seqno(ring, false));
 681         }
 682 }
 683
 684 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 685 {
 686         struct drm_info_node *node = m->private;
 687         struct drm_device *dev = node->minor->dev;
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         struct intel_engine_cs *ring;
 690         int ret, i;
 691
 692         ret = mutex_lock_interruptible(&dev->struct_mutex);
 693         if (ret)
 694                 return ret;
 695         intel_runtime_pm_get(dev_priv);
 696
 697         for_each_ring(ring, dev_priv, i)
 698                 i915_ring_seqno_info(m, ring);
 699
 700         intel_runtime_pm_put(dev_priv);
 701         mutex_unlock(&dev->struct_mutex);
 702
 703         return 0;
 704 }
 705
 706
 707 static int i915_interrupt_info(struct seq_file *m, void *data)
 708 {
 709         struct drm_info_node *node = m->private;
 710         struct drm_device *dev = node->minor->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct intel_engine_cs *ring;
 713         int ret, i, pipe;
 714
 715         ret = mutex_lock_interruptible(&dev->struct_mutex);
 716         if (ret)
 717                 return ret;
 718         intel_runtime_pm_get(dev_priv);
 719
 720         if (IS_CHERRYVIEW(dev)) {
 721                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 722                            I915_READ(GEN8_MASTER_IRQ));
 723
 724                 seq_printf(m, "Display IER:\t%08x\n",
 725                            I915_READ(VLV_IER));
 726                 seq_printf(m, "Display IIR:\t%08x\n",
 727                            I915_READ(VLV_IIR));
 728                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 729                            I915_READ(VLV_IIR_RW));
 730                 seq_printf(m, "Display IMR:\t%08x\n",
 731                            I915_READ(VLV_IMR));
 732                 for_each_pipe(dev_priv, pipe)
 733                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 734                                    pipe_name(pipe),
 735                                    I915_READ(PIPESTAT(pipe)));
 736
 737                 seq_printf(m, "Port hotplug:\t%08x\n",
 738                            I915_READ(PORT_HOTPLUG_EN));
 739                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 740                            I915_READ(VLV_DPFLIPSTAT));
 741                 seq_printf(m, "DPINVGTT:\t%08x\n",
 742                            I915_READ(DPINVGTT));
 743
 744                 for (i = 0; i < 4; i++) {
 745                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 746                                    i, I915_READ(GEN8_GT_IMR(i)));
 747                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 748                                    i, I915_READ(GEN8_GT_IIR(i)));
 749                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 750                                    i, I915_READ(GEN8_GT_IER(i)));
 751                 }
 752
 753                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 754                            I915_READ(GEN8_PCU_IMR));
 755                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 756                            I915_READ(GEN8_PCU_IIR));
 757                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 758                            I915_READ(GEN8_PCU_IER));
 759         } else if (INTEL_INFO(dev)->gen >= 8) {
 760                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 761                            I915_READ(GEN8_MASTER_IRQ));
 762
 763                 for (i = 0; i < 4; i++) {
 764                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 765                                    i, I915_READ(GEN8_GT_IMR(i)));
 766                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 767                                    i, I915_READ(GEN8_GT_IIR(i)));
 768                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 769                                    i, I915_READ(GEN8_GT_IER(i)));
 770                 }
 771
 772                 for_each_pipe(dev_priv, pipe) {
 773                         if (!intel_display_power_is_enabled(dev_priv,
 774                                                 POWER_DOMAIN_PIPE(pipe))) {
 775                                 seq_printf(m, "Pipe %c power disabled\n",
 776                                            pipe_name(pipe));
 777                                 continue;
 778                         }
 779                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 780                                    pipe_name(pipe),
 781                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 782                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 783                                    pipe_name(pipe),
 784                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 785                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 786                                    pipe_name(pipe),
 787                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 788                 }
 789
 790                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 791                            I915_READ(GEN8_DE_PORT_IMR));
 792                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 793                            I915_READ(GEN8_DE_PORT_IIR));
 794                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 795                            I915_READ(GEN8_DE_PORT_IER));
 796
 797                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 798                            I915_READ(GEN8_DE_MISC_IMR));
 799                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 800                            I915_READ(GEN8_DE_MISC_IIR));
 801                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 802                            I915_READ(GEN8_DE_MISC_IER));
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (IS_VALLEYVIEW(dev)) {
 811                 seq_printf(m, "Display IER:\t%08x\n",
 812                            I915_READ(VLV_IER));
 813                 seq_printf(m, "Display IIR:\t%08x\n",
 814                            I915_READ(VLV_IIR));
 815                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 816                            I915_READ(VLV_IIR_RW));
 817                 seq_printf(m, "Display IMR:\t%08x\n",
 818                            I915_READ(VLV_IMR));
 819                 for_each_pipe(dev_priv, pipe)
 820                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(PIPESTAT(pipe)));
 823
 824                 seq_printf(m, "Master IER:\t%08x\n",
 825                            I915_READ(VLV_MASTER_IER));
 826
 827                 seq_printf(m, "Render IER:\t%08x\n",
 828                            I915_READ(GTIER));
 829                 seq_printf(m, "Render IIR:\t%08x\n",
 830                            I915_READ(GTIIR));
 831                 seq_printf(m, "Render IMR:\t%08x\n",
 832                            I915_READ(GTIMR));
 833
 834                 seq_printf(m, "PM IER:\t\t%08x\n",
 835                            I915_READ(GEN6_PMIER));
 836                 seq_printf(m, "PM IIR:\t\t%08x\n",
 837                            I915_READ(GEN6_PMIIR));
 838                 seq_printf(m, "PM IMR:\t\t%08x\n",
 839                            I915_READ(GEN6_PMIMR));
 840
 841                 seq_printf(m, "Port hotplug:\t%08x\n",
 842                            I915_READ(PORT_HOTPLUG_EN));
 843                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 844                            I915_READ(VLV_DPFLIPSTAT));
 845                 seq_printf(m, "DPINVGTT:\t%08x\n",
 846                            I915_READ(DPINVGTT));
 847
 848         } else if (!HAS_PCH_SPLIT(dev)) {
 849                 seq_printf(m, "Interrupt enable:    %08x\n",
 850                            I915_READ(IER));
 851                 seq_printf(m, "Interrupt identity:  %08x\n",
 852                            I915_READ(IIR));
 853                 seq_printf(m, "Interrupt mask:      %08x\n",
 854                            I915_READ(IMR));
 855                 for_each_pipe(dev_priv, pipe)
 856                         seq_printf(m, "Pipe %c stat:         %08x\n",
 857                                    pipe_name(pipe),
 858                                    I915_READ(PIPESTAT(pipe)));
 859         } else {
 860                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 861                            I915_READ(DEIER));
 862                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 863                            I915_READ(DEIIR));
 864                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 865                            I915_READ(DEIMR));
 866                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 867                            I915_READ(SDEIER));
 868                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 869                            I915_READ(SDEIIR));
 870                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 871                            I915_READ(SDEIMR));
 872                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 873                            I915_READ(GTIER));
 874                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 875                            I915_READ(GTIIR));
 876                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 877                            I915_READ(GTIMR));
 878         }
 879         for_each_ring(ring, dev_priv, i) {
 880                 if (INTEL_INFO(dev)->gen >= 6) {
 881                         seq_printf(m,
 882                                    "Graphics Interrupt mask (%s):       %08x\n",
 883                                    ring->name, I915_READ_IMR(ring));
 884                 }
 885                 i915_ring_seqno_info(m, ring);
 886         }
 887         intel_runtime_pm_put(dev_priv);
 888         mutex_unlock(&dev->struct_mutex);
 889
 890         return 0;
 891 }
 892
 893 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 894 {
 895         struct drm_info_node *node = m->private;
 896         struct drm_device *dev = node->minor->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         int i, ret;
 899
 900         ret = mutex_lock_interruptible(&dev->struct_mutex);
 901         if (ret)
 902                 return ret;
 903
 904         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 905         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 906         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 907                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 908
 909                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 910                            i, dev_priv->fence_regs[i].pin_count);
 911                 if (obj == NULL)
 912                         seq_puts(m, "unused");
 913                 else
 914                         describe_obj(m, obj);
 915                 seq_putc(m, '\n');
 916         }
 917
 918         mutex_unlock(&dev->struct_mutex);
 919         return 0;
 920 }
 921
 922 static int i915_hws_info(struct seq_file *m, void *data)
 923 {
 924         struct drm_info_node *node = m->private;
 925         struct drm_device *dev = node->minor->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         struct intel_engine_cs *ring;
 928         const u32 *hws;
 929         int i;
 930
 931         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 932         hws = ring->status_page.page_addr;
 933         if (hws == NULL)
 934                 return 0;
 935
 936         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 937                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 938                            i * 4,
 939                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 940         }
 941         return 0;
 942 }
 943
 944 static ssize_t
 945 i915_error_state_write(struct file *filp,
 946                        const char __user *ubuf,
 947                        size_t cnt,
 948                        loff_t *ppos)
 949 {
 950         struct i915_error_state_file_priv *error_priv = filp->private_data;
 951         struct drm_device *dev = error_priv->dev;
 952         int ret;
 953
 954         DRM_DEBUG_DRIVER("Resetting error state\n");
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         i915_destroy_error_state(dev);
 961         mutex_unlock(&dev->struct_mutex);
 962
 963         return cnt;
 964 }
 965
 966 static int i915_error_state_open(struct inode *inode, struct file *file)
 967 {
 968         struct drm_device *dev = inode->i_private;
 969         struct i915_error_state_file_priv *error_priv;
 970
 971         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 972         if (!error_priv)
 973                 return -ENOMEM;
 974
 975         error_priv->dev = dev;
 976
 977         i915_error_state_get(dev, error_priv);
 978
 979         file->private_data = error_priv;
 980
 981         return 0;
 982 }
 983
 984 static int i915_error_state_release(struct inode *inode, struct file *file)
 985 {
 986         struct i915_error_state_file_priv *error_priv = file->private_data;
 987
 988         i915_error_state_put(error_priv);
 989         kfree(error_priv);
 990
 991         return 0;
 992 }
 993
 994 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 995                                      size_t count, loff_t *pos)
 996 {
 997         struct i915_error_state_file_priv *error_priv = file->private_data;
 998         struct drm_i915_error_state_buf error_str;
 999         loff_t tmp_pos = 0;
1000         ssize_t ret_count = 0;
1001         int ret;
1002
1003         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_error_state_to_str(&error_str, error_priv);
1008         if (ret)
1009                 goto out;
1010
1011         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012                                             error_str.buf,
1013                                             error_str.bytes);
1014
1015         if (ret_count < 0)
1016                 ret = ret_count;
1017         else
1018                 *pos = error_str.start + ret_count;
1019 out:
1020         i915_error_state_buf_release(&error_str);
1021         return ret ?: ret_count;
1022 }
1023
1024 static const struct file_operations i915_error_state_fops = {
1025         .owner = THIS_MODULE,
1026         .open = i915_error_state_open,
1027         .read = i915_error_state_read,
1028         .write = i915_error_state_write,
1029         .llseek = default_llseek,
1030         .release = i915_error_state_release,
1031 };
1032
1033 static int
1034 i915_next_seqno_get(void *data, u64 *val)
1035 {
1036         struct drm_device *dev = data;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         int ret;
1039
1040         ret = mutex_lock_interruptible(&dev->struct_mutex);
1041         if (ret)
1042                 return ret;
1043
1044         *val = dev_priv->next_seqno;
1045         mutex_unlock(&dev->struct_mutex);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 i915_next_seqno_set(void *data, u64 val)
1052 {
1053         struct drm_device *dev = data;
1054         int ret;
1055
1056         ret = mutex_lock_interruptible(&dev->struct_mutex);
1057         if (ret)
1058                 return ret;
1059
1060         ret = i915_gem_set_seqno(dev, val);
1061         mutex_unlock(&dev->struct_mutex);
1062
1063         return ret;
1064 }
1065
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067                         i915_next_seqno_get, i915_next_seqno_set,
1068                         "0x%llx\n");
1069
1070 static int i915_frequency_info(struct seq_file *m, void *unused)
1071 {
1072         struct drm_info_node *node = m->private;
1073         struct drm_device *dev = node->minor->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         int ret = 0;
1076
1077         intel_runtime_pm_get(dev_priv);
1078
1079         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
1081         if (IS_GEN5(dev)) {
1082                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088                            MEMSTAT_VID_SHIFT);
1089                 seq_printf(m, "Current P-state: %d\n",
1090                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1091         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092                    IS_BROADWELL(dev)) {
1093                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1096                 u32 rpmodectl, rpinclimit, rpdeclimit;
1097                 u32 rpstat, cagf, reqf;
1098                 u32 rpupei, rpcurup, rpprevup;
1099                 u32 rpdownei, rpcurdown, rpprevdown;
1100                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1101                 int max_freq;
1102
1103                 /* RPSTAT1 is in the GT power well */
1104                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105                 if (ret)
1106                         goto out;
1107
1108                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1109
1110                 reqf = I915_READ(GEN6_RPNSWREQ);
1111                 reqf &= ~GEN6_TURBO_DISABLE;
1112                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1113                         reqf >>= 24;
1114                 else
1115                         reqf >>= 25;
1116                 reqf = intel_gpu_freq(dev_priv, reqf);
1117
1118                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
1122                 rpstat = I915_READ(GEN6_RPSTAT1);
1123                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1129                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1130                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131                 else
1132                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133                 cagf = intel_gpu_freq(dev_priv, cagf);
1134
1135                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1136                 mutex_unlock(&dev->struct_mutex);
1137
1138                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139                         pm_ier = I915_READ(GEN6_PMIER);
1140                         pm_imr = I915_READ(GEN6_PMIMR);
1141                         pm_isr = I915_READ(GEN6_PMISR);
1142                         pm_iir = I915_READ(GEN6_PMIIR);
1143                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1144                 } else {
1145                         pm_ier = I915_READ(GEN8_GT_IER(2));
1146                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1147                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1148                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1149                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1150                 }
1151                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1153                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1154                 seq_printf(m, "Render p-state ratio: %d\n",
1155                            (gt_perf_status & 0xff00) >> 8);
1156                 seq_printf(m, "Render p-state VID: %d\n",
1157                            gt_perf_status & 0xff);
1158                 seq_printf(m, "Render p-state limit: %d\n",
1159                            rp_state_limits & 0xff);
1160                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1164                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1165                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1166                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167                            GEN6_CURICONT_MASK);
1168                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169                            GEN6_CURBSYTAVG_MASK);
1170                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171                            GEN6_CURBSYTAVG_MASK);
1172                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173                            GEN6_CURIAVG_MASK);
1174                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175                            GEN6_CURBSYTAVG_MASK);
1176                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177                            GEN6_CURBSYTAVG_MASK);
1178
1179                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1181                            intel_gpu_freq(dev_priv, max_freq));
1182
1183                 max_freq = (rp_state_cap & 0xff00) >> 8;
1184                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185                            intel_gpu_freq(dev_priv, max_freq));
1186
1187                 max_freq = rp_state_cap & 0xff;
1188                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189                            intel_gpu_freq(dev_priv, max_freq));
1190
1191                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1192                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1193         } else if (IS_VALLEYVIEW(dev)) {
1194                 u32 freq_sts;
1195
1196                 mutex_lock(&dev_priv->rps.hw_lock);
1197                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1198                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
1201                 seq_printf(m, "max GPU freq: %d MHz\n",
1202                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1203
1204                 seq_printf(m, "min GPU freq: %d MHz\n",
1205                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1206
1207                 seq_printf(m,
1208                            "efficient (RPe) frequency: %d MHz\n",
1209                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1210
1211                 seq_printf(m, "current GPU freq: %d MHz\n",
1212                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1213                 mutex_unlock(&dev_priv->rps.hw_lock);
1214         } else {
1215                 seq_puts(m, "no P-state info available\n");
1216         }
1217
1218 out:
1219         intel_runtime_pm_put(dev_priv);
1220         return ret;
1221 }
1222
1223 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1224 {
1225         struct drm_info_node *node = m->private;
1226         struct drm_device *dev = node->minor->dev;
1227         struct drm_i915_private *dev_priv = dev->dev_private;
1228         struct intel_engine_cs *ring;
1229         u64 acthd[I915_NUM_RINGS];
1230         u32 seqno[I915_NUM_RINGS];
1231         int i;
1232
1233         if (!i915.enable_hangcheck) {
1234                 seq_printf(m, "Hangcheck disabled\n");
1235                 return 0;
1236         }
1237
1238         intel_runtime_pm_get(dev_priv);
1239
1240         for_each_ring(ring, dev_priv, i) {
1241                 seqno[i] = ring->get_seqno(ring, false);
1242                 acthd[i] = intel_ring_get_active_head(ring);
1243         }
1244
1245         intel_runtime_pm_put(dev_priv);
1246
1247         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1248                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1249                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1250                                             jiffies));
1251         } else
1252                 seq_printf(m, "Hangcheck inactive\n");
1253
1254         for_each_ring(ring, dev_priv, i) {
1255                 seq_printf(m, "%s:\n", ring->name);
1256                 seq_printf(m, "\tseqno = %x [current %x]\n",
1257                            ring->hangcheck.seqno, seqno[i]);
1258                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1259                            (long long)ring->hangcheck.acthd,
1260                            (long long)acthd[i]);
1261                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1262                            (long long)ring->hangcheck.max_acthd);
1263                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1264                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int ironlake_drpc_info(struct seq_file *m)
1271 {
1272         struct drm_info_node *node = m->private;
1273         struct drm_device *dev = node->minor->dev;
1274         struct drm_i915_private *dev_priv = dev->dev_private;
1275         u32 rgvmodectl, rstdbyctl;
1276         u16 crstandvid;
1277         int ret;
1278
1279         ret = mutex_lock_interruptible(&dev->struct_mutex);
1280         if (ret)
1281                 return ret;
1282         intel_runtime_pm_get(dev_priv);
1283
1284         rgvmodectl = I915_READ(MEMMODECTL);
1285         rstdbyctl = I915_READ(RSTDBYCTL);
1286         crstandvid = I915_READ16(CRSTANDVID);
1287
1288         intel_runtime_pm_put(dev_priv);
1289         mutex_unlock(&dev->struct_mutex);
1290
1291         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1292                    "yes" : "no");
1293         seq_printf(m, "Boost freq: %d\n",
1294                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1295                    MEMMODE_BOOST_FREQ_SHIFT);
1296         seq_printf(m, "HW control enabled: %s\n",
1297                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1298         seq_printf(m, "SW control enabled: %s\n",
1299                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1300         seq_printf(m, "Gated voltage change: %s\n",
1301                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1302         seq_printf(m, "Starting frequency: P%d\n",
1303                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1304         seq_printf(m, "Max P-state: P%d\n",
1305                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1306         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1307         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1308         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1309         seq_printf(m, "Render standby enabled: %s\n",
1310                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1311         seq_puts(m, "Current RS state: ");
1312         switch (rstdbyctl & RSX_STATUS_MASK) {
1313         case RSX_STATUS_ON:
1314                 seq_puts(m, "on\n");
1315                 break;
1316         case RSX_STATUS_RC1:
1317                 seq_puts(m, "RC1\n");
1318                 break;
1319         case RSX_STATUS_RC1E:
1320                 seq_puts(m, "RC1E\n");
1321                 break;
1322         case RSX_STATUS_RS1:
1323                 seq_puts(m, "RS1\n");
1324                 break;
1325         case RSX_STATUS_RS2:
1326                 seq_puts(m, "RS2 (RC6)\n");
1327                 break;
1328         case RSX_STATUS_RS3:
1329                 seq_puts(m, "RC3 (RC6+)\n");
1330                 break;
1331         default:
1332                 seq_puts(m, "unknown\n");
1333                 break;
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int i915_forcewake_domains(struct seq_file *m, void *data)
1340 {
1341         struct drm_info_node *node = m->private;
1342         struct drm_device *dev = node->minor->dev;
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         struct intel_uncore_forcewake_domain *fw_domain;
1345         int i;
1346
1347         spin_lock_irq(&dev_priv->uncore.lock);
1348         for_each_fw_domain(fw_domain, dev_priv, i) {
1349                 seq_printf(m, "%s.wake_count = %u\n",
1350                            intel_uncore_forcewake_domain_to_str(i),
1351                            fw_domain->wake_count);
1352         }
1353         spin_unlock_irq(&dev_priv->uncore.lock);
1354
1355         return 0;
1356 }
1357
1358 static int vlv_drpc_info(struct seq_file *m)
1359 {
1360         struct drm_info_node *node = m->private;
1361         struct drm_device *dev = node->minor->dev;
1362         struct drm_i915_private *dev_priv = dev->dev_private;
1363         u32 rpmodectl1, rcctl1, pw_status;
1364
1365         intel_runtime_pm_get(dev_priv);
1366
1367         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1368         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1369         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1370
1371         intel_runtime_pm_put(dev_priv);
1372
1373         seq_printf(m, "Video Turbo Mode: %s\n",
1374                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1375         seq_printf(m, "Turbo enabled: %s\n",
1376                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1377         seq_printf(m, "HW control enabled: %s\n",
1378                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1379         seq_printf(m, "SW control enabled: %s\n",
1380                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1381                           GEN6_RP_MEDIA_SW_MODE));
1382         seq_printf(m, "RC6 Enabled: %s\n",
1383                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1384                                         GEN6_RC_CTL_EI_MODE(1))));
1385         seq_printf(m, "Render Power Well: %s\n",
1386                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1387         seq_printf(m, "Media Power Well: %s\n",
1388                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1389
1390         seq_printf(m, "Render RC6 residency since boot: %u\n",
1391                    I915_READ(VLV_GT_RENDER_RC6));
1392         seq_printf(m, "Media RC6 residency since boot: %u\n",
1393                    I915_READ(VLV_GT_MEDIA_RC6));
1394
1395         return i915_forcewake_domains(m, NULL);
1396 }
1397
1398 static int gen6_drpc_info(struct seq_file *m)
1399 {
1400         struct drm_info_node *node = m->private;
1401         struct drm_device *dev = node->minor->dev;
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1404         unsigned forcewake_count;
1405         int count = 0, ret;
1406
1407         ret = mutex_lock_interruptible(&dev->struct_mutex);
1408         if (ret)
1409                 return ret;
1410         intel_runtime_pm_get(dev_priv);
1411
1412         spin_lock_irq(&dev_priv->uncore.lock);
1413         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1414         spin_unlock_irq(&dev_priv->uncore.lock);
1415
1416         if (forcewake_count) {
1417                 seq_puts(m, "RC information inaccurate because somebody "
1418                             "holds a forcewake reference \n");
1419         } else {
1420                 /* NB: we cannot use forcewake, else we read the wrong values */
1421                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1422                         udelay(10);
1423                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1424         }
1425
1426         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1427         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1428
1429         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1430         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1431         mutex_unlock(&dev->struct_mutex);
1432         mutex_lock(&dev_priv->rps.hw_lock);
1433         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1434         mutex_unlock(&dev_priv->rps.hw_lock);
1435
1436         intel_runtime_pm_put(dev_priv);
1437
1438         seq_printf(m, "Video Turbo Mode: %s\n",
1439                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1440         seq_printf(m, "HW control enabled: %s\n",
1441                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1442         seq_printf(m, "SW control enabled: %s\n",
1443                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1444                           GEN6_RP_MEDIA_SW_MODE));
1445         seq_printf(m, "RC1e Enabled: %s\n",
1446                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1447         seq_printf(m, "RC6 Enabled: %s\n",
1448                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1449         seq_printf(m, "Deep RC6 Enabled: %s\n",
1450                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1451         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1452                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1453         seq_puts(m, "Current RC state: ");
1454         switch (gt_core_status & GEN6_RCn_MASK) {
1455         case GEN6_RC0:
1456                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1457                         seq_puts(m, "Core Power Down\n");
1458                 else
1459                         seq_puts(m, "on\n");
1460                 break;
1461         case GEN6_RC3:
1462                 seq_puts(m, "RC3\n");
1463                 break;
1464         case GEN6_RC6:
1465                 seq_puts(m, "RC6\n");
1466                 break;
1467         case GEN6_RC7:
1468                 seq_puts(m, "RC7\n");
1469                 break;
1470         default:
1471                 seq_puts(m, "Unknown\n");
1472                 break;
1473         }
1474
1475         seq_printf(m, "Core Power Down: %s\n",
1476                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1477
1478         /* Not exactly sure what this is */
1479         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1480                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1481         seq_printf(m, "RC6 residency since boot: %u\n",
1482                    I915_READ(GEN6_GT_GFX_RC6));
1483         seq_printf(m, "RC6+ residency since boot: %u\n",
1484                    I915_READ(GEN6_GT_GFX_RC6p));
1485         seq_printf(m, "RC6++ residency since boot: %u\n",
1486                    I915_READ(GEN6_GT_GFX_RC6pp));
1487
1488         seq_printf(m, "RC6   voltage: %dmV\n",
1489                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1490         seq_printf(m, "RC6+  voltage: %dmV\n",
1491                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1492         seq_printf(m, "RC6++ voltage: %dmV\n",
1493                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1494         return 0;
1495 }
1496
1497 static int i915_drpc_info(struct seq_file *m, void *unused)
1498 {
1499         struct drm_info_node *node = m->private;
1500         struct drm_device *dev = node->minor->dev;
1501
1502         if (IS_VALLEYVIEW(dev))
1503                 return vlv_drpc_info(m);
1504         else if (INTEL_INFO(dev)->gen >= 6)
1505                 return gen6_drpc_info(m);
1506         else
1507                 return ironlake_drpc_info(m);
1508 }
1509
1510 static int i915_fbc_status(struct seq_file *m, void *unused)
1511 {
1512         struct drm_info_node *node = m->private;
1513         struct drm_device *dev = node->minor->dev;
1514         struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516         if (!HAS_FBC(dev)) {
1517                 seq_puts(m, "FBC unsupported on this chipset\n");
1518                 return 0;
1519         }
1520
1521         intel_runtime_pm_get(dev_priv);
1522
1523         if (intel_fbc_enabled(dev)) {
1524                 seq_puts(m, "FBC enabled\n");
1525         } else {
1526                 seq_puts(m, "FBC disabled: ");
1527                 switch (dev_priv->fbc.no_fbc_reason) {
1528                 case FBC_OK:
1529                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1530                         break;
1531                 case FBC_UNSUPPORTED:
1532                         seq_puts(m, "unsupported by this chipset");
1533                         break;
1534                 case FBC_NO_OUTPUT:
1535                         seq_puts(m, "no outputs");
1536                         break;
1537                 case FBC_STOLEN_TOO_SMALL:
1538                         seq_puts(m, "not enough stolen memory");
1539                         break;
1540                 case FBC_UNSUPPORTED_MODE:
1541                         seq_puts(m, "mode not supported");
1542                         break;
1543                 case FBC_MODE_TOO_LARGE:
1544                         seq_puts(m, "mode too large");
1545                         break;
1546                 case FBC_BAD_PLANE:
1547                         seq_puts(m, "FBC unsupported on plane");
1548                         break;
1549                 case FBC_NOT_TILED:
1550                         seq_puts(m, "scanout buffer not tiled");
1551                         break;
1552                 case FBC_MULTIPLE_PIPES:
1553                         seq_puts(m, "multiple pipes are enabled");
1554                         break;
1555                 case FBC_MODULE_PARAM:
1556                         seq_puts(m, "disabled per module param (default off)");
1557                         break;
1558                 case FBC_CHIP_DEFAULT:
1559                         seq_puts(m, "disabled per chip default");
1560                         break;
1561                 default:
1562                         seq_puts(m, "unknown reason");
1563                 }
1564                 seq_putc(m, '\n');
1565         }
1566
1567         intel_runtime_pm_put(dev_priv);
1568
1569         return 0;
1570 }
1571
1572 static int i915_fbc_fc_get(void *data, u64 *val)
1573 {
1574         struct drm_device *dev = data;
1575         struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1578                 return -ENODEV;
1579
1580         drm_modeset_lock_all(dev);
1581         *val = dev_priv->fbc.false_color;
1582         drm_modeset_unlock_all(dev);
1583
1584         return 0;
1585 }
1586
1587 static int i915_fbc_fc_set(void *data, u64 val)
1588 {
1589         struct drm_device *dev = data;
1590         struct drm_i915_private *dev_priv = dev->dev_private;
1591         u32 reg;
1592
1593         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1594                 return -ENODEV;
1595
1596         drm_modeset_lock_all(dev);
1597
1598         reg = I915_READ(ILK_DPFC_CONTROL);
1599         dev_priv->fbc.false_color = val;
1600
1601         I915_WRITE(ILK_DPFC_CONTROL, val ?
1602                    (reg | FBC_CTL_FALSE_COLOR) :
1603                    (reg & ~FBC_CTL_FALSE_COLOR));
1604
1605         drm_modeset_unlock_all(dev);
1606         return 0;
1607 }
1608
1609 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1610                         i915_fbc_fc_get, i915_fbc_fc_set,
1611                         "%llu\n");
1612
1613 static int i915_ips_status(struct seq_file *m, void *unused)
1614 {
1615         struct drm_info_node *node = m->private;
1616         struct drm_device *dev = node->minor->dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618
1619         if (!HAS_IPS(dev)) {
1620                 seq_puts(m, "not supported\n");
1621                 return 0;
1622         }
1623
1624         intel_runtime_pm_get(dev_priv);
1625
1626         seq_printf(m, "Enabled by kernel parameter: %s\n",
1627                    yesno(i915.enable_ips));
1628
1629         if (INTEL_INFO(dev)->gen >= 8) {
1630                 seq_puts(m, "Currently: unknown\n");
1631         } else {
1632                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1633                         seq_puts(m, "Currently: enabled\n");
1634                 else
1635                         seq_puts(m, "Currently: disabled\n");
1636         }
1637
1638         intel_runtime_pm_put(dev_priv);
1639
1640         return 0;
1641 }
1642
1643 static int i915_sr_status(struct seq_file *m, void *unused)
1644 {
1645         struct drm_info_node *node = m->private;
1646         struct drm_device *dev = node->minor->dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         bool sr_enabled = false;
1649
1650         intel_runtime_pm_get(dev_priv);
1651
1652         if (HAS_PCH_SPLIT(dev))
1653                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1654         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1655                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1656         else if (IS_I915GM(dev))
1657                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1658         else if (IS_PINEVIEW(dev))
1659                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1660
1661         intel_runtime_pm_put(dev_priv);
1662
1663         seq_printf(m, "self-refresh: %s\n",
1664                    sr_enabled ? "enabled" : "disabled");
1665
1666         return 0;
1667 }
1668
1669 static int i915_emon_status(struct seq_file *m, void *unused)
1670 {
1671         struct drm_info_node *node = m->private;
1672         struct drm_device *dev = node->minor->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         unsigned long temp, chipset, gfx;
1675         int ret;
1676
1677         if (!IS_GEN5(dev))
1678                 return -ENODEV;
1679
1680         ret = mutex_lock_interruptible(&dev->struct_mutex);
1681         if (ret)
1682                 return ret;
1683
1684         temp = i915_mch_val(dev_priv);
1685         chipset = i915_chipset_val(dev_priv);
1686         gfx = i915_gfx_val(dev_priv);
1687         mutex_unlock(&dev->struct_mutex);
1688
1689         seq_printf(m, "GMCH temp: %ld\n", temp);
1690         seq_printf(m, "Chipset power: %ld\n", chipset);
1691         seq_printf(m, "GFX power: %ld\n", gfx);
1692         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1693
1694         return 0;
1695 }
1696
1697 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1698 {
1699         struct drm_info_node *node = m->private;
1700         struct drm_device *dev = node->minor->dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702         int ret = 0;
1703         int gpu_freq, ia_freq;
1704
1705         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1706                 seq_puts(m, "unsupported on this chipset\n");
1707                 return 0;
1708         }
1709
1710         intel_runtime_pm_get(dev_priv);
1711
1712         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1713
1714         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1715         if (ret)
1716                 goto out;
1717
1718         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1719
1720         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1721              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1722              gpu_freq++) {
1723                 ia_freq = gpu_freq;
1724                 sandybridge_pcode_read(dev_priv,
1725                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1726                                        &ia_freq);
1727                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1728                            intel_gpu_freq(dev_priv, gpu_freq),
1729                            ((ia_freq >> 0) & 0xff) * 100,
1730                            ((ia_freq >> 8) & 0xff) * 100);
1731         }
1732
1733         mutex_unlock(&dev_priv->rps.hw_lock);
1734
1735 out:
1736         intel_runtime_pm_put(dev_priv);
1737         return ret;
1738 }
1739
1740 static int i915_opregion(struct seq_file *m, void *unused)
1741 {
1742         struct drm_info_node *node = m->private;
1743         struct drm_device *dev = node->minor->dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_opregion *opregion = &dev_priv->opregion;
1746         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1747         int ret;
1748
1749         if (data == NULL)
1750                 return -ENOMEM;
1751
1752         ret = mutex_lock_interruptible(&dev->struct_mutex);
1753         if (ret)
1754                 goto out;
1755
1756         if (opregion->header) {
1757                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1758                 seq_write(m, data, OPREGION_SIZE);
1759         }
1760
1761         mutex_unlock(&dev->struct_mutex);
1762
1763 out:
1764         kfree(data);
1765         return 0;
1766 }
1767
1768 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1769 {
1770         struct drm_info_node *node = m->private;
1771         struct drm_device *dev = node->minor->dev;
1772         struct intel_fbdev *ifbdev = NULL;
1773         struct intel_framebuffer *fb;
1774
1775 #ifdef CONFIG_DRM_I915_FBDEV
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777
1778         ifbdev = dev_priv->fbdev;
1779         fb = to_intel_framebuffer(ifbdev->helper.fb);
1780
1781         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1782                    fb->base.width,
1783                    fb->base.height,
1784                    fb->base.depth,
1785                    fb->base.bits_per_pixel,
1786                    atomic_read(&fb->base.refcount.refcount));
1787         describe_obj(m, fb->obj);
1788         seq_putc(m, '\n');
1789 #endif
1790
1791         mutex_lock(&dev->mode_config.fb_lock);
1792         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1793                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1794                         continue;
1795
1796                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1797                            fb->base.width,
1798                            fb->base.height,
1799                            fb->base.depth,
1800                            fb->base.bits_per_pixel,
1801                            atomic_read(&fb->base.refcount.refcount));
1802                 describe_obj(m, fb->obj);
1803                 seq_putc(m, '\n');
1804         }
1805         mutex_unlock(&dev->mode_config.fb_lock);
1806
1807         return 0;
1808 }
1809
1810 static void describe_ctx_ringbuf(struct seq_file *m,
1811                                  struct intel_ringbuffer *ringbuf)
1812 {
1813         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1814                    ringbuf->space, ringbuf->head, ringbuf->tail,
1815                    ringbuf->last_retired_head);
1816 }
1817
1818 static int i915_context_status(struct seq_file *m, void *unused)
1819 {
1820         struct drm_info_node *node = m->private;
1821         struct drm_device *dev = node->minor->dev;
1822         struct drm_i915_private *dev_priv = dev->dev_private;
1823         struct intel_engine_cs *ring;
1824         struct intel_context *ctx;
1825         int ret, i;
1826
1827         ret = mutex_lock_interruptible(&dev->struct_mutex);
1828         if (ret)
1829                 return ret;
1830
1831         if (dev_priv->ips.pwrctx) {
1832                 seq_puts(m, "power context ");
1833                 describe_obj(m, dev_priv->ips.pwrctx);
1834                 seq_putc(m, '\n');
1835         }
1836
1837         if (dev_priv->ips.renderctx) {
1838                 seq_puts(m, "render context ");
1839                 describe_obj(m, dev_priv->ips.renderctx);
1840                 seq_putc(m, '\n');
1841         }
1842
1843         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1844                 if (!i915.enable_execlists &&
1845                     ctx->legacy_hw_ctx.rcs_state == NULL)
1846                         continue;
1847
1848                 seq_puts(m, "HW context ");
1849                 describe_ctx(m, ctx);
1850                 for_each_ring(ring, dev_priv, i) {
1851                         if (ring->default_context == ctx)
1852                                 seq_printf(m, "(default context %s) ",
1853                                            ring->name);
1854                 }
1855
1856                 if (i915.enable_execlists) {
1857                         seq_putc(m, '\n');
1858                         for_each_ring(ring, dev_priv, i) {
1859                                 struct drm_i915_gem_object *ctx_obj =
1860                                         ctx->engine[i].state;
1861                                 struct intel_ringbuffer *ringbuf =
1862                                         ctx->engine[i].ringbuf;
1863
1864                                 seq_printf(m, "%s: ", ring->name);
1865                                 if (ctx_obj)
1866                                         describe_obj(m, ctx_obj);
1867                                 if (ringbuf)
1868                                         describe_ctx_ringbuf(m, ringbuf);
1869                                 seq_putc(m, '\n');
1870                         }
1871                 } else {
1872                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1873                 }
1874
1875                 seq_putc(m, '\n');
1876         }
1877
1878         mutex_unlock(&dev->struct_mutex);
1879
1880         return 0;
1881 }
1882
1883 static void i915_dump_lrc_obj(struct seq_file *m,
1884                               struct intel_engine_cs *ring,
1885                               struct drm_i915_gem_object *ctx_obj)
1886 {
1887         struct page *page;
1888         uint32_t *reg_state;
1889         int j;
1890         unsigned long ggtt_offset = 0;
1891
1892         if (ctx_obj == NULL) {
1893                 seq_printf(m, "Context on %s with no gem object\n",
1894                            ring->name);
1895                 return;
1896         }
1897
1898         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1899                    intel_execlists_ctx_id(ctx_obj));
1900
1901         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1902                 seq_puts(m, "\tNot bound in GGTT\n");
1903         else
1904                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1905
1906         if (i915_gem_object_get_pages(ctx_obj)) {
1907                 seq_puts(m, "\tFailed to get pages for context object\n");
1908                 return;
1909         }
1910
1911         page = i915_gem_object_get_page(ctx_obj, 1);
1912         if (!WARN_ON(page == NULL)) {
1913                 reg_state = kmap_atomic(page);
1914
1915                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1916                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1917                                    ggtt_offset + 4096 + (j * 4),
1918                                    reg_state[j], reg_state[j + 1],
1919                                    reg_state[j + 2], reg_state[j + 3]);
1920                 }
1921                 kunmap_atomic(reg_state);
1922         }
1923
1924         seq_putc(m, '\n');
1925 }
1926
1927 static int i915_dump_lrc(struct seq_file *m, void *unused)
1928 {
1929         struct drm_info_node *node = (struct drm_info_node *) m->private;
1930         struct drm_device *dev = node->minor->dev;
1931         struct drm_i915_private *dev_priv = dev->dev_private;
1932         struct intel_engine_cs *ring;
1933         struct intel_context *ctx;
1934         int ret, i;
1935
1936         if (!i915.enable_execlists) {
1937                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1938                 return 0;
1939         }
1940
1941         ret = mutex_lock_interruptible(&dev->struct_mutex);
1942         if (ret)
1943                 return ret;
1944
1945         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1946                 for_each_ring(ring, dev_priv, i) {
1947                         if (ring->default_context != ctx)
1948                                 i915_dump_lrc_obj(m, ring,
1949                                                   ctx->engine[i].state);
1950                 }
1951         }
1952
1953         mutex_unlock(&dev->struct_mutex);
1954
1955         return 0;
1956 }
1957
1958 static int i915_execlists(struct seq_file *m, void *data)
1959 {
1960         struct drm_info_node *node = (struct drm_info_node *)m->private;
1961         struct drm_device *dev = node->minor->dev;
1962         struct drm_i915_private *dev_priv = dev->dev_private;
1963         struct intel_engine_cs *ring;
1964         u32 status_pointer;
1965         u8 read_pointer;
1966         u8 write_pointer;
1967         u32 status;
1968         u32 ctx_id;
1969         struct list_head *cursor;
1970         int ring_id, i;
1971         int ret;
1972
1973         if (!i915.enable_execlists) {
1974                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1975                 return 0;
1976         }
1977
1978         ret = mutex_lock_interruptible(&dev->struct_mutex);
1979         if (ret)
1980                 return ret;
1981
1982         intel_runtime_pm_get(dev_priv);
1983
1984         for_each_ring(ring, dev_priv, ring_id) {
1985                 struct drm_i915_gem_request *head_req = NULL;
1986                 int count = 0;
1987                 unsigned long flags;
1988
1989                 seq_printf(m, "%s\n", ring->name);
1990
1991                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1992                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1993                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1994                            status, ctx_id);
1995
1996                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1997                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1998
1999                 read_pointer = ring->next_context_status_buffer;
2000                 write_pointer = status_pointer & 0x07;
2001                 if (read_pointer > write_pointer)
2002                         write_pointer += 6;
2003                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2004                            read_pointer, write_pointer);
2005
2006                 for (i = 0; i < 6; i++) {
2007                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2008                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2009
2010                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2011                                    i, status, ctx_id);
2012                 }
2013
2014                 spin_lock_irqsave(&ring->execlist_lock, flags);
2015                 list_for_each(cursor, &ring->execlist_queue)
2016                         count++;
2017                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2018                                 struct drm_i915_gem_request, execlist_link);
2019                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2020
2021                 seq_printf(m, "\t%d requests in queue\n", count);
2022                 if (head_req) {
2023                         struct drm_i915_gem_object *ctx_obj;
2024
2025                         ctx_obj = head_req->ctx->engine[ring_id].state;
2026                         seq_printf(m, "\tHead request id: %u\n",
2027                                    intel_execlists_ctx_id(ctx_obj));
2028                         seq_printf(m, "\tHead request tail: %u\n",
2029                                    head_req->tail);
2030                 }
2031
2032                 seq_putc(m, '\n');
2033         }
2034
2035         intel_runtime_pm_put(dev_priv);
2036         mutex_unlock(&dev->struct_mutex);
2037
2038         return 0;
2039 }
2040
2041 static const char *swizzle_string(unsigned swizzle)
2042 {
2043         switch (swizzle) {
2044         case I915_BIT_6_SWIZZLE_NONE:
2045                 return "none";
2046         case I915_BIT_6_SWIZZLE_9:
2047                 return "bit9";
2048         case I915_BIT_6_SWIZZLE_9_10:
2049                 return "bit9/bit10";
2050         case I915_BIT_6_SWIZZLE_9_11:
2051                 return "bit9/bit11";
2052         case I915_BIT_6_SWIZZLE_9_10_11:
2053                 return "bit9/bit10/bit11";
2054         case I915_BIT_6_SWIZZLE_9_17:
2055                 return "bit9/bit17";
2056         case I915_BIT_6_SWIZZLE_9_10_17:
2057                 return "bit9/bit10/bit17";
2058         case I915_BIT_6_SWIZZLE_UNKNOWN:
2059                 return "unknown";
2060         }
2061
2062         return "bug";
2063 }
2064
2065 static int i915_swizzle_info(struct seq_file *m, void *data)
2066 {
2067         struct drm_info_node *node = m->private;
2068         struct drm_device *dev = node->minor->dev;
2069         struct drm_i915_private *dev_priv = dev->dev_private;
2070         int ret;
2071
2072         ret = mutex_lock_interruptible(&dev->struct_mutex);
2073         if (ret)
2074                 return ret;
2075         intel_runtime_pm_get(dev_priv);
2076
2077         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2078                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2079         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2080                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2081
2082         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2083                 seq_printf(m, "DDC = 0x%08x\n",
2084                            I915_READ(DCC));
2085                 seq_printf(m, "DDC2 = 0x%08x\n",
2086                            I915_READ(DCC2));
2087                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2088                            I915_READ16(C0DRB3));
2089                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2090                            I915_READ16(C1DRB3));
2091         } else if (INTEL_INFO(dev)->gen >= 6) {
2092                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2093                            I915_READ(MAD_DIMM_C0));
2094                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2095                            I915_READ(MAD_DIMM_C1));
2096                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2097                            I915_READ(MAD_DIMM_C2));
2098                 seq_printf(m, "TILECTL = 0x%08x\n",
2099                            I915_READ(TILECTL));
2100                 if (INTEL_INFO(dev)->gen >= 8)
2101                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2102                                    I915_READ(GAMTARBMODE));
2103                 else
2104                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2105                                    I915_READ(ARB_MODE));
2106                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2107                            I915_READ(DISP_ARB_CTL));
2108         }
2109
2110         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2111                 seq_puts(m, "L-shaped memory detected\n");
2112
2113         intel_runtime_pm_put(dev_priv);
2114         mutex_unlock(&dev->struct_mutex);
2115
2116         return 0;
2117 }
2118
2119 static int per_file_ctx(int id, void *ptr, void *data)
2120 {
2121         struct intel_context *ctx = ptr;
2122         struct seq_file *m = data;
2123         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2124
2125         if (!ppgtt) {
2126                 seq_printf(m, "  no ppgtt for context %d\n",
2127                            ctx->user_handle);
2128                 return 0;
2129         }
2130
2131         if (i915_gem_context_is_default(ctx))
2132                 seq_puts(m, "  default context:\n");
2133         else
2134                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2135         ppgtt->debug_dump(ppgtt, m);
2136
2137         return 0;
2138 }
2139
2140 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2141 {
2142         struct drm_i915_private *dev_priv = dev->dev_private;
2143         struct intel_engine_cs *ring;
2144         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2145         int unused, i;
2146
2147         if (!ppgtt)
2148                 return;
2149
2150         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2151         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2152         for_each_ring(ring, dev_priv, unused) {
2153                 seq_printf(m, "%s\n", ring->name);
2154                 for (i = 0; i < 4; i++) {
2155                         u32 offset = 0x270 + i * 8;
2156                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2157                         pdp <<= 32;
2158                         pdp |= I915_READ(ring->mmio_base + offset);
2159                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2160                 }
2161         }
2162 }
2163
2164 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2165 {
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167         struct intel_engine_cs *ring;
2168         struct drm_file *file;
2169         int i;
2170
2171         if (INTEL_INFO(dev)->gen == 6)
2172                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2173
2174         for_each_ring(ring, dev_priv, i) {
2175                 seq_printf(m, "%s\n", ring->name);
2176                 if (INTEL_INFO(dev)->gen == 7)
2177                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2178                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2179                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2180                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2181         }
2182         if (dev_priv->mm.aliasing_ppgtt) {
2183                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2184
2185                 seq_puts(m, "aliasing PPGTT:\n");
2186                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2187
2188                 ppgtt->debug_dump(ppgtt, m);
2189         }
2190
2191         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2192                 struct drm_i915_file_private *file_priv = file->driver_priv;
2193
2194                 seq_printf(m, "proc: %s\n",
2195                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2196                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2197         }
2198         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2199 }
2200
2201 static int i915_ppgtt_info(struct seq_file *m, void *data)
2202 {
2203         struct drm_info_node *node = m->private;
2204         struct drm_device *dev = node->minor->dev;
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206
2207         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2208         if (ret)
2209                 return ret;
2210         intel_runtime_pm_get(dev_priv);
2211
2212         if (INTEL_INFO(dev)->gen >= 8)
2213                 gen8_ppgtt_info(m, dev);
2214         else if (INTEL_INFO(dev)->gen >= 6)
2215                 gen6_ppgtt_info(m, dev);
2216
2217         intel_runtime_pm_put(dev_priv);
2218         mutex_unlock(&dev->struct_mutex);
2219
2220         return 0;
2221 }
2222
2223 static int i915_llc(struct seq_file *m, void *data)
2224 {
2225         struct drm_info_node *node = m->private;
2226         struct drm_device *dev = node->minor->dev;
2227         struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2230         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2231         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2232
2233         return 0;
2234 }
2235
2236 static int i915_edp_psr_status(struct seq_file *m, void *data)
2237 {
2238         struct drm_info_node *node = m->private;
2239         struct drm_device *dev = node->minor->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         u32 psrperf = 0;
2242         u32 stat[3];
2243         enum pipe pipe;
2244         bool enabled = false;
2245
2246         intel_runtime_pm_get(dev_priv);
2247
2248         mutex_lock(&dev_priv->psr.lock);
2249         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2250         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2251         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2252         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2253         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2254                    dev_priv->psr.busy_frontbuffer_bits);
2255         seq_printf(m, "Re-enable work scheduled: %s\n",
2256                    yesno(work_busy(&dev_priv->psr.work.work)));
2257
2258         if (HAS_PSR(dev)) {
2259                 if (HAS_DDI(dev))
2260                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2261                 else {
2262                         for_each_pipe(dev_priv, pipe) {
2263                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2264                                         VLV_EDP_PSR_CURR_STATE_MASK;
2265                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2266                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2267                                         enabled = true;
2268                         }
2269                 }
2270         }
2271         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2272
2273         if (!HAS_DDI(dev))
2274                 for_each_pipe(dev_priv, pipe) {
2275                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2276                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2277                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2278                 }
2279         seq_puts(m, "\n");
2280
2281         seq_printf(m, "Link standby: %s\n",
2282                    yesno((bool)dev_priv->psr.link_standby));
2283
2284         /* CHV PSR has no kind of performance counter */
2285         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2286                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2287                         EDP_PSR_PERF_CNT_MASK;
2288
2289                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2290         }
2291         mutex_unlock(&dev_priv->psr.lock);
2292
2293         intel_runtime_pm_put(dev_priv);
2294         return 0;
2295 }
2296
2297 static int i915_sink_crc(struct seq_file *m, void *data)
2298 {
2299         struct drm_info_node *node = m->private;
2300         struct drm_device *dev = node->minor->dev;
2301         struct intel_encoder *encoder;
2302         struct intel_connector *connector;
2303         struct intel_dp *intel_dp = NULL;
2304         int ret;
2305         u8 crc[6];
2306
2307         drm_modeset_lock_all(dev);
2308         list_for_each_entry(connector, &dev->mode_config.connector_list,
2309                             base.head) {
2310
2311                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2312                         continue;
2313
2314                 if (!connector->base.encoder)
2315                         continue;
2316
2317                 encoder = to_intel_encoder(connector->base.encoder);
2318                 if (encoder->type != INTEL_OUTPUT_EDP)
2319                         continue;
2320
2321                 intel_dp = enc_to_intel_dp(&encoder->base);
2322
2323                 ret = intel_dp_sink_crc(intel_dp, crc);
2324                 if (ret)
2325                         goto out;
2326
2327                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2328                            crc[0], crc[1], crc[2],
2329                            crc[3], crc[4], crc[5]);
2330                 goto out;
2331         }
2332         ret = -ENODEV;
2333 out:
2334         drm_modeset_unlock_all(dev);
2335         return ret;
2336 }
2337
2338 static int i915_energy_uJ(struct seq_file *m, void *data)
2339 {
2340         struct drm_info_node *node = m->private;
2341         struct drm_device *dev = node->minor->dev;
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         u64 power;
2344         u32 units;
2345
2346         if (INTEL_INFO(dev)->gen < 6)
2347                 return -ENODEV;
2348
2349         intel_runtime_pm_get(dev_priv);
2350
2351         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2352         power = (power & 0x1f00) >> 8;
2353         units = 1000000 / (1 << power); /* convert to uJ */
2354         power = I915_READ(MCH_SECP_NRG_STTS);
2355         power *= units;
2356
2357         intel_runtime_pm_put(dev_priv);
2358
2359         seq_printf(m, "%llu", (long long unsigned)power);
2360
2361         return 0;
2362 }
2363
2364 static int i915_pc8_status(struct seq_file *m, void *unused)
2365 {
2366         struct drm_info_node *node = m->private;
2367         struct drm_device *dev = node->minor->dev;
2368         struct drm_i915_private *dev_priv = dev->dev_private;
2369
2370         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2371                 seq_puts(m, "not supported\n");
2372                 return 0;
2373         }
2374
2375         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2376         seq_printf(m, "IRQs disabled: %s\n",
2377                    yesno(!intel_irqs_enabled(dev_priv)));
2378
2379         return 0;
2380 }
2381
2382 static const char *power_domain_str(enum intel_display_power_domain domain)
2383 {
2384         switch (domain) {
2385         case POWER_DOMAIN_PIPE_A:
2386                 return "PIPE_A";
2387         case POWER_DOMAIN_PIPE_B:
2388                 return "PIPE_B";
2389         case POWER_DOMAIN_PIPE_C:
2390                 return "PIPE_C";
2391         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2392                 return "PIPE_A_PANEL_FITTER";
2393         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2394                 return "PIPE_B_PANEL_FITTER";
2395         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2396                 return "PIPE_C_PANEL_FITTER";
2397         case POWER_DOMAIN_TRANSCODER_A:
2398                 return "TRANSCODER_A";
2399         case POWER_DOMAIN_TRANSCODER_B:
2400                 return "TRANSCODER_B";
2401         case POWER_DOMAIN_TRANSCODER_C:
2402                 return "TRANSCODER_C";
2403         case POWER_DOMAIN_TRANSCODER_EDP:
2404                 return "TRANSCODER_EDP";
2405         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2406                 return "PORT_DDI_A_2_LANES";
2407         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2408                 return "PORT_DDI_A_4_LANES";
2409         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2410                 return "PORT_DDI_B_2_LANES";
2411         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2412                 return "PORT_DDI_B_4_LANES";
2413         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2414                 return "PORT_DDI_C_2_LANES";
2415         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2416                 return "PORT_DDI_C_4_LANES";
2417         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2418                 return "PORT_DDI_D_2_LANES";
2419         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2420                 return "PORT_DDI_D_4_LANES";
2421         case POWER_DOMAIN_PORT_DSI:
2422                 return "PORT_DSI";
2423         case POWER_DOMAIN_PORT_CRT:
2424                 return "PORT_CRT";
2425         case POWER_DOMAIN_PORT_OTHER:
2426                 return "PORT_OTHER";
2427         case POWER_DOMAIN_VGA:
2428                 return "VGA";
2429         case POWER_DOMAIN_AUDIO:
2430                 return "AUDIO";
2431         case POWER_DOMAIN_PLLS:
2432                 return "PLLS";
2433         case POWER_DOMAIN_AUX_A:
2434                 return "AUX_A";
2435         case POWER_DOMAIN_AUX_B:
2436                 return "AUX_B";
2437         case POWER_DOMAIN_AUX_C:
2438                 return "AUX_C";
2439         case POWER_DOMAIN_AUX_D:
2440                 return "AUX_D";
2441         case POWER_DOMAIN_INIT:
2442                 return "INIT";
2443         default:
2444                 MISSING_CASE(domain);
2445                 return "?";
2446         }
2447 }
2448
2449 static int i915_power_domain_info(struct seq_file *m, void *unused)
2450 {
2451         struct drm_info_node *node = m->private;
2452         struct drm_device *dev = node->minor->dev;
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2455         int i;
2456
2457         mutex_lock(&power_domains->lock);
2458
2459         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2460         for (i = 0; i < power_domains->power_well_count; i++) {
2461                 struct i915_power_well *power_well;
2462                 enum intel_display_power_domain power_domain;
2463
2464                 power_well = &power_domains->power_wells[i];
2465                 seq_printf(m, "%-25s %d\n", power_well->name,
2466                            power_well->count);
2467
2468                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2469                      power_domain++) {
2470                         if (!(BIT(power_domain) & power_well->domains))
2471                                 continue;
2472
2473                         seq_printf(m, "  %-23s %d\n",
2474                                  power_domain_str(power_domain),
2475                                  power_domains->domain_use_count[power_domain]);
2476                 }
2477         }
2478
2479         mutex_unlock(&power_domains->lock);
2480
2481         return 0;
2482 }
2483
2484 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2485                                  struct drm_display_mode *mode)
2486 {
2487         int i;
2488
2489         for (i = 0; i < tabs; i++)
2490                 seq_putc(m, '\t');
2491
2492         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2493                    mode->base.id, mode->name,
2494                    mode->vrefresh, mode->clock,
2495                    mode->hdisplay, mode->hsync_start,
2496                    mode->hsync_end, mode->htotal,
2497                    mode->vdisplay, mode->vsync_start,
2498                    mode->vsync_end, mode->vtotal,
2499                    mode->type, mode->flags);
2500 }
2501
2502 static void intel_encoder_info(struct seq_file *m,
2503                                struct intel_crtc *intel_crtc,
2504                                struct intel_encoder *intel_encoder)
2505 {
2506         struct drm_info_node *node = m->private;
2507         struct drm_device *dev = node->minor->dev;
2508         struct drm_crtc *crtc = &intel_crtc->base;
2509         struct intel_connector *intel_connector;
2510         struct drm_encoder *encoder;
2511
2512         encoder = &intel_encoder->base;
2513         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2514                    encoder->base.id, encoder->name);
2515         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2516                 struct drm_connector *connector = &intel_connector->base;
2517                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2518                            connector->base.id,
2519                            connector->name,
2520                            drm_get_connector_status_name(connector->status));
2521                 if (connector->status == connector_status_connected) {
2522                         struct drm_display_mode *mode = &crtc->mode;
2523                         seq_printf(m, ", mode:\n");
2524                         intel_seq_print_mode(m, 2, mode);
2525                 } else {
2526                         seq_putc(m, '\n');
2527                 }
2528         }
2529 }
2530
2531 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2532 {
2533         struct drm_info_node *node = m->private;
2534         struct drm_device *dev = node->minor->dev;
2535         struct drm_crtc *crtc = &intel_crtc->base;
2536         struct intel_encoder *intel_encoder;
2537
2538         if (crtc->primary->fb)
2539                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2540                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2541                            crtc->primary->fb->width, crtc->primary->fb->height);
2542         else
2543                 seq_puts(m, "\tprimary plane disabled\n");
2544         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2545                 intel_encoder_info(m, intel_crtc, intel_encoder);
2546 }
2547
2548 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2549 {
2550         struct drm_display_mode *mode = panel->fixed_mode;
2551
2552         seq_printf(m, "\tfixed mode:\n");
2553         intel_seq_print_mode(m, 2, mode);
2554 }
2555
2556 static void intel_dp_info(struct seq_file *m,
2557                           struct intel_connector *intel_connector)
2558 {
2559         struct intel_encoder *intel_encoder = intel_connector->encoder;
2560         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2561
2562         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2563         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2564                    "no");
2565         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2566                 intel_panel_info(m, &intel_connector->panel);
2567 }
2568
2569 static void intel_hdmi_info(struct seq_file *m,
2570                             struct intel_connector *intel_connector)
2571 {
2572         struct intel_encoder *intel_encoder = intel_connector->encoder;
2573         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2574
2575         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2576                    "no");
2577 }
2578
2579 static void intel_lvds_info(struct seq_file *m,
2580                             struct intel_connector *intel_connector)
2581 {
2582         intel_panel_info(m, &intel_connector->panel);
2583 }
2584
2585 static void intel_connector_info(struct seq_file *m,
2586                                  struct drm_connector *connector)
2587 {
2588         struct intel_connector *intel_connector = to_intel_connector(connector);
2589         struct intel_encoder *intel_encoder = intel_connector->encoder;
2590         struct drm_display_mode *mode;
2591
2592         seq_printf(m, "connector %d: type %s, status: %s\n",
2593                    connector->base.id, connector->name,
2594                    drm_get_connector_status_name(connector->status));
2595         if (connector->status == connector_status_connected) {
2596                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2597                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2598                            connector->display_info.width_mm,
2599                            connector->display_info.height_mm);
2600                 seq_printf(m, "\tsubpixel order: %s\n",
2601                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2602                 seq_printf(m, "\tCEA rev: %d\n",
2603                            connector->display_info.cea_rev);
2604         }
2605         if (intel_encoder) {
2606                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2607                     intel_encoder->type == INTEL_OUTPUT_EDP)
2608                         intel_dp_info(m, intel_connector);
2609                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2610                         intel_hdmi_info(m, intel_connector);
2611                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2612                         intel_lvds_info(m, intel_connector);
2613         }
2614
2615         seq_printf(m, "\tmodes:\n");
2616         list_for_each_entry(mode, &connector->modes, head)
2617                 intel_seq_print_mode(m, 2, mode);
2618 }
2619
2620 static bool cursor_active(struct drm_device *dev, int pipe)
2621 {
2622         struct drm_i915_private *dev_priv = dev->dev_private;
2623         u32 state;
2624
2625         if (IS_845G(dev) || IS_I865G(dev))
2626                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2627         else
2628                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2629
2630         return state;
2631 }
2632
2633 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2634 {
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636         u32 pos;
2637
2638         pos = I915_READ(CURPOS(pipe));
2639
2640         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2641         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2642                 *x = -*x;
2643
2644         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2645         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2646                 *y = -*y;
2647
2648         return cursor_active(dev, pipe);
2649 }
2650
2651 static int i915_display_info(struct seq_file *m, void *unused)
2652 {
2653         struct drm_info_node *node = m->private;
2654         struct drm_device *dev = node->minor->dev;
2655         struct drm_i915_private *dev_priv = dev->dev_private;
2656         struct intel_crtc *crtc;
2657         struct drm_connector *connector;
2658
2659         intel_runtime_pm_get(dev_priv);
2660         drm_modeset_lock_all(dev);
2661         seq_printf(m, "CRTC info\n");
2662         seq_printf(m, "---------\n");
2663         for_each_intel_crtc(dev, crtc) {
2664                 bool active;
2665                 int x, y;
2666
2667                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2668                            crtc->base.base.id, pipe_name(crtc->pipe),
2669                            yesno(crtc->active), crtc->config->pipe_src_w,
2670                            crtc->config->pipe_src_h);
2671                 if (crtc->active) {
2672                         intel_crtc_info(m, crtc);
2673
2674                         active = cursor_position(dev, crtc->pipe, &x, &y);
2675                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2676                                    yesno(crtc->cursor_base),
2677                                    x, y, crtc->cursor_width, crtc->cursor_height,
2678                                    crtc->cursor_addr, yesno(active));
2679                 }
2680
2681                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2682                            yesno(!crtc->cpu_fifo_underrun_disabled),
2683                            yesno(!crtc->pch_fifo_underrun_disabled));
2684         }
2685
2686         seq_printf(m, "\n");
2687         seq_printf(m, "Connector info\n");
2688         seq_printf(m, "--------------\n");
2689         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2690                 intel_connector_info(m, connector);
2691         }
2692         drm_modeset_unlock_all(dev);
2693         intel_runtime_pm_put(dev_priv);
2694
2695         return 0;
2696 }
2697
2698 static int i915_semaphore_status(struct seq_file *m, void *unused)
2699 {
2700         struct drm_info_node *node = (struct drm_info_node *) m->private;
2701         struct drm_device *dev = node->minor->dev;
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_engine_cs *ring;
2704         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2705         int i, j, ret;
2706
2707         if (!i915_semaphore_is_enabled(dev)) {
2708                 seq_puts(m, "Semaphores are disabled\n");
2709                 return 0;
2710         }
2711
2712         ret = mutex_lock_interruptible(&dev->struct_mutex);
2713         if (ret)
2714                 return ret;
2715         intel_runtime_pm_get(dev_priv);
2716
2717         if (IS_BROADWELL(dev)) {
2718                 struct page *page;
2719                 uint64_t *seqno;
2720
2721                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2722
2723                 seqno = (uint64_t *)kmap_atomic(page);
2724                 for_each_ring(ring, dev_priv, i) {
2725                         uint64_t offset;
2726
2727                         seq_printf(m, "%s\n", ring->name);
2728
2729                         seq_puts(m, "  Last signal:");
2730                         for (j = 0; j < num_rings; j++) {
2731                                 offset = i * I915_NUM_RINGS + j;
2732                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2733                                            seqno[offset], offset * 8);
2734                         }
2735                         seq_putc(m, '\n');
2736
2737                         seq_puts(m, "  Last wait:  ");
2738                         for (j = 0; j < num_rings; j++) {
2739                                 offset = i + (j * I915_NUM_RINGS);
2740                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2741                                            seqno[offset], offset * 8);
2742                         }
2743                         seq_putc(m, '\n');
2744
2745                 }
2746                 kunmap_atomic(seqno);
2747         } else {
2748                 seq_puts(m, "  Last signal:");
2749                 for_each_ring(ring, dev_priv, i)
2750                         for (j = 0; j < num_rings; j++)
2751                                 seq_printf(m, "0x%08x\n",
2752                                            I915_READ(ring->semaphore.mbox.signal[j]));
2753                 seq_putc(m, '\n');
2754         }
2755
2756         seq_puts(m, "\nSync seqno:\n");
2757         for_each_ring(ring, dev_priv, i) {
2758                 for (j = 0; j < num_rings; j++) {
2759                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2760                 }
2761                 seq_putc(m, '\n');
2762         }
2763         seq_putc(m, '\n');
2764
2765         intel_runtime_pm_put(dev_priv);
2766         mutex_unlock(&dev->struct_mutex);
2767         return 0;
2768 }
2769
2770 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2771 {
2772         struct drm_info_node *node = (struct drm_info_node *) m->private;
2773         struct drm_device *dev = node->minor->dev;
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         int i;
2776
2777         drm_modeset_lock_all(dev);
2778         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2779                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2780
2781                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2782                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2783                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2784                 seq_printf(m, " tracked hardware state:\n");
2785                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2786                 seq_printf(m, " dpll_md: 0x%08x\n",
2787                            pll->config.hw_state.dpll_md);
2788                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2789                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2790                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2791         }
2792         drm_modeset_unlock_all(dev);
2793
2794         return 0;
2795 }
2796
2797 static int i915_wa_registers(struct seq_file *m, void *unused)
2798 {
2799         int i;
2800         int ret;
2801         struct drm_info_node *node = (struct drm_info_node *) m->private;
2802         struct drm_device *dev = node->minor->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804
2805         ret = mutex_lock_interruptible(&dev->struct_mutex);
2806         if (ret)
2807                 return ret;
2808
2809         intel_runtime_pm_get(dev_priv);
2810
2811         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2812         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2813                 u32 addr, mask, value, read;
2814                 bool ok;
2815
2816                 addr = dev_priv->workarounds.reg[i].addr;
2817                 mask = dev_priv->workarounds.reg[i].mask;
2818                 value = dev_priv->workarounds.reg[i].value;
2819                 read = I915_READ(addr);
2820                 ok = (value & mask) == (read & mask);
2821                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2822                            addr, value, mask, read, ok ? "OK" : "FAIL");
2823         }
2824
2825         intel_runtime_pm_put(dev_priv);
2826         mutex_unlock(&dev->struct_mutex);
2827
2828         return 0;
2829 }
2830
2831 static int i915_ddb_info(struct seq_file *m, void *unused)
2832 {
2833         struct drm_info_node *node = m->private;
2834         struct drm_device *dev = node->minor->dev;
2835         struct drm_i915_private *dev_priv = dev->dev_private;
2836         struct skl_ddb_allocation *ddb;
2837         struct skl_ddb_entry *entry;
2838         enum pipe pipe;
2839         int plane;
2840
2841         if (INTEL_INFO(dev)->gen < 9)
2842                 return 0;
2843
2844         drm_modeset_lock_all(dev);
2845
2846         ddb = &dev_priv->wm.skl_hw.ddb;
2847
2848         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2849
2850         for_each_pipe(dev_priv, pipe) {
2851                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2852
2853                 for_each_plane(pipe, plane) {
2854                         entry = &ddb->plane[pipe][plane];
2855                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2856                                    entry->start, entry->end,
2857                                    skl_ddb_entry_size(entry));
2858                 }
2859
2860                 entry = &ddb->cursor[pipe];
2861                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2862                            entry->end, skl_ddb_entry_size(entry));
2863         }
2864
2865         drm_modeset_unlock_all(dev);
2866
2867         return 0;
2868 }
2869
2870 struct pipe_crc_info {
2871         const char *name;
2872         struct drm_device *dev;
2873         enum pipe pipe;
2874 };
2875
2876 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2877 {
2878         struct drm_info_node *node = (struct drm_info_node *) m->private;
2879         struct drm_device *dev = node->minor->dev;
2880         struct drm_encoder *encoder;
2881         struct intel_encoder *intel_encoder;
2882         struct intel_digital_port *intel_dig_port;
2883         drm_modeset_lock_all(dev);
2884         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2885                 intel_encoder = to_intel_encoder(encoder);
2886                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2887                         continue;
2888                 intel_dig_port = enc_to_dig_port(encoder);
2889                 if (!intel_dig_port->dp.can_mst)
2890                         continue;
2891
2892                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2893         }
2894         drm_modeset_unlock_all(dev);
2895         return 0;
2896 }
2897
2898 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2899 {
2900         struct pipe_crc_info *info = inode->i_private;
2901         struct drm_i915_private *dev_priv = info->dev->dev_private;
2902         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2903
2904         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2905                 return -ENODEV;
2906
2907         spin_lock_irq(&pipe_crc->lock);
2908
2909         if (pipe_crc->opened) {
2910                 spin_unlock_irq(&pipe_crc->lock);
2911                 return -EBUSY; /* already open */
2912         }
2913
2914         pipe_crc->opened = true;
2915         filep->private_data = inode->i_private;
2916
2917         spin_unlock_irq(&pipe_crc->lock);
2918
2919         return 0;
2920 }
2921
2922 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2923 {
2924         struct pipe_crc_info *info = inode->i_private;
2925         struct drm_i915_private *dev_priv = info->dev->dev_private;
2926         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2927
2928         spin_lock_irq(&pipe_crc->lock);
2929         pipe_crc->opened = false;
2930         spin_unlock_irq(&pipe_crc->lock);
2931
2932         return 0;
2933 }
2934
2935 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2936 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2937 /* account for \'0' */
2938 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2939
2940 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2941 {
2942         assert_spin_locked(&pipe_crc->lock);
2943         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2944                         INTEL_PIPE_CRC_ENTRIES_NR);
2945 }
2946
2947 static ssize_t
2948 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2949                    loff_t *pos)
2950 {
2951         struct pipe_crc_info *info = filep->private_data;
2952         struct drm_device *dev = info->dev;
2953         struct drm_i915_private *dev_priv = dev->dev_private;
2954         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2955         char buf[PIPE_CRC_BUFFER_LEN];
2956         int n_entries;
2957         ssize_t bytes_read;
2958
2959         /*
2960          * Don't allow user space to provide buffers not big enough to hold
2961          * a line of data.
2962          */
2963         if (count < PIPE_CRC_LINE_LEN)
2964                 return -EINVAL;
2965
2966         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2967                 return 0;
2968
2969         /* nothing to read */
2970         spin_lock_irq(&pipe_crc->lock);
2971         while (pipe_crc_data_count(pipe_crc) == 0) {
2972                 int ret;
2973
2974                 if (filep->f_flags & O_NONBLOCK) {
2975                         spin_unlock_irq(&pipe_crc->lock);
2976                         return -EAGAIN;
2977                 }
2978
2979                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2980                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2981                 if (ret) {
2982                         spin_unlock_irq(&pipe_crc->lock);
2983                         return ret;
2984                 }
2985         }
2986
2987         /* We now have one or more entries to read */
2988         n_entries = count / PIPE_CRC_LINE_LEN;
2989
2990         bytes_read = 0;
2991         while (n_entries > 0) {
2992                 struct intel_pipe_crc_entry *entry =
2993                         &pipe_crc->entries[pipe_crc->tail];
2994                 int ret;
2995
2996                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2997                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2998                         break;
2999
3000                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3001                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3002
3003                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3004                                        "%8u %8x %8x %8x %8x %8x\n",
3005                                        entry->frame, entry->crc[0],
3006                                        entry->crc[1], entry->crc[2],
3007                                        entry->crc[3], entry->crc[4]);
3008
3009                 spin_unlock_irq(&pipe_crc->lock);
3010
3011                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3012                 if (ret == PIPE_CRC_LINE_LEN)
3013                         return -EFAULT;
3014
3015                 user_buf += PIPE_CRC_LINE_LEN;
3016                 n_entries--;
3017
3018                 spin_lock_irq(&pipe_crc->lock);
3019         }
3020
3021         spin_unlock_irq(&pipe_crc->lock);
3022
3023         return bytes_read;
3024 }
3025
3026 static const struct file_operations i915_pipe_crc_fops = {
3027         .owner = THIS_MODULE,
3028         .open = i915_pipe_crc_open,
3029         .read = i915_pipe_crc_read,
3030         .release = i915_pipe_crc_release,
3031 };
3032
3033 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3034         {
3035                 .name = "i915_pipe_A_crc",
3036                 .pipe = PIPE_A,
3037         },
3038         {
3039                 .name = "i915_pipe_B_crc",
3040                 .pipe = PIPE_B,
3041         },
3042         {
3043                 .name = "i915_pipe_C_crc",
3044                 .pipe = PIPE_C,
3045         },
3046 };
3047
3048 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3049                                 enum pipe pipe)
3050 {
3051         struct drm_device *dev = minor->dev;
3052         struct dentry *ent;
3053         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3054
3055         info->dev = dev;
3056         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3057                                   &i915_pipe_crc_fops);
3058         if (!ent)
3059                 return -ENOMEM;
3060
3061         return drm_add_fake_info_node(minor, ent, info);
3062 }
3063
3064 static const char * const pipe_crc_sources[] = {
3065         "none",
3066         "plane1",
3067         "plane2",
3068         "pf",
3069         "pipe",
3070         "TV",
3071         "DP-B",
3072         "DP-C",
3073         "DP-D",
3074         "auto",
3075 };
3076
3077 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3078 {
3079         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3080         return pipe_crc_sources[source];
3081 }
3082
3083 static int display_crc_ctl_show(struct seq_file *m, void *data)
3084 {
3085         struct drm_device *dev = m->private;
3086         struct drm_i915_private *dev_priv = dev->dev_private;
3087         int i;
3088
3089         for (i = 0; i < I915_MAX_PIPES; i++)
3090                 seq_printf(m, "%c %s\n", pipe_name(i),
3091                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3092
3093         return 0;
3094 }
3095
3096 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3097 {
3098         struct drm_device *dev = inode->i_private;
3099
3100         return single_open(file, display_crc_ctl_show, dev);
3101 }
3102
3103 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3104                                  uint32_t *val)
3105 {
3106         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3107                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3108
3109         switch (*source) {
3110         case INTEL_PIPE_CRC_SOURCE_PIPE:
3111                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3112                 break;
3113         case INTEL_PIPE_CRC_SOURCE_NONE:
3114                 *val = 0;
3115                 break;
3116         default:
3117                 return -EINVAL;
3118         }
3119
3120         return 0;
3121 }
3122
3123 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3124                                      enum intel_pipe_crc_source *source)
3125 {
3126         struct intel_encoder *encoder;
3127         struct intel_crtc *crtc;
3128         struct intel_digital_port *dig_port;
3129         int ret = 0;
3130
3131         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3132
3133         drm_modeset_lock_all(dev);
3134         for_each_intel_encoder(dev, encoder) {
3135                 if (!encoder->base.crtc)
3136                         continue;
3137
3138                 crtc = to_intel_crtc(encoder->base.crtc);
3139
3140                 if (crtc->pipe != pipe)
3141                         continue;
3142
3143                 switch (encoder->type) {
3144                 case INTEL_OUTPUT_TVOUT:
3145                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3146                         break;
3147                 case INTEL_OUTPUT_DISPLAYPORT:
3148                 case INTEL_OUTPUT_EDP:
3149                         dig_port = enc_to_dig_port(&encoder->base);
3150                         switch (dig_port->port) {
3151                         case PORT_B:
3152                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3153                                 break;
3154                         case PORT_C:
3155                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3156                                 break;
3157                         case PORT_D:
3158                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3159                                 break;
3160                         default:
3161                                 WARN(1, "nonexisting DP port %c\n",
3162                                      port_name(dig_port->port));
3163                                 break;
3164                         }
3165                         break;
3166                 default:
3167                         break;
3168                 }
3169         }
3170         drm_modeset_unlock_all(dev);
3171
3172         return ret;
3173 }
3174
3175 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3176                                 enum pipe pipe,
3177                                 enum intel_pipe_crc_source *source,
3178                                 uint32_t *val)
3179 {
3180         struct drm_i915_private *dev_priv = dev->dev_private;
3181         bool need_stable_symbols = false;
3182
3183         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3184                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3185                 if (ret)
3186                         return ret;
3187         }
3188
3189         switch (*source) {
3190         case INTEL_PIPE_CRC_SOURCE_PIPE:
3191                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3192                 break;
3193         case INTEL_PIPE_CRC_SOURCE_DP_B:
3194                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3195                 need_stable_symbols = true;
3196                 break;
3197         case INTEL_PIPE_CRC_SOURCE_DP_C:
3198                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3199                 need_stable_symbols = true;
3200                 break;
3201         case INTEL_PIPE_CRC_SOURCE_DP_D:
3202                 if (!IS_CHERRYVIEW(dev))
3203                         return -EINVAL;
3204                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3205                 need_stable_symbols = true;
3206                 break;
3207         case INTEL_PIPE_CRC_SOURCE_NONE:
3208                 *val = 0;
3209                 break;
3210         default:
3211                 return -EINVAL;
3212         }
3213
3214         /*
3215          * When the pipe CRC tap point is after the transcoders we need
3216          * to tweak symbol-level features to produce a deterministic series of
3217          * symbols for a given frame. We need to reset those features only once
3218          * a frame (instead of every nth symbol):
3219          *   - DC-balance: used to ensure a better clock recovery from the data
3220          *     link (SDVO)
3221          *   - DisplayPort scrambling: used for EMI reduction
3222          */
3223         if (need_stable_symbols) {
3224                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3225
3226                 tmp |= DC_BALANCE_RESET_VLV;
3227                 switch (pipe) {
3228                 case PIPE_A:
3229                         tmp |= PIPE_A_SCRAMBLE_RESET;
3230                         break;
3231                 case PIPE_B:
3232                         tmp |= PIPE_B_SCRAMBLE_RESET;
3233                         break;
3234                 case PIPE_C:
3235                         tmp |= PIPE_C_SCRAMBLE_RESET;
3236                         break;
3237                 default:
3238                         return -EINVAL;
3239                 }
3240                 I915_WRITE(PORT_DFT2_G4X, tmp);
3241         }
3242
3243         return 0;
3244 }
3245
3246 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3247                                  enum pipe pipe,
3248                                  enum intel_pipe_crc_source *source,
3249                                  uint32_t *val)
3250 {
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252         bool need_stable_symbols = false;
3253
3254         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3255                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3256                 if (ret)
3257                         return ret;
3258         }
3259
3260         switch (*source) {
3261         case INTEL_PIPE_CRC_SOURCE_PIPE:
3262                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3263                 break;
3264         case INTEL_PIPE_CRC_SOURCE_TV:
3265                 if (!SUPPORTS_TV(dev))
3266                         return -EINVAL;
3267                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3268                 break;
3269         case INTEL_PIPE_CRC_SOURCE_DP_B:
3270                 if (!IS_G4X(dev))
3271                         return -EINVAL;
3272                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3273                 need_stable_symbols = true;
3274                 break;
3275         case INTEL_PIPE_CRC_SOURCE_DP_C:
3276                 if (!IS_G4X(dev))
3277                         return -EINVAL;
3278                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3279                 need_stable_symbols = true;
3280                 break;
3281         case INTEL_PIPE_CRC_SOURCE_DP_D:
3282                 if (!IS_G4X(dev))
3283                         return -EINVAL;
3284                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3285                 need_stable_symbols = true;
3286                 break;
3287         case INTEL_PIPE_CRC_SOURCE_NONE:
3288                 *val = 0;
3289                 break;
3290         default:
3291                 return -EINVAL;
3292         }
3293
3294         /*
3295          * When the pipe CRC tap point is after the transcoders we need
3296          * to tweak symbol-level features to produce a deterministic series of
3297          * symbols for a given frame. We need to reset those features only once
3298          * a frame (instead of every nth symbol):
3299          *   - DC-balance: used to ensure a better clock recovery from the data
3300          *     link (SDVO)
3301          *   - DisplayPort scrambling: used for EMI reduction
3302          */
3303         if (need_stable_symbols) {
3304                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3305
3306                 WARN_ON(!IS_G4X(dev));
3307
3308                 I915_WRITE(PORT_DFT_I9XX,
3309                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3310
3311                 if (pipe == PIPE_A)
3312                         tmp |= PIPE_A_SCRAMBLE_RESET;
3313                 else
3314                         tmp |= PIPE_B_SCRAMBLE_RESET;
3315
3316                 I915_WRITE(PORT_DFT2_G4X, tmp);
3317         }
3318
3319         return 0;
3320 }
3321
3322 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3323                                          enum pipe pipe)
3324 {
3325         struct drm_i915_private *dev_priv = dev->dev_private;
3326         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3327
3328         switch (pipe) {
3329         case PIPE_A:
3330                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3331                 break;
3332         case PIPE_B:
3333                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3334                 break;
3335         case PIPE_C:
3336                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3337                 break;
3338         default:
3339                 return;
3340         }
3341         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3342                 tmp &= ~DC_BALANCE_RESET_VLV;
3343         I915_WRITE(PORT_DFT2_G4X, tmp);
3344
3345 }
3346
3347 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3348                                          enum pipe pipe)
3349 {
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3352
3353         if (pipe == PIPE_A)
3354                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3355         else
3356                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3357         I915_WRITE(PORT_DFT2_G4X, tmp);
3358
3359         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3360                 I915_WRITE(PORT_DFT_I9XX,
3361                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3362         }
3363 }
3364
3365 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3366                                 uint32_t *val)
3367 {
3368         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3369                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3370
3371         switch (*source) {
3372         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3373                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3374                 break;
3375         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3376                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3377                 break;
3378         case INTEL_PIPE_CRC_SOURCE_PIPE:
3379                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3380                 break;
3381         case INTEL_PIPE_CRC_SOURCE_NONE:
3382                 *val = 0;
3383                 break;
3384         default:
3385                 return -EINVAL;
3386         }
3387
3388         return 0;
3389 }
3390
3391 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3392 {
3393         struct drm_i915_private *dev_priv = dev->dev_private;
3394         struct intel_crtc *crtc =
3395                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3396
3397         drm_modeset_lock_all(dev);
3398         /*
3399          * If we use the eDP transcoder we need to make sure that we don't
3400          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3401          * relevant on hsw with pipe A when using the always-on power well
3402          * routing.
3403          */
3404         if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3405             !crtc->config->pch_pfit.enabled) {
3406                 crtc->config->pch_pfit.force_thru = true;
3407
3408                 intel_display_power_get(dev_priv,
3409                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3410
3411                 dev_priv->display.crtc_disable(&crtc->base);
3412                 dev_priv->display.crtc_enable(&crtc->base);
3413         }
3414         drm_modeset_unlock_all(dev);
3415 }
3416
3417 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3418 {
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         struct intel_crtc *crtc =
3421                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3422
3423         drm_modeset_lock_all(dev);
3424         /*
3425          * If we use the eDP transcoder we need to make sure that we don't
3426          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3427          * relevant on hsw with pipe A when using the always-on power well
3428          * routing.
3429          */
3430         if (crtc->config->pch_pfit.force_thru) {
3431                 crtc->config->pch_pfit.force_thru = false;
3432
3433                 dev_priv->display.crtc_disable(&crtc->base);
3434                 dev_priv->display.crtc_enable(&crtc->base);
3435
3436                 intel_display_power_put(dev_priv,
3437                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3438         }
3439         drm_modeset_unlock_all(dev);
3440 }
3441
3442 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3443                                 enum pipe pipe,
3444                                 enum intel_pipe_crc_source *source,
3445                                 uint32_t *val)
3446 {
3447         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3448                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3449
3450         switch (*source) {
3451         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3452                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3453                 break;
3454         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3455                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3456                 break;
3457         case INTEL_PIPE_CRC_SOURCE_PF:
3458                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3459                         hsw_trans_edp_pipe_A_crc_wa(dev);
3460
3461                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3462                 break;
3463         case INTEL_PIPE_CRC_SOURCE_NONE:
3464                 *val = 0;
3465                 break;
3466         default:
3467                 return -EINVAL;
3468         }
3469
3470         return 0;
3471 }
3472
3473 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3474                                enum intel_pipe_crc_source source)
3475 {
3476         struct drm_i915_private *dev_priv = dev->dev_private;
3477         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3478         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3479                                                                         pipe));
3480         u32 val = 0; /* shut up gcc */
3481         int ret;
3482
3483         if (pipe_crc->source == source)
3484                 return 0;
3485
3486         /* forbid changing the source without going back to 'none' */
3487         if (pipe_crc->source && source)
3488                 return -EINVAL;
3489
3490         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3491                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3492                 return -EIO;
3493         }
3494
3495         if (IS_GEN2(dev))
3496                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3497         else if (INTEL_INFO(dev)->gen < 5)
3498                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3499         else if (IS_VALLEYVIEW(dev))
3500                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3501         else if (IS_GEN5(dev) || IS_GEN6(dev))
3502                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3503         else
3504                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3505
3506         if (ret != 0)
3507                 return ret;
3508
3509         /* none -> real source transition */
3510         if (source) {
3511                 struct intel_pipe_crc_entry *entries;
3512
3513                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3514                                  pipe_name(pipe), pipe_crc_source_name(source));
3515
3516                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3517                                   sizeof(pipe_crc->entries[0]),
3518                                   GFP_KERNEL);
3519                 if (!entries)
3520                         return -ENOMEM;
3521
3522                 /*
3523                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3524                  * enabled and disabled dynamically based on package C states,
3525                  * user space can't make reliable use of the CRCs, so let's just
3526                  * completely disable it.
3527                  */
3528                 hsw_disable_ips(crtc);
3529
3530                 spin_lock_irq(&pipe_crc->lock);
3531                 kfree(pipe_crc->entries);
3532                 pipe_crc->entries = entries;
3533                 pipe_crc->head = 0;
3534                 pipe_crc->tail = 0;
3535                 spin_unlock_irq(&pipe_crc->lock);
3536         }
3537
3538         pipe_crc->source = source;
3539
3540         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3541         POSTING_READ(PIPE_CRC_CTL(pipe));
3542
3543         /* real source -> none transition */
3544         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3545                 struct intel_pipe_crc_entry *entries;
3546                 struct intel_crtc *crtc =
3547                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3548
3549                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3550                                  pipe_name(pipe));
3551
3552                 drm_modeset_lock(&crtc->base.mutex, NULL);
3553                 if (crtc->active)
3554                         intel_wait_for_vblank(dev, pipe);
3555                 drm_modeset_unlock(&crtc->base.mutex);
3556
3557                 spin_lock_irq(&pipe_crc->lock);
3558                 entries = pipe_crc->entries;
3559                 pipe_crc->entries = NULL;
3560                 pipe_crc->head = 0;
3561                 pipe_crc->tail = 0;
3562                 spin_unlock_irq(&pipe_crc->lock);
3563
3564                 kfree(entries);
3565
3566                 if (IS_G4X(dev))
3567                         g4x_undo_pipe_scramble_reset(dev, pipe);
3568                 else if (IS_VALLEYVIEW(dev))
3569                         vlv_undo_pipe_scramble_reset(dev, pipe);
3570                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3571                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3572
3573                 hsw_enable_ips(crtc);
3574         }
3575
3576         return 0;
3577 }
3578
3579 /*
3580  * Parse pipe CRC command strings:
3581  *   command: wsp* object wsp+ name wsp+ source wsp*
3582  *   object: 'pipe'
3583  *   name: (A | B | C)
3584  *   source: (none | plane1 | plane2 | pf)
3585  *   wsp: (#0x20 | #0x9 | #0xA)+
3586  *
3587  * eg.:
3588  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3589  *  "pipe A none"    ->  Stop CRC
3590  */
3591 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3592 {
3593         int n_words = 0;
3594
3595         while (*buf) {
3596                 char *end;
3597
3598                 /* skip leading white space */
3599                 buf = skip_spaces(buf);
3600                 if (!*buf)
3601                         break;  /* end of buffer */
3602
3603                 /* find end of word */
3604                 for (end = buf; *end && !isspace(*end); end++)
3605                         ;
3606
3607                 if (n_words == max_words) {
3608                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3609                                          max_words);
3610                         return -EINVAL; /* ran out of words[] before bytes */
3611                 }
3612
3613                 if (*end)
3614                         *end++ = '\0';
3615                 words[n_words++] = buf;
3616                 buf = end;
3617         }
3618
3619         return n_words;
3620 }
3621
3622 enum intel_pipe_crc_object {
3623         PIPE_CRC_OBJECT_PIPE,
3624 };
3625
3626 static const char * const pipe_crc_objects[] = {
3627         "pipe",
3628 };
3629
3630 static int
3631 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3632 {
3633         int i;
3634
3635         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3636                 if (!strcmp(buf, pipe_crc_objects[i])) {
3637                         *o = i;
3638                         return 0;
3639                     }
3640
3641         return -EINVAL;
3642 }
3643
3644 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3645 {
3646         const char name = buf[0];
3647
3648         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3649                 return -EINVAL;
3650
3651         *pipe = name - 'A';
3652
3653         return 0;
3654 }
3655
3656 static int
3657 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3658 {
3659         int i;
3660
3661         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3662                 if (!strcmp(buf, pipe_crc_sources[i])) {
3663                         *s = i;
3664                         return 0;
3665                     }
3666
3667         return -EINVAL;
3668 }
3669
3670 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3671 {
3672 #define N_WORDS 3
3673         int n_words;
3674         char *words[N_WORDS];
3675         enum pipe pipe;
3676         enum intel_pipe_crc_object object;
3677         enum intel_pipe_crc_source source;
3678
3679         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3680         if (n_words != N_WORDS) {
3681                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3682                                  N_WORDS);
3683                 return -EINVAL;
3684         }
3685
3686         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3687                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3688                 return -EINVAL;
3689         }
3690
3691         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3692                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3693                 return -EINVAL;
3694         }
3695
3696         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3697                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3698                 return -EINVAL;
3699         }
3700
3701         return pipe_crc_set_source(dev, pipe, source);
3702 }
3703
3704 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3705                                      size_t len, loff_t *offp)
3706 {
3707         struct seq_file *m = file->private_data;
3708         struct drm_device *dev = m->private;
3709         char *tmpbuf;
3710         int ret;
3711
3712         if (len == 0)
3713                 return 0;
3714
3715         if (len > PAGE_SIZE - 1) {
3716                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3717                                  PAGE_SIZE);
3718                 return -E2BIG;
3719         }
3720
3721         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3722         if (!tmpbuf)
3723                 return -ENOMEM;
3724
3725         if (copy_from_user(tmpbuf, ubuf, len)) {
3726                 ret = -EFAULT;
3727                 goto out;
3728         }
3729         tmpbuf[len] = '\0';
3730
3731         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3732
3733 out:
3734         kfree(tmpbuf);
3735         if (ret < 0)
3736                 return ret;
3737
3738         *offp += len;
3739         return len;
3740 }
3741
3742 static const struct file_operations i915_display_crc_ctl_fops = {
3743         .owner = THIS_MODULE,
3744         .open = display_crc_ctl_open,
3745         .read = seq_read,
3746         .llseek = seq_lseek,
3747         .release = single_release,
3748         .write = display_crc_ctl_write
3749 };
3750
3751 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3752 {
3753         struct drm_device *dev = m->private;
3754         int num_levels = ilk_wm_max_level(dev) + 1;
3755         int level;
3756
3757         drm_modeset_lock_all(dev);
3758
3759         for (level = 0; level < num_levels; level++) {
3760                 unsigned int latency = wm[level];
3761
3762                 /*
3763                  * - WM1+ latency values in 0.5us units
3764                  * - latencies are in us on gen9
3765                  */
3766                 if (INTEL_INFO(dev)->gen >= 9)
3767                         latency *= 10;
3768                 else if (level > 0)
3769                         latency *= 5;
3770
3771                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3772                            level, wm[level], latency / 10, latency % 10);
3773         }
3774
3775         drm_modeset_unlock_all(dev);
3776 }
3777
3778 static int pri_wm_latency_show(struct seq_file *m, void *data)
3779 {
3780         struct drm_device *dev = m->private;
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         const uint16_t *latencies;
3783
3784         if (INTEL_INFO(dev)->gen >= 9)
3785                 latencies = dev_priv->wm.skl_latency;
3786         else
3787                 latencies = to_i915(dev)->wm.pri_latency;
3788
3789         wm_latency_show(m, latencies);
3790
3791         return 0;
3792 }
3793
3794 static int spr_wm_latency_show(struct seq_file *m, void *data)
3795 {
3796         struct drm_device *dev = m->private;
3797         struct drm_i915_private *dev_priv = dev->dev_private;
3798         const uint16_t *latencies;
3799
3800         if (INTEL_INFO(dev)->gen >= 9)
3801                 latencies = dev_priv->wm.skl_latency;
3802         else
3803                 latencies = to_i915(dev)->wm.spr_latency;
3804
3805         wm_latency_show(m, latencies);
3806
3807         return 0;
3808 }
3809
3810 static int cur_wm_latency_show(struct seq_file *m, void *data)
3811 {
3812         struct drm_device *dev = m->private;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         const uint16_t *latencies;
3815
3816         if (INTEL_INFO(dev)->gen >= 9)
3817                 latencies = dev_priv->wm.skl_latency;
3818         else
3819                 latencies = to_i915(dev)->wm.cur_latency;
3820
3821         wm_latency_show(m, latencies);
3822
3823         return 0;
3824 }
3825
3826 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3827 {
3828         struct drm_device *dev = inode->i_private;
3829
3830         if (HAS_GMCH_DISPLAY(dev))
3831                 return -ENODEV;
3832
3833         return single_open(file, pri_wm_latency_show, dev);
3834 }
3835
3836 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3837 {
3838         struct drm_device *dev = inode->i_private;
3839
3840         if (HAS_GMCH_DISPLAY(dev))
3841                 return -ENODEV;
3842
3843         return single_open(file, spr_wm_latency_show, dev);
3844 }
3845
3846 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3847 {
3848         struct drm_device *dev = inode->i_private;
3849
3850         if (HAS_GMCH_DISPLAY(dev))
3851                 return -ENODEV;
3852
3853         return single_open(file, cur_wm_latency_show, dev);
3854 }
3855
3856 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3857                                 size_t len, loff_t *offp, uint16_t wm[8])
3858 {
3859         struct seq_file *m = file->private_data;
3860         struct drm_device *dev = m->private;
3861         uint16_t new[8] = { 0 };
3862         int num_levels = ilk_wm_max_level(dev) + 1;
3863         int level;
3864         int ret;
3865         char tmp[32];
3866
3867         if (len >= sizeof(tmp))
3868                 return -EINVAL;
3869
3870         if (copy_from_user(tmp, ubuf, len))
3871                 return -EFAULT;
3872
3873         tmp[len] = '\0';
3874
3875         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3876                      &new[0], &new[1], &new[2], &new[3],
3877                      &new[4], &new[5], &new[6], &new[7]);
3878         if (ret != num_levels)
3879                 return -EINVAL;
3880
3881         drm_modeset_lock_all(dev);
3882
3883         for (level = 0; level < num_levels; level++)
3884                 wm[level] = new[level];
3885
3886         drm_modeset_unlock_all(dev);
3887
3888         return len;
3889 }
3890
3891
3892 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3893                                     size_t len, loff_t *offp)
3894 {
3895         struct seq_file *m = file->private_data;
3896         struct drm_device *dev = m->private;
3897         struct drm_i915_private *dev_priv = dev->dev_private;
3898         uint16_t *latencies;
3899
3900         if (INTEL_INFO(dev)->gen >= 9)
3901                 latencies = dev_priv->wm.skl_latency;
3902         else
3903                 latencies = to_i915(dev)->wm.pri_latency;
3904
3905         return wm_latency_write(file, ubuf, len, offp, latencies);
3906 }
3907
3908 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3909                                     size_t len, loff_t *offp)
3910 {
3911         struct seq_file *m = file->private_data;
3912         struct drm_device *dev = m->private;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         uint16_t *latencies;
3915
3916         if (INTEL_INFO(dev)->gen >= 9)
3917                 latencies = dev_priv->wm.skl_latency;
3918         else
3919                 latencies = to_i915(dev)->wm.spr_latency;
3920
3921         return wm_latency_write(file, ubuf, len, offp, latencies);
3922 }
3923
3924 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3925                                     size_t len, loff_t *offp)
3926 {
3927         struct seq_file *m = file->private_data;
3928         struct drm_device *dev = m->private;
3929         struct drm_i915_private *dev_priv = dev->dev_private;
3930         uint16_t *latencies;
3931
3932         if (INTEL_INFO(dev)->gen >= 9)
3933                 latencies = dev_priv->wm.skl_latency;
3934         else
3935                 latencies = to_i915(dev)->wm.cur_latency;
3936
3937         return wm_latency_write(file, ubuf, len, offp, latencies);
3938 }
3939
3940 static const struct file_operations i915_pri_wm_latency_fops = {
3941         .owner = THIS_MODULE,
3942         .open = pri_wm_latency_open,
3943         .read = seq_read,
3944         .llseek = seq_lseek,
3945         .release = single_release,
3946         .write = pri_wm_latency_write
3947 };
3948
3949 static const struct file_operations i915_spr_wm_latency_fops = {
3950         .owner = THIS_MODULE,
3951         .open = spr_wm_latency_open,
3952         .read = seq_read,
3953         .llseek = seq_lseek,
3954         .release = single_release,
3955         .write = spr_wm_latency_write
3956 };
3957
3958 static const struct file_operations i915_cur_wm_latency_fops = {
3959         .owner = THIS_MODULE,
3960         .open = cur_wm_latency_open,
3961         .read = seq_read,
3962         .llseek = seq_lseek,
3963         .release = single_release,
3964         .write = cur_wm_latency_write
3965 };
3966
3967 static int
3968 i915_wedged_get(void *data, u64 *val)
3969 {
3970         struct drm_device *dev = data;
3971         struct drm_i915_private *dev_priv = dev->dev_private;
3972
3973         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3974
3975         return 0;
3976 }
3977
3978 static int
3979 i915_wedged_set(void *data, u64 val)
3980 {
3981         struct drm_device *dev = data;
3982         struct drm_i915_private *dev_priv = dev->dev_private;
3983
3984         /*
3985          * There is no safeguard against this debugfs entry colliding
3986          * with the hangcheck calling same i915_handle_error() in
3987          * parallel, causing an explosion. For now we assume that the
3988          * test harness is responsible enough not to inject gpu hangs
3989          * while it is writing to 'i915_wedged'
3990          */
3991
3992         if (i915_reset_in_progress(&dev_priv->gpu_error))
3993                 return -EAGAIN;
3994
3995         intel_runtime_pm_get(dev_priv);
3996
3997         i915_handle_error(dev, val,
3998                           "Manually setting wedged to %llu", val);
3999
4000         intel_runtime_pm_put(dev_priv);
4001
4002         return 0;
4003 }
4004
4005 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4006                         i915_wedged_get, i915_wedged_set,
4007                         "%llu\n");
4008
4009 static int
4010 i915_ring_stop_get(void *data, u64 *val)
4011 {
4012         struct drm_device *dev = data;
4013         struct drm_i915_private *dev_priv = dev->dev_private;
4014
4015         *val = dev_priv->gpu_error.stop_rings;
4016
4017         return 0;
4018 }
4019
4020 static int
4021 i915_ring_stop_set(void *data, u64 val)
4022 {
4023         struct drm_device *dev = data;
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         int ret;
4026
4027         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4028
4029         ret = mutex_lock_interruptible(&dev->struct_mutex);
4030         if (ret)
4031                 return ret;
4032
4033         dev_priv->gpu_error.stop_rings = val;
4034         mutex_unlock(&dev->struct_mutex);
4035
4036         return 0;
4037 }
4038
4039 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4040                         i915_ring_stop_get, i915_ring_stop_set,
4041                         "0x%08llx\n");
4042
4043 static int
4044 i915_ring_missed_irq_get(void *data, u64 *val)
4045 {
4046         struct drm_device *dev = data;
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048
4049         *val = dev_priv->gpu_error.missed_irq_rings;
4050         return 0;
4051 }
4052
4053 static int
4054 i915_ring_missed_irq_set(void *data, u64 val)
4055 {
4056         struct drm_device *dev = data;
4057         struct drm_i915_private *dev_priv = dev->dev_private;
4058         int ret;
4059
4060         /* Lock against concurrent debugfs callers */
4061         ret = mutex_lock_interruptible(&dev->struct_mutex);
4062         if (ret)
4063                 return ret;
4064         dev_priv->gpu_error.missed_irq_rings = val;
4065         mutex_unlock(&dev->struct_mutex);
4066
4067         return 0;
4068 }
4069
4070 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4071                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4072                         "0x%08llx\n");
4073
4074 static int
4075 i915_ring_test_irq_get(void *data, u64 *val)
4076 {
4077         struct drm_device *dev = data;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079
4080         *val = dev_priv->gpu_error.test_irq_rings;
4081
4082         return 0;
4083 }
4084
4085 static int
4086 i915_ring_test_irq_set(void *data, u64 val)
4087 {
4088         struct drm_device *dev = data;
4089         struct drm_i915_private *dev_priv = dev->dev_private;
4090         int ret;
4091
4092         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4093
4094         /* Lock against concurrent debugfs callers */
4095         ret = mutex_lock_interruptible(&dev->struct_mutex);
4096         if (ret)
4097                 return ret;
4098
4099         dev_priv->gpu_error.test_irq_rings = val;
4100         mutex_unlock(&dev->struct_mutex);
4101
4102         return 0;
4103 }
4104
4105 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4106                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4107                         "0x%08llx\n");
4108
4109 #define DROP_UNBOUND 0x1
4110 #define DROP_BOUND 0x2
4111 #define DROP_RETIRE 0x4
4112 #define DROP_ACTIVE 0x8
4113 #define DROP_ALL (DROP_UNBOUND | \
4114                   DROP_BOUND | \
4115                   DROP_RETIRE | \
4116                   DROP_ACTIVE)
4117 static int
4118 i915_drop_caches_get(void *data, u64 *val)
4119 {
4120         *val = DROP_ALL;
4121
4122         return 0;
4123 }
4124
4125 static int
4126 i915_drop_caches_set(void *data, u64 val)
4127 {
4128         struct drm_device *dev = data;
4129         struct drm_i915_private *dev_priv = dev->dev_private;
4130         int ret;
4131
4132         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4133
4134         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4135          * on ioctls on -EAGAIN. */
4136         ret = mutex_lock_interruptible(&dev->struct_mutex);
4137         if (ret)
4138                 return ret;
4139
4140         if (val & DROP_ACTIVE) {
4141                 ret = i915_gpu_idle(dev);
4142                 if (ret)
4143                         goto unlock;
4144         }
4145
4146         if (val & (DROP_RETIRE | DROP_ACTIVE))
4147                 i915_gem_retire_requests(dev);
4148
4149         if (val & DROP_BOUND)
4150                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4151
4152         if (val & DROP_UNBOUND)
4153                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4154
4155 unlock:
4156         mutex_unlock(&dev->struct_mutex);
4157
4158         return ret;
4159 }
4160
4161 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4162                         i915_drop_caches_get, i915_drop_caches_set,
4163                         "0x%08llx\n");
4164
4165 static int
4166 i915_max_freq_get(void *data, u64 *val)
4167 {
4168         struct drm_device *dev = data;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         int ret;
4171
4172         if (INTEL_INFO(dev)->gen < 6)
4173                 return -ENODEV;
4174
4175         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4176
4177         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4178         if (ret)
4179                 return ret;
4180
4181         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4182         mutex_unlock(&dev_priv->rps.hw_lock);
4183
4184         return 0;
4185 }
4186
4187 static int
4188 i915_max_freq_set(void *data, u64 val)
4189 {
4190         struct drm_device *dev = data;
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         u32 rp_state_cap, hw_max, hw_min;
4193         int ret;
4194
4195         if (INTEL_INFO(dev)->gen < 6)
4196                 return -ENODEV;
4197
4198         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4199
4200         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4201
4202         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4203         if (ret)
4204                 return ret;
4205
4206         /*
4207          * Turbo will still be enabled, but won't go above the set value.
4208          */
4209         if (IS_VALLEYVIEW(dev)) {
4210                 val = intel_freq_opcode(dev_priv, val);
4211
4212                 hw_max = dev_priv->rps.max_freq;
4213                 hw_min = dev_priv->rps.min_freq;
4214         } else {
4215                 val = intel_freq_opcode(dev_priv, val);
4216
4217                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4218                 hw_max = dev_priv->rps.max_freq;
4219                 hw_min = (rp_state_cap >> 16) & 0xff;
4220         }
4221
4222         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4223                 mutex_unlock(&dev_priv->rps.hw_lock);
4224                 return -EINVAL;
4225         }
4226
4227         dev_priv->rps.max_freq_softlimit = val;
4228
4229         if (IS_VALLEYVIEW(dev))
4230                 valleyview_set_rps(dev, val);
4231         else
4232                 gen6_set_rps(dev, val);
4233
4234         mutex_unlock(&dev_priv->rps.hw_lock);
4235
4236         return 0;
4237 }
4238
4239 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4240                         i915_max_freq_get, i915_max_freq_set,
4241                         "%llu\n");
4242
4243 static int
4244 i915_min_freq_get(void *data, u64 *val)
4245 {
4246         struct drm_device *dev = data;
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         int ret;
4249
4250         if (INTEL_INFO(dev)->gen < 6)
4251                 return -ENODEV;
4252
4253         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4254
4255         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4256         if (ret)
4257                 return ret;
4258
4259         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4260         mutex_unlock(&dev_priv->rps.hw_lock);
4261
4262         return 0;
4263 }
4264
4265 static int
4266 i915_min_freq_set(void *data, u64 val)
4267 {
4268         struct drm_device *dev = data;
4269         struct drm_i915_private *dev_priv = dev->dev_private;
4270         u32 rp_state_cap, hw_max, hw_min;
4271         int ret;
4272
4273         if (INTEL_INFO(dev)->gen < 6)
4274                 return -ENODEV;
4275
4276         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4277
4278         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4279
4280         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4281         if (ret)
4282                 return ret;
4283
4284         /*
4285          * Turbo will still be enabled, but won't go below the set value.
4286          */
4287         if (IS_VALLEYVIEW(dev)) {
4288                 val = intel_freq_opcode(dev_priv, val);
4289
4290                 hw_max = dev_priv->rps.max_freq;
4291                 hw_min = dev_priv->rps.min_freq;
4292         } else {
4293                 val = intel_freq_opcode(dev_priv, val);
4294
4295                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4296                 hw_max = dev_priv->rps.max_freq;
4297                 hw_min = (rp_state_cap >> 16) & 0xff;
4298         }
4299
4300         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4301                 mutex_unlock(&dev_priv->rps.hw_lock);
4302                 return -EINVAL;
4303         }
4304
4305         dev_priv->rps.min_freq_softlimit = val;
4306
4307         if (IS_VALLEYVIEW(dev))
4308                 valleyview_set_rps(dev, val);
4309         else
4310                 gen6_set_rps(dev, val);
4311
4312         mutex_unlock(&dev_priv->rps.hw_lock);
4313
4314         return 0;
4315 }
4316
4317 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4318                         i915_min_freq_get, i915_min_freq_set,
4319                         "%llu\n");
4320
4321 static int
4322 i915_cache_sharing_get(void *data, u64 *val)
4323 {
4324         struct drm_device *dev = data;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         u32 snpcr;
4327         int ret;
4328
4329         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4330                 return -ENODEV;
4331
4332         ret = mutex_lock_interruptible(&dev->struct_mutex);
4333         if (ret)
4334                 return ret;
4335         intel_runtime_pm_get(dev_priv);
4336
4337         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4338
4339         intel_runtime_pm_put(dev_priv);
4340         mutex_unlock(&dev_priv->dev->struct_mutex);
4341
4342         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4343
4344         return 0;
4345 }
4346
4347 static int
4348 i915_cache_sharing_set(void *data, u64 val)
4349 {
4350         struct drm_device *dev = data;
4351         struct drm_i915_private *dev_priv = dev->dev_private;
4352         u32 snpcr;
4353
4354         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4355                 return -ENODEV;
4356
4357         if (val > 3)
4358                 return -EINVAL;
4359
4360         intel_runtime_pm_get(dev_priv);
4361         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4362
4363         /* Update the cache sharing policy here as well */
4364         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4365         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4366         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4367         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4368
4369         intel_runtime_pm_put(dev_priv);
4370         return 0;
4371 }
4372
4373 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4374                         i915_cache_sharing_get, i915_cache_sharing_set,
4375                         "%llu\n");
4376
4377 static int i915_forcewake_open(struct inode *inode, struct file *file)
4378 {
4379         struct drm_device *dev = inode->i_private;
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381
4382         if (INTEL_INFO(dev)->gen < 6)
4383                 return 0;
4384
4385         intel_runtime_pm_get(dev_priv);
4386         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4387
4388         return 0;
4389 }
4390
4391 static int i915_forcewake_release(struct inode *inode, struct file *file)
4392 {
4393         struct drm_device *dev = inode->i_private;
4394         struct drm_i915_private *dev_priv = dev->dev_private;
4395
4396         if (INTEL_INFO(dev)->gen < 6)
4397                 return 0;
4398
4399         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4400         intel_runtime_pm_put(dev_priv);
4401
4402         return 0;
4403 }
4404
4405 static const struct file_operations i915_forcewake_fops = {
4406         .owner = THIS_MODULE,
4407         .open = i915_forcewake_open,
4408         .release = i915_forcewake_release,
4409 };
4410
4411 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4412 {
4413         struct drm_device *dev = minor->dev;
4414         struct dentry *ent;
4415
4416         ent = debugfs_create_file("i915_forcewake_user",
4417                                   S_IRUSR,
4418                                   root, dev,
4419                                   &i915_forcewake_fops);
4420         if (!ent)
4421                 return -ENOMEM;
4422
4423         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4424 }
4425
4426 static int i915_debugfs_create(struct dentry *root,
4427                                struct drm_minor *minor,
4428                                const char *name,
4429                                const struct file_operations *fops)
4430 {
4431         struct drm_device *dev = minor->dev;
4432         struct dentry *ent;
4433
4434         ent = debugfs_create_file(name,
4435                                   S_IRUGO | S_IWUSR,
4436                                   root, dev,
4437                                   fops);
4438         if (!ent)
4439                 return -ENOMEM;
4440
4441         return drm_add_fake_info_node(minor, ent, fops);
4442 }
4443
4444 static const struct drm_info_list i915_debugfs_list[] = {
4445         {"i915_capabilities", i915_capabilities, 0},
4446         {"i915_gem_objects", i915_gem_object_info, 0},
4447         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4448         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4449         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4450         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4451         {"i915_gem_stolen", i915_gem_stolen_list_info },
4452         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4453         {"i915_gem_request", i915_gem_request_info, 0},
4454         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4455         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4456         {"i915_gem_interrupt", i915_interrupt_info, 0},
4457         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4458         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4459         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4460         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4461         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4462         {"i915_frequency_info", i915_frequency_info, 0},
4463         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4464         {"i915_drpc_info", i915_drpc_info, 0},
4465         {"i915_emon_status", i915_emon_status, 0},
4466         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4467         {"i915_fbc_status", i915_fbc_status, 0},
4468         {"i915_ips_status", i915_ips_status, 0},
4469         {"i915_sr_status", i915_sr_status, 0},
4470         {"i915_opregion", i915_opregion, 0},
4471         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4472         {"i915_context_status", i915_context_status, 0},
4473         {"i915_dump_lrc", i915_dump_lrc, 0},
4474         {"i915_execlists", i915_execlists, 0},
4475         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4476         {"i915_swizzle_info", i915_swizzle_info, 0},
4477         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4478         {"i915_llc", i915_llc, 0},
4479         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4480         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4481         {"i915_energy_uJ", i915_energy_uJ, 0},
4482         {"i915_pc8_status", i915_pc8_status, 0},
4483         {"i915_power_domain_info", i915_power_domain_info, 0},
4484         {"i915_display_info", i915_display_info, 0},
4485         {"i915_semaphore_status", i915_semaphore_status, 0},
4486         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4487         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4488         {"i915_wa_registers", i915_wa_registers, 0},
4489         {"i915_ddb_info", i915_ddb_info, 0},
4490 };
4491 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4492
4493 static const struct i915_debugfs_files {
4494         const char *name;
4495         const struct file_operations *fops;
4496 } i915_debugfs_files[] = {
4497         {"i915_wedged", &i915_wedged_fops},
4498         {"i915_max_freq", &i915_max_freq_fops},
4499         {"i915_min_freq", &i915_min_freq_fops},
4500         {"i915_cache_sharing", &i915_cache_sharing_fops},
4501         {"i915_ring_stop", &i915_ring_stop_fops},
4502         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4503         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4504         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4505         {"i915_error_state", &i915_error_state_fops},
4506         {"i915_next_seqno", &i915_next_seqno_fops},
4507         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4508         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4509         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4510         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4511         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4512 };
4513
4514 void intel_display_crc_init(struct drm_device *dev)
4515 {
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         enum pipe pipe;
4518
4519         for_each_pipe(dev_priv, pipe) {
4520                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4521
4522                 pipe_crc->opened = false;
4523                 spin_lock_init(&pipe_crc->lock);
4524                 init_waitqueue_head(&pipe_crc->wq);
4525         }
4526 }
4527
4528 int i915_debugfs_init(struct drm_minor *minor)
4529 {
4530         int ret, i;
4531
4532         ret = i915_forcewake_create(minor->debugfs_root, minor);
4533         if (ret)
4534                 return ret;
4535
4536         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4537                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4538                 if (ret)
4539                         return ret;
4540         }
4541
4542         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4543                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4544                                           i915_debugfs_files[i].name,
4545                                           i915_debugfs_files[i].fops);
4546                 if (ret)
4547                         return ret;
4548         }
4549
4550         return drm_debugfs_create_files(i915_debugfs_list,
4551                                         I915_DEBUGFS_ENTRIES,
4552                                         minor->debugfs_root, minor);
4553 }
4554
4555 void i915_debugfs_cleanup(struct drm_minor *minor)
4556 {
4557         int i;
4558
4559         drm_debugfs_remove_files(i915_debugfs_list,
4560                                  I915_DEBUGFS_ENTRIES, minor);
4561
4562         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4563                                  1, minor);
4564
4565         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4566                 struct drm_info_list *info_list =
4567                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4568
4569                 drm_debugfs_remove_files(info_list, 1, minor);
4570         }
4571
4572         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4573                 struct drm_info_list *info_list =
4574                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4575
4576                 drm_debugfs_remove_files(info_list, 1, minor);
4577         }
4578 }