drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .gen = 8, .num_pipes = 3,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .is_valleyview = 1,
 353         .display_mmio_offset = VLV_DISPLAY_BASE,
 354         GEN_CHV_PIPEOFFSETS,
 355         CURSOR_OFFSETS,
 356 };
 357
 358 static const struct intel_device_info intel_skylake_info = {
 359         .is_preliminary = 1,
 360         .is_skylake = 1,
 361         .gen = 9, .num_pipes = 3,
 362         .need_gfx_hws = 1, .has_hotplug = 1,
 363         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 364         .has_llc = 1,
 365         .has_ddi = 1,
 366         .has_fbc = 1,
 367         GEN_DEFAULT_PIPEOFFSETS,
 368         IVB_CURSOR_OFFSETS,
 369 };
 370
 371 static const struct intel_device_info intel_skylake_gt3_info = {
 372         .is_preliminary = 1,
 373         .is_skylake = 1,
 374         .gen = 9, .num_pipes = 3,
 375         .need_gfx_hws = 1, .has_hotplug = 1,
 376         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 377         .has_llc = 1,
 378         .has_ddi = 1,
 379         .has_fbc = 1,
 380         GEN_DEFAULT_PIPEOFFSETS,
 381         IVB_CURSOR_OFFSETS,
 382 };
 383
 384 static const struct intel_device_info intel_broxton_info = {
 385         .is_preliminary = 1,
 386         .gen = 9,
 387         .need_gfx_hws = 1, .has_hotplug = 1,
 388         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 389         .num_pipes = 3,
 390         .has_ddi = 1,
 391         .has_fbc = 1,
 392         GEN_DEFAULT_PIPEOFFSETS,
 393         IVB_CURSOR_OFFSETS,
 394 };
 395
 396 /*
 397  * Make sure any device matches here are from most specific to most
 398  * general.  For example, since the Quanta match is based on the subsystem
 399  * and subvendor IDs, we need it to come before the more general IVB
 400  * PCI ID matches, otherwise we'll use the wrong info struct above.
 401  */
 402 #define INTEL_PCI_IDS \
 403         INTEL_I830_IDS(&intel_i830_info),       \
 404         INTEL_I845G_IDS(&intel_845g_info),      \
 405         INTEL_I85X_IDS(&intel_i85x_info),       \
 406         INTEL_I865G_IDS(&intel_i865g_info),     \
 407         INTEL_I915G_IDS(&intel_i915g_info),     \
 408         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 409         INTEL_I945G_IDS(&intel_i945g_info),     \
 410         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 411         INTEL_I965G_IDS(&intel_i965g_info),     \
 412         INTEL_G33_IDS(&intel_g33_info),         \
 413         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 414         INTEL_GM45_IDS(&intel_gm45_info),       \
 415         INTEL_G45_IDS(&intel_g45_info),         \
 416         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 417         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 418         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 419         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 420         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 421         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 422         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 423         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 424         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 425         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 426         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 427         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 428         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 429         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 430         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 431         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 432         INTEL_CHV_IDS(&intel_cherryview_info),  \
 433         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
 434         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
 435         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),     \
 436         INTEL_BXT_IDS(&intel_broxton_info)
 437
 438 static const struct pci_device_id pciidlist[] = {               /* aka */
 439         INTEL_PCI_IDS,
 440         {0, 0, 0}
 441 };
 442
 443 #if defined(CONFIG_DRM_I915_KMS)
 444 MODULE_DEVICE_TABLE(pci, pciidlist);
 445 #endif
 446
 447 void intel_detect_pch(struct drm_device *dev)
 448 {
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450         struct pci_dev *pch = NULL;
 451
 452         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 453          * (which really amounts to a PCH but no South Display).
 454          */
 455         if (INTEL_INFO(dev)->num_pipes == 0) {
 456                 dev_priv->pch_type = PCH_NOP;
 457                 return;
 458         }
 459
 460         /*
 461          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 462          * make graphics device passthrough work easy for VMM, that only
 463          * need to expose ISA bridge to let driver know the real hardware
 464          * underneath. This is a requirement from virtualization team.
 465          *
 466          * In some virtualized environments (e.g. XEN), there is irrelevant
 467          * ISA bridge in the system. To work reliably, we should scan trhough
 468          * all the ISA bridge devices and check for the first match, instead
 469          * of only checking the first one.
 470          */
 471         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 472                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 473                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 474                         dev_priv->pch_id = id;
 475
 476                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 477                                 dev_priv->pch_type = PCH_IBX;
 478                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 479                                 WARN_ON(!IS_GEN5(dev));
 480                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 481                                 dev_priv->pch_type = PCH_CPT;
 482                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 483                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 484                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 485                                 /* PantherPoint is CPT compatible */
 486                                 dev_priv->pch_type = PCH_CPT;
 487                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 488                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 489                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 490                                 dev_priv->pch_type = PCH_LPT;
 491                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 492                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 493                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 494                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 495                                 dev_priv->pch_type = PCH_LPT;
 496                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 497                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 498                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 499                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 500                                 dev_priv->pch_type = PCH_SPT;
 501                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 502                                 WARN_ON(!IS_SKYLAKE(dev));
 503                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 504                                 dev_priv->pch_type = PCH_SPT;
 505                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 506                                 WARN_ON(!IS_SKYLAKE(dev));
 507                         } else
 508                                 continue;
 509
 510                         break;
 511                 }
 512         }
 513         if (!pch)
 514                 DRM_DEBUG_KMS("No PCH found.\n");
 515
 516         pci_dev_put(pch);
 517 }
 518
 519 bool i915_semaphore_is_enabled(struct drm_device *dev)
 520 {
 521         if (INTEL_INFO(dev)->gen < 6)
 522                 return false;
 523
 524         if (i915.semaphores >= 0)
 525                 return i915.semaphores;
 526
 527         /* TODO: make semaphores and Execlists play nicely together */
 528         if (i915.enable_execlists)
 529                 return false;
 530
 531         /* Until we get further testing... */
 532         if (IS_GEN8(dev))
 533                 return false;
 534
 535 #ifdef CONFIG_INTEL_IOMMU
 536         /* Enable semaphores on SNB when IO remapping is off */
 537         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 538                 return false;
 539 #endif
 540
 541         return true;
 542 }
 543
 544 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 545 {
 546         spin_lock_irq(&dev_priv->irq_lock);
 547
 548         dev_priv->long_hpd_port_mask = 0;
 549         dev_priv->short_hpd_port_mask = 0;
 550         dev_priv->hpd_event_bits = 0;
 551
 552         spin_unlock_irq(&dev_priv->irq_lock);
 553
 554         cancel_work_sync(&dev_priv->dig_port_work);
 555         cancel_work_sync(&dev_priv->hotplug_work);
 556         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 557 }
 558
 559 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 560 {
 561         struct drm_device *dev = dev_priv->dev;
 562         struct drm_encoder *encoder;
 563
 564         drm_modeset_lock_all(dev);
 565         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 566                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 567
 568                 if (intel_encoder->suspend)
 569                         intel_encoder->suspend(intel_encoder);
 570         }
 571         drm_modeset_unlock_all(dev);
 572 }
 573
 574 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 575 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 576                               bool rpm_resume);
 577
 578 static int i915_drm_suspend(struct drm_device *dev)
 579 {
 580         struct drm_i915_private *dev_priv = dev->dev_private;
 581         struct drm_crtc *crtc;
 582         pci_power_t opregion_target_state;
 583         int error;
 584
 585         /* ignore lid events during suspend */
 586         mutex_lock(&dev_priv->modeset_restore_lock);
 587         dev_priv->modeset_restore = MODESET_SUSPENDED;
 588         mutex_unlock(&dev_priv->modeset_restore_lock);
 589
 590         /* We do a lot of poking in a lot of registers, make sure they work
 591          * properly. */
 592         intel_display_set_init_power(dev_priv, true);
 593
 594         drm_kms_helper_poll_disable(dev);
 595
 596         pci_save_state(dev->pdev);
 597
 598         error = i915_gem_suspend(dev);
 599         if (error) {
 600                 dev_err(&dev->pdev->dev,
 601                         "GEM idle failed, resume might fail\n");
 602                 return error;
 603         }
 604
 605         intel_suspend_gt_powersave(dev);
 606
 607         /*
 608          * Disable CRTCs directly since we want to preserve sw state
 609          * for _thaw. Also, power gate the CRTC power wells.
 610          */
 611         drm_modeset_lock_all(dev);
 612         for_each_crtc(dev, crtc)
 613                 intel_crtc_control(crtc, false);
 614         drm_modeset_unlock_all(dev);
 615
 616         intel_dp_mst_suspend(dev);
 617
 618         intel_runtime_pm_disable_interrupts(dev_priv);
 619         intel_hpd_cancel_work(dev_priv);
 620
 621         intel_suspend_encoders(dev_priv);
 622
 623         intel_suspend_hw(dev);
 624
 625         i915_gem_suspend_gtt_mappings(dev);
 626
 627         i915_save_state(dev);
 628
 629         opregion_target_state = PCI_D3cold;
 630 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 631         if (acpi_target_system_state() < ACPI_STATE_S3)
 632                 opregion_target_state = PCI_D1;
 633 #endif
 634         intel_opregion_notify_adapter(dev, opregion_target_state);
 635
 636         intel_uncore_forcewake_reset(dev, false);
 637         intel_opregion_fini(dev);
 638
 639         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 640
 641         dev_priv->suspend_count++;
 642
 643         intel_display_set_init_power(dev_priv, false);
 644
 645         return 0;
 646 }
 647
 648 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 649 {
 650         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 651         int ret;
 652
 653         ret = intel_suspend_complete(dev_priv);
 654
 655         if (ret) {
 656                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 657
 658                 return ret;
 659         }
 660
 661         pci_disable_device(drm_dev->pdev);
 662         /*
 663          * During hibernation on some GEN4 platforms the BIOS may try to access
 664          * the device even though it's already in D3 and hang the machine. So
 665          * leave the device in D0 on those platforms and hope the BIOS will
 666          * power down the device properly. Platforms where this was seen:
 667          * Lenovo Thinkpad X301, X61s
 668          */
 669         if (!(hibernation &&
 670               drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
 671               INTEL_INFO(dev_priv)->gen == 4))
 672                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 673
 674         return 0;
 675 }
 676
 677 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
 678 {
 679         int error;
 680
 681         if (!dev || !dev->dev_private) {
 682                 DRM_ERROR("dev: %p\n", dev);
 683                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 684                 return -ENODEV;
 685         }
 686
 687         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 688                          state.event != PM_EVENT_FREEZE))
 689                 return -EINVAL;
 690
 691         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 692                 return 0;
 693
 694         error = i915_drm_suspend(dev);
 695         if (error)
 696                 return error;
 697
 698         return i915_drm_suspend_late(dev, false);
 699 }
 700
 701 static int i915_drm_resume(struct drm_device *dev)
 702 {
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704
 705         mutex_lock(&dev->struct_mutex);
 706         i915_gem_restore_gtt_mappings(dev);
 707         mutex_unlock(&dev->struct_mutex);
 708
 709         i915_restore_state(dev);
 710         intel_opregion_setup(dev);
 711
 712         intel_init_pch_refclk(dev);
 713         drm_mode_config_reset(dev);
 714
 715         mutex_lock(&dev->struct_mutex);
 716         if (i915_gem_init_hw(dev)) {
 717                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 718                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 719         }
 720         mutex_unlock(&dev->struct_mutex);
 721
 722         /* We need working interrupts for modeset enabling ... */
 723         intel_runtime_pm_enable_interrupts(dev_priv);
 724
 725         intel_modeset_init_hw(dev);
 726
 727         spin_lock_irq(&dev_priv->irq_lock);
 728         if (dev_priv->display.hpd_irq_setup)
 729                 dev_priv->display.hpd_irq_setup(dev);
 730         spin_unlock_irq(&dev_priv->irq_lock);
 731
 732         drm_modeset_lock_all(dev);
 733         intel_modeset_setup_hw_state(dev, true);
 734         drm_modeset_unlock_all(dev);
 735
 736         intel_dp_mst_resume(dev);
 737
 738         /*
 739          * ... but also need to make sure that hotplug processing
 740          * doesn't cause havoc. Like in the driver load code we don't
 741          * bother with the tiny race here where we might loose hotplug
 742          * notifications.
 743          * */
 744         intel_hpd_init(dev_priv);
 745         /* Config may have changed between suspend and resume */
 746         drm_helper_hpd_irq_event(dev);
 747
 748         intel_opregion_init(dev);
 749
 750         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 751
 752         mutex_lock(&dev_priv->modeset_restore_lock);
 753         dev_priv->modeset_restore = MODESET_DONE;
 754         mutex_unlock(&dev_priv->modeset_restore_lock);
 755
 756         intel_opregion_notify_adapter(dev, PCI_D0);
 757
 758         drm_kms_helper_poll_enable(dev);
 759
 760         return 0;
 761 }
 762
 763 static int i915_drm_resume_early(struct drm_device *dev)
 764 {
 765         struct drm_i915_private *dev_priv = dev->dev_private;
 766         int ret = 0;
 767
 768         /*
 769          * We have a resume ordering issue with the snd-hda driver also
 770          * requiring our device to be power up. Due to the lack of a
 771          * parent/child relationship we currently solve this with an early
 772          * resume hook.
 773          *
 774          * FIXME: This should be solved with a special hdmi sink device or
 775          * similar so that power domains can be employed.
 776          */
 777         if (pci_enable_device(dev->pdev))
 778                 return -EIO;
 779
 780         pci_set_master(dev->pdev);
 781
 782         if (IS_VALLEYVIEW(dev_priv))
 783                 ret = vlv_resume_prepare(dev_priv, false);
 784         if (ret)
 785                 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
 786
 787         intel_uncore_early_sanitize(dev, true);
 788
 789         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 790                 hsw_disable_pc8(dev_priv);
 791
 792         intel_uncore_sanitize(dev);
 793         intel_power_domains_init_hw(dev_priv);
 794
 795         return ret;
 796 }
 797
 798 int i915_resume_legacy(struct drm_device *dev)
 799 {
 800         int ret;
 801
 802         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 803                 return 0;
 804
 805         ret = i915_drm_resume_early(dev);
 806         if (ret)
 807                 return ret;
 808
 809         return i915_drm_resume(dev);
 810 }
 811
 812 /**
 813  * i915_reset - reset chip after a hang
 814  * @dev: drm device to reset
 815  *
 816  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 817  * reset or otherwise an error code.
 818  *
 819  * Procedure is fairly simple:
 820  *   - reset the chip using the reset reg
 821  *   - re-init context state
 822  *   - re-init hardware status page
 823  *   - re-init ring buffer
 824  *   - re-init interrupt state
 825  *   - re-init display
 826  */
 827 int i915_reset(struct drm_device *dev)
 828 {
 829         struct drm_i915_private *dev_priv = dev->dev_private;
 830         bool simulated;
 831         int ret;
 832
 833         if (!i915.reset)
 834                 return 0;
 835
 836         intel_reset_gt_powersave(dev);
 837
 838         mutex_lock(&dev->struct_mutex);
 839
 840         i915_gem_reset(dev);
 841
 842         simulated = dev_priv->gpu_error.stop_rings != 0;
 843
 844         ret = intel_gpu_reset(dev);
 845
 846         /* Also reset the gpu hangman. */
 847         if (simulated) {
 848                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 849                 dev_priv->gpu_error.stop_rings = 0;
 850                 if (ret == -ENODEV) {
 851                         DRM_INFO("Reset not implemented, but ignoring "
 852                                  "error for simulated gpu hangs\n");
 853                         ret = 0;
 854                 }
 855         }
 856
 857         if (i915_stop_ring_allow_warn(dev_priv))
 858                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 859
 860         if (ret) {
 861                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 862                 mutex_unlock(&dev->struct_mutex);
 863                 return ret;
 864         }
 865
 866         intel_overlay_reset(dev_priv);
 867
 868         /* Ok, now get things going again... */
 869
 870         /*
 871          * Everything depends on having the GTT running, so we need to start
 872          * there.  Fortunately we don't need to do this unless we reset the
 873          * chip at a PCI level.
 874          *
 875          * Next we need to restore the context, but we don't use those
 876          * yet either...
 877          *
 878          * Ring buffer needs to be re-initialized in the KMS case, or if X
 879          * was running at the time of the reset (i.e. we weren't VT
 880          * switched away).
 881          */
 882
 883         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 884         dev_priv->gpu_error.reload_in_reset = true;
 885
 886         ret = i915_gem_init_hw(dev);
 887
 888         dev_priv->gpu_error.reload_in_reset = false;
 889
 890         mutex_unlock(&dev->struct_mutex);
 891         if (ret) {
 892                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 893                 return ret;
 894         }
 895
 896         /*
 897          * rps/rc6 re-init is necessary to restore state lost after the
 898          * reset and the re-install of gt irqs. Skip for ironlake per
 899          * previous concerns that it doesn't respond well to some forms
 900          * of re-init after reset.
 901          */
 902         if (INTEL_INFO(dev)->gen > 5)
 903                 intel_enable_gt_powersave(dev);
 904
 905         return 0;
 906 }
 907
 908 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 909 {
 910         struct intel_device_info *intel_info =
 911                 (struct intel_device_info *) ent->driver_data;
 912
 913         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 914                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 915                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 916                 return -ENODEV;
 917         }
 918
 919         /* Only bind to function 0 of the device. Early generations
 920          * used function 1 as a placeholder for multi-head. This causes
 921          * us confusion instead, especially on the systems where both
 922          * functions have the same PCI-ID!
 923          */
 924         if (PCI_FUNC(pdev->devfn))
 925                 return -ENODEV;
 926
 927         driver.driver_features &= ~(DRIVER_USE_AGP);
 928
 929         return drm_get_pci_dev(pdev, ent, &driver);
 930 }
 931
 932 static void
 933 i915_pci_remove(struct pci_dev *pdev)
 934 {
 935         struct drm_device *dev = pci_get_drvdata(pdev);
 936
 937         drm_put_dev(dev);
 938 }
 939
 940 static int i915_pm_suspend(struct device *dev)
 941 {
 942         struct pci_dev *pdev = to_pci_dev(dev);
 943         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 944
 945         if (!drm_dev || !drm_dev->dev_private) {
 946                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 947                 return -ENODEV;
 948         }
 949
 950         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 951                 return 0;
 952
 953         return i915_drm_suspend(drm_dev);
 954 }
 955
 956 static int i915_pm_suspend_late(struct device *dev)
 957 {
 958         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 959
 960         /*
 961          * We have a suspedn ordering issue with the snd-hda driver also
 962          * requiring our device to be power up. Due to the lack of a
 963          * parent/child relationship we currently solve this with an late
 964          * suspend hook.
 965          *
 966          * FIXME: This should be solved with a special hdmi sink device or
 967          * similar so that power domains can be employed.
 968          */
 969         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 970                 return 0;
 971
 972         return i915_drm_suspend_late(drm_dev, false);
 973 }
 974
 975 static int i915_pm_poweroff_late(struct device *dev)
 976 {
 977         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 978
 979         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 980                 return 0;
 981
 982         return i915_drm_suspend_late(drm_dev, true);
 983 }
 984
 985 static int i915_pm_resume_early(struct device *dev)
 986 {
 987         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 988
 989         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 990                 return 0;
 991
 992         return i915_drm_resume_early(drm_dev);
 993 }
 994
 995 static int i915_pm_resume(struct device *dev)
 996 {
 997         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 998
 999         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1000                 return 0;
1001
1002         return i915_drm_resume(drm_dev);
1003 }
1004
1005 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1006 {
1007         hsw_enable_pc8(dev_priv);
1008
1009         return 0;
1010 }
1011
1012 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1013 {
1014         struct drm_device *dev = dev_priv->dev;
1015
1016         /* TODO: when DC5 support is added disable DC5 here. */
1017
1018         broxton_ddi_phy_uninit(dev);
1019         broxton_uninit_cdclk(dev);
1020         bxt_enable_dc9(dev_priv);
1021
1022         return 0;
1023 }
1024
1025 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1026 {
1027         struct drm_device *dev = dev_priv->dev;
1028
1029         /* TODO: when CSR FW support is added make sure the FW is loaded */
1030
1031         bxt_disable_dc9(dev_priv);
1032
1033         /*
1034          * TODO: when DC5 support is added enable DC5 here if the CSR FW
1035          * is available.
1036          */
1037         broxton_init_cdclk(dev);
1038         broxton_ddi_phy_init(dev);
1039         intel_prepare_ddi(dev);
1040
1041         return 0;
1042 }
1043
1044 /*
1045  * Save all Gunit registers that may be lost after a D3 and a subsequent
1046  * S0i[R123] transition. The list of registers needing a save/restore is
1047  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1048  * registers in the following way:
1049  * - Driver: saved/restored by the driver
1050  * - Punit : saved/restored by the Punit firmware
1051  * - No, w/o marking: no need to save/restore, since the register is R/O or
1052  *                    used internally by the HW in a way that doesn't depend
1053  *                    keeping the content across a suspend/resume.
1054  * - Debug : used for debugging
1055  *
1056  * We save/restore all registers marked with 'Driver', with the following
1057  * exceptions:
1058  * - Registers out of use, including also registers marked with 'Debug'.
1059  *   These have no effect on the driver's operation, so we don't save/restore
1060  *   them to reduce the overhead.
1061  * - Registers that are fully setup by an initialization function called from
1062  *   the resume path. For example many clock gating and RPS/RC6 registers.
1063  * - Registers that provide the right functionality with their reset defaults.
1064  *
1065  * TODO: Except for registers that based on the above 3 criteria can be safely
1066  * ignored, we save/restore all others, practically treating the HW context as
1067  * a black-box for the driver. Further investigation is needed to reduce the
1068  * saved/restored registers even further, by following the same 3 criteria.
1069  */
1070 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1071 {
1072         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1073         int i;
1074
1075         /* GAM 0x4000-0x4770 */
1076         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1077         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1078         s->arb_mode             = I915_READ(ARB_MODE);
1079         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1080         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1081
1082         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1083                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1084
1085         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1086         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1087
1088         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1089         s->ecochk               = I915_READ(GAM_ECOCHK);
1090         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1091         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1092
1093         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1094
1095         /* MBC 0x9024-0x91D0, 0x8500 */
1096         s->g3dctl               = I915_READ(VLV_G3DCTL);
1097         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1098         s->mbctl                = I915_READ(GEN6_MBCTL);
1099
1100         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1101         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1102         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1103         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1104         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1105         s->rstctl               = I915_READ(GEN6_RSTCTL);
1106         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1107
1108         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1109         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1110         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1111         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1112         s->ecobus               = I915_READ(ECOBUS);
1113         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1114         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1115         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1116         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1117         s->rcedata              = I915_READ(VLV_RCEDATA);
1118         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1119
1120         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1121         s->gt_imr               = I915_READ(GTIMR);
1122         s->gt_ier               = I915_READ(GTIER);
1123         s->pm_imr               = I915_READ(GEN6_PMIMR);
1124         s->pm_ier               = I915_READ(GEN6_PMIER);
1125
1126         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1127                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1128
1129         /* GT SA CZ domain, 0x100000-0x138124 */
1130         s->tilectl              = I915_READ(TILECTL);
1131         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1132         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1133         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1134         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1135
1136         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1137         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1138         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1139         s->pcbr                 = I915_READ(VLV_PCBR);
1140         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1141
1142         /*
1143          * Not saving any of:
1144          * DFT,         0x9800-0x9EC0
1145          * SARB,        0xB000-0xB1FC
1146          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1147          * PCI CFG
1148          */
1149 }
1150
1151 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1152 {
1153         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1154         u32 val;
1155         int i;
1156
1157         /* GAM 0x4000-0x4770 */
1158         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1159         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1160         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1161         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1162         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1163
1164         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1165                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1166
1167         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1168         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1169
1170         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1171         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1172         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1173         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1174
1175         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1176
1177         /* MBC 0x9024-0x91D0, 0x8500 */
1178         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1179         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1180         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1181
1182         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1183         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1184         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1185         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1186         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1187         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1188         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1189
1190         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1191         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1192         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1193         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1194         I915_WRITE(ECOBUS,              s->ecobus);
1195         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1196         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1197         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1198         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1199         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1200         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1201
1202         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1203         I915_WRITE(GTIMR,               s->gt_imr);
1204         I915_WRITE(GTIER,               s->gt_ier);
1205         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1206         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1207
1208         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1209                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1210
1211         /* GT SA CZ domain, 0x100000-0x138124 */
1212         I915_WRITE(TILECTL,                     s->tilectl);
1213         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1214         /*
1215          * Preserve the GT allow wake and GFX force clock bit, they are not
1216          * be restored, as they are used to control the s0ix suspend/resume
1217          * sequence by the caller.
1218          */
1219         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1220         val &= VLV_GTLC_ALLOWWAKEREQ;
1221         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1222         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1223
1224         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1225         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1226         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1227         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1228
1229         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1230
1231         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1232         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1233         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1234         I915_WRITE(VLV_PCBR,                    s->pcbr);
1235         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1236 }
1237
1238 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1239 {
1240         u32 val;
1241         int err;
1242
1243         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1244
1245 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1246         /* Wait for a previous force-off to settle */
1247         if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) {
1248                 /* WARN_ON only for the Valleyview */
1249                 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1250
1251                 err = wait_for(!COND, 20);
1252                 if (err) {
1253                         DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1254                                   I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1255                         return err;
1256                 }
1257         }
1258
1259         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1260         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1261         if (force_on)
1262                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1263         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1264
1265         if (!force_on)
1266                 return 0;
1267
1268         err = wait_for(COND, 20);
1269         if (err)
1270                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1271                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1272
1273         return err;
1274 #undef COND
1275 }
1276
1277 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1278 {
1279         u32 val;
1280         int err = 0;
1281
1282         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1283         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1284         if (allow)
1285                 val |= VLV_GTLC_ALLOWWAKEREQ;
1286         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1287         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1288
1289 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1290               allow)
1291         err = wait_for(COND, 1);
1292         if (err)
1293                 DRM_ERROR("timeout disabling GT waking\n");
1294         return err;
1295 #undef COND
1296 }
1297
1298 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1299                                  bool wait_for_on)
1300 {
1301         u32 mask;
1302         u32 val;
1303         int err;
1304
1305         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1306         val = wait_for_on ? mask : 0;
1307 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1308         if (COND)
1309                 return 0;
1310
1311         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1312                         wait_for_on ? "on" : "off",
1313                         I915_READ(VLV_GTLC_PW_STATUS));
1314
1315         /*
1316          * RC6 transitioning can be delayed up to 2 msec (see
1317          * valleyview_enable_rps), use 3 msec for safety.
1318          */
1319         err = wait_for(COND, 3);
1320         if (err)
1321                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1322                           wait_for_on ? "on" : "off");
1323
1324         return err;
1325 #undef COND
1326 }
1327
1328 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1329 {
1330         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1331                 return;
1332
1333         DRM_ERROR("GT register access while GT waking disabled\n");
1334         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1335 }
1336
1337 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1338 {
1339         u32 mask;
1340         int err;
1341
1342         /*
1343          * Bspec defines the following GT well on flags as debug only, so
1344          * don't treat them as hard failures.
1345          */
1346         (void)vlv_wait_for_gt_wells(dev_priv, false);
1347
1348         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1349         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1350
1351         vlv_check_no_gt_access(dev_priv);
1352
1353         err = vlv_force_gfx_clock(dev_priv, true);
1354         if (err)
1355                 goto err1;
1356
1357         err = vlv_allow_gt_wake(dev_priv, false);
1358         if (err)
1359                 goto err2;
1360
1361         if (!IS_CHERRYVIEW(dev_priv->dev))
1362                 vlv_save_gunit_s0ix_state(dev_priv);
1363
1364         err = vlv_force_gfx_clock(dev_priv, false);
1365         if (err)
1366                 goto err2;
1367
1368         return 0;
1369
1370 err2:
1371         /* For safety always re-enable waking and disable gfx clock forcing */
1372         vlv_allow_gt_wake(dev_priv, true);
1373 err1:
1374         vlv_force_gfx_clock(dev_priv, false);
1375
1376         return err;
1377 }
1378
1379 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1380                                 bool rpm_resume)
1381 {
1382         struct drm_device *dev = dev_priv->dev;
1383         int err;
1384         int ret;
1385
1386         /*
1387          * If any of the steps fail just try to continue, that's the best we
1388          * can do at this point. Return the first error code (which will also
1389          * leave RPM permanently disabled).
1390          */
1391         ret = vlv_force_gfx_clock(dev_priv, true);
1392
1393         if (!IS_CHERRYVIEW(dev_priv->dev))
1394                 vlv_restore_gunit_s0ix_state(dev_priv);
1395
1396         err = vlv_allow_gt_wake(dev_priv, true);
1397         if (!ret)
1398                 ret = err;
1399
1400         err = vlv_force_gfx_clock(dev_priv, false);
1401         if (!ret)
1402                 ret = err;
1403
1404         vlv_check_no_gt_access(dev_priv);
1405
1406         if (rpm_resume) {
1407                 intel_init_clock_gating(dev);
1408                 i915_gem_restore_fences(dev);
1409         }
1410
1411         return ret;
1412 }
1413
1414 static int intel_runtime_suspend(struct device *device)
1415 {
1416         struct pci_dev *pdev = to_pci_dev(device);
1417         struct drm_device *dev = pci_get_drvdata(pdev);
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         int ret;
1420
1421         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1422                 return -ENODEV;
1423
1424         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1425                 return -ENODEV;
1426
1427         DRM_DEBUG_KMS("Suspending device\n");
1428
1429         /*
1430          * We could deadlock here in case another thread holding struct_mutex
1431          * calls RPM suspend concurrently, since the RPM suspend will wait
1432          * first for this RPM suspend to finish. In this case the concurrent
1433          * RPM resume will be followed by its RPM suspend counterpart. Still
1434          * for consistency return -EAGAIN, which will reschedule this suspend.
1435          */
1436         if (!mutex_trylock(&dev->struct_mutex)) {
1437                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1438                 /*
1439                  * Bump the expiration timestamp, otherwise the suspend won't
1440                  * be rescheduled.
1441                  */
1442                 pm_runtime_mark_last_busy(device);
1443
1444                 return -EAGAIN;
1445         }
1446         /*
1447          * We are safe here against re-faults, since the fault handler takes
1448          * an RPM reference.
1449          */
1450         i915_gem_release_all_mmaps(dev_priv);
1451         mutex_unlock(&dev->struct_mutex);
1452
1453         intel_suspend_gt_powersave(dev);
1454         intel_runtime_pm_disable_interrupts(dev_priv);
1455
1456         ret = intel_suspend_complete(dev_priv);
1457         if (ret) {
1458                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1459                 intel_runtime_pm_enable_interrupts(dev_priv);
1460
1461                 return ret;
1462         }
1463
1464         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1465         intel_uncore_forcewake_reset(dev, false);
1466         dev_priv->pm.suspended = true;
1467
1468         /*
1469          * FIXME: We really should find a document that references the arguments
1470          * used below!
1471          */
1472         if (IS_HASWELL(dev)) {
1473                 /*
1474                  * current versions of firmware which depend on this opregion
1475                  * notification have repurposed the D1 definition to mean
1476                  * "runtime suspended" vs. what you would normally expect (D3)
1477                  * to distinguish it from notifications that might be sent via
1478                  * the suspend path.
1479                  */
1480                 intel_opregion_notify_adapter(dev, PCI_D1);
1481         } else {
1482                 /*
1483                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1484                  * being detected, and the call we do at intel_runtime_resume()
1485                  * won't be able to restore them. Since PCI_D3hot matches the
1486                  * actual specification and appears to be working, use it. Let's
1487                  * assume the other non-Haswell platforms will stay the same as
1488                  * Broadwell.
1489                  */
1490                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1491         }
1492
1493         assert_forcewakes_inactive(dev_priv);
1494
1495         DRM_DEBUG_KMS("Device suspended\n");
1496         return 0;
1497 }
1498
1499 static int intel_runtime_resume(struct device *device)
1500 {
1501         struct pci_dev *pdev = to_pci_dev(device);
1502         struct drm_device *dev = pci_get_drvdata(pdev);
1503         struct drm_i915_private *dev_priv = dev->dev_private;
1504         int ret = 0;
1505
1506         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1507                 return -ENODEV;
1508
1509         DRM_DEBUG_KMS("Resuming device\n");
1510
1511         intel_opregion_notify_adapter(dev, PCI_D0);
1512         dev_priv->pm.suspended = false;
1513
1514         if (IS_GEN6(dev_priv))
1515                 intel_init_pch_refclk(dev);
1516
1517         if (IS_BROXTON(dev))
1518                 ret = bxt_resume_prepare(dev_priv);
1519         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1520                 hsw_disable_pc8(dev_priv);
1521         else if (IS_VALLEYVIEW(dev_priv))
1522                 ret = vlv_resume_prepare(dev_priv, true);
1523
1524         /*
1525          * No point of rolling back things in case of an error, as the best
1526          * we can do is to hope that things will still work (and disable RPM).
1527          */
1528         i915_gem_init_swizzling(dev);
1529         gen6_update_ring_freq(dev);
1530
1531         intel_runtime_pm_enable_interrupts(dev_priv);
1532         intel_enable_gt_powersave(dev);
1533
1534         if (ret)
1535                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1536         else
1537                 DRM_DEBUG_KMS("Device resumed\n");
1538
1539         return ret;
1540 }
1541
1542 /*
1543  * This function implements common functionality of runtime and system
1544  * suspend sequence.
1545  */
1546 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1547 {
1548         struct drm_device *dev = dev_priv->dev;
1549         int ret;
1550
1551         if (IS_BROXTON(dev))
1552                 ret = bxt_suspend_complete(dev_priv);
1553         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1554                 ret = hsw_suspend_complete(dev_priv);
1555         else if (IS_VALLEYVIEW(dev))
1556                 ret = vlv_suspend_complete(dev_priv);
1557         else
1558                 ret = 0;
1559
1560         return ret;
1561 }
1562
1563 static const struct dev_pm_ops i915_pm_ops = {
1564         /*
1565          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1566          * PMSG_RESUME]
1567          */
1568         .suspend = i915_pm_suspend,
1569         .suspend_late = i915_pm_suspend_late,
1570         .resume_early = i915_pm_resume_early,
1571         .resume = i915_pm_resume,
1572
1573         /*
1574          * S4 event handlers
1575          * @freeze, @freeze_late    : called (1) before creating the
1576          *                            hibernation image [PMSG_FREEZE] and
1577          *                            (2) after rebooting, before restoring
1578          *                            the image [PMSG_QUIESCE]
1579          * @thaw, @thaw_early       : called (1) after creating the hibernation
1580          *                            image, before writing it [PMSG_THAW]
1581          *                            and (2) after failing to create or
1582          *                            restore the image [PMSG_RECOVER]
1583          * @poweroff, @poweroff_late: called after writing the hibernation
1584          *                            image, before rebooting [PMSG_HIBERNATE]
1585          * @restore, @restore_early : called after rebooting and restoring the
1586          *                            hibernation image [PMSG_RESTORE]
1587          */
1588         .freeze = i915_pm_suspend,
1589         .freeze_late = i915_pm_suspend_late,
1590         .thaw_early = i915_pm_resume_early,
1591         .thaw = i915_pm_resume,
1592         .poweroff = i915_pm_suspend,
1593         .poweroff_late = i915_pm_poweroff_late,
1594         .restore_early = i915_pm_resume_early,
1595         .restore = i915_pm_resume,
1596
1597         /* S0ix (via runtime suspend) event handlers */
1598         .runtime_suspend = intel_runtime_suspend,
1599         .runtime_resume = intel_runtime_resume,
1600 };
1601
1602 static const struct vm_operations_struct i915_gem_vm_ops = {
1603         .fault = i915_gem_fault,
1604         .open = drm_gem_vm_open,
1605         .close = drm_gem_vm_close,
1606 };
1607
1608 static const struct file_operations i915_driver_fops = {
1609         .owner = THIS_MODULE,
1610         .open = drm_open,
1611         .release = drm_release,
1612         .unlocked_ioctl = drm_ioctl,
1613         .mmap = drm_gem_mmap,
1614         .poll = drm_poll,
1615         .read = drm_read,
1616 #ifdef CONFIG_COMPAT
1617         .compat_ioctl = i915_compat_ioctl,
1618 #endif
1619         .llseek = noop_llseek,
1620 };
1621
1622 static struct drm_driver driver = {
1623         /* Don't use MTRRs here; the Xserver or userspace app should
1624          * deal with them for Intel hardware.
1625          */
1626         .driver_features =
1627             DRIVER_USE_AGP |
1628             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1629             DRIVER_RENDER,
1630         .load = i915_driver_load,
1631         .unload = i915_driver_unload,
1632         .open = i915_driver_open,
1633         .lastclose = i915_driver_lastclose,
1634         .preclose = i915_driver_preclose,
1635         .postclose = i915_driver_postclose,
1636         .set_busid = drm_pci_set_busid,
1637
1638         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1639         .suspend = i915_suspend_legacy,
1640         .resume = i915_resume_legacy,
1641
1642         .device_is_agp = i915_driver_device_is_agp,
1643 #if defined(CONFIG_DEBUG_FS)
1644         .debugfs_init = i915_debugfs_init,
1645         .debugfs_cleanup = i915_debugfs_cleanup,
1646 #endif
1647         .gem_free_object = i915_gem_free_object,
1648         .gem_vm_ops = &i915_gem_vm_ops,
1649
1650         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1651         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1652         .gem_prime_export = i915_gem_prime_export,
1653         .gem_prime_import = i915_gem_prime_import,
1654
1655         .dumb_create = i915_gem_dumb_create,
1656         .dumb_map_offset = i915_gem_mmap_gtt,
1657         .dumb_destroy = drm_gem_dumb_destroy,
1658         .ioctls = i915_ioctls,
1659         .fops = &i915_driver_fops,
1660         .name = DRIVER_NAME,
1661         .desc = DRIVER_DESC,
1662         .date = DRIVER_DATE,
1663         .major = DRIVER_MAJOR,
1664         .minor = DRIVER_MINOR,
1665         .patchlevel = DRIVER_PATCHLEVEL,
1666 };
1667
1668 static struct pci_driver i915_pci_driver = {
1669         .name = DRIVER_NAME,
1670         .id_table = pciidlist,
1671         .probe = i915_pci_probe,
1672         .remove = i915_pci_remove,
1673         .driver.pm = &i915_pm_ops,
1674 };
1675
1676 static int __init i915_init(void)
1677 {
1678         driver.num_ioctls = i915_max_ioctl;
1679
1680         /*
1681          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1682          * explicitly disabled with the module pararmeter.
1683          *
1684          * Otherwise, just follow the parameter (defaulting to off).
1685          *
1686          * Allow optional vga_text_mode_force boot option to override
1687          * the default behavior.
1688          */
1689 #if defined(CONFIG_DRM_I915_KMS)
1690         if (i915.modeset != 0)
1691                 driver.driver_features |= DRIVER_MODESET;
1692 #endif
1693         if (i915.modeset == 1)
1694                 driver.driver_features |= DRIVER_MODESET;
1695
1696 #ifdef CONFIG_VGA_CONSOLE
1697         if (vgacon_text_force() && i915.modeset == -1)
1698                 driver.driver_features &= ~DRIVER_MODESET;
1699 #endif
1700
1701         if (!(driver.driver_features & DRIVER_MODESET)) {
1702                 driver.get_vblank_timestamp = NULL;
1703                 /* Silently fail loading to not upset userspace. */
1704                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1705                 return 0;
1706         }
1707
1708         /*
1709          * FIXME: Note that we're lying to the DRM core here so that we can get access
1710          * to the atomic ioctl and the atomic properties.  Only plane operations on
1711          * a single CRTC will actually work.
1712          */
1713         if (i915.nuclear_pageflip)
1714                 driver.driver_features |= DRIVER_ATOMIC;
1715
1716         return drm_pci_init(&driver, &i915_pci_driver);
1717 }
1718
1719 static void __exit i915_exit(void)
1720 {
1721         if (!(driver.driver_features & DRIVER_MODESET))
1722                 return; /* Never loaded a driver. */
1723
1724         drm_pci_exit(&driver, &i915_pci_driver);
1725 }
1726
1727 module_init(i915_init);
1728 module_exit(i915_exit);
1729
1730 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1731 MODULE_AUTHOR("Intel Corporation");
1732
1733 MODULE_DESCRIPTION(DRIVER_DESC);
1734 MODULE_LICENSE("GPL and additional rights");