drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_vgpu.h"
  53 #include "intel_drv.h"
  54 #include "intel_uc.h"
  55
  56 static struct drm_driver driver;
  57
  58 static unsigned int i915_load_fail_count;
  59
  60 bool __i915_inject_load_failure(const char *func, int line)
  61 {
  62         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  63                 return false;
  64
  65         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  66                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  67                          i915_modparams.inject_load_failure, func, line);
  68                 return true;
  69         }
  70
  71         return false;
  72 }
  73
  74 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  75 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  76                     "providing the dmesg log by booting with drm.debug=0xf"
  77
  78 void
  79 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  80               const char *fmt, ...)
  81 {
  82         static bool shown_bug_once;
  83         struct device *kdev = dev_priv->drm.dev;
  84         bool is_error = level[1] <= KERN_ERR[1];
  85         bool is_debug = level[1] == KERN_DEBUG[1];
  86         struct va_format vaf;
  87         va_list args;
  88
  89         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  90                 return;
  91
  92         va_start(args, fmt);
  93
  94         vaf.fmt = fmt;
  95         vaf.va = &args;
  96
  97         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  98                    __builtin_return_address(0), &vaf);
  99
 100         if (is_error && !shown_bug_once) {
 101                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 102                 shown_bug_once = true;
 103         }
 104
 105         va_end(args);
 106 }
 107
 108 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 109 {
 110         return i915_modparams.inject_load_failure &&
 111                i915_load_fail_count == i915_modparams.inject_load_failure;
 112 }
 113
 114 #define i915_load_error(dev_priv, fmt, ...)                                  \
 115         __i915_printk(dev_priv,                                              \
 116                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 117                       fmt, ##__VA_ARGS__)
 118
 119
 120 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 121 {
 122         enum intel_pch ret = PCH_NOP;
 123
 124         /*
 125          * In a virtualized passthrough environment we can be in a
 126          * setup where the ISA bridge is not able to be passed through.
 127          * In this case, a south bridge can be emulated and we have to
 128          * make an educated guess as to which PCH is really there.
 129          */
 130
 131         if (IS_GEN5(dev_priv)) {
 132                 ret = PCH_IBX;
 133                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 134         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 135                 ret = PCH_CPT;
 136                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
 137         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 138                 ret = PCH_LPT;
 139                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 140                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 141                 else
 142                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 143                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 144         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 145                 ret = PCH_SPT;
 146                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 147         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 148                 ret = PCH_CNP;
 149                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 150         }
 151
 152         return ret;
 153 }
 154
 155 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 156 {
 157         struct pci_dev *pch = NULL;
 158
 159         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 160          * (which really amounts to a PCH but no South Display).
 161          */
 162         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 163                 dev_priv->pch_type = PCH_NOP;
 164                 return;
 165         }
 166
 167         /*
 168          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 169          * make graphics device passthrough work easy for VMM, that only
 170          * need to expose ISA bridge to let driver know the real hardware
 171          * underneath. This is a requirement from virtualization team.
 172          *
 173          * In some virtualized environments (e.g. XEN), there is irrelevant
 174          * ISA bridge in the system. To work reliably, we should scan trhough
 175          * all the ISA bridge devices and check for the first match, instead
 176          * of only checking the first one.
 177          */
 178         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 179                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 180                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 181
 182                         dev_priv->pch_id = id;
 183
 184                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 185                                 dev_priv->pch_type = PCH_IBX;
 186                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 187                                 WARN_ON(!IS_GEN5(dev_priv));
 188                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 189                                 dev_priv->pch_type = PCH_CPT;
 190                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 191                                 WARN_ON(!IS_GEN6(dev_priv) &&
 192                                         !IS_IVYBRIDGE(dev_priv));
 193                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 194                                 /* PantherPoint is CPT compatible */
 195                                 dev_priv->pch_type = PCH_CPT;
 196                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 197                                 WARN_ON(!IS_GEN6(dev_priv) &&
 198                                         !IS_IVYBRIDGE(dev_priv));
 199                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 200                                 dev_priv->pch_type = PCH_LPT;
 201                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 202                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 203                                         !IS_BROADWELL(dev_priv));
 204                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 205                                         IS_BDW_ULT(dev_priv));
 206                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 207                                 dev_priv->pch_type = PCH_LPT;
 208                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 209                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 210                                         !IS_BROADWELL(dev_priv));
 211                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 212                                         !IS_BDW_ULT(dev_priv));
 213                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
 214                                 /* WildcatPoint is LPT compatible */
 215                                 dev_priv->pch_type = PCH_LPT;
 216                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 217                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 218                                         !IS_BROADWELL(dev_priv));
 219                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 220                                         IS_BDW_ULT(dev_priv));
 221                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
 222                                 /* WildcatPoint is LPT compatible */
 223                                 dev_priv->pch_type = PCH_LPT;
 224                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 225                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 226                                         !IS_BROADWELL(dev_priv));
 227                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 228                                         !IS_BDW_ULT(dev_priv));
 229                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 230                                 dev_priv->pch_type = PCH_SPT;
 231                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 232                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 233                                         !IS_KABYLAKE(dev_priv));
 234                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 235                                 dev_priv->pch_type = PCH_SPT;
 236                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 237                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 238                                         !IS_KABYLAKE(dev_priv));
 239                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 240                                 dev_priv->pch_type = PCH_KBP;
 241                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 242                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 243                                         !IS_KABYLAKE(dev_priv) &&
 244                                         !IS_COFFEELAKE(dev_priv));
 245                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 246                                 dev_priv->pch_type = PCH_CNP;
 247                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 248                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 249                                         !IS_COFFEELAKE(dev_priv));
 250                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 251                                 dev_priv->pch_type = PCH_CNP;
 252                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 253                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 254                                         !IS_COFFEELAKE(dev_priv));
 255                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 256                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 257                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 258                                     pch->subsystem_vendor ==
 259                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 260                                     pch->subsystem_device ==
 261                                             PCI_SUBDEVICE_ID_QEMU)) {
 262                                 dev_priv->pch_type =
 263                                         intel_virt_detect_pch(dev_priv);
 264                         } else
 265                                 continue;
 266
 267                         break;
 268                 }
 269         }
 270         if (!pch)
 271                 DRM_DEBUG_KMS("No PCH found.\n");
 272
 273         pci_dev_put(pch);
 274 }
 275
 276 static int i915_getparam(struct drm_device *dev, void *data,
 277                          struct drm_file *file_priv)
 278 {
 279         struct drm_i915_private *dev_priv = to_i915(dev);
 280         struct pci_dev *pdev = dev_priv->drm.pdev;
 281         drm_i915_getparam_t *param = data;
 282         int value;
 283
 284         switch (param->param) {
 285         case I915_PARAM_IRQ_ACTIVE:
 286         case I915_PARAM_ALLOW_BATCHBUFFER:
 287         case I915_PARAM_LAST_DISPATCH:
 288         case I915_PARAM_HAS_EXEC_CONSTANTS:
 289                 /* Reject all old ums/dri params. */
 290                 return -ENODEV;
 291         case I915_PARAM_CHIPSET_ID:
 292                 value = pdev->device;
 293                 break;
 294         case I915_PARAM_REVISION:
 295                 value = pdev->revision;
 296                 break;
 297         case I915_PARAM_NUM_FENCES_AVAIL:
 298                 value = dev_priv->num_fence_regs;
 299                 break;
 300         case I915_PARAM_HAS_OVERLAY:
 301                 value = dev_priv->overlay ? 1 : 0;
 302                 break;
 303         case I915_PARAM_HAS_BSD:
 304                 value = !!dev_priv->engine[VCS];
 305                 break;
 306         case I915_PARAM_HAS_BLT:
 307                 value = !!dev_priv->engine[BCS];
 308                 break;
 309         case I915_PARAM_HAS_VEBOX:
 310                 value = !!dev_priv->engine[VECS];
 311                 break;
 312         case I915_PARAM_HAS_BSD2:
 313                 value = !!dev_priv->engine[VCS2];
 314                 break;
 315         case I915_PARAM_HAS_LLC:
 316                 value = HAS_LLC(dev_priv);
 317                 break;
 318         case I915_PARAM_HAS_WT:
 319                 value = HAS_WT(dev_priv);
 320                 break;
 321         case I915_PARAM_HAS_ALIASING_PPGTT:
 322                 value = USES_PPGTT(dev_priv);
 323                 break;
 324         case I915_PARAM_HAS_SEMAPHORES:
 325                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 326                 break;
 327         case I915_PARAM_HAS_SECURE_BATCHES:
 328                 value = capable(CAP_SYS_ADMIN);
 329                 break;
 330         case I915_PARAM_CMD_PARSER_VERSION:
 331                 value = i915_cmd_parser_get_version(dev_priv);
 332                 break;
 333         case I915_PARAM_SUBSLICE_TOTAL:
 334                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 335                 if (!value)
 336                         return -ENODEV;
 337                 break;
 338         case I915_PARAM_EU_TOTAL:
 339                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 340                 if (!value)
 341                         return -ENODEV;
 342                 break;
 343         case I915_PARAM_HAS_GPU_RESET:
 344                 value = i915_modparams.enable_hangcheck &&
 345                         intel_has_gpu_reset(dev_priv);
 346                 if (value && intel_has_reset_engine(dev_priv))
 347                         value = 2;
 348                 break;
 349         case I915_PARAM_HAS_RESOURCE_STREAMER:
 350                 value = HAS_RESOURCE_STREAMER(dev_priv);
 351                 break;
 352         case I915_PARAM_HAS_POOLED_EU:
 353                 value = HAS_POOLED_EU(dev_priv);
 354                 break;
 355         case I915_PARAM_MIN_EU_IN_POOL:
 356                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 357                 break;
 358         case I915_PARAM_HUC_STATUS:
 359                 intel_runtime_pm_get(dev_priv);
 360                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 361                 intel_runtime_pm_put(dev_priv);
 362                 break;
 363         case I915_PARAM_MMAP_GTT_VERSION:
 364                 /* Though we've started our numbering from 1, and so class all
 365                  * earlier versions as 0, in effect their value is undefined as
 366                  * the ioctl will report EINVAL for the unknown param!
 367                  */
 368                 value = i915_gem_mmap_gtt_version();
 369                 break;
 370         case I915_PARAM_HAS_SCHEDULER:
 371                 value = 0;
 372                 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
 373                         value |= I915_SCHEDULER_CAP_ENABLED;
 374                         value |= I915_SCHEDULER_CAP_PRIORITY;
 375                         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv))
 376                                 value |= I915_SCHEDULER_CAP_PREEMPTION;
 377                 }
 378                 break;
 379
 380         case I915_PARAM_MMAP_VERSION:
 381                 /* Remember to bump this if the version changes! */
 382         case I915_PARAM_HAS_GEM:
 383         case I915_PARAM_HAS_PAGEFLIPPING:
 384         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 385         case I915_PARAM_HAS_RELAXED_FENCING:
 386         case I915_PARAM_HAS_COHERENT_RINGS:
 387         case I915_PARAM_HAS_RELAXED_DELTA:
 388         case I915_PARAM_HAS_GEN7_SOL_RESET:
 389         case I915_PARAM_HAS_WAIT_TIMEOUT:
 390         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 391         case I915_PARAM_HAS_PINNED_BATCHES:
 392         case I915_PARAM_HAS_EXEC_NO_RELOC:
 393         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 394         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 395         case I915_PARAM_HAS_EXEC_SOFTPIN:
 396         case I915_PARAM_HAS_EXEC_ASYNC:
 397         case I915_PARAM_HAS_EXEC_FENCE:
 398         case I915_PARAM_HAS_EXEC_CAPTURE:
 399         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 400         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 401                 /* For the time being all of these are always true;
 402                  * if some supported hardware does not have one of these
 403                  * features this value needs to be provided from
 404                  * INTEL_INFO(), a feature macro, or similar.
 405                  */
 406                 value = 1;
 407                 break;
 408         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 409                 value = intel_engines_has_context_isolation(dev_priv);
 410                 break;
 411         case I915_PARAM_SLICE_MASK:
 412                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 413                 if (!value)
 414                         return -ENODEV;
 415                 break;
 416         case I915_PARAM_SUBSLICE_MASK:
 417                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 418                 if (!value)
 419                         return -ENODEV;
 420                 break;
 421         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 422                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 423                 break;
 424         default:
 425                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 426                 return -EINVAL;
 427         }
 428
 429         if (put_user(value, param->value))
 430                 return -EFAULT;
 431
 432         return 0;
 433 }
 434
 435 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 436 {
 437         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 438         if (!dev_priv->bridge_dev) {
 439                 DRM_ERROR("bridge device not found\n");
 440                 return -1;
 441         }
 442         return 0;
 443 }
 444
 445 /* Allocate space for the MCH regs if needed, return nonzero on error */
 446 static int
 447 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 448 {
 449         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 450         u32 temp_lo, temp_hi = 0;
 451         u64 mchbar_addr;
 452         int ret;
 453
 454         if (INTEL_GEN(dev_priv) >= 4)
 455                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 456         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 457         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 458
 459         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 460 #ifdef CONFIG_PNP
 461         if (mchbar_addr &&
 462             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 463                 return 0;
 464 #endif
 465
 466         /* Get some space for it */
 467         dev_priv->mch_res.name = "i915 MCHBAR";
 468         dev_priv->mch_res.flags = IORESOURCE_MEM;
 469         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 470                                      &dev_priv->mch_res,
 471                                      MCHBAR_SIZE, MCHBAR_SIZE,
 472                                      PCIBIOS_MIN_MEM,
 473                                      0, pcibios_align_resource,
 474                                      dev_priv->bridge_dev);
 475         if (ret) {
 476                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 477                 dev_priv->mch_res.start = 0;
 478                 return ret;
 479         }
 480
 481         if (INTEL_GEN(dev_priv) >= 4)
 482                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 483                                        upper_32_bits(dev_priv->mch_res.start));
 484
 485         pci_write_config_dword(dev_priv->bridge_dev, reg,
 486                                lower_32_bits(dev_priv->mch_res.start));
 487         return 0;
 488 }
 489
 490 /* Setup MCHBAR if possible, return true if we should disable it again */
 491 static void
 492 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 493 {
 494         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 495         u32 temp;
 496         bool enabled;
 497
 498         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 499                 return;
 500
 501         dev_priv->mchbar_need_disable = false;
 502
 503         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 504                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 505                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 506         } else {
 507                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 508                 enabled = temp & 1;
 509         }
 510
 511         /* If it's already enabled, don't have to do anything */
 512         if (enabled)
 513                 return;
 514
 515         if (intel_alloc_mchbar_resource(dev_priv))
 516                 return;
 517
 518         dev_priv->mchbar_need_disable = true;
 519
 520         /* Space is allocated or reserved, so enable it. */
 521         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 522                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 523                                        temp | DEVEN_MCHBAR_EN);
 524         } else {
 525                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 526                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 527         }
 528 }
 529
 530 static void
 531 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 532 {
 533         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 534
 535         if (dev_priv->mchbar_need_disable) {
 536                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 537                         u32 deven_val;
 538
 539                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 540                                               &deven_val);
 541                         deven_val &= ~DEVEN_MCHBAR_EN;
 542                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 543                                                deven_val);
 544                 } else {
 545                         u32 mchbar_val;
 546
 547                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 548                                               &mchbar_val);
 549                         mchbar_val &= ~1;
 550                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 551                                                mchbar_val);
 552                 }
 553         }
 554
 555         if (dev_priv->mch_res.start)
 556                 release_resource(&dev_priv->mch_res);
 557 }
 558
 559 /* true = enable decode, false = disable decoder */
 560 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 561 {
 562         struct drm_i915_private *dev_priv = cookie;
 563
 564         intel_modeset_vga_set_state(dev_priv, state);
 565         if (state)
 566                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 567                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 568         else
 569                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 570 }
 571
 572 static int i915_resume_switcheroo(struct drm_device *dev);
 573 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 574
 575 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 576 {
 577         struct drm_device *dev = pci_get_drvdata(pdev);
 578         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 579
 580         if (state == VGA_SWITCHEROO_ON) {
 581                 pr_info("switched on\n");
 582                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 583                 /* i915 resume handler doesn't set to D0 */
 584                 pci_set_power_state(pdev, PCI_D0);
 585                 i915_resume_switcheroo(dev);
 586                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 587         } else {
 588                 pr_info("switched off\n");
 589                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 590                 i915_suspend_switcheroo(dev, pmm);
 591                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 592         }
 593 }
 594
 595 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 596 {
 597         struct drm_device *dev = pci_get_drvdata(pdev);
 598
 599         /*
 600          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 601          * locking inversion with the driver load path. And the access here is
 602          * completely racy anyway. So don't bother with locking for now.
 603          */
 604         return dev->open_count == 0;
 605 }
 606
 607 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 608         .set_gpu_state = i915_switcheroo_set_state,
 609         .reprobe = NULL,
 610         .can_switch = i915_switcheroo_can_switch,
 611 };
 612
 613 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 614 {
 615         /* Flush any outstanding unpin_work. */
 616         i915_gem_drain_workqueue(dev_priv);
 617
 618         mutex_lock(&dev_priv->drm.struct_mutex);
 619         intel_uc_fini_hw(dev_priv);
 620         i915_gem_cleanup_engines(dev_priv);
 621         i915_gem_contexts_fini(dev_priv);
 622         mutex_unlock(&dev_priv->drm.struct_mutex);
 623
 624         i915_gem_cleanup_userptr(dev_priv);
 625
 626         i915_gem_drain_freed_objects(dev_priv);
 627
 628         WARN_ON(!list_empty(&dev_priv->contexts.list));
 629 }
 630
 631 static int i915_load_modeset_init(struct drm_device *dev)
 632 {
 633         struct drm_i915_private *dev_priv = to_i915(dev);
 634         struct pci_dev *pdev = dev_priv->drm.pdev;
 635         int ret;
 636
 637         if (i915_inject_load_failure())
 638                 return -ENODEV;
 639
 640         intel_bios_init(dev_priv);
 641
 642         /* If we have > 1 VGA cards, then we need to arbitrate access
 643          * to the common VGA resources.
 644          *
 645          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 646          * then we do not take part in VGA arbitration and the
 647          * vga_client_register() fails with -ENODEV.
 648          */
 649         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 650         if (ret && ret != -ENODEV)
 651                 goto out;
 652
 653         intel_register_dsm_handler();
 654
 655         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 656         if (ret)
 657                 goto cleanup_vga_client;
 658
 659         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 660         intel_update_rawclk(dev_priv);
 661
 662         intel_power_domains_init_hw(dev_priv, false);
 663
 664         intel_csr_ucode_init(dev_priv);
 665
 666         ret = intel_irq_install(dev_priv);
 667         if (ret)
 668                 goto cleanup_csr;
 669
 670         intel_setup_gmbus(dev_priv);
 671
 672         /* Important: The output setup functions called by modeset_init need
 673          * working irqs for e.g. gmbus and dp aux transfers. */
 674         ret = intel_modeset_init(dev);
 675         if (ret)
 676                 goto cleanup_irq;
 677
 678         intel_uc_init_fw(dev_priv);
 679
 680         ret = i915_gem_init(dev_priv);
 681         if (ret)
 682                 goto cleanup_uc;
 683
 684         intel_setup_overlay(dev_priv);
 685
 686         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 687                 return 0;
 688
 689         ret = intel_fbdev_init(dev);
 690         if (ret)
 691                 goto cleanup_gem;
 692
 693         /* Only enable hotplug handling once the fbdev is fully set up. */
 694         intel_hpd_init(dev_priv);
 695
 696         return 0;
 697
 698 cleanup_gem:
 699         if (i915_gem_suspend(dev_priv))
 700                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 701         i915_gem_fini(dev_priv);
 702 cleanup_uc:
 703         intel_uc_fini_fw(dev_priv);
 704 cleanup_irq:
 705         drm_irq_uninstall(dev);
 706         intel_teardown_gmbus(dev_priv);
 707 cleanup_csr:
 708         intel_csr_ucode_fini(dev_priv);
 709         intel_power_domains_fini(dev_priv);
 710         vga_switcheroo_unregister_client(pdev);
 711 cleanup_vga_client:
 712         vga_client_register(pdev, NULL, NULL, NULL);
 713 out:
 714         return ret;
 715 }
 716
 717 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 718 {
 719         struct apertures_struct *ap;
 720         struct pci_dev *pdev = dev_priv->drm.pdev;
 721         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 722         bool primary;
 723         int ret;
 724
 725         ap = alloc_apertures(1);
 726         if (!ap)
 727                 return -ENOMEM;
 728
 729         ap->ranges[0].base = ggtt->mappable_base;
 730         ap->ranges[0].size = ggtt->mappable_end;
 731
 732         primary =
 733                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 734
 735         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 736
 737         kfree(ap);
 738
 739         return ret;
 740 }
 741
 742 #if !defined(CONFIG_VGA_CONSOLE)
 743 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 744 {
 745         return 0;
 746 }
 747 #elif !defined(CONFIG_DUMMY_CONSOLE)
 748 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 749 {
 750         return -ENODEV;
 751 }
 752 #else
 753 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 754 {
 755         int ret = 0;
 756
 757         DRM_INFO("Replacing VGA console driver\n");
 758
 759         console_lock();
 760         if (con_is_bound(&vga_con))
 761                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 762         if (ret == 0) {
 763                 ret = do_unregister_con_driver(&vga_con);
 764
 765                 /* Ignore "already unregistered". */
 766                 if (ret == -ENODEV)
 767                         ret = 0;
 768         }
 769         console_unlock();
 770
 771         return ret;
 772 }
 773 #endif
 774
 775 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 776 {
 777         /*
 778          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 779          * CHV x1 PHY (DP/HDMI D)
 780          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 781          */
 782         if (IS_CHERRYVIEW(dev_priv)) {
 783                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 784                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 785         } else if (IS_VALLEYVIEW(dev_priv)) {
 786                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 787         }
 788 }
 789
 790 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 791 {
 792         /*
 793          * The i915 workqueue is primarily used for batched retirement of
 794          * requests (and thus managing bo) once the task has been completed
 795          * by the GPU. i915_gem_retire_requests() is called directly when we
 796          * need high-priority retirement, such as waiting for an explicit
 797          * bo.
 798          *
 799          * It is also used for periodic low-priority events, such as
 800          * idle-timers and recording error state.
 801          *
 802          * All tasks on the workqueue are expected to acquire the dev mutex
 803          * so there is no point in running more than one instance of the
 804          * workqueue at any time.  Use an ordered one.
 805          */
 806         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 807         if (dev_priv->wq == NULL)
 808                 goto out_err;
 809
 810         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 811         if (dev_priv->hotplug.dp_wq == NULL)
 812                 goto out_free_wq;
 813
 814         return 0;
 815
 816 out_free_wq:
 817         destroy_workqueue(dev_priv->wq);
 818 out_err:
 819         DRM_ERROR("Failed to allocate workqueues.\n");
 820
 821         return -ENOMEM;
 822 }
 823
 824 static void i915_engines_cleanup(struct drm_i915_private *i915)
 825 {
 826         struct intel_engine_cs *engine;
 827         enum intel_engine_id id;
 828
 829         for_each_engine(engine, i915, id)
 830                 kfree(engine);
 831 }
 832
 833 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 834 {
 835         destroy_workqueue(dev_priv->hotplug.dp_wq);
 836         destroy_workqueue(dev_priv->wq);
 837 }
 838
 839 /*
 840  * We don't keep the workarounds for pre-production hardware, so we expect our
 841  * driver to fail on these machines in one way or another. A little warning on
 842  * dmesg may help both the user and the bug triagers.
 843  *
 844  * Our policy for removing pre-production workarounds is to keep the
 845  * current gen workarounds as a guide to the bring-up of the next gen
 846  * (workarounds have a habit of persisting!). Anything older than that
 847  * should be removed along with the complications they introduce.
 848  */
 849 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 850 {
 851         bool pre = false;
 852
 853         pre |= IS_HSW_EARLY_SDV(dev_priv);
 854         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 855         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 856
 857         if (pre) {
 858                 DRM_ERROR("This is a pre-production stepping. "
 859                           "It may not be fully functional.\n");
 860                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 861         }
 862 }
 863
 864 /**
 865  * i915_driver_init_early - setup state not requiring device access
 866  * @dev_priv: device private
 867  *
 868  * Initialize everything that is a "SW-only" state, that is state not
 869  * requiring accessing the device or exposing the driver via kernel internal
 870  * or userspace interfaces. Example steps belonging here: lock initialization,
 871  * system memory allocation, setting up device specific attributes and
 872  * function hooks not requiring accessing the device.
 873  */
 874 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 875                                   const struct pci_device_id *ent)
 876 {
 877         const struct intel_device_info *match_info =
 878                 (struct intel_device_info *)ent->driver_data;
 879         struct intel_device_info *device_info;
 880         int ret = 0;
 881
 882         if (i915_inject_load_failure())
 883                 return -ENODEV;
 884
 885         /* Setup the write-once "constant" device info */
 886         device_info = mkwrite_device_info(dev_priv);
 887         memcpy(device_info, match_info, sizeof(*device_info));
 888         device_info->device_id = dev_priv->drm.pdev->device;
 889
 890         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 891                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 892         device_info->platform_mask = BIT(device_info->platform);
 893
 894         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 895         device_info->gen_mask = BIT(device_info->gen - 1);
 896
 897         spin_lock_init(&dev_priv->irq_lock);
 898         spin_lock_init(&dev_priv->gpu_error.lock);
 899         mutex_init(&dev_priv->backlight_lock);
 900         spin_lock_init(&dev_priv->uncore.lock);
 901
 902         mutex_init(&dev_priv->sb_lock);
 903         mutex_init(&dev_priv->modeset_restore_lock);
 904         mutex_init(&dev_priv->av_mutex);
 905         mutex_init(&dev_priv->wm.wm_mutex);
 906         mutex_init(&dev_priv->pps_mutex);
 907
 908         intel_uc_init_early(dev_priv);
 909         i915_memcpy_init_early(dev_priv);
 910
 911         ret = i915_workqueues_init(dev_priv);
 912         if (ret < 0)
 913                 goto err_engines;
 914
 915         /* This must be called before any calls to HAS_PCH_* */
 916         intel_detect_pch(dev_priv);
 917
 918         intel_pm_setup(dev_priv);
 919         intel_init_dpio(dev_priv);
 920         intel_power_domains_init(dev_priv);
 921         intel_irq_init(dev_priv);
 922         intel_hangcheck_init(dev_priv);
 923         intel_init_display_hooks(dev_priv);
 924         intel_init_clock_gating_hooks(dev_priv);
 925         intel_init_audio_hooks(dev_priv);
 926         ret = i915_gem_load_init(dev_priv);
 927         if (ret < 0)
 928                 goto err_irq;
 929
 930         intel_display_crc_init(dev_priv);
 931
 932         intel_device_info_dump(dev_priv);
 933
 934         intel_detect_preproduction_hw(dev_priv);
 935
 936         return 0;
 937
 938 err_irq:
 939         intel_irq_fini(dev_priv);
 940         i915_workqueues_cleanup(dev_priv);
 941 err_engines:
 942         i915_engines_cleanup(dev_priv);
 943         return ret;
 944 }
 945
 946 /**
 947  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 948  * @dev_priv: device private
 949  */
 950 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 951 {
 952         i915_gem_load_cleanup(dev_priv);
 953         intel_irq_fini(dev_priv);
 954         i915_workqueues_cleanup(dev_priv);
 955         i915_engines_cleanup(dev_priv);
 956 }
 957
 958 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 959 {
 960         struct pci_dev *pdev = dev_priv->drm.pdev;
 961         int mmio_bar;
 962         int mmio_size;
 963
 964         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 965         /*
 966          * Before gen4, the registers and the GTT are behind different BARs.
 967          * However, from gen4 onwards, the registers and the GTT are shared
 968          * in the same BAR, so we want to restrict this ioremap from
 969          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 970          * the register BAR remains the same size for all the earlier
 971          * generations up to Ironlake.
 972          */
 973         if (INTEL_GEN(dev_priv) < 5)
 974                 mmio_size = 512 * 1024;
 975         else
 976                 mmio_size = 2 * 1024 * 1024;
 977         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 978         if (dev_priv->regs == NULL) {
 979                 DRM_ERROR("failed to map registers\n");
 980
 981                 return -EIO;
 982         }
 983
 984         /* Try to make sure MCHBAR is enabled before poking at it */
 985         intel_setup_mchbar(dev_priv);
 986
 987         return 0;
 988 }
 989
 990 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 991 {
 992         struct pci_dev *pdev = dev_priv->drm.pdev;
 993
 994         intel_teardown_mchbar(dev_priv);
 995         pci_iounmap(pdev, dev_priv->regs);
 996 }
 997
 998 /**
 999  * i915_driver_init_mmio - setup device MMIO
1000  * @dev_priv: device private
1001  *
1002  * Setup minimal device state necessary for MMIO accesses later in the
1003  * initialization sequence. The setup here should avoid any other device-wide
1004  * side effects or exposing the driver via kernel internal or user space
1005  * interfaces.
1006  */
1007 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1008 {
1009         int ret;
1010
1011         if (i915_inject_load_failure())
1012                 return -ENODEV;
1013
1014         if (i915_get_bridge_dev(dev_priv))
1015                 return -EIO;
1016
1017         ret = i915_mmio_setup(dev_priv);
1018         if (ret < 0)
1019                 goto err_bridge;
1020
1021         intel_uncore_init(dev_priv);
1022
1023         intel_uc_init_mmio(dev_priv);
1024
1025         ret = intel_engines_init_mmio(dev_priv);
1026         if (ret)
1027                 goto err_uncore;
1028
1029         i915_gem_init_mmio(dev_priv);
1030
1031         return 0;
1032
1033 err_uncore:
1034         intel_uncore_fini(dev_priv);
1035 err_bridge:
1036         pci_dev_put(dev_priv->bridge_dev);
1037
1038         return ret;
1039 }
1040
1041 /**
1042  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1043  * @dev_priv: device private
1044  */
1045 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1046 {
1047         intel_uncore_fini(dev_priv);
1048         i915_mmio_cleanup(dev_priv);
1049         pci_dev_put(dev_priv->bridge_dev);
1050 }
1051
1052 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1053 {
1054         /*
1055          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1056          * user's requested state against the hardware/driver capabilities.  We
1057          * do this now so that we can print out any log messages once rather
1058          * than every time we check intel_enable_ppgtt().
1059          */
1060         i915_modparams.enable_ppgtt =
1061                 intel_sanitize_enable_ppgtt(dev_priv,
1062                                             i915_modparams.enable_ppgtt);
1063         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1064
1065         intel_uc_sanitize_options(dev_priv);
1066
1067         intel_gvt_sanitize_options(dev_priv);
1068 }
1069
1070 /**
1071  * i915_driver_init_hw - setup state requiring device access
1072  * @dev_priv: device private
1073  *
1074  * Setup state that requires accessing the device, but doesn't require
1075  * exposing the driver via kernel internal or userspace interfaces.
1076  */
1077 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1078 {
1079         struct pci_dev *pdev = dev_priv->drm.pdev;
1080         int ret;
1081
1082         if (i915_inject_load_failure())
1083                 return -ENODEV;
1084
1085         intel_device_info_runtime_init(dev_priv);
1086
1087         intel_sanitize_options(dev_priv);
1088
1089         i915_perf_init(dev_priv);
1090
1091         ret = i915_ggtt_probe_hw(dev_priv);
1092         if (ret)
1093                 return ret;
1094
1095         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1096          * otherwise the vga fbdev driver falls over. */
1097         ret = i915_kick_out_firmware_fb(dev_priv);
1098         if (ret) {
1099                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1100                 goto out_ggtt;
1101         }
1102
1103         ret = i915_kick_out_vgacon(dev_priv);
1104         if (ret) {
1105                 DRM_ERROR("failed to remove conflicting VGA console\n");
1106                 goto out_ggtt;
1107         }
1108
1109         ret = i915_ggtt_init_hw(dev_priv);
1110         if (ret)
1111                 return ret;
1112
1113         ret = i915_ggtt_enable_hw(dev_priv);
1114         if (ret) {
1115                 DRM_ERROR("failed to enable GGTT\n");
1116                 goto out_ggtt;
1117         }
1118
1119         pci_set_master(pdev);
1120
1121         /* overlay on gen2 is broken and can't address above 1G */
1122         if (IS_GEN2(dev_priv)) {
1123                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1124                 if (ret) {
1125                         DRM_ERROR("failed to set DMA mask\n");
1126
1127                         goto out_ggtt;
1128                 }
1129         }
1130
1131         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1132          * using 32bit addressing, overwriting memory if HWS is located
1133          * above 4GB.
1134          *
1135          * The documentation also mentions an issue with undefined
1136          * behaviour if any general state is accessed within a page above 4GB,
1137          * which also needs to be handled carefully.
1138          */
1139         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1140                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1141
1142                 if (ret) {
1143                         DRM_ERROR("failed to set DMA mask\n");
1144
1145                         goto out_ggtt;
1146                 }
1147         }
1148
1149         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1150                            PM_QOS_DEFAULT_VALUE);
1151
1152         intel_uncore_sanitize(dev_priv);
1153
1154         intel_opregion_setup(dev_priv);
1155
1156         i915_gem_load_init_fences(dev_priv);
1157
1158         /* On the 945G/GM, the chipset reports the MSI capability on the
1159          * integrated graphics even though the support isn't actually there
1160          * according to the published specs.  It doesn't appear to function
1161          * correctly in testing on 945G.
1162          * This may be a side effect of MSI having been made available for PEG
1163          * and the registers being closely associated.
1164          *
1165          * According to chipset errata, on the 965GM, MSI interrupts may
1166          * be lost or delayed, and was defeatured. MSI interrupts seem to
1167          * get lost on g4x as well, and interrupt delivery seems to stay
1168          * properly dead afterwards. So we'll just disable them for all
1169          * pre-gen5 chipsets.
1170          */
1171         if (INTEL_GEN(dev_priv) >= 5) {
1172                 if (pci_enable_msi(pdev) < 0)
1173                         DRM_DEBUG_DRIVER("can't enable MSI");
1174         }
1175
1176         ret = intel_gvt_init(dev_priv);
1177         if (ret)
1178                 goto out_ggtt;
1179
1180         return 0;
1181
1182 out_ggtt:
1183         i915_ggtt_cleanup_hw(dev_priv);
1184
1185         return ret;
1186 }
1187
1188 /**
1189  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1190  * @dev_priv: device private
1191  */
1192 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1193 {
1194         struct pci_dev *pdev = dev_priv->drm.pdev;
1195
1196         i915_perf_fini(dev_priv);
1197
1198         if (pdev->msi_enabled)
1199                 pci_disable_msi(pdev);
1200
1201         pm_qos_remove_request(&dev_priv->pm_qos);
1202         i915_ggtt_cleanup_hw(dev_priv);
1203 }
1204
1205 /**
1206  * i915_driver_register - register the driver with the rest of the system
1207  * @dev_priv: device private
1208  *
1209  * Perform any steps necessary to make the driver available via kernel
1210  * internal or userspace interfaces.
1211  */
1212 static void i915_driver_register(struct drm_i915_private *dev_priv)
1213 {
1214         struct drm_device *dev = &dev_priv->drm;
1215
1216         i915_gem_shrinker_register(dev_priv);
1217         i915_pmu_register(dev_priv);
1218
1219         /*
1220          * Notify a valid surface after modesetting,
1221          * when running inside a VM.
1222          */
1223         if (intel_vgpu_active(dev_priv))
1224                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1225
1226         /* Reveal our presence to userspace */
1227         if (drm_dev_register(dev, 0) == 0) {
1228                 i915_debugfs_register(dev_priv);
1229                 i915_guc_log_register(dev_priv);
1230                 i915_setup_sysfs(dev_priv);
1231
1232                 /* Depends on sysfs having been initialized */
1233                 i915_perf_register(dev_priv);
1234         } else
1235                 DRM_ERROR("Failed to register driver for userspace access!\n");
1236
1237         if (INTEL_INFO(dev_priv)->num_pipes) {
1238                 /* Must be done after probing outputs */
1239                 intel_opregion_register(dev_priv);
1240                 acpi_video_register();
1241         }
1242
1243         if (IS_GEN5(dev_priv))
1244                 intel_gpu_ips_init(dev_priv);
1245
1246         intel_audio_init(dev_priv);
1247
1248         /*
1249          * Some ports require correctly set-up hpd registers for detection to
1250          * work properly (leading to ghost connected connector status), e.g. VGA
1251          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1252          * irqs are fully enabled. We do it last so that the async config
1253          * cannot run before the connectors are registered.
1254          */
1255         intel_fbdev_initial_config_async(dev);
1256
1257         /*
1258          * We need to coordinate the hotplugs with the asynchronous fbdev
1259          * configuration, for which we use the fbdev->async_cookie.
1260          */
1261         if (INTEL_INFO(dev_priv)->num_pipes)
1262                 drm_kms_helper_poll_init(dev);
1263 }
1264
1265 /**
1266  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1267  * @dev_priv: device private
1268  */
1269 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1270 {
1271         intel_fbdev_unregister(dev_priv);
1272         intel_audio_deinit(dev_priv);
1273
1274         /*
1275          * After flushing the fbdev (incl. a late async config which will
1276          * have delayed queuing of a hotplug event), then flush the hotplug
1277          * events.
1278          */
1279         drm_kms_helper_poll_fini(&dev_priv->drm);
1280
1281         intel_gpu_ips_teardown();
1282         acpi_video_unregister();
1283         intel_opregion_unregister(dev_priv);
1284
1285         i915_perf_unregister(dev_priv);
1286         i915_pmu_unregister(dev_priv);
1287
1288         i915_teardown_sysfs(dev_priv);
1289         i915_guc_log_unregister(dev_priv);
1290         drm_dev_unregister(&dev_priv->drm);
1291
1292         i915_gem_shrinker_unregister(dev_priv);
1293 }
1294
1295 /**
1296  * i915_driver_load - setup chip and create an initial config
1297  * @pdev: PCI device
1298  * @ent: matching PCI ID entry
1299  *
1300  * The driver load routine has to do several things:
1301  *   - drive output discovery via intel_modeset_init()
1302  *   - initialize the memory manager
1303  *   - allocate initial config memory
1304  *   - setup the DRM framebuffer with the allocated memory
1305  */
1306 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1307 {
1308         const struct intel_device_info *match_info =
1309                 (struct intel_device_info *)ent->driver_data;
1310         struct drm_i915_private *dev_priv;
1311         int ret;
1312
1313         /* Enable nuclear pageflip on ILK+ */
1314         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1315                 driver.driver_features &= ~DRIVER_ATOMIC;
1316
1317         ret = -ENOMEM;
1318         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1319         if (dev_priv)
1320                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1321         if (ret) {
1322                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1323                 goto out_free;
1324         }
1325
1326         dev_priv->drm.pdev = pdev;
1327         dev_priv->drm.dev_private = dev_priv;
1328
1329         ret = pci_enable_device(pdev);
1330         if (ret)
1331                 goto out_fini;
1332
1333         pci_set_drvdata(pdev, &dev_priv->drm);
1334         /*
1335          * Disable the system suspend direct complete optimization, which can
1336          * leave the device suspended skipping the driver's suspend handlers
1337          * if the device was already runtime suspended. This is needed due to
1338          * the difference in our runtime and system suspend sequence and
1339          * becaue the HDA driver may require us to enable the audio power
1340          * domain during system suspend.
1341          */
1342         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1343
1344         ret = i915_driver_init_early(dev_priv, ent);
1345         if (ret < 0)
1346                 goto out_pci_disable;
1347
1348         intel_runtime_pm_get(dev_priv);
1349
1350         ret = i915_driver_init_mmio(dev_priv);
1351         if (ret < 0)
1352                 goto out_runtime_pm_put;
1353
1354         ret = i915_driver_init_hw(dev_priv);
1355         if (ret < 0)
1356                 goto out_cleanup_mmio;
1357
1358         /*
1359          * TODO: move the vblank init and parts of modeset init steps into one
1360          * of the i915_driver_init_/i915_driver_register functions according
1361          * to the role/effect of the given init step.
1362          */
1363         if (INTEL_INFO(dev_priv)->num_pipes) {
1364                 ret = drm_vblank_init(&dev_priv->drm,
1365                                       INTEL_INFO(dev_priv)->num_pipes);
1366                 if (ret)
1367                         goto out_cleanup_hw;
1368         }
1369
1370         ret = i915_load_modeset_init(&dev_priv->drm);
1371         if (ret < 0)
1372                 goto out_cleanup_hw;
1373
1374         i915_driver_register(dev_priv);
1375
1376         intel_runtime_pm_enable(dev_priv);
1377
1378         intel_init_ipc(dev_priv);
1379
1380         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1381                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1382         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1383                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1384
1385         intel_runtime_pm_put(dev_priv);
1386
1387         return 0;
1388
1389 out_cleanup_hw:
1390         i915_driver_cleanup_hw(dev_priv);
1391 out_cleanup_mmio:
1392         i915_driver_cleanup_mmio(dev_priv);
1393 out_runtime_pm_put:
1394         intel_runtime_pm_put(dev_priv);
1395         i915_driver_cleanup_early(dev_priv);
1396 out_pci_disable:
1397         pci_disable_device(pdev);
1398 out_fini:
1399         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1400         drm_dev_fini(&dev_priv->drm);
1401 out_free:
1402         kfree(dev_priv);
1403         return ret;
1404 }
1405
1406 void i915_driver_unload(struct drm_device *dev)
1407 {
1408         struct drm_i915_private *dev_priv = to_i915(dev);
1409         struct pci_dev *pdev = dev_priv->drm.pdev;
1410
1411         i915_driver_unregister(dev_priv);
1412
1413         if (i915_gem_suspend(dev_priv))
1414                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1415
1416         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1417
1418         drm_atomic_helper_shutdown(dev);
1419
1420         intel_gvt_cleanup(dev_priv);
1421
1422         intel_modeset_cleanup(dev);
1423
1424         /*
1425          * free the memory space allocated for the child device
1426          * config parsed from VBT
1427          */
1428         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1429                 kfree(dev_priv->vbt.child_dev);
1430                 dev_priv->vbt.child_dev = NULL;
1431                 dev_priv->vbt.child_dev_num = 0;
1432         }
1433         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1434         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1435         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1436         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1437
1438         vga_switcheroo_unregister_client(pdev);
1439         vga_client_register(pdev, NULL, NULL, NULL);
1440
1441         intel_csr_ucode_fini(dev_priv);
1442
1443         /* Free error state after interrupts are fully disabled. */
1444         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1445         i915_reset_error_state(dev_priv);
1446
1447         i915_gem_fini(dev_priv);
1448         intel_uc_fini_fw(dev_priv);
1449         intel_fbc_cleanup_cfb(dev_priv);
1450
1451         intel_power_domains_fini(dev_priv);
1452
1453         i915_driver_cleanup_hw(dev_priv);
1454         i915_driver_cleanup_mmio(dev_priv);
1455
1456         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1457 }
1458
1459 static void i915_driver_release(struct drm_device *dev)
1460 {
1461         struct drm_i915_private *dev_priv = to_i915(dev);
1462
1463         i915_driver_cleanup_early(dev_priv);
1464         drm_dev_fini(&dev_priv->drm);
1465
1466         kfree(dev_priv);
1467 }
1468
1469 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1470 {
1471         struct drm_i915_private *i915 = to_i915(dev);
1472         int ret;
1473
1474         ret = i915_gem_open(i915, file);
1475         if (ret)
1476                 return ret;
1477
1478         return 0;
1479 }
1480
1481 /**
1482  * i915_driver_lastclose - clean up after all DRM clients have exited
1483  * @dev: DRM device
1484  *
1485  * Take care of cleaning up after all DRM clients have exited.  In the
1486  * mode setting case, we want to restore the kernel's initial mode (just
1487  * in case the last client left us in a bad state).
1488  *
1489  * Additionally, in the non-mode setting case, we'll tear down the GTT
1490  * and DMA structures, since the kernel won't be using them, and clea
1491  * up any GEM state.
1492  */
1493 static void i915_driver_lastclose(struct drm_device *dev)
1494 {
1495         intel_fbdev_restore_mode(dev);
1496         vga_switcheroo_process_delayed_switch();
1497 }
1498
1499 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1500 {
1501         struct drm_i915_file_private *file_priv = file->driver_priv;
1502
1503         mutex_lock(&dev->struct_mutex);
1504         i915_gem_context_close(file);
1505         i915_gem_release(dev, file);
1506         mutex_unlock(&dev->struct_mutex);
1507
1508         kfree(file_priv);
1509 }
1510
1511 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1512 {
1513         struct drm_device *dev = &dev_priv->drm;
1514         struct intel_encoder *encoder;
1515
1516         drm_modeset_lock_all(dev);
1517         for_each_intel_encoder(dev, encoder)
1518                 if (encoder->suspend)
1519                         encoder->suspend(encoder);
1520         drm_modeset_unlock_all(dev);
1521 }
1522
1523 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1524                               bool rpm_resume);
1525 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1526
1527 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1528 {
1529 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1530         if (acpi_target_system_state() < ACPI_STATE_S3)
1531                 return true;
1532 #endif
1533         return false;
1534 }
1535
1536 static int i915_drm_suspend(struct drm_device *dev)
1537 {
1538         struct drm_i915_private *dev_priv = to_i915(dev);
1539         struct pci_dev *pdev = dev_priv->drm.pdev;
1540         pci_power_t opregion_target_state;
1541         int error;
1542
1543         /* ignore lid events during suspend */
1544         mutex_lock(&dev_priv->modeset_restore_lock);
1545         dev_priv->modeset_restore = MODESET_SUSPENDED;
1546         mutex_unlock(&dev_priv->modeset_restore_lock);
1547
1548         disable_rpm_wakeref_asserts(dev_priv);
1549
1550         /* We do a lot of poking in a lot of registers, make sure they work
1551          * properly. */
1552         intel_display_set_init_power(dev_priv, true);
1553
1554         drm_kms_helper_poll_disable(dev);
1555
1556         pci_save_state(pdev);
1557
1558         error = i915_gem_suspend(dev_priv);
1559         if (error) {
1560                 dev_err(&pdev->dev,
1561                         "GEM idle failed, resume might fail\n");
1562                 goto out;
1563         }
1564
1565         intel_display_suspend(dev);
1566
1567         intel_dp_mst_suspend(dev);
1568
1569         intel_runtime_pm_disable_interrupts(dev_priv);
1570         intel_hpd_cancel_work(dev_priv);
1571
1572         intel_suspend_encoders(dev_priv);
1573
1574         intel_suspend_hw(dev_priv);
1575
1576         i915_gem_suspend_gtt_mappings(dev_priv);
1577
1578         i915_save_state(dev_priv);
1579
1580         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1581         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1582
1583         intel_uncore_suspend(dev_priv);
1584         intel_opregion_unregister(dev_priv);
1585
1586         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1587
1588         dev_priv->suspend_count++;
1589
1590         intel_csr_ucode_suspend(dev_priv);
1591
1592 out:
1593         enable_rpm_wakeref_asserts(dev_priv);
1594
1595         return error;
1596 }
1597
1598 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1599 {
1600         struct drm_i915_private *dev_priv = to_i915(dev);
1601         struct pci_dev *pdev = dev_priv->drm.pdev;
1602         bool fw_csr;
1603         int ret;
1604
1605         disable_rpm_wakeref_asserts(dev_priv);
1606
1607         intel_display_set_init_power(dev_priv, false);
1608
1609         fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1610                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1611         /*
1612          * In case of firmware assisted context save/restore don't manually
1613          * deinit the power domains. This also means the CSR/DMC firmware will
1614          * stay active, it will power down any HW resources as required and
1615          * also enable deeper system power states that would be blocked if the
1616          * firmware was inactive.
1617          */
1618         if (!fw_csr)
1619                 intel_power_domains_suspend(dev_priv);
1620
1621         ret = 0;
1622         if (IS_GEN9_LP(dev_priv))
1623                 bxt_enable_dc9(dev_priv);
1624         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1625                 hsw_enable_pc8(dev_priv);
1626         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1627                 ret = vlv_suspend_complete(dev_priv);
1628
1629         if (ret) {
1630                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1631                 if (!fw_csr)
1632                         intel_power_domains_init_hw(dev_priv, true);
1633
1634                 goto out;
1635         }
1636
1637         pci_disable_device(pdev);
1638         /*
1639          * During hibernation on some platforms the BIOS may try to access
1640          * the device even though it's already in D3 and hang the machine. So
1641          * leave the device in D0 on those platforms and hope the BIOS will
1642          * power down the device properly. The issue was seen on multiple old
1643          * GENs with different BIOS vendors, so having an explicit blacklist
1644          * is inpractical; apply the workaround on everything pre GEN6. The
1645          * platforms where the issue was seen:
1646          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1647          * Fujitsu FSC S7110
1648          * Acer Aspire 1830T
1649          */
1650         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1651                 pci_set_power_state(pdev, PCI_D3hot);
1652
1653         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1654
1655 out:
1656         enable_rpm_wakeref_asserts(dev_priv);
1657
1658         return ret;
1659 }
1660
1661 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1662 {
1663         int error;
1664
1665         if (!dev) {
1666                 DRM_ERROR("dev: %p\n", dev);
1667                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1668                 return -ENODEV;
1669         }
1670
1671         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1672                          state.event != PM_EVENT_FREEZE))
1673                 return -EINVAL;
1674
1675         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1676                 return 0;
1677
1678         error = i915_drm_suspend(dev);
1679         if (error)
1680                 return error;
1681
1682         return i915_drm_suspend_late(dev, false);
1683 }
1684
1685 static int i915_drm_resume(struct drm_device *dev)
1686 {
1687         struct drm_i915_private *dev_priv = to_i915(dev);
1688         int ret;
1689
1690         disable_rpm_wakeref_asserts(dev_priv);
1691         intel_sanitize_gt_powersave(dev_priv);
1692
1693         ret = i915_ggtt_enable_hw(dev_priv);
1694         if (ret)
1695                 DRM_ERROR("failed to re-enable GGTT\n");
1696
1697         intel_csr_ucode_resume(dev_priv);
1698
1699         i915_restore_state(dev_priv);
1700         intel_pps_unlock_regs_wa(dev_priv);
1701         intel_opregion_setup(dev_priv);
1702
1703         intel_init_pch_refclk(dev_priv);
1704
1705         /*
1706          * Interrupts have to be enabled before any batches are run. If not the
1707          * GPU will hang. i915_gem_init_hw() will initiate batches to
1708          * update/restore the context.
1709          *
1710          * drm_mode_config_reset() needs AUX interrupts.
1711          *
1712          * Modeset enabling in intel_modeset_init_hw() also needs working
1713          * interrupts.
1714          */
1715         intel_runtime_pm_enable_interrupts(dev_priv);
1716
1717         drm_mode_config_reset(dev);
1718
1719         i915_gem_resume(dev_priv);
1720
1721         intel_modeset_init_hw(dev);
1722         intel_init_clock_gating(dev_priv);
1723
1724         spin_lock_irq(&dev_priv->irq_lock);
1725         if (dev_priv->display.hpd_irq_setup)
1726                 dev_priv->display.hpd_irq_setup(dev_priv);
1727         spin_unlock_irq(&dev_priv->irq_lock);
1728
1729         intel_dp_mst_resume(dev);
1730
1731         intel_display_resume(dev);
1732
1733         drm_kms_helper_poll_enable(dev);
1734
1735         /*
1736          * ... but also need to make sure that hotplug processing
1737          * doesn't cause havoc. Like in the driver load code we don't
1738          * bother with the tiny race here where we might loose hotplug
1739          * notifications.
1740          * */
1741         intel_hpd_init(dev_priv);
1742
1743         intel_opregion_register(dev_priv);
1744
1745         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1746
1747         mutex_lock(&dev_priv->modeset_restore_lock);
1748         dev_priv->modeset_restore = MODESET_DONE;
1749         mutex_unlock(&dev_priv->modeset_restore_lock);
1750
1751         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1752
1753         enable_rpm_wakeref_asserts(dev_priv);
1754
1755         return 0;
1756 }
1757
1758 static int i915_drm_resume_early(struct drm_device *dev)
1759 {
1760         struct drm_i915_private *dev_priv = to_i915(dev);
1761         struct pci_dev *pdev = dev_priv->drm.pdev;
1762         int ret;
1763
1764         /*
1765          * We have a resume ordering issue with the snd-hda driver also
1766          * requiring our device to be power up. Due to the lack of a
1767          * parent/child relationship we currently solve this with an early
1768          * resume hook.
1769          *
1770          * FIXME: This should be solved with a special hdmi sink device or
1771          * similar so that power domains can be employed.
1772          */
1773
1774         /*
1775          * Note that we need to set the power state explicitly, since we
1776          * powered off the device during freeze and the PCI core won't power
1777          * it back up for us during thaw. Powering off the device during
1778          * freeze is not a hard requirement though, and during the
1779          * suspend/resume phases the PCI core makes sure we get here with the
1780          * device powered on. So in case we change our freeze logic and keep
1781          * the device powered we can also remove the following set power state
1782          * call.
1783          */
1784         ret = pci_set_power_state(pdev, PCI_D0);
1785         if (ret) {
1786                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1787                 goto out;
1788         }
1789
1790         /*
1791          * Note that pci_enable_device() first enables any parent bridge
1792          * device and only then sets the power state for this device. The
1793          * bridge enabling is a nop though, since bridge devices are resumed
1794          * first. The order of enabling power and enabling the device is
1795          * imposed by the PCI core as described above, so here we preserve the
1796          * same order for the freeze/thaw phases.
1797          *
1798          * TODO: eventually we should remove pci_disable_device() /
1799          * pci_enable_enable_device() from suspend/resume. Due to how they
1800          * depend on the device enable refcount we can't anyway depend on them
1801          * disabling/enabling the device.
1802          */
1803         if (pci_enable_device(pdev)) {
1804                 ret = -EIO;
1805                 goto out;
1806         }
1807
1808         pci_set_master(pdev);
1809
1810         disable_rpm_wakeref_asserts(dev_priv);
1811
1812         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1813                 ret = vlv_resume_prepare(dev_priv, false);
1814         if (ret)
1815                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1816                           ret);
1817
1818         intel_uncore_resume_early(dev_priv);
1819
1820         if (IS_GEN9_LP(dev_priv)) {
1821                 if (!dev_priv->suspended_to_idle)
1822                         gen9_sanitize_dc_state(dev_priv);
1823                 bxt_disable_dc9(dev_priv);
1824         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1825                 hsw_disable_pc8(dev_priv);
1826         }
1827
1828         intel_uncore_sanitize(dev_priv);
1829
1830         if (IS_GEN9_LP(dev_priv) ||
1831             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1832                 intel_power_domains_init_hw(dev_priv, true);
1833
1834         i915_gem_sanitize(dev_priv);
1835
1836         enable_rpm_wakeref_asserts(dev_priv);
1837
1838 out:
1839         dev_priv->suspended_to_idle = false;
1840
1841         return ret;
1842 }
1843
1844 static int i915_resume_switcheroo(struct drm_device *dev)
1845 {
1846         int ret;
1847
1848         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1849                 return 0;
1850
1851         ret = i915_drm_resume_early(dev);
1852         if (ret)
1853                 return ret;
1854
1855         return i915_drm_resume(dev);
1856 }
1857
1858 /**
1859  * i915_reset - reset chip after a hang
1860  * @i915: #drm_i915_private to reset
1861  * @flags: Instructions
1862  *
1863  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1864  * on failure.
1865  *
1866  * Caller must hold the struct_mutex.
1867  *
1868  * Procedure is fairly simple:
1869  *   - reset the chip using the reset reg
1870  *   - re-init context state
1871  *   - re-init hardware status page
1872  *   - re-init ring buffer
1873  *   - re-init interrupt state
1874  *   - re-init display
1875  */
1876 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1877 {
1878         struct i915_gpu_error *error = &i915->gpu_error;
1879         int ret;
1880         int i;
1881
1882         might_sleep();
1883         lockdep_assert_held(&i915->drm.struct_mutex);
1884         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1885
1886         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1887                 return;
1888
1889         /* Clear any previous failed attempts at recovery. Time to try again. */
1890         if (!i915_gem_unset_wedged(i915))
1891                 goto wakeup;
1892
1893         if (!(flags & I915_RESET_QUIET))
1894                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1895         error->reset_count++;
1896
1897         disable_irq(i915->drm.irq);
1898         ret = i915_gem_reset_prepare(i915);
1899         if (ret) {
1900                 DRM_ERROR("GPU recovery failed\n");
1901                 intel_gpu_reset(i915, ALL_ENGINES);
1902                 goto error;
1903         }
1904
1905         if (!intel_has_gpu_reset(i915)) {
1906                 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1907                 goto error;
1908         }
1909
1910         for (i = 0; i < 3; i++) {
1911                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1912                 if (ret == 0)
1913                         break;
1914
1915                 msleep(100);
1916         }
1917         if (ret) {
1918                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1919                 goto error;
1920         }
1921
1922         i915_gem_reset(i915);
1923         intel_overlay_reset(i915);
1924
1925         /* Ok, now get things going again... */
1926
1927         /*
1928          * Everything depends on having the GTT running, so we need to start
1929          * there.
1930          */
1931         ret = i915_ggtt_enable_hw(i915);
1932         if (ret) {
1933                 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1934                 goto error;
1935         }
1936
1937         /*
1938          * Next we need to restore the context, but we don't use those
1939          * yet either...
1940          *
1941          * Ring buffer needs to be re-initialized in the KMS case, or if X
1942          * was running at the time of the reset (i.e. we weren't VT
1943          * switched away).
1944          */
1945         ret = i915_gem_init_hw(i915);
1946         if (ret) {
1947                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1948                 goto error;
1949         }
1950
1951         i915_queue_hangcheck(i915);
1952
1953 finish:
1954         i915_gem_reset_finish(i915);
1955         enable_irq(i915->drm.irq);
1956
1957 wakeup:
1958         clear_bit(I915_RESET_HANDOFF, &error->flags);
1959         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1960         return;
1961
1962 error:
1963         i915_gem_set_wedged(i915);
1964         i915_gem_retire_requests(i915);
1965         goto finish;
1966 }
1967
1968 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
1969                                         struct intel_engine_cs *engine)
1970 {
1971         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
1972 }
1973
1974 /**
1975  * i915_reset_engine - reset GPU engine to recover from a hang
1976  * @engine: engine to reset
1977  * @flags: options
1978  *
1979  * Reset a specific GPU engine. Useful if a hang is detected.
1980  * Returns zero on successful reset or otherwise an error code.
1981  *
1982  * Procedure is:
1983  *  - identifies the request that caused the hang and it is dropped
1984  *  - reset engine (which will force the engine to idle)
1985  *  - re-init/configure engine
1986  */
1987 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1988 {
1989         struct i915_gpu_error *error = &engine->i915->gpu_error;
1990         struct drm_i915_gem_request *active_request;
1991         int ret;
1992
1993         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1994
1995         if (!(flags & I915_RESET_QUIET)) {
1996                 dev_notice(engine->i915->drm.dev,
1997                            "Resetting %s after gpu hang\n", engine->name);
1998         }
1999         error->reset_engine_count[engine->id]++;
2000
2001         active_request = i915_gem_reset_prepare_engine(engine);
2002         if (IS_ERR(active_request)) {
2003                 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
2004                 ret = PTR_ERR(active_request);
2005                 goto out;
2006         }
2007
2008         if (!engine->i915->guc.execbuf_client)
2009                 ret = intel_gt_reset_engine(engine->i915, engine);
2010         else
2011                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2012         if (ret) {
2013                 /* If we fail here, we expect to fallback to a global reset */
2014                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2015                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2016                                  engine->name, ret);
2017                 goto out;
2018         }
2019
2020         /*
2021          * The request that caused the hang is stuck on elsp, we know the
2022          * active request and can drop it, adjust head to skip the offending
2023          * request to resume executing remaining requests in the queue.
2024          */
2025         i915_gem_reset_engine(engine, active_request);
2026
2027         /*
2028          * The engine and its registers (and workarounds in case of render)
2029          * have been reset to their default values. Follow the init_ring
2030          * process to program RING_MODE, HWSP and re-enable submission.
2031          */
2032         ret = engine->init_hw(engine);
2033         if (ret)
2034                 goto out;
2035
2036 out:
2037         i915_gem_reset_finish_engine(engine);
2038         return ret;
2039 }
2040
2041 static int i915_pm_suspend(struct device *kdev)
2042 {
2043         struct pci_dev *pdev = to_pci_dev(kdev);
2044         struct drm_device *dev = pci_get_drvdata(pdev);
2045
2046         if (!dev) {
2047                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2048                 return -ENODEV;
2049         }
2050
2051         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2052                 return 0;
2053
2054         return i915_drm_suspend(dev);
2055 }
2056
2057 static int i915_pm_suspend_late(struct device *kdev)
2058 {
2059         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2060
2061         /*
2062          * We have a suspend ordering issue with the snd-hda driver also
2063          * requiring our device to be power up. Due to the lack of a
2064          * parent/child relationship we currently solve this with an late
2065          * suspend hook.
2066          *
2067          * FIXME: This should be solved with a special hdmi sink device or
2068          * similar so that power domains can be employed.
2069          */
2070         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2071                 return 0;
2072
2073         return i915_drm_suspend_late(dev, false);
2074 }
2075
2076 static int i915_pm_poweroff_late(struct device *kdev)
2077 {
2078         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2079
2080         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2081                 return 0;
2082
2083         return i915_drm_suspend_late(dev, true);
2084 }
2085
2086 static int i915_pm_resume_early(struct device *kdev)
2087 {
2088         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2089
2090         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2091                 return 0;
2092
2093         return i915_drm_resume_early(dev);
2094 }
2095
2096 static int i915_pm_resume(struct device *kdev)
2097 {
2098         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2099
2100         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2101                 return 0;
2102
2103         return i915_drm_resume(dev);
2104 }
2105
2106 /* freeze: before creating the hibernation_image */
2107 static int i915_pm_freeze(struct device *kdev)
2108 {
2109         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2110         int ret;
2111
2112         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2113                 ret = i915_drm_suspend(dev);
2114                 if (ret)
2115                         return ret;
2116         }
2117
2118         ret = i915_gem_freeze(kdev_to_i915(kdev));
2119         if (ret)
2120                 return ret;
2121
2122         return 0;
2123 }
2124
2125 static int i915_pm_freeze_late(struct device *kdev)
2126 {
2127         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2128         int ret;
2129
2130         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2131                 ret = i915_drm_suspend_late(dev, true);
2132                 if (ret)
2133                         return ret;
2134         }
2135
2136         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2137         if (ret)
2138                 return ret;
2139
2140         return 0;
2141 }
2142
2143 /* thaw: called after creating the hibernation image, but before turning off. */
2144 static int i915_pm_thaw_early(struct device *kdev)
2145 {
2146         return i915_pm_resume_early(kdev);
2147 }
2148
2149 static int i915_pm_thaw(struct device *kdev)
2150 {
2151         return i915_pm_resume(kdev);
2152 }
2153
2154 /* restore: called after loading the hibernation image. */
2155 static int i915_pm_restore_early(struct device *kdev)
2156 {
2157         return i915_pm_resume_early(kdev);
2158 }
2159
2160 static int i915_pm_restore(struct device *kdev)
2161 {
2162         return i915_pm_resume(kdev);
2163 }
2164
2165 /*
2166  * Save all Gunit registers that may be lost after a D3 and a subsequent
2167  * S0i[R123] transition. The list of registers needing a save/restore is
2168  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2169  * registers in the following way:
2170  * - Driver: saved/restored by the driver
2171  * - Punit : saved/restored by the Punit firmware
2172  * - No, w/o marking: no need to save/restore, since the register is R/O or
2173  *                    used internally by the HW in a way that doesn't depend
2174  *                    keeping the content across a suspend/resume.
2175  * - Debug : used for debugging
2176  *
2177  * We save/restore all registers marked with 'Driver', with the following
2178  * exceptions:
2179  * - Registers out of use, including also registers marked with 'Debug'.
2180  *   These have no effect on the driver's operation, so we don't save/restore
2181  *   them to reduce the overhead.
2182  * - Registers that are fully setup by an initialization function called from
2183  *   the resume path. For example many clock gating and RPS/RC6 registers.
2184  * - Registers that provide the right functionality with their reset defaults.
2185  *
2186  * TODO: Except for registers that based on the above 3 criteria can be safely
2187  * ignored, we save/restore all others, practically treating the HW context as
2188  * a black-box for the driver. Further investigation is needed to reduce the
2189  * saved/restored registers even further, by following the same 3 criteria.
2190  */
2191 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2192 {
2193         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2194         int i;
2195
2196         /* GAM 0x4000-0x4770 */
2197         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2198         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2199         s->arb_mode             = I915_READ(ARB_MODE);
2200         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2201         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2202
2203         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2204                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2205
2206         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2207         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2208
2209         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2210         s->ecochk               = I915_READ(GAM_ECOCHK);
2211         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2212         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2213
2214         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2215
2216         /* MBC 0x9024-0x91D0, 0x8500 */
2217         s->g3dctl               = I915_READ(VLV_G3DCTL);
2218         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2219         s->mbctl                = I915_READ(GEN6_MBCTL);
2220
2221         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2222         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2223         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2224         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2225         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2226         s->rstctl               = I915_READ(GEN6_RSTCTL);
2227         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2228
2229         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2230         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2231         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2232         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2233         s->ecobus               = I915_READ(ECOBUS);
2234         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2235         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2236         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2237         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2238         s->rcedata              = I915_READ(VLV_RCEDATA);
2239         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2240
2241         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2242         s->gt_imr               = I915_READ(GTIMR);
2243         s->gt_ier               = I915_READ(GTIER);
2244         s->pm_imr               = I915_READ(GEN6_PMIMR);
2245         s->pm_ier               = I915_READ(GEN6_PMIER);
2246
2247         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2248                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2249
2250         /* GT SA CZ domain, 0x100000-0x138124 */
2251         s->tilectl              = I915_READ(TILECTL);
2252         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2253         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2254         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2255         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2256
2257         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2258         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2259         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2260         s->pcbr                 = I915_READ(VLV_PCBR);
2261         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2262
2263         /*
2264          * Not saving any of:
2265          * DFT,         0x9800-0x9EC0
2266          * SARB,        0xB000-0xB1FC
2267          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2268          * PCI CFG
2269          */
2270 }
2271
2272 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2273 {
2274         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2275         u32 val;
2276         int i;
2277
2278         /* GAM 0x4000-0x4770 */
2279         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2280         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2281         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2282         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2283         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2284
2285         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2286                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2287
2288         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2289         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2290
2291         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2292         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2293         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2294         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2295
2296         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2297
2298         /* MBC 0x9024-0x91D0, 0x8500 */
2299         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2300         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2301         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2302
2303         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2304         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2305         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2306         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2307         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2308         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2309         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2310
2311         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2312         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2313         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2314         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2315         I915_WRITE(ECOBUS,              s->ecobus);
2316         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2317         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2318         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2319         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2320         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2321         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2322
2323         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2324         I915_WRITE(GTIMR,               s->gt_imr);
2325         I915_WRITE(GTIER,               s->gt_ier);
2326         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2327         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2328
2329         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2330                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2331
2332         /* GT SA CZ domain, 0x100000-0x138124 */
2333         I915_WRITE(TILECTL,                     s->tilectl);
2334         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2335         /*
2336          * Preserve the GT allow wake and GFX force clock bit, they are not
2337          * be restored, as they are used to control the s0ix suspend/resume
2338          * sequence by the caller.
2339          */
2340         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2341         val &= VLV_GTLC_ALLOWWAKEREQ;
2342         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2343         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2344
2345         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2346         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2347         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2348         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2349
2350         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2351
2352         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2353         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2354         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2355         I915_WRITE(VLV_PCBR,                    s->pcbr);
2356         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2357 }
2358
2359 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2360                                   u32 mask, u32 val)
2361 {
2362         /* The HW does not like us polling for PW_STATUS frequently, so
2363          * use the sleeping loop rather than risk the busy spin within
2364          * intel_wait_for_register().
2365          *
2366          * Transitioning between RC6 states should be at most 2ms (see
2367          * valleyview_enable_rps) so use a 3ms timeout.
2368          */
2369         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2370                         3);
2371 }
2372
2373 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2374 {
2375         u32 val;
2376         int err;
2377
2378         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2379         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2380         if (force_on)
2381                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2382         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2383
2384         if (!force_on)
2385                 return 0;
2386
2387         err = intel_wait_for_register(dev_priv,
2388                                       VLV_GTLC_SURVIVABILITY_REG,
2389                                       VLV_GFX_CLK_STATUS_BIT,
2390                                       VLV_GFX_CLK_STATUS_BIT,
2391                                       20);
2392         if (err)
2393                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2394                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2395
2396         return err;
2397 }
2398
2399 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2400 {
2401         u32 mask;
2402         u32 val;
2403         int err;
2404
2405         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2406         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2407         if (allow)
2408                 val |= VLV_GTLC_ALLOWWAKEREQ;
2409         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2410         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2411
2412         mask = VLV_GTLC_ALLOWWAKEACK;
2413         val = allow ? mask : 0;
2414
2415         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2416         if (err)
2417                 DRM_ERROR("timeout disabling GT waking\n");
2418
2419         return err;
2420 }
2421
2422 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2423                                   bool wait_for_on)
2424 {
2425         u32 mask;
2426         u32 val;
2427
2428         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2429         val = wait_for_on ? mask : 0;
2430
2431         /*
2432          * RC6 transitioning can be delayed up to 2 msec (see
2433          * valleyview_enable_rps), use 3 msec for safety.
2434          */
2435         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2436                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2437                           onoff(wait_for_on));
2438 }
2439
2440 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2441 {
2442         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2443                 return;
2444
2445         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2446         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2447 }
2448
2449 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2450 {
2451         u32 mask;
2452         int err;
2453
2454         /*
2455          * Bspec defines the following GT well on flags as debug only, so
2456          * don't treat them as hard failures.
2457          */
2458         vlv_wait_for_gt_wells(dev_priv, false);
2459
2460         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2461         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2462
2463         vlv_check_no_gt_access(dev_priv);
2464
2465         err = vlv_force_gfx_clock(dev_priv, true);
2466         if (err)
2467                 goto err1;
2468
2469         err = vlv_allow_gt_wake(dev_priv, false);
2470         if (err)
2471                 goto err2;
2472
2473         if (!IS_CHERRYVIEW(dev_priv))
2474                 vlv_save_gunit_s0ix_state(dev_priv);
2475
2476         err = vlv_force_gfx_clock(dev_priv, false);
2477         if (err)
2478                 goto err2;
2479
2480         return 0;
2481
2482 err2:
2483         /* For safety always re-enable waking and disable gfx clock forcing */
2484         vlv_allow_gt_wake(dev_priv, true);
2485 err1:
2486         vlv_force_gfx_clock(dev_priv, false);
2487
2488         return err;
2489 }
2490
2491 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2492                                 bool rpm_resume)
2493 {
2494         int err;
2495         int ret;
2496
2497         /*
2498          * If any of the steps fail just try to continue, that's the best we
2499          * can do at this point. Return the first error code (which will also
2500          * leave RPM permanently disabled).
2501          */
2502         ret = vlv_force_gfx_clock(dev_priv, true);
2503
2504         if (!IS_CHERRYVIEW(dev_priv))
2505                 vlv_restore_gunit_s0ix_state(dev_priv);
2506
2507         err = vlv_allow_gt_wake(dev_priv, true);
2508         if (!ret)
2509                 ret = err;
2510
2511         err = vlv_force_gfx_clock(dev_priv, false);
2512         if (!ret)
2513                 ret = err;
2514
2515         vlv_check_no_gt_access(dev_priv);
2516
2517         if (rpm_resume)
2518                 intel_init_clock_gating(dev_priv);
2519
2520         return ret;
2521 }
2522
2523 static int intel_runtime_suspend(struct device *kdev)
2524 {
2525         struct pci_dev *pdev = to_pci_dev(kdev);
2526         struct drm_device *dev = pci_get_drvdata(pdev);
2527         struct drm_i915_private *dev_priv = to_i915(dev);
2528         int ret;
2529
2530         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2531                 return -ENODEV;
2532
2533         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2534                 return -ENODEV;
2535
2536         DRM_DEBUG_KMS("Suspending device\n");
2537
2538         disable_rpm_wakeref_asserts(dev_priv);
2539
2540         /*
2541          * We are safe here against re-faults, since the fault handler takes
2542          * an RPM reference.
2543          */
2544         i915_gem_runtime_suspend(dev_priv);
2545
2546         intel_guc_suspend(dev_priv);
2547
2548         intel_runtime_pm_disable_interrupts(dev_priv);
2549
2550         intel_uncore_suspend(dev_priv);
2551
2552         ret = 0;
2553         if (IS_GEN9_LP(dev_priv)) {
2554                 bxt_display_core_uninit(dev_priv);
2555                 bxt_enable_dc9(dev_priv);
2556         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2557                 hsw_enable_pc8(dev_priv);
2558         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2559                 ret = vlv_suspend_complete(dev_priv);
2560         }
2561
2562         if (ret) {
2563                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2564                 intel_uncore_runtime_resume(dev_priv);
2565
2566                 intel_runtime_pm_enable_interrupts(dev_priv);
2567
2568                 enable_rpm_wakeref_asserts(dev_priv);
2569
2570                 return ret;
2571         }
2572
2573         enable_rpm_wakeref_asserts(dev_priv);
2574         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2575
2576         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2577                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2578
2579         dev_priv->runtime_pm.suspended = true;
2580
2581         /*
2582          * FIXME: We really should find a document that references the arguments
2583          * used below!
2584          */
2585         if (IS_BROADWELL(dev_priv)) {
2586                 /*
2587                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2588                  * being detected, and the call we do at intel_runtime_resume()
2589                  * won't be able to restore them. Since PCI_D3hot matches the
2590                  * actual specification and appears to be working, use it.
2591                  */
2592                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2593         } else {
2594                 /*
2595                  * current versions of firmware which depend on this opregion
2596                  * notification have repurposed the D1 definition to mean
2597                  * "runtime suspended" vs. what you would normally expect (D3)
2598                  * to distinguish it from notifications that might be sent via
2599                  * the suspend path.
2600                  */
2601                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2602         }
2603
2604         assert_forcewakes_inactive(dev_priv);
2605
2606         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2607                 intel_hpd_poll_init(dev_priv);
2608
2609         DRM_DEBUG_KMS("Device suspended\n");
2610         return 0;
2611 }
2612
2613 static int intel_runtime_resume(struct device *kdev)
2614 {
2615         struct pci_dev *pdev = to_pci_dev(kdev);
2616         struct drm_device *dev = pci_get_drvdata(pdev);
2617         struct drm_i915_private *dev_priv = to_i915(dev);
2618         int ret = 0;
2619
2620         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2621                 return -ENODEV;
2622
2623         DRM_DEBUG_KMS("Resuming device\n");
2624
2625         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2626         disable_rpm_wakeref_asserts(dev_priv);
2627
2628         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2629         dev_priv->runtime_pm.suspended = false;
2630         if (intel_uncore_unclaimed_mmio(dev_priv))
2631                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2632
2633         intel_guc_resume(dev_priv);
2634
2635         if (IS_GEN9_LP(dev_priv)) {
2636                 bxt_disable_dc9(dev_priv);
2637                 bxt_display_core_init(dev_priv, true);
2638                 if (dev_priv->csr.dmc_payload &&
2639                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2640                         gen9_enable_dc5(dev_priv);
2641         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2642                 hsw_disable_pc8(dev_priv);
2643         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2644                 ret = vlv_resume_prepare(dev_priv, true);
2645         }
2646
2647         intel_uncore_runtime_resume(dev_priv);
2648
2649         /*
2650          * No point of rolling back things in case of an error, as the best
2651          * we can do is to hope that things will still work (and disable RPM).
2652          */
2653         i915_gem_init_swizzling(dev_priv);
2654         i915_gem_restore_fences(dev_priv);
2655
2656         intel_runtime_pm_enable_interrupts(dev_priv);
2657
2658         /*
2659          * On VLV/CHV display interrupts are part of the display
2660          * power well, so hpd is reinitialized from there. For
2661          * everyone else do it here.
2662          */
2663         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2664                 intel_hpd_init(dev_priv);
2665
2666         intel_enable_ipc(dev_priv);
2667
2668         enable_rpm_wakeref_asserts(dev_priv);
2669
2670         if (ret)
2671                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2672         else
2673                 DRM_DEBUG_KMS("Device resumed\n");
2674
2675         return ret;
2676 }
2677
2678 const struct dev_pm_ops i915_pm_ops = {
2679         /*
2680          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2681          * PMSG_RESUME]
2682          */
2683         .suspend = i915_pm_suspend,
2684         .suspend_late = i915_pm_suspend_late,
2685         .resume_early = i915_pm_resume_early,
2686         .resume = i915_pm_resume,
2687
2688         /*
2689          * S4 event handlers
2690          * @freeze, @freeze_late    : called (1) before creating the
2691          *                            hibernation image [PMSG_FREEZE] and
2692          *                            (2) after rebooting, before restoring
2693          *                            the image [PMSG_QUIESCE]
2694          * @thaw, @thaw_early       : called (1) after creating the hibernation
2695          *                            image, before writing it [PMSG_THAW]
2696          *                            and (2) after failing to create or
2697          *                            restore the image [PMSG_RECOVER]
2698          * @poweroff, @poweroff_late: called after writing the hibernation
2699          *                            image, before rebooting [PMSG_HIBERNATE]
2700          * @restore, @restore_early : called after rebooting and restoring the
2701          *                            hibernation image [PMSG_RESTORE]
2702          */
2703         .freeze = i915_pm_freeze,
2704         .freeze_late = i915_pm_freeze_late,
2705         .thaw_early = i915_pm_thaw_early,
2706         .thaw = i915_pm_thaw,
2707         .poweroff = i915_pm_suspend,
2708         .poweroff_late = i915_pm_poweroff_late,
2709         .restore_early = i915_pm_restore_early,
2710         .restore = i915_pm_restore,
2711
2712         /* S0ix (via runtime suspend) event handlers */
2713         .runtime_suspend = intel_runtime_suspend,
2714         .runtime_resume = intel_runtime_resume,
2715 };
2716
2717 static const struct vm_operations_struct i915_gem_vm_ops = {
2718         .fault = i915_gem_fault,
2719         .open = drm_gem_vm_open,
2720         .close = drm_gem_vm_close,
2721 };
2722
2723 static const struct file_operations i915_driver_fops = {
2724         .owner = THIS_MODULE,
2725         .open = drm_open,
2726         .release = drm_release,
2727         .unlocked_ioctl = drm_ioctl,
2728         .mmap = drm_gem_mmap,
2729         .poll = drm_poll,
2730         .read = drm_read,
2731         .compat_ioctl = i915_compat_ioctl,
2732         .llseek = noop_llseek,
2733 };
2734
2735 static int
2736 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2737                           struct drm_file *file)
2738 {
2739         return -ENODEV;
2740 }
2741
2742 static const struct drm_ioctl_desc i915_ioctls[] = {
2743         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2744         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2745         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2746         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2747         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2748         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2749         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2750         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2751         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2752         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2753         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2754         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2755         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2756         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2757         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2758         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2759         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2760         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2761         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2762         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2763         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2764         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2765         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2766         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2767         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2768         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2769         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2770         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2771         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2772         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2773         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2774         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2775         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2776         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2777         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2778         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2779         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2780         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2781         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2782         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2783         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2784         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2785         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2786         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2787         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2788         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2789         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2790         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2791         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2792         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2793         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2794         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2795         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2796         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2797         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2798 };
2799
2800 static struct drm_driver driver = {
2801         /* Don't use MTRRs here; the Xserver or userspace app should
2802          * deal with them for Intel hardware.
2803          */
2804         .driver_features =
2805             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2806             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2807         .release = i915_driver_release,
2808         .open = i915_driver_open,
2809         .lastclose = i915_driver_lastclose,
2810         .postclose = i915_driver_postclose,
2811
2812         .gem_close_object = i915_gem_close_object,
2813         .gem_free_object_unlocked = i915_gem_free_object,
2814         .gem_vm_ops = &i915_gem_vm_ops,
2815
2816         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2817         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2818         .gem_prime_export = i915_gem_prime_export,
2819         .gem_prime_import = i915_gem_prime_import,
2820
2821         .dumb_create = i915_gem_dumb_create,
2822         .dumb_map_offset = i915_gem_mmap_gtt,
2823         .ioctls = i915_ioctls,
2824         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2825         .fops = &i915_driver_fops,
2826         .name = DRIVER_NAME,
2827         .desc = DRIVER_DESC,
2828         .date = DRIVER_DATE,
2829         .major = DRIVER_MAJOR,
2830         .minor = DRIVER_MINOR,
2831         .patchlevel = DRIVER_PATCHLEVEL,
2832 };
2833
2834 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2835 #include "selftests/mock_drm.c"
2836 #endif