drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/console.h>
  39 #include <linux/module.h>
  40 #include <linux/pm_runtime.h>
  41 #include <drm/drm_crtc_helper.h>
  42
  43 static struct drm_driver driver;
  44
  45 #define GEN_DEFAULT_PIPEOFFSETS \
  46         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  47                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  48         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  49                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  50         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  51
  52 #define GEN_CHV_PIPEOFFSETS \
  53         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  54                           CHV_PIPE_C_OFFSET }, \
  55         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  56                            CHV_TRANSCODER_C_OFFSET, }, \
  57         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  58                              CHV_PALETTE_C_OFFSET }
  59
  60 #define CURSOR_OFFSETS \
  61         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  62
  63 #define IVB_CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  65
  66 static const struct intel_device_info intel_i830_info = {
  67         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  68         .has_overlay = 1, .overlay_needs_physical = 1,
  69         .ring_mask = RENDER_RING,
  70         GEN_DEFAULT_PIPEOFFSETS,
  71         CURSOR_OFFSETS,
  72 };
  73
  74 static const struct intel_device_info intel_845g_info = {
  75         .gen = 2, .num_pipes = 1,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_i85x_info = {
  83         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  84         .cursor_needs_physical = 1,
  85         .has_overlay = 1, .overlay_needs_physical = 1,
  86         .has_fbc = 1,
  87         .ring_mask = RENDER_RING,
  88         GEN_DEFAULT_PIPEOFFSETS,
  89         CURSOR_OFFSETS,
  90 };
  91
  92 static const struct intel_device_info intel_i865g_info = {
  93         .gen = 2, .num_pipes = 1,
  94         .has_overlay = 1, .overlay_needs_physical = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i915g_info = {
 101         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107 static const struct intel_device_info intel_i915gm_info = {
 108         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 109         .cursor_needs_physical = 1,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .supports_tv = 1,
 112         .has_fbc = 1,
 113         .ring_mask = RENDER_RING,
 114         GEN_DEFAULT_PIPEOFFSETS,
 115         CURSOR_OFFSETS,
 116 };
 117 static const struct intel_device_info intel_i945g_info = {
 118         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 119         .has_overlay = 1, .overlay_needs_physical = 1,
 120         .ring_mask = RENDER_RING,
 121         GEN_DEFAULT_PIPEOFFSETS,
 122         CURSOR_OFFSETS,
 123 };
 124 static const struct intel_device_info intel_i945gm_info = {
 125         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 126         .has_hotplug = 1, .cursor_needs_physical = 1,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .supports_tv = 1,
 129         .has_fbc = 1,
 130         .ring_mask = RENDER_RING,
 131         GEN_DEFAULT_PIPEOFFSETS,
 132         CURSOR_OFFSETS,
 133 };
 134
 135 static const struct intel_device_info intel_i965g_info = {
 136         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 137         .has_hotplug = 1,
 138         .has_overlay = 1,
 139         .ring_mask = RENDER_RING,
 140         GEN_DEFAULT_PIPEOFFSETS,
 141         CURSOR_OFFSETS,
 142 };
 143
 144 static const struct intel_device_info intel_i965gm_info = {
 145         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 146         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 147         .has_overlay = 1,
 148         .supports_tv = 1,
 149         .ring_mask = RENDER_RING,
 150         GEN_DEFAULT_PIPEOFFSETS,
 151         CURSOR_OFFSETS,
 152 };
 153
 154 static const struct intel_device_info intel_g33_info = {
 155         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_overlay = 1,
 158         .ring_mask = RENDER_RING,
 159         GEN_DEFAULT_PIPEOFFSETS,
 160         CURSOR_OFFSETS,
 161 };
 162
 163 static const struct intel_device_info intel_g45_info = {
 164         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 165         .has_pipe_cxsr = 1, .has_hotplug = 1,
 166         .ring_mask = RENDER_RING | BSD_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_gm45_info = {
 172         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 173         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 174         .has_pipe_cxsr = 1, .has_hotplug = 1,
 175         .supports_tv = 1,
 176         .ring_mask = RENDER_RING | BSD_RING,
 177         GEN_DEFAULT_PIPEOFFSETS,
 178         CURSOR_OFFSETS,
 179 };
 180
 181 static const struct intel_device_info intel_pineview_info = {
 182         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 183         .need_gfx_hws = 1, .has_hotplug = 1,
 184         .has_overlay = 1,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_ironlake_d_info = {
 190         .gen = 5, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .ring_mask = RENDER_RING | BSD_RING,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_m_info = {
 198         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .has_fbc = 1,
 201         .ring_mask = RENDER_RING | BSD_RING,
 202         GEN_DEFAULT_PIPEOFFSETS,
 203         CURSOR_OFFSETS,
 204 };
 205
 206 static const struct intel_device_info intel_sandybridge_d_info = {
 207         .gen = 6, .num_pipes = 2,
 208         .need_gfx_hws = 1, .has_hotplug = 1,
 209         .has_fbc = 1,
 210         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 211         .has_llc = 1,
 212         GEN_DEFAULT_PIPEOFFSETS,
 213         CURSOR_OFFSETS,
 214 };
 215
 216 static const struct intel_device_info intel_sandybridge_m_info = {
 217         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 221         .has_llc = 1,
 222         GEN_DEFAULT_PIPEOFFSETS,
 223         CURSOR_OFFSETS,
 224 };
 225
 226 #define GEN7_FEATURES  \
 227         .gen = 7, .num_pipes = 3, \
 228         .need_gfx_hws = 1, .has_hotplug = 1, \
 229         .has_fbc = 1, \
 230         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 231         .has_llc = 1
 232
 233 static const struct intel_device_info intel_ivybridge_d_info = {
 234         GEN7_FEATURES,
 235         .is_ivybridge = 1,
 236         GEN_DEFAULT_PIPEOFFSETS,
 237         IVB_CURSOR_OFFSETS,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_m_info = {
 241         GEN7_FEATURES,
 242         .is_ivybridge = 1,
 243         .is_mobile = 1,
 244         GEN_DEFAULT_PIPEOFFSETS,
 245         IVB_CURSOR_OFFSETS,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_q_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .num_pipes = 0, /* legal, last one wins */
 252         GEN_DEFAULT_PIPEOFFSETS,
 253         IVB_CURSOR_OFFSETS,
 254 };
 255
 256 static const struct intel_device_info intel_valleyview_m_info = {
 257         GEN7_FEATURES,
 258         .is_mobile = 1,
 259         .num_pipes = 2,
 260         .is_valleyview = 1,
 261         .display_mmio_offset = VLV_DISPLAY_BASE,
 262         .has_fbc = 0, /* legal, last one wins */
 263         .has_llc = 0, /* legal, last one wins */
 264         GEN_DEFAULT_PIPEOFFSETS,
 265         CURSOR_OFFSETS,
 266 };
 267
 268 static const struct intel_device_info intel_valleyview_d_info = {
 269         GEN7_FEATURES,
 270         .num_pipes = 2,
 271         .is_valleyview = 1,
 272         .display_mmio_offset = VLV_DISPLAY_BASE,
 273         .has_fbc = 0, /* legal, last one wins */
 274         .has_llc = 0, /* legal, last one wins */
 275         GEN_DEFAULT_PIPEOFFSETS,
 276         CURSOR_OFFSETS,
 277 };
 278
 279 static const struct intel_device_info intel_haswell_d_info = {
 280         GEN7_FEATURES,
 281         .is_haswell = 1,
 282         .has_ddi = 1,
 283         .has_fpga_dbg = 1,
 284         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 285         GEN_DEFAULT_PIPEOFFSETS,
 286         IVB_CURSOR_OFFSETS,
 287 };
 288
 289 static const struct intel_device_info intel_haswell_m_info = {
 290         GEN7_FEATURES,
 291         .is_haswell = 1,
 292         .is_mobile = 1,
 293         .has_ddi = 1,
 294         .has_fpga_dbg = 1,
 295         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 296         GEN_DEFAULT_PIPEOFFSETS,
 297         IVB_CURSOR_OFFSETS,
 298 };
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         .gen = 8, .num_pipes = 3,
 302         .need_gfx_hws = 1, .has_hotplug = 1,
 303         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 304         .has_llc = 1,
 305         .has_ddi = 1,
 306         .has_fpga_dbg = 1,
 307         .has_fbc = 1,
 308         GEN_DEFAULT_PIPEOFFSETS,
 309         IVB_CURSOR_OFFSETS,
 310 };
 311
 312 static const struct intel_device_info intel_broadwell_m_info = {
 313         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 314         .need_gfx_hws = 1, .has_hotplug = 1,
 315         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 316         .has_llc = 1,
 317         .has_ddi = 1,
 318         .has_fpga_dbg = 1,
 319         .has_fbc = 1,
 320         GEN_DEFAULT_PIPEOFFSETS,
 321         IVB_CURSOR_OFFSETS,
 322 };
 323
 324 static const struct intel_device_info intel_broadwell_gt3d_info = {
 325         .gen = 8, .num_pipes = 3,
 326         .need_gfx_hws = 1, .has_hotplug = 1,
 327         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 328         .has_llc = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .has_fbc = 1,
 332         GEN_DEFAULT_PIPEOFFSETS,
 333         IVB_CURSOR_OFFSETS,
 334 };
 335
 336 static const struct intel_device_info intel_broadwell_gt3m_info = {
 337         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 338         .need_gfx_hws = 1, .has_hotplug = 1,
 339         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 340         .has_llc = 1,
 341         .has_ddi = 1,
 342         .has_fpga_dbg = 1,
 343         .has_fbc = 1,
 344         GEN_DEFAULT_PIPEOFFSETS,
 345         IVB_CURSOR_OFFSETS,
 346 };
 347
 348 static const struct intel_device_info intel_cherryview_info = {
 349         .gen = 8, .num_pipes = 3,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .is_valleyview = 1,
 353         .display_mmio_offset = VLV_DISPLAY_BASE,
 354         GEN_CHV_PIPEOFFSETS,
 355         CURSOR_OFFSETS,
 356 };
 357
 358 static const struct intel_device_info intel_skylake_info = {
 359         .is_preliminary = 1,
 360         .is_skylake = 1,
 361         .gen = 9, .num_pipes = 3,
 362         .need_gfx_hws = 1, .has_hotplug = 1,
 363         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 364         .has_llc = 1,
 365         .has_ddi = 1,
 366         .has_fbc = 1,
 367         GEN_DEFAULT_PIPEOFFSETS,
 368         IVB_CURSOR_OFFSETS,
 369 };
 370
 371 static const struct intel_device_info intel_skylake_gt3_info = {
 372         .is_preliminary = 1,
 373         .is_skylake = 1,
 374         .gen = 9, .num_pipes = 3,
 375         .need_gfx_hws = 1, .has_hotplug = 1,
 376         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 377         .has_llc = 1,
 378         .has_ddi = 1,
 379         .has_fbc = 1,
 380         GEN_DEFAULT_PIPEOFFSETS,
 381         IVB_CURSOR_OFFSETS,
 382 };
 383
 384 static const struct intel_device_info intel_broxton_info = {
 385         .is_preliminary = 1,
 386         .gen = 9,
 387         .need_gfx_hws = 1, .has_hotplug = 1,
 388         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 389         .num_pipes = 3,
 390         .has_ddi = 1,
 391         .has_fbc = 1,
 392         GEN_DEFAULT_PIPEOFFSETS,
 393         IVB_CURSOR_OFFSETS,
 394 };
 395
 396 /*
 397  * Make sure any device matches here are from most specific to most
 398  * general.  For example, since the Quanta match is based on the subsystem
 399  * and subvendor IDs, we need it to come before the more general IVB
 400  * PCI ID matches, otherwise we'll use the wrong info struct above.
 401  */
 402 #define INTEL_PCI_IDS \
 403         INTEL_I830_IDS(&intel_i830_info),       \
 404         INTEL_I845G_IDS(&intel_845g_info),      \
 405         INTEL_I85X_IDS(&intel_i85x_info),       \
 406         INTEL_I865G_IDS(&intel_i865g_info),     \
 407         INTEL_I915G_IDS(&intel_i915g_info),     \
 408         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 409         INTEL_I945G_IDS(&intel_i945g_info),     \
 410         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 411         INTEL_I965G_IDS(&intel_i965g_info),     \
 412         INTEL_G33_IDS(&intel_g33_info),         \
 413         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 414         INTEL_GM45_IDS(&intel_gm45_info),       \
 415         INTEL_G45_IDS(&intel_g45_info),         \
 416         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 417         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 418         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 419         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 420         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 421         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 422         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 423         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 424         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 425         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 426         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 427         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 428         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),   \
 429         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),   \
 430         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
 431         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
 432         INTEL_CHV_IDS(&intel_cherryview_info),  \
 433         INTEL_SKL_GT1_IDS(&intel_skylake_info), \
 434         INTEL_SKL_GT2_IDS(&intel_skylake_info), \
 435         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),     \
 436         INTEL_BXT_IDS(&intel_broxton_info)
 437
 438 static const struct pci_device_id pciidlist[] = {               /* aka */
 439         INTEL_PCI_IDS,
 440         {0, 0, 0}
 441 };
 442
 443 #if defined(CONFIG_DRM_I915_KMS)
 444 MODULE_DEVICE_TABLE(pci, pciidlist);
 445 #endif
 446
 447 void intel_detect_pch(struct drm_device *dev)
 448 {
 449         struct drm_i915_private *dev_priv = dev->dev_private;
 450         struct pci_dev *pch = NULL;
 451
 452         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 453          * (which really amounts to a PCH but no South Display).
 454          */
 455         if (INTEL_INFO(dev)->num_pipes == 0) {
 456                 dev_priv->pch_type = PCH_NOP;
 457                 return;
 458         }
 459
 460         /*
 461          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 462          * make graphics device passthrough work easy for VMM, that only
 463          * need to expose ISA bridge to let driver know the real hardware
 464          * underneath. This is a requirement from virtualization team.
 465          *
 466          * In some virtualized environments (e.g. XEN), there is irrelevant
 467          * ISA bridge in the system. To work reliably, we should scan trhough
 468          * all the ISA bridge devices and check for the first match, instead
 469          * of only checking the first one.
 470          */
 471         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 472                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 473                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 474                         dev_priv->pch_id = id;
 475
 476                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 477                                 dev_priv->pch_type = PCH_IBX;
 478                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 479                                 WARN_ON(!IS_GEN5(dev));
 480                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 481                                 dev_priv->pch_type = PCH_CPT;
 482                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 483                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 484                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 485                                 /* PantherPoint is CPT compatible */
 486                                 dev_priv->pch_type = PCH_CPT;
 487                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 488                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 489                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 490                                 dev_priv->pch_type = PCH_LPT;
 491                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 492                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 493                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 494                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 495                                 dev_priv->pch_type = PCH_LPT;
 496                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 497                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 498                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 499                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 500                                 dev_priv->pch_type = PCH_SPT;
 501                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 502                                 WARN_ON(!IS_SKYLAKE(dev));
 503                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 504                                 dev_priv->pch_type = PCH_SPT;
 505                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 506                                 WARN_ON(!IS_SKYLAKE(dev));
 507                         } else
 508                                 continue;
 509
 510                         break;
 511                 }
 512         }
 513         if (!pch)
 514                 DRM_DEBUG_KMS("No PCH found.\n");
 515
 516         pci_dev_put(pch);
 517 }
 518
 519 bool i915_semaphore_is_enabled(struct drm_device *dev)
 520 {
 521         if (INTEL_INFO(dev)->gen < 6)
 522                 return false;
 523
 524         if (i915.semaphores >= 0)
 525                 return i915.semaphores;
 526
 527         /* TODO: make semaphores and Execlists play nicely together */
 528         if (i915.enable_execlists)
 529                 return false;
 530
 531         /* Until we get further testing... */
 532         if (IS_GEN8(dev))
 533                 return false;
 534
 535 #ifdef CONFIG_INTEL_IOMMU
 536         /* Enable semaphores on SNB when IO remapping is off */
 537         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 538                 return false;
 539 #endif
 540
 541         return true;
 542 }
 543
 544 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
 545 {
 546         spin_lock_irq(&dev_priv->irq_lock);
 547
 548         dev_priv->long_hpd_port_mask = 0;
 549         dev_priv->short_hpd_port_mask = 0;
 550         dev_priv->hpd_event_bits = 0;
 551
 552         spin_unlock_irq(&dev_priv->irq_lock);
 553
 554         cancel_work_sync(&dev_priv->dig_port_work);
 555         cancel_work_sync(&dev_priv->hotplug_work);
 556         cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
 557 }
 558
 559 void i915_firmware_load_error_print(const char *fw_path, int err)
 560 {
 561         DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err);
 562
 563         /*
 564          * If the reason is not known assume -ENOENT since that's the most
 565          * usual failure mode.
 566          */
 567         if (!err)
 568                 err = -ENOENT;
 569
 570         if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT))
 571                 return;
 572
 573         DRM_ERROR(
 574           "The driver is built-in, so to load the firmware you need to\n"
 575           "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
 576           "in your initrd/initramfs image.\n");
 577 }
 578
 579 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 580 {
 581         struct drm_device *dev = dev_priv->dev;
 582         struct drm_encoder *encoder;
 583
 584         drm_modeset_lock_all(dev);
 585         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 586                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 587
 588                 if (intel_encoder->suspend)
 589                         intel_encoder->suspend(intel_encoder);
 590         }
 591         drm_modeset_unlock_all(dev);
 592 }
 593
 594 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 595 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 596                               bool rpm_resume);
 597 static int skl_resume_prepare(struct drm_i915_private *dev_priv);
 598 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 599
 600
 601 static int i915_drm_suspend(struct drm_device *dev)
 602 {
 603         struct drm_i915_private *dev_priv = dev->dev_private;
 604         struct drm_crtc *crtc;
 605         pci_power_t opregion_target_state;
 606         int error;
 607
 608         /* ignore lid events during suspend */
 609         mutex_lock(&dev_priv->modeset_restore_lock);
 610         dev_priv->modeset_restore = MODESET_SUSPENDED;
 611         mutex_unlock(&dev_priv->modeset_restore_lock);
 612
 613         /* We do a lot of poking in a lot of registers, make sure they work
 614          * properly. */
 615         intel_display_set_init_power(dev_priv, true);
 616
 617         drm_kms_helper_poll_disable(dev);
 618
 619         pci_save_state(dev->pdev);
 620
 621         error = i915_gem_suspend(dev);
 622         if (error) {
 623                 dev_err(&dev->pdev->dev,
 624                         "GEM idle failed, resume might fail\n");
 625                 return error;
 626         }
 627
 628         intel_suspend_gt_powersave(dev);
 629
 630         /*
 631          * Disable CRTCs directly since we want to preserve sw state
 632          * for _thaw. Also, power gate the CRTC power wells.
 633          */
 634         drm_modeset_lock_all(dev);
 635         for_each_crtc(dev, crtc)
 636                 intel_crtc_control(crtc, false);
 637         drm_modeset_unlock_all(dev);
 638
 639         intel_dp_mst_suspend(dev);
 640
 641         intel_runtime_pm_disable_interrupts(dev_priv);
 642         intel_hpd_cancel_work(dev_priv);
 643
 644         intel_suspend_encoders(dev_priv);
 645
 646         intel_suspend_hw(dev);
 647
 648         i915_gem_suspend_gtt_mappings(dev);
 649
 650         i915_save_state(dev);
 651
 652         opregion_target_state = PCI_D3cold;
 653 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 654         if (acpi_target_system_state() < ACPI_STATE_S3)
 655                 opregion_target_state = PCI_D1;
 656 #endif
 657         intel_opregion_notify_adapter(dev, opregion_target_state);
 658
 659         intel_uncore_forcewake_reset(dev, false);
 660         intel_opregion_fini(dev);
 661
 662         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 663
 664         dev_priv->suspend_count++;
 665
 666         intel_display_set_init_power(dev_priv, false);
 667
 668         return 0;
 669 }
 670
 671 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 672 {
 673         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 674         int ret;
 675
 676         ret = intel_suspend_complete(dev_priv);
 677
 678         if (ret) {
 679                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 680
 681                 return ret;
 682         }
 683
 684         pci_disable_device(drm_dev->pdev);
 685         /*
 686          * During hibernation on some GEN4 platforms the BIOS may try to access
 687          * the device even though it's already in D3 and hang the machine. So
 688          * leave the device in D0 on those platforms and hope the BIOS will
 689          * power down the device properly. Platforms where this was seen:
 690          * Lenovo Thinkpad X301, X61s
 691          */
 692         if (!(hibernation &&
 693               drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
 694               INTEL_INFO(dev_priv)->gen == 4))
 695                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 696
 697         return 0;
 698 }
 699
 700 int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
 701 {
 702         int error;
 703
 704         if (!dev || !dev->dev_private) {
 705                 DRM_ERROR("dev: %p\n", dev);
 706                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 707                 return -ENODEV;
 708         }
 709
 710         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 711                          state.event != PM_EVENT_FREEZE))
 712                 return -EINVAL;
 713
 714         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 715                 return 0;
 716
 717         error = i915_drm_suspend(dev);
 718         if (error)
 719                 return error;
 720
 721         return i915_drm_suspend_late(dev, false);
 722 }
 723
 724 static int i915_drm_resume(struct drm_device *dev)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727
 728         mutex_lock(&dev->struct_mutex);
 729         i915_gem_restore_gtt_mappings(dev);
 730         mutex_unlock(&dev->struct_mutex);
 731
 732         i915_restore_state(dev);
 733         intel_opregion_setup(dev);
 734
 735         intel_init_pch_refclk(dev);
 736         drm_mode_config_reset(dev);
 737
 738         /*
 739          * Interrupts have to be enabled before any batches are run. If not the
 740          * GPU will hang. i915_gem_init_hw() will initiate batches to
 741          * update/restore the context.
 742          *
 743          * Modeset enabling in intel_modeset_init_hw() also needs working
 744          * interrupts.
 745          */
 746         intel_runtime_pm_enable_interrupts(dev_priv);
 747
 748         mutex_lock(&dev->struct_mutex);
 749         if (i915_gem_init_hw(dev)) {
 750                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 751                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 752         }
 753         mutex_unlock(&dev->struct_mutex);
 754
 755         intel_modeset_init_hw(dev);
 756
 757         spin_lock_irq(&dev_priv->irq_lock);
 758         if (dev_priv->display.hpd_irq_setup)
 759                 dev_priv->display.hpd_irq_setup(dev);
 760         spin_unlock_irq(&dev_priv->irq_lock);
 761
 762         drm_modeset_lock_all(dev);
 763         intel_modeset_setup_hw_state(dev, true);
 764         drm_modeset_unlock_all(dev);
 765
 766         intel_dp_mst_resume(dev);
 767
 768         /*
 769          * ... but also need to make sure that hotplug processing
 770          * doesn't cause havoc. Like in the driver load code we don't
 771          * bother with the tiny race here where we might loose hotplug
 772          * notifications.
 773          * */
 774         intel_hpd_init(dev_priv);
 775         /* Config may have changed between suspend and resume */
 776         drm_helper_hpd_irq_event(dev);
 777
 778         intel_opregion_init(dev);
 779
 780         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 781
 782         mutex_lock(&dev_priv->modeset_restore_lock);
 783         dev_priv->modeset_restore = MODESET_DONE;
 784         mutex_unlock(&dev_priv->modeset_restore_lock);
 785
 786         intel_opregion_notify_adapter(dev, PCI_D0);
 787
 788         drm_kms_helper_poll_enable(dev);
 789
 790         return 0;
 791 }
 792
 793 static int i915_drm_resume_early(struct drm_device *dev)
 794 {
 795         struct drm_i915_private *dev_priv = dev->dev_private;
 796         int ret = 0;
 797
 798         /*
 799          * We have a resume ordering issue with the snd-hda driver also
 800          * requiring our device to be power up. Due to the lack of a
 801          * parent/child relationship we currently solve this with an early
 802          * resume hook.
 803          *
 804          * FIXME: This should be solved with a special hdmi sink device or
 805          * similar so that power domains can be employed.
 806          */
 807         if (pci_enable_device(dev->pdev))
 808                 return -EIO;
 809
 810         pci_set_master(dev->pdev);
 811
 812         if (IS_VALLEYVIEW(dev_priv))
 813                 ret = vlv_resume_prepare(dev_priv, false);
 814         if (ret)
 815                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 816                           ret);
 817
 818         intel_uncore_early_sanitize(dev, true);
 819
 820         if (IS_BROXTON(dev))
 821                 ret = bxt_resume_prepare(dev_priv);
 822         else if (IS_SKYLAKE(dev_priv))
 823                 ret = skl_resume_prepare(dev_priv);
 824         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 825                 hsw_disable_pc8(dev_priv);
 826
 827         intel_uncore_sanitize(dev);
 828         intel_power_domains_init_hw(dev_priv);
 829
 830         return ret;
 831 }
 832
 833 int i915_resume_legacy(struct drm_device *dev)
 834 {
 835         int ret;
 836
 837         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 838                 return 0;
 839
 840         ret = i915_drm_resume_early(dev);
 841         if (ret)
 842                 return ret;
 843
 844         return i915_drm_resume(dev);
 845 }
 846
 847 /**
 848  * i915_reset - reset chip after a hang
 849  * @dev: drm device to reset
 850  *
 851  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 852  * reset or otherwise an error code.
 853  *
 854  * Procedure is fairly simple:
 855  *   - reset the chip using the reset reg
 856  *   - re-init context state
 857  *   - re-init hardware status page
 858  *   - re-init ring buffer
 859  *   - re-init interrupt state
 860  *   - re-init display
 861  */
 862 int i915_reset(struct drm_device *dev)
 863 {
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         bool simulated;
 866         int ret;
 867
 868         if (!i915.reset)
 869                 return 0;
 870
 871         intel_reset_gt_powersave(dev);
 872
 873         mutex_lock(&dev->struct_mutex);
 874
 875         i915_gem_reset(dev);
 876
 877         simulated = dev_priv->gpu_error.stop_rings != 0;
 878
 879         ret = intel_gpu_reset(dev);
 880
 881         /* Also reset the gpu hangman. */
 882         if (simulated) {
 883                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 884                 dev_priv->gpu_error.stop_rings = 0;
 885                 if (ret == -ENODEV) {
 886                         DRM_INFO("Reset not implemented, but ignoring "
 887                                  "error for simulated gpu hangs\n");
 888                         ret = 0;
 889                 }
 890         }
 891
 892         if (i915_stop_ring_allow_warn(dev_priv))
 893                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 894
 895         if (ret) {
 896                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 897                 mutex_unlock(&dev->struct_mutex);
 898                 return ret;
 899         }
 900
 901         intel_overlay_reset(dev_priv);
 902
 903         /* Ok, now get things going again... */
 904
 905         /*
 906          * Everything depends on having the GTT running, so we need to start
 907          * there.  Fortunately we don't need to do this unless we reset the
 908          * chip at a PCI level.
 909          *
 910          * Next we need to restore the context, but we don't use those
 911          * yet either...
 912          *
 913          * Ring buffer needs to be re-initialized in the KMS case, or if X
 914          * was running at the time of the reset (i.e. we weren't VT
 915          * switched away).
 916          */
 917
 918         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
 919         dev_priv->gpu_error.reload_in_reset = true;
 920
 921         ret = i915_gem_init_hw(dev);
 922
 923         dev_priv->gpu_error.reload_in_reset = false;
 924
 925         mutex_unlock(&dev->struct_mutex);
 926         if (ret) {
 927                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 928                 return ret;
 929         }
 930
 931         /*
 932          * rps/rc6 re-init is necessary to restore state lost after the
 933          * reset and the re-install of gt irqs. Skip for ironlake per
 934          * previous concerns that it doesn't respond well to some forms
 935          * of re-init after reset.
 936          */
 937         if (INTEL_INFO(dev)->gen > 5)
 938                 intel_enable_gt_powersave(dev);
 939
 940         return 0;
 941 }
 942
 943 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 944 {
 945         struct intel_device_info *intel_info =
 946                 (struct intel_device_info *) ent->driver_data;
 947
 948         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
 949                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 950                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 951                 return -ENODEV;
 952         }
 953
 954         /* Only bind to function 0 of the device. Early generations
 955          * used function 1 as a placeholder for multi-head. This causes
 956          * us confusion instead, especially on the systems where both
 957          * functions have the same PCI-ID!
 958          */
 959         if (PCI_FUNC(pdev->devfn))
 960                 return -ENODEV;
 961
 962         driver.driver_features &= ~(DRIVER_USE_AGP);
 963
 964         return drm_get_pci_dev(pdev, ent, &driver);
 965 }
 966
 967 static void
 968 i915_pci_remove(struct pci_dev *pdev)
 969 {
 970         struct drm_device *dev = pci_get_drvdata(pdev);
 971
 972         drm_put_dev(dev);
 973 }
 974
 975 static int i915_pm_suspend(struct device *dev)
 976 {
 977         struct pci_dev *pdev = to_pci_dev(dev);
 978         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 979
 980         if (!drm_dev || !drm_dev->dev_private) {
 981                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 982                 return -ENODEV;
 983         }
 984
 985         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 986                 return 0;
 987
 988         return i915_drm_suspend(drm_dev);
 989 }
 990
 991 static int i915_pm_suspend_late(struct device *dev)
 992 {
 993         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
 994
 995         /*
 996          * We have a suspend ordering issue with the snd-hda driver also
 997          * requiring our device to be power up. Due to the lack of a
 998          * parent/child relationship we currently solve this with an late
 999          * suspend hook.
1000          *
1001          * FIXME: This should be solved with a special hdmi sink device or
1002          * similar so that power domains can be employed.
1003          */
1004         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1005                 return 0;
1006
1007         return i915_drm_suspend_late(drm_dev, false);
1008 }
1009
1010 static int i915_pm_poweroff_late(struct device *dev)
1011 {
1012         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1013
1014         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1015                 return 0;
1016
1017         return i915_drm_suspend_late(drm_dev, true);
1018 }
1019
1020 static int i915_pm_resume_early(struct device *dev)
1021 {
1022         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1023
1024         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1025                 return 0;
1026
1027         return i915_drm_resume_early(drm_dev);
1028 }
1029
1030 static int i915_pm_resume(struct device *dev)
1031 {
1032         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1033
1034         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1035                 return 0;
1036
1037         return i915_drm_resume(drm_dev);
1038 }
1039
1040 static int skl_suspend_complete(struct drm_i915_private *dev_priv)
1041 {
1042         /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1043
1044         /*
1045          * This is to ensure that CSR isn't identified as loaded before
1046          * CSR-loading program is called during runtime-resume.
1047          */
1048         intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED);
1049
1050         skl_uninit_cdclk(dev_priv);
1051
1052         return 0;
1053 }
1054
1055 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1056 {
1057         hsw_enable_pc8(dev_priv);
1058
1059         return 0;
1060 }
1061
1062 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1063 {
1064         struct drm_device *dev = dev_priv->dev;
1065
1066         /* TODO: when DC5 support is added disable DC5 here. */
1067
1068         broxton_ddi_phy_uninit(dev);
1069         broxton_uninit_cdclk(dev);
1070         bxt_enable_dc9(dev_priv);
1071
1072         return 0;
1073 }
1074
1075 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1076 {
1077         struct drm_device *dev = dev_priv->dev;
1078
1079         /* TODO: when CSR FW support is added make sure the FW is loaded */
1080
1081         bxt_disable_dc9(dev_priv);
1082
1083         /*
1084          * TODO: when DC5 support is added enable DC5 here if the CSR FW
1085          * is available.
1086          */
1087         broxton_init_cdclk(dev);
1088         broxton_ddi_phy_init(dev);
1089         intel_prepare_ddi(dev);
1090
1091         return 0;
1092 }
1093
1094 static int skl_resume_prepare(struct drm_i915_private *dev_priv)
1095 {
1096         struct drm_device *dev = dev_priv->dev;
1097
1098         skl_init_cdclk(dev_priv);
1099         intel_csr_load_program(dev);
1100
1101         return 0;
1102 }
1103
1104 /*
1105  * Save all Gunit registers that may be lost after a D3 and a subsequent
1106  * S0i[R123] transition. The list of registers needing a save/restore is
1107  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1108  * registers in the following way:
1109  * - Driver: saved/restored by the driver
1110  * - Punit : saved/restored by the Punit firmware
1111  * - No, w/o marking: no need to save/restore, since the register is R/O or
1112  *                    used internally by the HW in a way that doesn't depend
1113  *                    keeping the content across a suspend/resume.
1114  * - Debug : used for debugging
1115  *
1116  * We save/restore all registers marked with 'Driver', with the following
1117  * exceptions:
1118  * - Registers out of use, including also registers marked with 'Debug'.
1119  *   These have no effect on the driver's operation, so we don't save/restore
1120  *   them to reduce the overhead.
1121  * - Registers that are fully setup by an initialization function called from
1122  *   the resume path. For example many clock gating and RPS/RC6 registers.
1123  * - Registers that provide the right functionality with their reset defaults.
1124  *
1125  * TODO: Except for registers that based on the above 3 criteria can be safely
1126  * ignored, we save/restore all others, practically treating the HW context as
1127  * a black-box for the driver. Further investigation is needed to reduce the
1128  * saved/restored registers even further, by following the same 3 criteria.
1129  */
1130 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1131 {
1132         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1133         int i;
1134
1135         /* GAM 0x4000-0x4770 */
1136         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1137         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1138         s->arb_mode             = I915_READ(ARB_MODE);
1139         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1140         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1141
1142         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1143                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1144
1145         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1146         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1147
1148         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1149         s->ecochk               = I915_READ(GAM_ECOCHK);
1150         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1151         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1152
1153         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1154
1155         /* MBC 0x9024-0x91D0, 0x8500 */
1156         s->g3dctl               = I915_READ(VLV_G3DCTL);
1157         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1158         s->mbctl                = I915_READ(GEN6_MBCTL);
1159
1160         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1161         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1162         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1163         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1164         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1165         s->rstctl               = I915_READ(GEN6_RSTCTL);
1166         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1167
1168         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1169         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1170         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1171         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1172         s->ecobus               = I915_READ(ECOBUS);
1173         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1174         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1175         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1176         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1177         s->rcedata              = I915_READ(VLV_RCEDATA);
1178         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1179
1180         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1181         s->gt_imr               = I915_READ(GTIMR);
1182         s->gt_ier               = I915_READ(GTIER);
1183         s->pm_imr               = I915_READ(GEN6_PMIMR);
1184         s->pm_ier               = I915_READ(GEN6_PMIER);
1185
1186         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1187                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1188
1189         /* GT SA CZ domain, 0x100000-0x138124 */
1190         s->tilectl              = I915_READ(TILECTL);
1191         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1192         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1193         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1194         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1195
1196         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1197         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1198         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1199         s->pcbr                 = I915_READ(VLV_PCBR);
1200         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1201
1202         /*
1203          * Not saving any of:
1204          * DFT,         0x9800-0x9EC0
1205          * SARB,        0xB000-0xB1FC
1206          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1207          * PCI CFG
1208          */
1209 }
1210
1211 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1212 {
1213         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1214         u32 val;
1215         int i;
1216
1217         /* GAM 0x4000-0x4770 */
1218         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1219         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1220         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1221         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1222         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1223
1224         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1225                 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1226
1227         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1228         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1229
1230         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1231         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1232         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1233         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1234
1235         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1236
1237         /* MBC 0x9024-0x91D0, 0x8500 */
1238         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1239         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1240         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1241
1242         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1243         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1244         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1245         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1246         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1247         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1248         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1249
1250         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1251         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1252         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1253         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1254         I915_WRITE(ECOBUS,              s->ecobus);
1255         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1256         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1257         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1258         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1259         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1260         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1261
1262         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1263         I915_WRITE(GTIMR,               s->gt_imr);
1264         I915_WRITE(GTIER,               s->gt_ier);
1265         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1266         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1267
1268         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1269                 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1270
1271         /* GT SA CZ domain, 0x100000-0x138124 */
1272         I915_WRITE(TILECTL,                     s->tilectl);
1273         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1274         /*
1275          * Preserve the GT allow wake and GFX force clock bit, they are not
1276          * be restored, as they are used to control the s0ix suspend/resume
1277          * sequence by the caller.
1278          */
1279         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1280         val &= VLV_GTLC_ALLOWWAKEREQ;
1281         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1282         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1283
1284         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1285         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1286         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1287         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1288
1289         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1290
1291         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1292         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1293         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1294         I915_WRITE(VLV_PCBR,                    s->pcbr);
1295         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1296 }
1297
1298 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1299 {
1300         u32 val;
1301         int err;
1302
1303 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1304
1305         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1306         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1307         if (force_on)
1308                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1309         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1310
1311         if (!force_on)
1312                 return 0;
1313
1314         err = wait_for(COND, 20);
1315         if (err)
1316                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1317                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1318
1319         return err;
1320 #undef COND
1321 }
1322
1323 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1324 {
1325         u32 val;
1326         int err = 0;
1327
1328         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1329         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1330         if (allow)
1331                 val |= VLV_GTLC_ALLOWWAKEREQ;
1332         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1333         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1334
1335 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1336               allow)
1337         err = wait_for(COND, 1);
1338         if (err)
1339                 DRM_ERROR("timeout disabling GT waking\n");
1340         return err;
1341 #undef COND
1342 }
1343
1344 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1345                                  bool wait_for_on)
1346 {
1347         u32 mask;
1348         u32 val;
1349         int err;
1350
1351         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1352         val = wait_for_on ? mask : 0;
1353 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1354         if (COND)
1355                 return 0;
1356
1357         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1358                         wait_for_on ? "on" : "off",
1359                         I915_READ(VLV_GTLC_PW_STATUS));
1360
1361         /*
1362          * RC6 transitioning can be delayed up to 2 msec (see
1363          * valleyview_enable_rps), use 3 msec for safety.
1364          */
1365         err = wait_for(COND, 3);
1366         if (err)
1367                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1368                           wait_for_on ? "on" : "off");
1369
1370         return err;
1371 #undef COND
1372 }
1373
1374 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1375 {
1376         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1377                 return;
1378
1379         DRM_ERROR("GT register access while GT waking disabled\n");
1380         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1381 }
1382
1383 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1384 {
1385         u32 mask;
1386         int err;
1387
1388         /*
1389          * Bspec defines the following GT well on flags as debug only, so
1390          * don't treat them as hard failures.
1391          */
1392         (void)vlv_wait_for_gt_wells(dev_priv, false);
1393
1394         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1395         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1396
1397         vlv_check_no_gt_access(dev_priv);
1398
1399         err = vlv_force_gfx_clock(dev_priv, true);
1400         if (err)
1401                 goto err1;
1402
1403         err = vlv_allow_gt_wake(dev_priv, false);
1404         if (err)
1405                 goto err2;
1406
1407         if (!IS_CHERRYVIEW(dev_priv->dev))
1408                 vlv_save_gunit_s0ix_state(dev_priv);
1409
1410         err = vlv_force_gfx_clock(dev_priv, false);
1411         if (err)
1412                 goto err2;
1413
1414         return 0;
1415
1416 err2:
1417         /* For safety always re-enable waking and disable gfx clock forcing */
1418         vlv_allow_gt_wake(dev_priv, true);
1419 err1:
1420         vlv_force_gfx_clock(dev_priv, false);
1421
1422         return err;
1423 }
1424
1425 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1426                                 bool rpm_resume)
1427 {
1428         struct drm_device *dev = dev_priv->dev;
1429         int err;
1430         int ret;
1431
1432         /*
1433          * If any of the steps fail just try to continue, that's the best we
1434          * can do at this point. Return the first error code (which will also
1435          * leave RPM permanently disabled).
1436          */
1437         ret = vlv_force_gfx_clock(dev_priv, true);
1438
1439         if (!IS_CHERRYVIEW(dev_priv->dev))
1440                 vlv_restore_gunit_s0ix_state(dev_priv);
1441
1442         err = vlv_allow_gt_wake(dev_priv, true);
1443         if (!ret)
1444                 ret = err;
1445
1446         err = vlv_force_gfx_clock(dev_priv, false);
1447         if (!ret)
1448                 ret = err;
1449
1450         vlv_check_no_gt_access(dev_priv);
1451
1452         if (rpm_resume) {
1453                 intel_init_clock_gating(dev);
1454                 i915_gem_restore_fences(dev);
1455         }
1456
1457         return ret;
1458 }
1459
1460 static int intel_runtime_suspend(struct device *device)
1461 {
1462         struct pci_dev *pdev = to_pci_dev(device);
1463         struct drm_device *dev = pci_get_drvdata(pdev);
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465         int ret;
1466
1467         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1468                 return -ENODEV;
1469
1470         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1471                 return -ENODEV;
1472
1473         DRM_DEBUG_KMS("Suspending device\n");
1474
1475         /*
1476          * We could deadlock here in case another thread holding struct_mutex
1477          * calls RPM suspend concurrently, since the RPM suspend will wait
1478          * first for this RPM suspend to finish. In this case the concurrent
1479          * RPM resume will be followed by its RPM suspend counterpart. Still
1480          * for consistency return -EAGAIN, which will reschedule this suspend.
1481          */
1482         if (!mutex_trylock(&dev->struct_mutex)) {
1483                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1484                 /*
1485                  * Bump the expiration timestamp, otherwise the suspend won't
1486                  * be rescheduled.
1487                  */
1488                 pm_runtime_mark_last_busy(device);
1489
1490                 return -EAGAIN;
1491         }
1492         /*
1493          * We are safe here against re-faults, since the fault handler takes
1494          * an RPM reference.
1495          */
1496         i915_gem_release_all_mmaps(dev_priv);
1497         mutex_unlock(&dev->struct_mutex);
1498
1499         intel_suspend_gt_powersave(dev);
1500         intel_runtime_pm_disable_interrupts(dev_priv);
1501
1502         ret = intel_suspend_complete(dev_priv);
1503         if (ret) {
1504                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1505                 intel_runtime_pm_enable_interrupts(dev_priv);
1506
1507                 return ret;
1508         }
1509
1510         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1511         intel_uncore_forcewake_reset(dev, false);
1512         dev_priv->pm.suspended = true;
1513
1514         /*
1515          * FIXME: We really should find a document that references the arguments
1516          * used below!
1517          */
1518         if (IS_HASWELL(dev)) {
1519                 /*
1520                  * current versions of firmware which depend on this opregion
1521                  * notification have repurposed the D1 definition to mean
1522                  * "runtime suspended" vs. what you would normally expect (D3)
1523                  * to distinguish it from notifications that might be sent via
1524                  * the suspend path.
1525                  */
1526                 intel_opregion_notify_adapter(dev, PCI_D1);
1527         } else {
1528                 /*
1529                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1530                  * being detected, and the call we do at intel_runtime_resume()
1531                  * won't be able to restore them. Since PCI_D3hot matches the
1532                  * actual specification and appears to be working, use it. Let's
1533                  * assume the other non-Haswell platforms will stay the same as
1534                  * Broadwell.
1535                  */
1536                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1537         }
1538
1539         assert_forcewakes_inactive(dev_priv);
1540
1541         DRM_DEBUG_KMS("Device suspended\n");
1542         return 0;
1543 }
1544
1545 static int intel_runtime_resume(struct device *device)
1546 {
1547         struct pci_dev *pdev = to_pci_dev(device);
1548         struct drm_device *dev = pci_get_drvdata(pdev);
1549         struct drm_i915_private *dev_priv = dev->dev_private;
1550         int ret = 0;
1551
1552         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1553                 return -ENODEV;
1554
1555         DRM_DEBUG_KMS("Resuming device\n");
1556
1557         intel_opregion_notify_adapter(dev, PCI_D0);
1558         dev_priv->pm.suspended = false;
1559
1560         if (IS_GEN6(dev_priv))
1561                 intel_init_pch_refclk(dev);
1562
1563         if (IS_BROXTON(dev))
1564                 ret = bxt_resume_prepare(dev_priv);
1565         else if (IS_SKYLAKE(dev))
1566                 ret = skl_resume_prepare(dev_priv);
1567         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1568                 hsw_disable_pc8(dev_priv);
1569         else if (IS_VALLEYVIEW(dev_priv))
1570                 ret = vlv_resume_prepare(dev_priv, true);
1571
1572         /*
1573          * No point of rolling back things in case of an error, as the best
1574          * we can do is to hope that things will still work (and disable RPM).
1575          */
1576         i915_gem_init_swizzling(dev);
1577         gen6_update_ring_freq(dev);
1578
1579         intel_runtime_pm_enable_interrupts(dev_priv);
1580         intel_enable_gt_powersave(dev);
1581
1582         if (ret)
1583                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1584         else
1585                 DRM_DEBUG_KMS("Device resumed\n");
1586
1587         return ret;
1588 }
1589
1590 /*
1591  * This function implements common functionality of runtime and system
1592  * suspend sequence.
1593  */
1594 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1595 {
1596         int ret;
1597
1598         if (IS_BROXTON(dev_priv))
1599                 ret = bxt_suspend_complete(dev_priv);
1600         else if (IS_SKYLAKE(dev_priv))
1601                 ret = skl_suspend_complete(dev_priv);
1602         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1603                 ret = hsw_suspend_complete(dev_priv);
1604         else if (IS_VALLEYVIEW(dev_priv))
1605                 ret = vlv_suspend_complete(dev_priv);
1606         else
1607                 ret = 0;
1608
1609         return ret;
1610 }
1611
1612 static const struct dev_pm_ops i915_pm_ops = {
1613         /*
1614          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1615          * PMSG_RESUME]
1616          */
1617         .suspend = i915_pm_suspend,
1618         .suspend_late = i915_pm_suspend_late,
1619         .resume_early = i915_pm_resume_early,
1620         .resume = i915_pm_resume,
1621
1622         /*
1623          * S4 event handlers
1624          * @freeze, @freeze_late    : called (1) before creating the
1625          *                            hibernation image [PMSG_FREEZE] and
1626          *                            (2) after rebooting, before restoring
1627          *                            the image [PMSG_QUIESCE]
1628          * @thaw, @thaw_early       : called (1) after creating the hibernation
1629          *                            image, before writing it [PMSG_THAW]
1630          *                            and (2) after failing to create or
1631          *                            restore the image [PMSG_RECOVER]
1632          * @poweroff, @poweroff_late: called after writing the hibernation
1633          *                            image, before rebooting [PMSG_HIBERNATE]
1634          * @restore, @restore_early : called after rebooting and restoring the
1635          *                            hibernation image [PMSG_RESTORE]
1636          */
1637         .freeze = i915_pm_suspend,
1638         .freeze_late = i915_pm_suspend_late,
1639         .thaw_early = i915_pm_resume_early,
1640         .thaw = i915_pm_resume,
1641         .poweroff = i915_pm_suspend,
1642         .poweroff_late = i915_pm_poweroff_late,
1643         .restore_early = i915_pm_resume_early,
1644         .restore = i915_pm_resume,
1645
1646         /* S0ix (via runtime suspend) event handlers */
1647         .runtime_suspend = intel_runtime_suspend,
1648         .runtime_resume = intel_runtime_resume,
1649 };
1650
1651 static const struct vm_operations_struct i915_gem_vm_ops = {
1652         .fault = i915_gem_fault,
1653         .open = drm_gem_vm_open,
1654         .close = drm_gem_vm_close,
1655 };
1656
1657 static const struct file_operations i915_driver_fops = {
1658         .owner = THIS_MODULE,
1659         .open = drm_open,
1660         .release = drm_release,
1661         .unlocked_ioctl = drm_ioctl,
1662         .mmap = drm_gem_mmap,
1663         .poll = drm_poll,
1664         .read = drm_read,
1665 #ifdef CONFIG_COMPAT
1666         .compat_ioctl = i915_compat_ioctl,
1667 #endif
1668         .llseek = noop_llseek,
1669 };
1670
1671 static struct drm_driver driver = {
1672         /* Don't use MTRRs here; the Xserver or userspace app should
1673          * deal with them for Intel hardware.
1674          */
1675         .driver_features =
1676             DRIVER_USE_AGP |
1677             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1678             DRIVER_RENDER,
1679         .load = i915_driver_load,
1680         .unload = i915_driver_unload,
1681         .open = i915_driver_open,
1682         .lastclose = i915_driver_lastclose,
1683         .preclose = i915_driver_preclose,
1684         .postclose = i915_driver_postclose,
1685         .set_busid = drm_pci_set_busid,
1686
1687         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1688         .suspend = i915_suspend_legacy,
1689         .resume = i915_resume_legacy,
1690
1691         .device_is_agp = i915_driver_device_is_agp,
1692 #if defined(CONFIG_DEBUG_FS)
1693         .debugfs_init = i915_debugfs_init,
1694         .debugfs_cleanup = i915_debugfs_cleanup,
1695 #endif
1696         .gem_free_object = i915_gem_free_object,
1697         .gem_vm_ops = &i915_gem_vm_ops,
1698
1699         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1700         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1701         .gem_prime_export = i915_gem_prime_export,
1702         .gem_prime_import = i915_gem_prime_import,
1703
1704         .dumb_create = i915_gem_dumb_create,
1705         .dumb_map_offset = i915_gem_mmap_gtt,
1706         .dumb_destroy = drm_gem_dumb_destroy,
1707         .ioctls = i915_ioctls,
1708         .fops = &i915_driver_fops,
1709         .name = DRIVER_NAME,
1710         .desc = DRIVER_DESC,
1711         .date = DRIVER_DATE,
1712         .major = DRIVER_MAJOR,
1713         .minor = DRIVER_MINOR,
1714         .patchlevel = DRIVER_PATCHLEVEL,
1715 };
1716
1717 static struct pci_driver i915_pci_driver = {
1718         .name = DRIVER_NAME,
1719         .id_table = pciidlist,
1720         .probe = i915_pci_probe,
1721         .remove = i915_pci_remove,
1722         .driver.pm = &i915_pm_ops,
1723 };
1724
1725 static int __init i915_init(void)
1726 {
1727         driver.num_ioctls = i915_max_ioctl;
1728
1729         /*
1730          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1731          * explicitly disabled with the module pararmeter.
1732          *
1733          * Otherwise, just follow the parameter (defaulting to off).
1734          *
1735          * Allow optional vga_text_mode_force boot option to override
1736          * the default behavior.
1737          */
1738 #if defined(CONFIG_DRM_I915_KMS)
1739         if (i915.modeset != 0)
1740                 driver.driver_features |= DRIVER_MODESET;
1741 #endif
1742         if (i915.modeset == 1)
1743                 driver.driver_features |= DRIVER_MODESET;
1744
1745 #ifdef CONFIG_VGA_CONSOLE
1746         if (vgacon_text_force() && i915.modeset == -1)
1747                 driver.driver_features &= ~DRIVER_MODESET;
1748 #endif
1749
1750         if (!(driver.driver_features & DRIVER_MODESET)) {
1751                 driver.get_vblank_timestamp = NULL;
1752                 /* Silently fail loading to not upset userspace. */
1753                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1754                 return 0;
1755         }
1756
1757         /*
1758          * FIXME: Note that we're lying to the DRM core here so that we can get access
1759          * to the atomic ioctl and the atomic properties.  Only plane operations on
1760          * a single CRTC will actually work.
1761          */
1762         if (i915.nuclear_pageflip)
1763                 driver.driver_features |= DRIVER_ATOMIC;
1764
1765         return drm_pci_init(&driver, &i915_pci_driver);
1766 }
1767
1768 static void __exit i915_exit(void)
1769 {
1770         if (!(driver.driver_features & DRIVER_MODESET))
1771                 return; /* Never loaded a driver. */
1772
1773         drm_pci_exit(&driver, &i915_pci_driver);
1774 }
1775
1776 module_init(i915_init);
1777 module_exit(i915_exit);
1778
1779 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1780 MODULE_AUTHOR("Intel Corporation");
1781
1782 MODULE_DESCRIPTION(DRIVER_DESC);
1783 MODULE_LICENSE("GPL and additional rights");