drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *kdev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(kdev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 182                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 183                                 /* PantherPoint is CPT compatible */
 184                                 dev_priv->pch_type = PCH_CPT;
 185                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 186                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 187                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_LPT;
 189                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 190                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 191                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 192                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 193                                 dev_priv->pch_type = PCH_LPT;
 194                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 195                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 196                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 197                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_SPT;
 199                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 200                                 WARN_ON(!IS_SKYLAKE(dev) &&
 201                                         !IS_KABYLAKE(dev));
 202                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 203                                 dev_priv->pch_type = PCH_SPT;
 204                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 205                                 WARN_ON(!IS_SKYLAKE(dev) &&
 206                                         !IS_KABYLAKE(dev));
 207                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 208                                 dev_priv->pch_type = PCH_KBP;
 209                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 210                                 WARN_ON(!IS_KABYLAKE(dev));
 211                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 212                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 213                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 214                                     pch->subsystem_vendor ==
 215                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 216                                     pch->subsystem_device ==
 217                                             PCI_SUBDEVICE_ID_QEMU)) {
 218                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 219                         } else
 220                                 continue;
 221
 222                         break;
 223                 }
 224         }
 225         if (!pch)
 226                 DRM_DEBUG_KMS("No PCH found.\n");
 227
 228         pci_dev_put(pch);
 229 }
 230
 231 static int i915_getparam(struct drm_device *dev, void *data,
 232                          struct drm_file *file_priv)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(dev);
 235         struct pci_dev *pdev = dev_priv->drm.pdev;
 236         drm_i915_getparam_t *param = data;
 237         int value;
 238
 239         switch (param->param) {
 240         case I915_PARAM_IRQ_ACTIVE:
 241         case I915_PARAM_ALLOW_BATCHBUFFER:
 242         case I915_PARAM_LAST_DISPATCH:
 243         case I915_PARAM_HAS_EXEC_CONSTANTS:
 244                 /* Reject all old ums/dri params. */
 245                 return -ENODEV;
 246         case I915_PARAM_CHIPSET_ID:
 247                 value = pdev->device;
 248                 break;
 249         case I915_PARAM_REVISION:
 250                 value = pdev->revision;
 251                 break;
 252         case I915_PARAM_NUM_FENCES_AVAIL:
 253                 value = dev_priv->num_fence_regs;
 254                 break;
 255         case I915_PARAM_HAS_OVERLAY:
 256                 value = dev_priv->overlay ? 1 : 0;
 257                 break;
 258         case I915_PARAM_HAS_BSD:
 259                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 260                 break;
 261         case I915_PARAM_HAS_BLT:
 262                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 263                 break;
 264         case I915_PARAM_HAS_VEBOX:
 265                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 266                 break;
 267         case I915_PARAM_HAS_BSD2:
 268                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 269                 break;
 270         case I915_PARAM_HAS_LLC:
 271                 value = HAS_LLC(dev_priv);
 272                 break;
 273         case I915_PARAM_HAS_WT:
 274                 value = HAS_WT(dev_priv);
 275                 break;
 276         case I915_PARAM_HAS_ALIASING_PPGTT:
 277                 value = USES_PPGTT(dev_priv);
 278                 break;
 279         case I915_PARAM_HAS_SEMAPHORES:
 280                 value = i915.semaphores;
 281                 break;
 282         case I915_PARAM_HAS_SECURE_BATCHES:
 283                 value = capable(CAP_SYS_ADMIN);
 284                 break;
 285         case I915_PARAM_CMD_PARSER_VERSION:
 286                 value = i915_cmd_parser_get_version(dev_priv);
 287                 break;
 288         case I915_PARAM_SUBSLICE_TOTAL:
 289                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 290                 if (!value)
 291                         return -ENODEV;
 292                 break;
 293         case I915_PARAM_EU_TOTAL:
 294                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 295                 if (!value)
 296                         return -ENODEV;
 297                 break;
 298         case I915_PARAM_HAS_GPU_RESET:
 299                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 300                 break;
 301         case I915_PARAM_HAS_RESOURCE_STREAMER:
 302                 value = HAS_RESOURCE_STREAMER(dev_priv);
 303                 break;
 304         case I915_PARAM_HAS_POOLED_EU:
 305                 value = HAS_POOLED_EU(dev_priv);
 306                 break;
 307         case I915_PARAM_MIN_EU_IN_POOL:
 308                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 309                 break;
 310         case I915_PARAM_MMAP_GTT_VERSION:
 311                 /* Though we've started our numbering from 1, and so class all
 312                  * earlier versions as 0, in effect their value is undefined as
 313                  * the ioctl will report EINVAL for the unknown param!
 314                  */
 315                 value = i915_gem_mmap_gtt_version();
 316                 break;
 317         case I915_PARAM_MMAP_VERSION:
 318                 /* Remember to bump this if the version changes! */
 319         case I915_PARAM_HAS_GEM:
 320         case I915_PARAM_HAS_PAGEFLIPPING:
 321         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 322         case I915_PARAM_HAS_RELAXED_FENCING:
 323         case I915_PARAM_HAS_COHERENT_RINGS:
 324         case I915_PARAM_HAS_RELAXED_DELTA:
 325         case I915_PARAM_HAS_GEN7_SOL_RESET:
 326         case I915_PARAM_HAS_WAIT_TIMEOUT:
 327         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 328         case I915_PARAM_HAS_PINNED_BATCHES:
 329         case I915_PARAM_HAS_EXEC_NO_RELOC:
 330         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 331         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 332         case I915_PARAM_HAS_EXEC_SOFTPIN:
 333                 /* For the time being all of these are always true;
 334                  * if some supported hardware does not have one of these
 335                  * features this value needs to be provided from
 336                  * INTEL_INFO(), a feature macro, or similar.
 337                  */
 338                 value = 1;
 339                 break;
 340         default:
 341                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 342                 return -EINVAL;
 343         }
 344
 345         if (put_user(value, param->value))
 346                 return -EFAULT;
 347
 348         return 0;
 349 }
 350
 351 static int i915_get_bridge_dev(struct drm_device *dev)
 352 {
 353         struct drm_i915_private *dev_priv = to_i915(dev);
 354
 355         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 356         if (!dev_priv->bridge_dev) {
 357                 DRM_ERROR("bridge device not found\n");
 358                 return -1;
 359         }
 360         return 0;
 361 }
 362
 363 /* Allocate space for the MCH regs if needed, return nonzero on error */
 364 static int
 365 intel_alloc_mchbar_resource(struct drm_device *dev)
 366 {
 367         struct drm_i915_private *dev_priv = to_i915(dev);
 368         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 369         u32 temp_lo, temp_hi = 0;
 370         u64 mchbar_addr;
 371         int ret;
 372
 373         if (INTEL_INFO(dev)->gen >= 4)
 374                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 375         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 376         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 377
 378         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 379 #ifdef CONFIG_PNP
 380         if (mchbar_addr &&
 381             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 382                 return 0;
 383 #endif
 384
 385         /* Get some space for it */
 386         dev_priv->mch_res.name = "i915 MCHBAR";
 387         dev_priv->mch_res.flags = IORESOURCE_MEM;
 388         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 389                                      &dev_priv->mch_res,
 390                                      MCHBAR_SIZE, MCHBAR_SIZE,
 391                                      PCIBIOS_MIN_MEM,
 392                                      0, pcibios_align_resource,
 393                                      dev_priv->bridge_dev);
 394         if (ret) {
 395                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 396                 dev_priv->mch_res.start = 0;
 397                 return ret;
 398         }
 399
 400         if (INTEL_INFO(dev)->gen >= 4)
 401                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 402                                        upper_32_bits(dev_priv->mch_res.start));
 403
 404         pci_write_config_dword(dev_priv->bridge_dev, reg,
 405                                lower_32_bits(dev_priv->mch_res.start));
 406         return 0;
 407 }
 408
 409 /* Setup MCHBAR if possible, return true if we should disable it again */
 410 static void
 411 intel_setup_mchbar(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = to_i915(dev);
 414         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 415         u32 temp;
 416         bool enabled;
 417
 418         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 419                 return;
 420
 421         dev_priv->mchbar_need_disable = false;
 422
 423         if (IS_I915G(dev) || IS_I915GM(dev)) {
 424                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 425                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 426         } else {
 427                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 428                 enabled = temp & 1;
 429         }
 430
 431         /* If it's already enabled, don't have to do anything */
 432         if (enabled)
 433                 return;
 434
 435         if (intel_alloc_mchbar_resource(dev))
 436                 return;
 437
 438         dev_priv->mchbar_need_disable = true;
 439
 440         /* Space is allocated or reserved, so enable it. */
 441         if (IS_I915G(dev) || IS_I915GM(dev)) {
 442                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 443                                        temp | DEVEN_MCHBAR_EN);
 444         } else {
 445                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 446                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 447         }
 448 }
 449
 450 static void
 451 intel_teardown_mchbar(struct drm_device *dev)
 452 {
 453         struct drm_i915_private *dev_priv = to_i915(dev);
 454         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 455
 456         if (dev_priv->mchbar_need_disable) {
 457                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 458                         u32 deven_val;
 459
 460                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 461                                               &deven_val);
 462                         deven_val &= ~DEVEN_MCHBAR_EN;
 463                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 464                                                deven_val);
 465                 } else {
 466                         u32 mchbar_val;
 467
 468                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 469                                               &mchbar_val);
 470                         mchbar_val &= ~1;
 471                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 472                                                mchbar_val);
 473                 }
 474         }
 475
 476         if (dev_priv->mch_res.start)
 477                 release_resource(&dev_priv->mch_res);
 478 }
 479
 480 /* true = enable decode, false = disable decoder */
 481 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 482 {
 483         struct drm_device *dev = cookie;
 484
 485         intel_modeset_vga_set_state(dev, state);
 486         if (state)
 487                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 488                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 489         else
 490                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 491 }
 492
 493 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 494 {
 495         struct drm_device *dev = pci_get_drvdata(pdev);
 496         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 497
 498         if (state == VGA_SWITCHEROO_ON) {
 499                 pr_info("switched on\n");
 500                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 501                 /* i915 resume handler doesn't set to D0 */
 502                 pci_set_power_state(pdev, PCI_D0);
 503                 i915_resume_switcheroo(dev);
 504                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 505         } else {
 506                 pr_info("switched off\n");
 507                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 508                 i915_suspend_switcheroo(dev, pmm);
 509                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 510         }
 511 }
 512
 513 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 514 {
 515         struct drm_device *dev = pci_get_drvdata(pdev);
 516
 517         /*
 518          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 519          * locking inversion with the driver load path. And the access here is
 520          * completely racy anyway. So don't bother with locking for now.
 521          */
 522         return dev->open_count == 0;
 523 }
 524
 525 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 526         .set_gpu_state = i915_switcheroo_set_state,
 527         .reprobe = NULL,
 528         .can_switch = i915_switcheroo_can_switch,
 529 };
 530
 531 static void i915_gem_fini(struct drm_device *dev)
 532 {
 533         struct drm_i915_private *dev_priv = to_i915(dev);
 534
 535         /*
 536          * Neither the BIOS, ourselves or any other kernel
 537          * expects the system to be in execlists mode on startup,
 538          * so we need to reset the GPU back to legacy mode. And the only
 539          * known way to disable logical contexts is through a GPU reset.
 540          *
 541          * So in order to leave the system in a known default configuration,
 542          * always reset the GPU upon unload. Afterwards we then clean up the
 543          * GEM state tracking, flushing off the requests and leaving the
 544          * system in a known idle state.
 545          *
 546          * Note that is of the upmost importance that the GPU is idle and
 547          * all stray writes are flushed *before* we dismantle the backing
 548          * storage for the pinned objects.
 549          *
 550          * However, since we are uncertain that reseting the GPU on older
 551          * machines is a good idea, we don't - just in case it leaves the
 552          * machine in an unusable condition.
 553          */
 554         if (HAS_HW_CONTEXTS(dev)) {
 555                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 556                 WARN_ON(reset && reset != -ENODEV);
 557         }
 558
 559         mutex_lock(&dev->struct_mutex);
 560         i915_gem_cleanup_engines(dev);
 561         i915_gem_context_fini(dev);
 562         mutex_unlock(&dev->struct_mutex);
 563
 564         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 565 }
 566
 567 static int i915_load_modeset_init(struct drm_device *dev)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(dev);
 570         struct pci_dev *pdev = dev_priv->drm.pdev;
 571         int ret;
 572
 573         if (i915_inject_load_failure())
 574                 return -ENODEV;
 575
 576         intel_bios_init(dev_priv);
 577
 578         /* If we have > 1 VGA cards, then we need to arbitrate access
 579          * to the common VGA resources.
 580          *
 581          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 582          * then we do not take part in VGA arbitration and the
 583          * vga_client_register() fails with -ENODEV.
 584          */
 585         ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
 586         if (ret && ret != -ENODEV)
 587                 goto out;
 588
 589         intel_register_dsm_handler();
 590
 591         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 592         if (ret)
 593                 goto cleanup_vga_client;
 594
 595         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 596         intel_update_rawclk(dev_priv);
 597
 598         intel_power_domains_init_hw(dev_priv, false);
 599
 600         intel_csr_ucode_init(dev_priv);
 601
 602         ret = intel_irq_install(dev_priv);
 603         if (ret)
 604                 goto cleanup_csr;
 605
 606         intel_setup_gmbus(dev);
 607
 608         /* Important: The output setup functions called by modeset_init need
 609          * working irqs for e.g. gmbus and dp aux transfers. */
 610         intel_modeset_init(dev);
 611
 612         intel_guc_init(dev);
 613
 614         ret = i915_gem_init(dev);
 615         if (ret)
 616                 goto cleanup_irq;
 617
 618         intel_modeset_gem_init(dev);
 619
 620         if (INTEL_INFO(dev)->num_pipes == 0)
 621                 return 0;
 622
 623         ret = intel_fbdev_init(dev);
 624         if (ret)
 625                 goto cleanup_gem;
 626
 627         /* Only enable hotplug handling once the fbdev is fully set up. */
 628         intel_hpd_init(dev_priv);
 629
 630         drm_kms_helper_poll_init(dev);
 631
 632         return 0;
 633
 634 cleanup_gem:
 635         i915_gem_fini(dev);
 636 cleanup_irq:
 637         intel_guc_fini(dev);
 638         drm_irq_uninstall(dev);
 639         intel_teardown_gmbus(dev);
 640 cleanup_csr:
 641         intel_csr_ucode_fini(dev_priv);
 642         intel_power_domains_fini(dev_priv);
 643         vga_switcheroo_unregister_client(pdev);
 644 cleanup_vga_client:
 645         vga_client_register(pdev, NULL, NULL, NULL);
 646 out:
 647         return ret;
 648 }
 649
 650 #if IS_ENABLED(CONFIG_FB)
 651 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 652 {
 653         struct apertures_struct *ap;
 654         struct pci_dev *pdev = dev_priv->drm.pdev;
 655         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 656         bool primary;
 657         int ret;
 658
 659         ap = alloc_apertures(1);
 660         if (!ap)
 661                 return -ENOMEM;
 662
 663         ap->ranges[0].base = ggtt->mappable_base;
 664         ap->ranges[0].size = ggtt->mappable_end;
 665
 666         primary =
 667                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 668
 669         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 670
 671         kfree(ap);
 672
 673         return ret;
 674 }
 675 #else
 676 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 677 {
 678         return 0;
 679 }
 680 #endif
 681
 682 #if !defined(CONFIG_VGA_CONSOLE)
 683 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 684 {
 685         return 0;
 686 }
 687 #elif !defined(CONFIG_DUMMY_CONSOLE)
 688 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 689 {
 690         return -ENODEV;
 691 }
 692 #else
 693 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 694 {
 695         int ret = 0;
 696
 697         DRM_INFO("Replacing VGA console driver\n");
 698
 699         console_lock();
 700         if (con_is_bound(&vga_con))
 701                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 702         if (ret == 0) {
 703                 ret = do_unregister_con_driver(&vga_con);
 704
 705                 /* Ignore "already unregistered". */
 706                 if (ret == -ENODEV)
 707                         ret = 0;
 708         }
 709         console_unlock();
 710
 711         return ret;
 712 }
 713 #endif
 714
 715 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 716 {
 717         /*
 718          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 719          * CHV x1 PHY (DP/HDMI D)
 720          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 721          */
 722         if (IS_CHERRYVIEW(dev_priv)) {
 723                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 724                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 725         } else if (IS_VALLEYVIEW(dev_priv)) {
 726                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 727         }
 728 }
 729
 730 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 731 {
 732         /*
 733          * The i915 workqueue is primarily used for batched retirement of
 734          * requests (and thus managing bo) once the task has been completed
 735          * by the GPU. i915_gem_retire_requests() is called directly when we
 736          * need high-priority retirement, such as waiting for an explicit
 737          * bo.
 738          *
 739          * It is also used for periodic low-priority events, such as
 740          * idle-timers and recording error state.
 741          *
 742          * All tasks on the workqueue are expected to acquire the dev mutex
 743          * so there is no point in running more than one instance of the
 744          * workqueue at any time.  Use an ordered one.
 745          */
 746         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 747         if (dev_priv->wq == NULL)
 748                 goto out_err;
 749
 750         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 751         if (dev_priv->hotplug.dp_wq == NULL)
 752                 goto out_free_wq;
 753
 754         return 0;
 755
 756 out_free_wq:
 757         destroy_workqueue(dev_priv->wq);
 758 out_err:
 759         DRM_ERROR("Failed to allocate workqueues.\n");
 760
 761         return -ENOMEM;
 762 }
 763
 764 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 765 {
 766         destroy_workqueue(dev_priv->hotplug.dp_wq);
 767         destroy_workqueue(dev_priv->wq);
 768 }
 769
 770 /**
 771  * i915_driver_init_early - setup state not requiring device access
 772  * @dev_priv: device private
 773  *
 774  * Initialize everything that is a "SW-only" state, that is state not
 775  * requiring accessing the device or exposing the driver via kernel internal
 776  * or userspace interfaces. Example steps belonging here: lock initialization,
 777  * system memory allocation, setting up device specific attributes and
 778  * function hooks not requiring accessing the device.
 779  */
 780 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 781                                   const struct pci_device_id *ent)
 782 {
 783         const struct intel_device_info *match_info =
 784                 (struct intel_device_info *)ent->driver_data;
 785         struct intel_device_info *device_info;
 786         int ret = 0;
 787
 788         if (i915_inject_load_failure())
 789                 return -ENODEV;
 790
 791         /* Setup the write-once "constant" device info */
 792         device_info = mkwrite_device_info(dev_priv);
 793         memcpy(device_info, match_info, sizeof(*device_info));
 794         device_info->device_id = dev_priv->drm.pdev->device;
 795
 796         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 797         device_info->gen_mask = BIT(device_info->gen - 1);
 798
 799         spin_lock_init(&dev_priv->irq_lock);
 800         spin_lock_init(&dev_priv->gpu_error.lock);
 801         mutex_init(&dev_priv->backlight_lock);
 802         spin_lock_init(&dev_priv->uncore.lock);
 803         spin_lock_init(&dev_priv->mm.object_stat_lock);
 804         spin_lock_init(&dev_priv->mmio_flip_lock);
 805         mutex_init(&dev_priv->sb_lock);
 806         mutex_init(&dev_priv->modeset_restore_lock);
 807         mutex_init(&dev_priv->av_mutex);
 808         mutex_init(&dev_priv->wm.wm_mutex);
 809         mutex_init(&dev_priv->pps_mutex);
 810
 811         i915_memcpy_init_early(dev_priv);
 812
 813         ret = i915_workqueues_init(dev_priv);
 814         if (ret < 0)
 815                 return ret;
 816
 817         ret = intel_gvt_init(dev_priv);
 818         if (ret < 0)
 819                 goto err_workqueues;
 820
 821         /* This must be called before any calls to HAS_PCH_* */
 822         intel_detect_pch(&dev_priv->drm);
 823
 824         intel_pm_setup(&dev_priv->drm);
 825         intel_init_dpio(dev_priv);
 826         intel_power_domains_init(dev_priv);
 827         intel_irq_init(dev_priv);
 828         intel_init_display_hooks(dev_priv);
 829         intel_init_clock_gating_hooks(dev_priv);
 830         intel_init_audio_hooks(dev_priv);
 831         i915_gem_load_init(&dev_priv->drm);
 832
 833         intel_display_crc_init(dev_priv);
 834
 835         intel_device_info_dump(dev_priv);
 836
 837         /* Not all pre-production machines fall into this category, only the
 838          * very first ones. Almost everything should work, except for maybe
 839          * suspend/resume. And we don't implement workarounds that affect only
 840          * pre-production machines. */
 841         if (IS_HSW_EARLY_SDV(dev_priv))
 842                 DRM_INFO("This is an early pre-production Haswell machine. "
 843                          "It may not be fully functional.\n");
 844
 845         return 0;
 846
 847 err_workqueues:
 848         i915_workqueues_cleanup(dev_priv);
 849         return ret;
 850 }
 851
 852 /**
 853  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 854  * @dev_priv: device private
 855  */
 856 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 857 {
 858         i915_gem_load_cleanup(&dev_priv->drm);
 859         i915_workqueues_cleanup(dev_priv);
 860 }
 861
 862 static int i915_mmio_setup(struct drm_device *dev)
 863 {
 864         struct drm_i915_private *dev_priv = to_i915(dev);
 865         struct pci_dev *pdev = dev_priv->drm.pdev;
 866         int mmio_bar;
 867         int mmio_size;
 868
 869         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 870         /*
 871          * Before gen4, the registers and the GTT are behind different BARs.
 872          * However, from gen4 onwards, the registers and the GTT are shared
 873          * in the same BAR, so we want to restrict this ioremap from
 874          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 875          * the register BAR remains the same size for all the earlier
 876          * generations up to Ironlake.
 877          */
 878         if (INTEL_INFO(dev)->gen < 5)
 879                 mmio_size = 512 * 1024;
 880         else
 881                 mmio_size = 2 * 1024 * 1024;
 882         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 883         if (dev_priv->regs == NULL) {
 884                 DRM_ERROR("failed to map registers\n");
 885
 886                 return -EIO;
 887         }
 888
 889         /* Try to make sure MCHBAR is enabled before poking at it */
 890         intel_setup_mchbar(dev);
 891
 892         return 0;
 893 }
 894
 895 static void i915_mmio_cleanup(struct drm_device *dev)
 896 {
 897         struct drm_i915_private *dev_priv = to_i915(dev);
 898         struct pci_dev *pdev = dev_priv->drm.pdev;
 899
 900         intel_teardown_mchbar(dev);
 901         pci_iounmap(pdev, dev_priv->regs);
 902 }
 903
 904 /**
 905  * i915_driver_init_mmio - setup device MMIO
 906  * @dev_priv: device private
 907  *
 908  * Setup minimal device state necessary for MMIO accesses later in the
 909  * initialization sequence. The setup here should avoid any other device-wide
 910  * side effects or exposing the driver via kernel internal or user space
 911  * interfaces.
 912  */
 913 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 914 {
 915         struct drm_device *dev = &dev_priv->drm;
 916         int ret;
 917
 918         if (i915_inject_load_failure())
 919                 return -ENODEV;
 920
 921         if (i915_get_bridge_dev(dev))
 922                 return -EIO;
 923
 924         ret = i915_mmio_setup(dev);
 925         if (ret < 0)
 926                 goto put_bridge;
 927
 928         intel_uncore_init(dev_priv);
 929
 930         return 0;
 931
 932 put_bridge:
 933         pci_dev_put(dev_priv->bridge_dev);
 934
 935         return ret;
 936 }
 937
 938 /**
 939  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 940  * @dev_priv: device private
 941  */
 942 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 943 {
 944         struct drm_device *dev = &dev_priv->drm;
 945
 946         intel_uncore_fini(dev_priv);
 947         i915_mmio_cleanup(dev);
 948         pci_dev_put(dev_priv->bridge_dev);
 949 }
 950
 951 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 952 {
 953         i915.enable_execlists =
 954                 intel_sanitize_enable_execlists(dev_priv,
 955                                                 i915.enable_execlists);
 956
 957         /*
 958          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 959          * user's requested state against the hardware/driver capabilities.  We
 960          * do this now so that we can print out any log messages once rather
 961          * than every time we check intel_enable_ppgtt().
 962          */
 963         i915.enable_ppgtt =
 964                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 965         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 966
 967         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 968         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 969 }
 970
 971 /**
 972  * i915_driver_init_hw - setup state requiring device access
 973  * @dev_priv: device private
 974  *
 975  * Setup state that requires accessing the device, but doesn't require
 976  * exposing the driver via kernel internal or userspace interfaces.
 977  */
 978 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 979 {
 980         struct pci_dev *pdev = dev_priv->drm.pdev;
 981         struct drm_device *dev = &dev_priv->drm;
 982         int ret;
 983
 984         if (i915_inject_load_failure())
 985                 return -ENODEV;
 986
 987         intel_device_info_runtime_init(dev_priv);
 988
 989         intel_sanitize_options(dev_priv);
 990
 991         ret = i915_ggtt_probe_hw(dev_priv);
 992         if (ret)
 993                 return ret;
 994
 995         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 996          * otherwise the vga fbdev driver falls over. */
 997         ret = i915_kick_out_firmware_fb(dev_priv);
 998         if (ret) {
 999                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1000                 goto out_ggtt;
1001         }
1002
1003         ret = i915_kick_out_vgacon(dev_priv);
1004         if (ret) {
1005                 DRM_ERROR("failed to remove conflicting VGA console\n");
1006                 goto out_ggtt;
1007         }
1008
1009         ret = i915_ggtt_init_hw(dev_priv);
1010         if (ret)
1011                 return ret;
1012
1013         ret = i915_ggtt_enable_hw(dev_priv);
1014         if (ret) {
1015                 DRM_ERROR("failed to enable GGTT\n");
1016                 goto out_ggtt;
1017         }
1018
1019         pci_set_master(pdev);
1020
1021         /* overlay on gen2 is broken and can't address above 1G */
1022         if (IS_GEN2(dev)) {
1023                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1024                 if (ret) {
1025                         DRM_ERROR("failed to set DMA mask\n");
1026
1027                         goto out_ggtt;
1028                 }
1029         }
1030
1031         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1032          * using 32bit addressing, overwriting memory if HWS is located
1033          * above 4GB.
1034          *
1035          * The documentation also mentions an issue with undefined
1036          * behaviour if any general state is accessed within a page above 4GB,
1037          * which also needs to be handled carefully.
1038          */
1039         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1040                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1041
1042                 if (ret) {
1043                         DRM_ERROR("failed to set DMA mask\n");
1044
1045                         goto out_ggtt;
1046                 }
1047         }
1048
1049         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1050                            PM_QOS_DEFAULT_VALUE);
1051
1052         intel_uncore_sanitize(dev_priv);
1053
1054         intel_opregion_setup(dev_priv);
1055
1056         i915_gem_load_init_fences(dev_priv);
1057
1058         /* On the 945G/GM, the chipset reports the MSI capability on the
1059          * integrated graphics even though the support isn't actually there
1060          * according to the published specs.  It doesn't appear to function
1061          * correctly in testing on 945G.
1062          * This may be a side effect of MSI having been made available for PEG
1063          * and the registers being closely associated.
1064          *
1065          * According to chipset errata, on the 965GM, MSI interrupts may
1066          * be lost or delayed, but we use them anyways to avoid
1067          * stuck interrupts on some machines.
1068          */
1069         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1070                 if (pci_enable_msi(pdev) < 0)
1071                         DRM_DEBUG_DRIVER("can't enable MSI");
1072         }
1073
1074         return 0;
1075
1076 out_ggtt:
1077         i915_ggtt_cleanup_hw(dev_priv);
1078
1079         return ret;
1080 }
1081
1082 /**
1083  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1084  * @dev_priv: device private
1085  */
1086 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1087 {
1088         struct pci_dev *pdev = dev_priv->drm.pdev;
1089
1090         if (pdev->msi_enabled)
1091                 pci_disable_msi(pdev);
1092
1093         pm_qos_remove_request(&dev_priv->pm_qos);
1094         i915_ggtt_cleanup_hw(dev_priv);
1095 }
1096
1097 /**
1098  * i915_driver_register - register the driver with the rest of the system
1099  * @dev_priv: device private
1100  *
1101  * Perform any steps necessary to make the driver available via kernel
1102  * internal or userspace interfaces.
1103  */
1104 static void i915_driver_register(struct drm_i915_private *dev_priv)
1105 {
1106         struct drm_device *dev = &dev_priv->drm;
1107
1108         i915_gem_shrinker_init(dev_priv);
1109
1110         /*
1111          * Notify a valid surface after modesetting,
1112          * when running inside a VM.
1113          */
1114         if (intel_vgpu_active(dev_priv))
1115                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1116
1117         /* Reveal our presence to userspace */
1118         if (drm_dev_register(dev, 0) == 0) {
1119                 i915_debugfs_register(dev_priv);
1120                 i915_setup_sysfs(dev_priv);
1121         } else
1122                 DRM_ERROR("Failed to register driver for userspace access!\n");
1123
1124         if (INTEL_INFO(dev_priv)->num_pipes) {
1125                 /* Must be done after probing outputs */
1126                 intel_opregion_register(dev_priv);
1127                 acpi_video_register();
1128         }
1129
1130         if (IS_GEN5(dev_priv))
1131                 intel_gpu_ips_init(dev_priv);
1132
1133         if (intel_lpe_audio_init(dev_priv) < 0)
1134                 i915_audio_component_init(dev_priv);
1135
1136         /*
1137          * Some ports require correctly set-up hpd registers for detection to
1138          * work properly (leading to ghost connected connector status), e.g. VGA
1139          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1140          * irqs are fully enabled. We do it last so that the async config
1141          * cannot run before the connectors are registered.
1142          */
1143         intel_fbdev_initial_config_async(dev);
1144 }
1145
1146 /**
1147  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1148  * @dev_priv: device private
1149  */
1150 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1151 {
1152         if (HAS_LPE_AUDIO(dev_priv))
1153                 intel_lpe_audio_teardown(dev_priv);
1154         else
1155                 i915_audio_component_cleanup(dev_priv);
1156
1157         intel_gpu_ips_teardown();
1158         acpi_video_unregister();
1159         intel_opregion_unregister(dev_priv);
1160
1161         i915_teardown_sysfs(dev_priv);
1162         i915_debugfs_unregister(dev_priv);
1163         drm_dev_unregister(&dev_priv->drm);
1164
1165         i915_gem_shrinker_cleanup(dev_priv);
1166 }
1167
1168 /**
1169  * i915_driver_load - setup chip and create an initial config
1170  * @dev: DRM device
1171  * @flags: startup flags
1172  *
1173  * The driver load routine has to do several things:
1174  *   - drive output discovery via intel_modeset_init()
1175  *   - initialize the memory manager
1176  *   - allocate initial config memory
1177  *   - setup the DRM framebuffer with the allocated memory
1178  */
1179 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1180 {
1181         struct drm_i915_private *dev_priv;
1182         int ret;
1183
1184         if (i915.nuclear_pageflip)
1185                 driver.driver_features |= DRIVER_ATOMIC;
1186
1187         ret = -ENOMEM;
1188         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1189         if (dev_priv)
1190                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1191         if (ret) {
1192                 dev_printk(KERN_ERR, &pdev->dev,
1193                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1194                 kfree(dev_priv);
1195                 return ret;
1196         }
1197
1198         dev_priv->drm.pdev = pdev;
1199         dev_priv->drm.dev_private = dev_priv;
1200
1201         ret = pci_enable_device(pdev);
1202         if (ret)
1203                 goto out_free_priv;
1204
1205         pci_set_drvdata(pdev, &dev_priv->drm);
1206         /*
1207          * Disable the system suspend direct complete optimization, which can
1208          * leave the device suspended skipping the driver's suspend handlers
1209          * if the device was already runtime suspended. This is needed due to
1210          * the difference in our runtime and system suspend sequence and
1211          * becaue the HDA driver may require us to enable the audio power
1212          * domain during system suspend.
1213          */
1214         pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
1215
1216         ret = i915_driver_init_early(dev_priv, ent);
1217         if (ret < 0)
1218                 goto out_pci_disable;
1219
1220         intel_runtime_pm_get(dev_priv);
1221
1222         ret = i915_driver_init_mmio(dev_priv);
1223         if (ret < 0)
1224                 goto out_runtime_pm_put;
1225
1226         ret = i915_driver_init_hw(dev_priv);
1227         if (ret < 0)
1228                 goto out_cleanup_mmio;
1229
1230         /*
1231          * TODO: move the vblank init and parts of modeset init steps into one
1232          * of the i915_driver_init_/i915_driver_register functions according
1233          * to the role/effect of the given init step.
1234          */
1235         if (INTEL_INFO(dev_priv)->num_pipes) {
1236                 ret = drm_vblank_init(&dev_priv->drm,
1237                                       INTEL_INFO(dev_priv)->num_pipes);
1238                 if (ret)
1239                         goto out_cleanup_hw;
1240         }
1241
1242         ret = i915_load_modeset_init(&dev_priv->drm);
1243         if (ret < 0)
1244                 goto out_cleanup_vblank;
1245
1246         i915_driver_register(dev_priv);
1247
1248         intel_runtime_pm_enable(dev_priv);
1249
1250         /* Everything is in place, we can now relax! */
1251         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1252                  driver.name, driver.major, driver.minor, driver.patchlevel,
1253                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1254
1255         intel_runtime_pm_put(dev_priv);
1256
1257         return 0;
1258
1259 out_cleanup_vblank:
1260         drm_vblank_cleanup(&dev_priv->drm);
1261 out_cleanup_hw:
1262         i915_driver_cleanup_hw(dev_priv);
1263 out_cleanup_mmio:
1264         i915_driver_cleanup_mmio(dev_priv);
1265 out_runtime_pm_put:
1266         intel_runtime_pm_put(dev_priv);
1267         i915_driver_cleanup_early(dev_priv);
1268 out_pci_disable:
1269         pci_disable_device(pdev);
1270 out_free_priv:
1271         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1272         drm_dev_unref(&dev_priv->drm);
1273         return ret;
1274 }
1275
1276 void i915_driver_unload(struct drm_device *dev)
1277 {
1278         struct drm_i915_private *dev_priv = to_i915(dev);
1279         struct pci_dev *pdev = dev_priv->drm.pdev;
1280
1281         intel_fbdev_fini(dev);
1282
1283         if (i915_gem_suspend(dev))
1284                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1285
1286         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1287
1288         i915_driver_unregister(dev_priv);
1289
1290         drm_vblank_cleanup(dev);
1291
1292         intel_modeset_cleanup(dev);
1293
1294         /*
1295          * free the memory space allocated for the child device
1296          * config parsed from VBT
1297          */
1298         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1299                 kfree(dev_priv->vbt.child_dev);
1300                 dev_priv->vbt.child_dev = NULL;
1301                 dev_priv->vbt.child_dev_num = 0;
1302         }
1303         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1304         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1305         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1306         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1307
1308         vga_switcheroo_unregister_client(pdev);
1309         vga_client_register(pdev, NULL, NULL, NULL);
1310
1311         intel_csr_ucode_fini(dev_priv);
1312
1313         /* Free error state after interrupts are fully disabled. */
1314         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1315         i915_destroy_error_state(dev);
1316
1317         /* Flush any outstanding unpin_work. */
1318         drain_workqueue(dev_priv->wq);
1319
1320         intel_guc_fini(dev);
1321         i915_gem_fini(dev);
1322         intel_fbc_cleanup_cfb(dev_priv);
1323
1324         intel_power_domains_fini(dev_priv);
1325
1326         i915_driver_cleanup_hw(dev_priv);
1327         i915_driver_cleanup_mmio(dev_priv);
1328
1329         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1330
1331         i915_driver_cleanup_early(dev_priv);
1332 }
1333
1334 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1335 {
1336         int ret;
1337
1338         ret = i915_gem_open(dev, file);
1339         if (ret)
1340                 return ret;
1341
1342         return 0;
1343 }
1344
1345 /**
1346  * i915_driver_lastclose - clean up after all DRM clients have exited
1347  * @dev: DRM device
1348  *
1349  * Take care of cleaning up after all DRM clients have exited.  In the
1350  * mode setting case, we want to restore the kernel's initial mode (just
1351  * in case the last client left us in a bad state).
1352  *
1353  * Additionally, in the non-mode setting case, we'll tear down the GTT
1354  * and DMA structures, since the kernel won't be using them, and clea
1355  * up any GEM state.
1356  */
1357 static void i915_driver_lastclose(struct drm_device *dev)
1358 {
1359         intel_fbdev_restore_mode(dev);
1360         vga_switcheroo_process_delayed_switch();
1361 }
1362
1363 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1364 {
1365         mutex_lock(&dev->struct_mutex);
1366         i915_gem_context_close(dev, file);
1367         i915_gem_release(dev, file);
1368         mutex_unlock(&dev->struct_mutex);
1369 }
1370
1371 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1372 {
1373         struct drm_i915_file_private *file_priv = file->driver_priv;
1374
1375         kfree(file_priv);
1376 }
1377
1378 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1379 {
1380         struct drm_device *dev = &dev_priv->drm;
1381         struct intel_encoder *encoder;
1382
1383         drm_modeset_lock_all(dev);
1384         for_each_intel_encoder(dev, encoder)
1385                 if (encoder->suspend)
1386                         encoder->suspend(encoder);
1387         drm_modeset_unlock_all(dev);
1388 }
1389
1390 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1391                               bool rpm_resume);
1392 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1393
1394 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1395 {
1396 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1397         if (acpi_target_system_state() < ACPI_STATE_S3)
1398                 return true;
1399 #endif
1400         return false;
1401 }
1402
1403 static int i915_drm_suspend(struct drm_device *dev)
1404 {
1405         struct drm_i915_private *dev_priv = to_i915(dev);
1406         struct pci_dev *pdev = dev_priv->drm.pdev;
1407         pci_power_t opregion_target_state;
1408         int error;
1409
1410         /* ignore lid events during suspend */
1411         mutex_lock(&dev_priv->modeset_restore_lock);
1412         dev_priv->modeset_restore = MODESET_SUSPENDED;
1413         mutex_unlock(&dev_priv->modeset_restore_lock);
1414
1415         disable_rpm_wakeref_asserts(dev_priv);
1416
1417         /* We do a lot of poking in a lot of registers, make sure they work
1418          * properly. */
1419         intel_display_set_init_power(dev_priv, true);
1420
1421         drm_kms_helper_poll_disable(dev);
1422
1423         pci_save_state(pdev);
1424
1425         error = i915_gem_suspend(dev);
1426         if (error) {
1427                 dev_err(&pdev->dev,
1428                         "GEM idle failed, resume might fail\n");
1429                 goto out;
1430         }
1431
1432         intel_guc_suspend(dev);
1433
1434         intel_display_suspend(dev);
1435
1436         intel_dp_mst_suspend(dev);
1437
1438         intel_runtime_pm_disable_interrupts(dev_priv);
1439         intel_hpd_cancel_work(dev_priv);
1440
1441         intel_suspend_encoders(dev_priv);
1442
1443         intel_suspend_hw(dev);
1444
1445         i915_gem_suspend_gtt_mappings(dev);
1446
1447         i915_save_state(dev);
1448
1449         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1450         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1451
1452         intel_uncore_suspend(dev_priv);
1453         intel_opregion_unregister(dev_priv);
1454
1455         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1456
1457         dev_priv->suspend_count++;
1458
1459         intel_csr_ucode_suspend(dev_priv);
1460
1461 out:
1462         enable_rpm_wakeref_asserts(dev_priv);
1463
1464         return error;
1465 }
1466
1467 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1468 {
1469         struct drm_i915_private *dev_priv = to_i915(dev);
1470         struct pci_dev *pdev = dev_priv->drm.pdev;
1471         bool fw_csr;
1472         int ret;
1473
1474         disable_rpm_wakeref_asserts(dev_priv);
1475
1476         intel_display_set_init_power(dev_priv, false);
1477
1478         fw_csr = !IS_BROXTON(dev_priv) &&
1479                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1480         /*
1481          * In case of firmware assisted context save/restore don't manually
1482          * deinit the power domains. This also means the CSR/DMC firmware will
1483          * stay active, it will power down any HW resources as required and
1484          * also enable deeper system power states that would be blocked if the
1485          * firmware was inactive.
1486          */
1487         if (!fw_csr)
1488                 intel_power_domains_suspend(dev_priv);
1489
1490         ret = 0;
1491         if (IS_BROXTON(dev_priv))
1492                 bxt_enable_dc9(dev_priv);
1493         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1494                 hsw_enable_pc8(dev_priv);
1495         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1496                 ret = vlv_suspend_complete(dev_priv);
1497
1498         if (ret) {
1499                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1500                 if (!fw_csr)
1501                         intel_power_domains_init_hw(dev_priv, true);
1502
1503                 goto out;
1504         }
1505
1506         pci_disable_device(pdev);
1507         /*
1508          * During hibernation on some platforms the BIOS may try to access
1509          * the device even though it's already in D3 and hang the machine. So
1510          * leave the device in D0 on those platforms and hope the BIOS will
1511          * power down the device properly. The issue was seen on multiple old
1512          * GENs with different BIOS vendors, so having an explicit blacklist
1513          * is inpractical; apply the workaround on everything pre GEN6. The
1514          * platforms where the issue was seen:
1515          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1516          * Fujitsu FSC S7110
1517          * Acer Aspire 1830T
1518          */
1519         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1520                 pci_set_power_state(pdev, PCI_D3hot);
1521
1522         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1523
1524 out:
1525         enable_rpm_wakeref_asserts(dev_priv);
1526
1527         return ret;
1528 }
1529
1530 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1531 {
1532         int error;
1533
1534         if (!dev) {
1535                 DRM_ERROR("dev: %p\n", dev);
1536                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1537                 return -ENODEV;
1538         }
1539
1540         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1541                          state.event != PM_EVENT_FREEZE))
1542                 return -EINVAL;
1543
1544         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1545                 return 0;
1546
1547         error = i915_drm_suspend(dev);
1548         if (error)
1549                 return error;
1550
1551         return i915_drm_suspend_late(dev, false);
1552 }
1553
1554 static int i915_drm_resume(struct drm_device *dev)
1555 {
1556         struct drm_i915_private *dev_priv = to_i915(dev);
1557         int ret;
1558
1559         disable_rpm_wakeref_asserts(dev_priv);
1560         intel_sanitize_gt_powersave(dev_priv);
1561
1562         ret = i915_ggtt_enable_hw(dev_priv);
1563         if (ret)
1564                 DRM_ERROR("failed to re-enable GGTT\n");
1565
1566         intel_csr_ucode_resume(dev_priv);
1567
1568         i915_gem_resume(dev);
1569
1570         i915_restore_state(dev);
1571         intel_pps_unlock_regs_wa(dev_priv);
1572         intel_opregion_setup(dev_priv);
1573
1574         intel_init_pch_refclk(dev);
1575         drm_mode_config_reset(dev);
1576
1577         /*
1578          * Interrupts have to be enabled before any batches are run. If not the
1579          * GPU will hang. i915_gem_init_hw() will initiate batches to
1580          * update/restore the context.
1581          *
1582          * Modeset enabling in intel_modeset_init_hw() also needs working
1583          * interrupts.
1584          */
1585         intel_runtime_pm_enable_interrupts(dev_priv);
1586
1587         mutex_lock(&dev->struct_mutex);
1588         if (i915_gem_init_hw(dev)) {
1589                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1590                 i915_gem_set_wedged(dev_priv);
1591         }
1592         mutex_unlock(&dev->struct_mutex);
1593
1594         intel_guc_resume(dev);
1595
1596         intel_modeset_init_hw(dev);
1597
1598         spin_lock_irq(&dev_priv->irq_lock);
1599         if (dev_priv->display.hpd_irq_setup)
1600                 dev_priv->display.hpd_irq_setup(dev_priv);
1601         spin_unlock_irq(&dev_priv->irq_lock);
1602
1603         intel_dp_mst_resume(dev);
1604
1605         intel_display_resume(dev);
1606
1607         /*
1608          * ... but also need to make sure that hotplug processing
1609          * doesn't cause havoc. Like in the driver load code we don't
1610          * bother with the tiny race here where we might loose hotplug
1611          * notifications.
1612          * */
1613         intel_hpd_init(dev_priv);
1614         /* Config may have changed between suspend and resume */
1615         drm_helper_hpd_irq_event(dev);
1616
1617         intel_opregion_register(dev_priv);
1618
1619         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1620
1621         mutex_lock(&dev_priv->modeset_restore_lock);
1622         dev_priv->modeset_restore = MODESET_DONE;
1623         mutex_unlock(&dev_priv->modeset_restore_lock);
1624
1625         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1626
1627         intel_autoenable_gt_powersave(dev_priv);
1628         drm_kms_helper_poll_enable(dev);
1629
1630         enable_rpm_wakeref_asserts(dev_priv);
1631
1632         return 0;
1633 }
1634
1635 static int i915_drm_resume_early(struct drm_device *dev)
1636 {
1637         struct drm_i915_private *dev_priv = to_i915(dev);
1638         struct pci_dev *pdev = dev_priv->drm.pdev;
1639         int ret;
1640
1641         /*
1642          * We have a resume ordering issue with the snd-hda driver also
1643          * requiring our device to be power up. Due to the lack of a
1644          * parent/child relationship we currently solve this with an early
1645          * resume hook.
1646          *
1647          * FIXME: This should be solved with a special hdmi sink device or
1648          * similar so that power domains can be employed.
1649          */
1650
1651         /*
1652          * Note that we need to set the power state explicitly, since we
1653          * powered off the device during freeze and the PCI core won't power
1654          * it back up for us during thaw. Powering off the device during
1655          * freeze is not a hard requirement though, and during the
1656          * suspend/resume phases the PCI core makes sure we get here with the
1657          * device powered on. So in case we change our freeze logic and keep
1658          * the device powered we can also remove the following set power state
1659          * call.
1660          */
1661         ret = pci_set_power_state(pdev, PCI_D0);
1662         if (ret) {
1663                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1664                 goto out;
1665         }
1666
1667         /*
1668          * Note that pci_enable_device() first enables any parent bridge
1669          * device and only then sets the power state for this device. The
1670          * bridge enabling is a nop though, since bridge devices are resumed
1671          * first. The order of enabling power and enabling the device is
1672          * imposed by the PCI core as described above, so here we preserve the
1673          * same order for the freeze/thaw phases.
1674          *
1675          * TODO: eventually we should remove pci_disable_device() /
1676          * pci_enable_enable_device() from suspend/resume. Due to how they
1677          * depend on the device enable refcount we can't anyway depend on them
1678          * disabling/enabling the device.
1679          */
1680         if (pci_enable_device(pdev)) {
1681                 ret = -EIO;
1682                 goto out;
1683         }
1684
1685         pci_set_master(pdev);
1686
1687         disable_rpm_wakeref_asserts(dev_priv);
1688
1689         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1690                 ret = vlv_resume_prepare(dev_priv, false);
1691         if (ret)
1692                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1693                           ret);
1694
1695         intel_uncore_resume_early(dev_priv);
1696
1697         if (IS_BROXTON(dev_priv)) {
1698                 if (!dev_priv->suspended_to_idle)
1699                         gen9_sanitize_dc_state(dev_priv);
1700                 bxt_disable_dc9(dev_priv);
1701         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1702                 hsw_disable_pc8(dev_priv);
1703         }
1704
1705         intel_uncore_sanitize(dev_priv);
1706
1707         if (IS_BROXTON(dev_priv) ||
1708             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1709                 intel_power_domains_init_hw(dev_priv, true);
1710
1711         enable_rpm_wakeref_asserts(dev_priv);
1712
1713 out:
1714         dev_priv->suspended_to_idle = false;
1715
1716         return ret;
1717 }
1718
1719 int i915_resume_switcheroo(struct drm_device *dev)
1720 {
1721         int ret;
1722
1723         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1724                 return 0;
1725
1726         ret = i915_drm_resume_early(dev);
1727         if (ret)
1728                 return ret;
1729
1730         return i915_drm_resume(dev);
1731 }
1732
1733 /**
1734  * i915_reset - reset chip after a hang
1735  * @dev: drm device to reset
1736  *
1737  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1738  * on failure.
1739  *
1740  * Caller must hold the struct_mutex.
1741  *
1742  * Procedure is fairly simple:
1743  *   - reset the chip using the reset reg
1744  *   - re-init context state
1745  *   - re-init hardware status page
1746  *   - re-init ring buffer
1747  *   - re-init interrupt state
1748  *   - re-init display
1749  */
1750 void i915_reset(struct drm_i915_private *dev_priv)
1751 {
1752         struct drm_device *dev = &dev_priv->drm;
1753         struct i915_gpu_error *error = &dev_priv->gpu_error;
1754         int ret;
1755
1756         lockdep_assert_held(&dev->struct_mutex);
1757
1758         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1759                 return;
1760
1761         /* Clear any previous failed attempts at recovery. Time to try again. */
1762         __clear_bit(I915_WEDGED, &error->flags);
1763         error->reset_count++;
1764
1765         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1766         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1767         if (ret) {
1768                 if (ret != -ENODEV)
1769                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1770                 else
1771                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1772                 goto error;
1773         }
1774
1775         i915_gem_reset(dev_priv);
1776         intel_overlay_reset(dev_priv);
1777
1778         /* Ok, now get things going again... */
1779
1780         /*
1781          * Everything depends on having the GTT running, so we need to start
1782          * there.  Fortunately we don't need to do this unless we reset the
1783          * chip at a PCI level.
1784          *
1785          * Next we need to restore the context, but we don't use those
1786          * yet either...
1787          *
1788          * Ring buffer needs to be re-initialized in the KMS case, or if X
1789          * was running at the time of the reset (i.e. we weren't VT
1790          * switched away).
1791          */
1792         ret = i915_gem_init_hw(dev);
1793         if (ret) {
1794                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1795                 goto error;
1796         }
1797
1798 wakeup:
1799         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1800         return;
1801
1802 error:
1803         i915_gem_set_wedged(dev_priv);
1804         goto wakeup;
1805 }
1806
1807 static int i915_pm_suspend(struct device *kdev)
1808 {
1809         struct pci_dev *pdev = to_pci_dev(kdev);
1810         struct drm_device *dev = pci_get_drvdata(pdev);
1811
1812         if (!dev) {
1813                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1814                 return -ENODEV;
1815         }
1816
1817         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1818                 return 0;
1819
1820         return i915_drm_suspend(dev);
1821 }
1822
1823 static int i915_pm_suspend_late(struct device *kdev)
1824 {
1825         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1826
1827         /*
1828          * We have a suspend ordering issue with the snd-hda driver also
1829          * requiring our device to be power up. Due to the lack of a
1830          * parent/child relationship we currently solve this with an late
1831          * suspend hook.
1832          *
1833          * FIXME: This should be solved with a special hdmi sink device or
1834          * similar so that power domains can be employed.
1835          */
1836         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1837                 return 0;
1838
1839         return i915_drm_suspend_late(dev, false);
1840 }
1841
1842 static int i915_pm_poweroff_late(struct device *kdev)
1843 {
1844         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1845
1846         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1847                 return 0;
1848
1849         return i915_drm_suspend_late(dev, true);
1850 }
1851
1852 static int i915_pm_resume_early(struct device *kdev)
1853 {
1854         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1855
1856         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1857                 return 0;
1858
1859         return i915_drm_resume_early(dev);
1860 }
1861
1862 static int i915_pm_resume(struct device *kdev)
1863 {
1864         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1865
1866         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1867                 return 0;
1868
1869         return i915_drm_resume(dev);
1870 }
1871
1872 /* freeze: before creating the hibernation_image */
1873 static int i915_pm_freeze(struct device *kdev)
1874 {
1875         int ret;
1876
1877         ret = i915_pm_suspend(kdev);
1878         if (ret)
1879                 return ret;
1880
1881         ret = i915_gem_freeze(kdev_to_i915(kdev));
1882         if (ret)
1883                 return ret;
1884
1885         return 0;
1886 }
1887
1888 static int i915_pm_freeze_late(struct device *kdev)
1889 {
1890         int ret;
1891
1892         ret = i915_pm_suspend_late(kdev);
1893         if (ret)
1894                 return ret;
1895
1896         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1897         if (ret)
1898                 return ret;
1899
1900         return 0;
1901 }
1902
1903 /* thaw: called after creating the hibernation image, but before turning off. */
1904 static int i915_pm_thaw_early(struct device *kdev)
1905 {
1906         return i915_pm_resume_early(kdev);
1907 }
1908
1909 static int i915_pm_thaw(struct device *kdev)
1910 {
1911         return i915_pm_resume(kdev);
1912 }
1913
1914 /* restore: called after loading the hibernation image. */
1915 static int i915_pm_restore_early(struct device *kdev)
1916 {
1917         return i915_pm_resume_early(kdev);
1918 }
1919
1920 static int i915_pm_restore(struct device *kdev)
1921 {
1922         return i915_pm_resume(kdev);
1923 }
1924
1925 /*
1926  * Save all Gunit registers that may be lost after a D3 and a subsequent
1927  * S0i[R123] transition. The list of registers needing a save/restore is
1928  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1929  * registers in the following way:
1930  * - Driver: saved/restored by the driver
1931  * - Punit : saved/restored by the Punit firmware
1932  * - No, w/o marking: no need to save/restore, since the register is R/O or
1933  *                    used internally by the HW in a way that doesn't depend
1934  *                    keeping the content across a suspend/resume.
1935  * - Debug : used for debugging
1936  *
1937  * We save/restore all registers marked with 'Driver', with the following
1938  * exceptions:
1939  * - Registers out of use, including also registers marked with 'Debug'.
1940  *   These have no effect on the driver's operation, so we don't save/restore
1941  *   them to reduce the overhead.
1942  * - Registers that are fully setup by an initialization function called from
1943  *   the resume path. For example many clock gating and RPS/RC6 registers.
1944  * - Registers that provide the right functionality with their reset defaults.
1945  *
1946  * TODO: Except for registers that based on the above 3 criteria can be safely
1947  * ignored, we save/restore all others, practically treating the HW context as
1948  * a black-box for the driver. Further investigation is needed to reduce the
1949  * saved/restored registers even further, by following the same 3 criteria.
1950  */
1951 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1952 {
1953         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1954         int i;
1955
1956         /* GAM 0x4000-0x4770 */
1957         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1958         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1959         s->arb_mode             = I915_READ(ARB_MODE);
1960         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1961         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1962
1963         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1964                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1965
1966         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1967         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1968
1969         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1970         s->ecochk               = I915_READ(GAM_ECOCHK);
1971         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1972         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1973
1974         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1975
1976         /* MBC 0x9024-0x91D0, 0x8500 */
1977         s->g3dctl               = I915_READ(VLV_G3DCTL);
1978         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1979         s->mbctl                = I915_READ(GEN6_MBCTL);
1980
1981         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1982         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1983         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1984         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1985         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1986         s->rstctl               = I915_READ(GEN6_RSTCTL);
1987         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1988
1989         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1990         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1991         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1992         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1993         s->ecobus               = I915_READ(ECOBUS);
1994         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1995         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1996         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1997         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1998         s->rcedata              = I915_READ(VLV_RCEDATA);
1999         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2000
2001         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2002         s->gt_imr               = I915_READ(GTIMR);
2003         s->gt_ier               = I915_READ(GTIER);
2004         s->pm_imr               = I915_READ(GEN6_PMIMR);
2005         s->pm_ier               = I915_READ(GEN6_PMIER);
2006
2007         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2008                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2009
2010         /* GT SA CZ domain, 0x100000-0x138124 */
2011         s->tilectl              = I915_READ(TILECTL);
2012         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2013         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2014         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2015         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2016
2017         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2018         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2019         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2020         s->pcbr                 = I915_READ(VLV_PCBR);
2021         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2022
2023         /*
2024          * Not saving any of:
2025          * DFT,         0x9800-0x9EC0
2026          * SARB,        0xB000-0xB1FC
2027          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2028          * PCI CFG
2029          */
2030 }
2031
2032 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2033 {
2034         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2035         u32 val;
2036         int i;
2037
2038         /* GAM 0x4000-0x4770 */
2039         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2040         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2041         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2042         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2043         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2044
2045         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2046                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2047
2048         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2049         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2050
2051         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2052         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2053         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2054         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2055
2056         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2057
2058         /* MBC 0x9024-0x91D0, 0x8500 */
2059         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2060         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2061         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2062
2063         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2064         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2065         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2066         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2067         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2068         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2069         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2070
2071         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2072         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2073         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2074         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2075         I915_WRITE(ECOBUS,              s->ecobus);
2076         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2077         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2078         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2079         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2080         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2081         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2082
2083         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2084         I915_WRITE(GTIMR,               s->gt_imr);
2085         I915_WRITE(GTIER,               s->gt_ier);
2086         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2087         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2088
2089         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2090                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2091
2092         /* GT SA CZ domain, 0x100000-0x138124 */
2093         I915_WRITE(TILECTL,                     s->tilectl);
2094         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2095         /*
2096          * Preserve the GT allow wake and GFX force clock bit, they are not
2097          * be restored, as they are used to control the s0ix suspend/resume
2098          * sequence by the caller.
2099          */
2100         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2101         val &= VLV_GTLC_ALLOWWAKEREQ;
2102         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2103         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2104
2105         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2106         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2107         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2108         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2109
2110         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2111
2112         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2113         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2114         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2115         I915_WRITE(VLV_PCBR,                    s->pcbr);
2116         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2117 }
2118
2119 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2120 {
2121         u32 val;
2122         int err;
2123
2124         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2125         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2126         if (force_on)
2127                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2128         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2129
2130         if (!force_on)
2131                 return 0;
2132
2133         err = intel_wait_for_register(dev_priv,
2134                                       VLV_GTLC_SURVIVABILITY_REG,
2135                                       VLV_GFX_CLK_STATUS_BIT,
2136                                       VLV_GFX_CLK_STATUS_BIT,
2137                                       20);
2138         if (err)
2139                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2140                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2141
2142         return err;
2143 }
2144
2145 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2146 {
2147         u32 val;
2148         int err = 0;
2149
2150         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2151         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2152         if (allow)
2153                 val |= VLV_GTLC_ALLOWWAKEREQ;
2154         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2155         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2156
2157         err = intel_wait_for_register(dev_priv,
2158                                       VLV_GTLC_PW_STATUS,
2159                                       VLV_GTLC_ALLOWWAKEACK,
2160                                       allow,
2161                                       1);
2162         if (err)
2163                 DRM_ERROR("timeout disabling GT waking\n");
2164
2165         return err;
2166 }
2167
2168 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2169                                  bool wait_for_on)
2170 {
2171         u32 mask;
2172         u32 val;
2173         int err;
2174
2175         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2176         val = wait_for_on ? mask : 0;
2177         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2178                 return 0;
2179
2180         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2181                       onoff(wait_for_on),
2182                       I915_READ(VLV_GTLC_PW_STATUS));
2183
2184         /*
2185          * RC6 transitioning can be delayed up to 2 msec (see
2186          * valleyview_enable_rps), use 3 msec for safety.
2187          */
2188         err = intel_wait_for_register(dev_priv,
2189                                       VLV_GTLC_PW_STATUS, mask, val,
2190                                       3);
2191         if (err)
2192                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2193                           onoff(wait_for_on));
2194
2195         return err;
2196 }
2197
2198 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2199 {
2200         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2201                 return;
2202
2203         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2204         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2205 }
2206
2207 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2208 {
2209         u32 mask;
2210         int err;
2211
2212         /*
2213          * Bspec defines the following GT well on flags as debug only, so
2214          * don't treat them as hard failures.
2215          */
2216         (void)vlv_wait_for_gt_wells(dev_priv, false);
2217
2218         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2219         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2220
2221         vlv_check_no_gt_access(dev_priv);
2222
2223         err = vlv_force_gfx_clock(dev_priv, true);
2224         if (err)
2225                 goto err1;
2226
2227         err = vlv_allow_gt_wake(dev_priv, false);
2228         if (err)
2229                 goto err2;
2230
2231         if (!IS_CHERRYVIEW(dev_priv))
2232                 vlv_save_gunit_s0ix_state(dev_priv);
2233
2234         err = vlv_force_gfx_clock(dev_priv, false);
2235         if (err)
2236                 goto err2;
2237
2238         return 0;
2239
2240 err2:
2241         /* For safety always re-enable waking and disable gfx clock forcing */
2242         vlv_allow_gt_wake(dev_priv, true);
2243 err1:
2244         vlv_force_gfx_clock(dev_priv, false);
2245
2246         return err;
2247 }
2248
2249 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2250                                 bool rpm_resume)
2251 {
2252         struct drm_device *dev = &dev_priv->drm;
2253         int err;
2254         int ret;
2255
2256         /*
2257          * If any of the steps fail just try to continue, that's the best we
2258          * can do at this point. Return the first error code (which will also
2259          * leave RPM permanently disabled).
2260          */
2261         ret = vlv_force_gfx_clock(dev_priv, true);
2262
2263         if (!IS_CHERRYVIEW(dev_priv))
2264                 vlv_restore_gunit_s0ix_state(dev_priv);
2265
2266         err = vlv_allow_gt_wake(dev_priv, true);
2267         if (!ret)
2268                 ret = err;
2269
2270         err = vlv_force_gfx_clock(dev_priv, false);
2271         if (!ret)
2272                 ret = err;
2273
2274         vlv_check_no_gt_access(dev_priv);
2275
2276         if (rpm_resume) {
2277                 intel_init_clock_gating(dev);
2278                 i915_gem_restore_fences(dev);
2279         }
2280
2281         return ret;
2282 }
2283
2284 static int intel_runtime_suspend(struct device *kdev)
2285 {
2286         struct pci_dev *pdev = to_pci_dev(kdev);
2287         struct drm_device *dev = pci_get_drvdata(pdev);
2288         struct drm_i915_private *dev_priv = to_i915(dev);
2289         int ret;
2290
2291         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2292                 return -ENODEV;
2293
2294         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2295                 return -ENODEV;
2296
2297         DRM_DEBUG_KMS("Suspending device\n");
2298
2299         /*
2300          * We could deadlock here in case another thread holding struct_mutex
2301          * calls RPM suspend concurrently, since the RPM suspend will wait
2302          * first for this RPM suspend to finish. In this case the concurrent
2303          * RPM resume will be followed by its RPM suspend counterpart. Still
2304          * for consistency return -EAGAIN, which will reschedule this suspend.
2305          */
2306         if (!mutex_trylock(&dev->struct_mutex)) {
2307                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2308                 /*
2309                  * Bump the expiration timestamp, otherwise the suspend won't
2310                  * be rescheduled.
2311                  */
2312                 pm_runtime_mark_last_busy(kdev);
2313
2314                 return -EAGAIN;
2315         }
2316
2317         disable_rpm_wakeref_asserts(dev_priv);
2318
2319         /*
2320          * We are safe here against re-faults, since the fault handler takes
2321          * an RPM reference.
2322          */
2323         i915_gem_release_all_mmaps(dev_priv);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_guc_suspend(dev);
2327
2328         intel_runtime_pm_disable_interrupts(dev_priv);
2329
2330         ret = 0;
2331         if (IS_BROXTON(dev_priv)) {
2332                 bxt_display_core_uninit(dev_priv);
2333                 bxt_enable_dc9(dev_priv);
2334         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2335                 hsw_enable_pc8(dev_priv);
2336         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2337                 ret = vlv_suspend_complete(dev_priv);
2338         }
2339
2340         if (ret) {
2341                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2342                 intel_runtime_pm_enable_interrupts(dev_priv);
2343
2344                 enable_rpm_wakeref_asserts(dev_priv);
2345
2346                 return ret;
2347         }
2348
2349         intel_uncore_suspend(dev_priv);
2350
2351         enable_rpm_wakeref_asserts(dev_priv);
2352         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2353
2354         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2355                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2356
2357         dev_priv->pm.suspended = true;
2358
2359         /*
2360          * FIXME: We really should find a document that references the arguments
2361          * used below!
2362          */
2363         if (IS_BROADWELL(dev_priv)) {
2364                 /*
2365                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2366                  * being detected, and the call we do at intel_runtime_resume()
2367                  * won't be able to restore them. Since PCI_D3hot matches the
2368                  * actual specification and appears to be working, use it.
2369                  */
2370                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2371         } else {
2372                 /*
2373                  * current versions of firmware which depend on this opregion
2374                  * notification have repurposed the D1 definition to mean
2375                  * "runtime suspended" vs. what you would normally expect (D3)
2376                  * to distinguish it from notifications that might be sent via
2377                  * the suspend path.
2378                  */
2379                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2380         }
2381
2382         assert_forcewakes_inactive(dev_priv);
2383
2384         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2385                 intel_hpd_poll_init(dev_priv);
2386
2387         DRM_DEBUG_KMS("Device suspended\n");
2388         return 0;
2389 }
2390
2391 static int intel_runtime_resume(struct device *kdev)
2392 {
2393         struct pci_dev *pdev = to_pci_dev(kdev);
2394         struct drm_device *dev = pci_get_drvdata(pdev);
2395         struct drm_i915_private *dev_priv = to_i915(dev);
2396         int ret = 0;
2397
2398         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2399                 return -ENODEV;
2400
2401         DRM_DEBUG_KMS("Resuming device\n");
2402
2403         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2404         disable_rpm_wakeref_asserts(dev_priv);
2405
2406         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2407         dev_priv->pm.suspended = false;
2408         if (intel_uncore_unclaimed_mmio(dev_priv))
2409                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2410
2411         intel_guc_resume(dev);
2412
2413         if (IS_GEN6(dev_priv))
2414                 intel_init_pch_refclk(dev);
2415
2416         if (IS_BROXTON(dev)) {
2417                 bxt_disable_dc9(dev_priv);
2418                 bxt_display_core_init(dev_priv, true);
2419                 if (dev_priv->csr.dmc_payload &&
2420                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2421                         gen9_enable_dc5(dev_priv);
2422         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2423                 hsw_disable_pc8(dev_priv);
2424         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2425                 ret = vlv_resume_prepare(dev_priv, true);
2426         }
2427
2428         /*
2429          * No point of rolling back things in case of an error, as the best
2430          * we can do is to hope that things will still work (and disable RPM).
2431          */
2432         i915_gem_init_swizzling(dev);
2433
2434         intel_runtime_pm_enable_interrupts(dev_priv);
2435
2436         /*
2437          * On VLV/CHV display interrupts are part of the display
2438          * power well, so hpd is reinitialized from there. For
2439          * everyone else do it here.
2440          */
2441         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2442                 intel_hpd_init(dev_priv);
2443
2444         enable_rpm_wakeref_asserts(dev_priv);
2445
2446         if (ret)
2447                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2448         else
2449                 DRM_DEBUG_KMS("Device resumed\n");
2450
2451         return ret;
2452 }
2453
2454 const struct dev_pm_ops i915_pm_ops = {
2455         /*
2456          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2457          * PMSG_RESUME]
2458          */
2459         .suspend = i915_pm_suspend,
2460         .suspend_late = i915_pm_suspend_late,
2461         .resume_early = i915_pm_resume_early,
2462         .resume = i915_pm_resume,
2463
2464         /*
2465          * S4 event handlers
2466          * @freeze, @freeze_late    : called (1) before creating the
2467          *                            hibernation image [PMSG_FREEZE] and
2468          *                            (2) after rebooting, before restoring
2469          *                            the image [PMSG_QUIESCE]
2470          * @thaw, @thaw_early       : called (1) after creating the hibernation
2471          *                            image, before writing it [PMSG_THAW]
2472          *                            and (2) after failing to create or
2473          *                            restore the image [PMSG_RECOVER]
2474          * @poweroff, @poweroff_late: called after writing the hibernation
2475          *                            image, before rebooting [PMSG_HIBERNATE]
2476          * @restore, @restore_early : called after rebooting and restoring the
2477          *                            hibernation image [PMSG_RESTORE]
2478          */
2479         .freeze = i915_pm_freeze,
2480         .freeze_late = i915_pm_freeze_late,
2481         .thaw_early = i915_pm_thaw_early,
2482         .thaw = i915_pm_thaw,
2483         .poweroff = i915_pm_suspend,
2484         .poweroff_late = i915_pm_poweroff_late,
2485         .restore_early = i915_pm_restore_early,
2486         .restore = i915_pm_restore,
2487
2488         /* S0ix (via runtime suspend) event handlers */
2489         .runtime_suspend = intel_runtime_suspend,
2490         .runtime_resume = intel_runtime_resume,
2491 };
2492
2493 static const struct vm_operations_struct i915_gem_vm_ops = {
2494         .fault = i915_gem_fault,
2495         .open = drm_gem_vm_open,
2496         .close = drm_gem_vm_close,
2497 };
2498
2499 static const struct file_operations i915_driver_fops = {
2500         .owner = THIS_MODULE,
2501         .open = drm_open,
2502         .release = drm_release,
2503         .unlocked_ioctl = drm_ioctl,
2504         .mmap = drm_gem_mmap,
2505         .poll = drm_poll,
2506         .read = drm_read,
2507 #ifdef CONFIG_COMPAT
2508         .compat_ioctl = i915_compat_ioctl,
2509 #endif
2510         .llseek = noop_llseek,
2511 };
2512
2513 static int
2514 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2515                           struct drm_file *file)
2516 {
2517         return -ENODEV;
2518 }
2519
2520 static const struct drm_ioctl_desc i915_ioctls[] = {
2521         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2522         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2523         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2524         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2525         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2526         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2527         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2528         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2529         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2530         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2531         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2532         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2533         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2534         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2535         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2536         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2537         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2538         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2539         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2540         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2541         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2542         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2554         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2556         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2557         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2560         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2565         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2567         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2568         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2569         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2570         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2571         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2572         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2573 };
2574
2575 static struct drm_driver driver = {
2576         /* Don't use MTRRs here; the Xserver or userspace app should
2577          * deal with them for Intel hardware.
2578          */
2579         .driver_features =
2580             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2581             DRIVER_RENDER | DRIVER_MODESET,
2582         .open = i915_driver_open,
2583         .lastclose = i915_driver_lastclose,
2584         .preclose = i915_driver_preclose,
2585         .postclose = i915_driver_postclose,
2586         .set_busid = drm_pci_set_busid,
2587
2588         .gem_close_object = i915_gem_close_object,
2589         .gem_free_object = i915_gem_free_object,
2590         .gem_vm_ops = &i915_gem_vm_ops,
2591
2592         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2593         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2594         .gem_prime_export = i915_gem_prime_export,
2595         .gem_prime_import = i915_gem_prime_import,
2596
2597         .dumb_create = i915_gem_dumb_create,
2598         .dumb_map_offset = i915_gem_mmap_gtt,
2599         .dumb_destroy = drm_gem_dumb_destroy,
2600         .ioctls = i915_ioctls,
2601         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2602         .fops = &i915_driver_fops,
2603         .name = DRIVER_NAME,
2604         .desc = DRIVER_DESC,
2605         .date = DRIVER_DATE,
2606         .major = DRIVER_MAJOR,
2607         .minor = DRIVER_MINOR,
2608         .patchlevel = DRIVER_PATCHLEVEL,
2609 };