drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34 #include <uapi/drm/drm_fourcc.h>
  35
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/backlight.h>
  40 #include <linux/hash.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43 #include <linux/mm_types.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/pm_qos.h>
  46 #include <linux/dma-resv.h>
  47 #include <linux/shmem_fs.h>
  48 #include <linux/stackdepot.h>
  49 #include <linux/xarray.h>
  50
  51 #include <drm/intel-gtt.h>
  52 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  53 #include <drm/drm_gem.h>
  54 #include <drm/drm_auth.h>
  55 #include <drm/drm_cache.h>
  56 #include <drm/drm_util.h>
  57 #include <drm/drm_dsc.h>
  58 #include <drm/drm_atomic.h>
  59 #include <drm/drm_connector.h>
  60 #include <drm/i915_mei_hdcp_interface.h>
  61
  62 #include "i915_fixed.h"
  63 #include "i915_params.h"
  64 #include "i915_reg.h"
  65 #include "i915_utils.h"
  66
  67 #include "display/intel_bios.h"
  68 #include "display/intel_display.h"
  69 #include "display/intel_display_power.h"
  70 #include "display/intel_dpll_mgr.h"
  71 #include "display/intel_dsb.h"
  72 #include "display/intel_frontbuffer.h"
  73 #include "display/intel_gmbus.h"
  74 #include "display/intel_opregion.h"
  75
  76 #include "gem/i915_gem_context_types.h"
  77 #include "gem/i915_gem_shrinker.h"
  78 #include "gem/i915_gem_stolen.h"
  79
  80 #include "gt/intel_lrc.h"
  81 #include "gt/intel_engine.h"
  82 #include "gt/intel_gt_types.h"
  83 #include "gt/intel_workarounds.h"
  84 #include "gt/uc/intel_uc.h"
  85
  86 #include "intel_device_info.h"
  87 #include "intel_pch.h"
  88 #include "intel_runtime_pm.h"
  89 #include "intel_memory_region.h"
  90 #include "intel_uncore.h"
  91 #include "intel_wakeref.h"
  92 #include "intel_wopcm.h"
  93
  94 #include "i915_gem.h"
  95 #include "i915_gem_fence_reg.h"
  96 #include "i915_gem_gtt.h"
  97 #include "i915_gpu_error.h"
  98 #include "i915_perf_types.h"
  99 #include "i915_request.h"
 100 #include "i915_scheduler.h"
 101 #include "gt/intel_timeline.h"
 102 #include "i915_vma.h"
 103 #include "i915_irq.h"
 104
 105 #include "intel_region_lmem.h"
 106
 107 #include "intel_gvt.h"
 108
 109 /* General customization:
 110  */
 111
 112 #define DRIVER_NAME             "i915"
 113 #define DRIVER_DESC             "Intel Graphics"
 114 #define DRIVER_DATE             "20200114"
 115 #define DRIVER_TIMESTAMP        1579001978
 116
 117 struct drm_i915_gem_object;
 118
 119 enum hpd_pin {
 120         HPD_NONE = 0,
 121         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 122         HPD_CRT,
 123         HPD_SDVO_B,
 124         HPD_SDVO_C,
 125         HPD_PORT_A,
 126         HPD_PORT_B,
 127         HPD_PORT_C,
 128         HPD_PORT_D,
 129         HPD_PORT_E,
 130         HPD_PORT_F,
 131         HPD_PORT_G,
 132         HPD_PORT_H,
 133         HPD_PORT_I,
 134
 135         HPD_NUM_PINS
 136 };
 137
 138 #define for_each_hpd_pin(__pin) \
 139         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 140
 141 /* Threshold == 5 for long IRQs, 50 for short */
 142 #define HPD_STORM_DEFAULT_THRESHOLD 50
 143
 144 struct i915_hotplug {
 145         struct delayed_work hotplug_work;
 146
 147         struct {
 148                 unsigned long last_jiffies;
 149                 int count;
 150                 enum {
 151                         HPD_ENABLED = 0,
 152                         HPD_DISABLED = 1,
 153                         HPD_MARK_DISABLED = 2
 154                 } state;
 155         } stats[HPD_NUM_PINS];
 156         u32 event_bits;
 157         u32 retry_bits;
 158         struct delayed_work reenable_work;
 159
 160         u32 long_port_mask;
 161         u32 short_port_mask;
 162         struct work_struct dig_port_work;
 163
 164         struct work_struct poll_init_work;
 165         bool poll_enabled;
 166
 167         unsigned int hpd_storm_threshold;
 168         /* Whether or not to count short HPD IRQs in HPD storms */
 169         u8 hpd_short_storm_enabled;
 170
 171         /*
 172          * if we get a HPD irq from DP and a HPD irq from non-DP
 173          * the non-DP HPD could block the workqueue on a mode config
 174          * mutex getting, that userspace may have taken. However
 175          * userspace is waiting on the DP workqueue to run which is
 176          * blocked behind the non-DP one.
 177          */
 178         struct workqueue_struct *dp_wq;
 179 };
 180
 181 #define I915_GEM_GPU_DOMAINS \
 182         (I915_GEM_DOMAIN_RENDER | \
 183          I915_GEM_DOMAIN_SAMPLER | \
 184          I915_GEM_DOMAIN_COMMAND | \
 185          I915_GEM_DOMAIN_INSTRUCTION | \
 186          I915_GEM_DOMAIN_VERTEX)
 187
 188 struct drm_i915_private;
 189 struct i915_mm_struct;
 190 struct i915_mmu_object;
 191
 192 struct drm_i915_file_private {
 193         struct drm_i915_private *dev_priv;
 194
 195         union {
 196                 struct drm_file *file;
 197                 struct rcu_head rcu;
 198         };
 199
 200         struct {
 201                 spinlock_t lock;
 202                 struct list_head request_list;
 203         } mm;
 204
 205         struct xarray context_xa;
 206
 207         struct idr vm_idr;
 208         struct mutex vm_idr_lock; /* guards vm_idr */
 209
 210         unsigned int bsd_engine;
 211
 212 /*
 213  * Every context ban increments per client ban score. Also
 214  * hangs in short succession increments ban score. If ban threshold
 215  * is reached, client is considered banned and submitting more work
 216  * will fail. This is a stop gap measure to limit the badly behaving
 217  * clients access to gpu. Note that unbannable contexts never increment
 218  * the client ban score.
 219  */
 220 #define I915_CLIENT_SCORE_HANG_FAST     1
 221 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
 222 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
 223 #define I915_CLIENT_SCORE_BANNED        9
 224         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
 225         atomic_t ban_score;
 226         unsigned long hang_timestamp;
 227 };
 228
 229 /* Interface history:
 230  *
 231  * 1.1: Original.
 232  * 1.2: Add Power Management
 233  * 1.3: Add vblank support
 234  * 1.4: Fix cmdbuffer path, add heap destroy
 235  * 1.5: Add vblank pipe configuration
 236  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 237  *      - Support vertical blank on secondary display pipe
 238  */
 239 #define DRIVER_MAJOR            1
 240 #define DRIVER_MINOR            6
 241 #define DRIVER_PATCHLEVEL       0
 242
 243 struct intel_overlay;
 244 struct intel_overlay_error_state;
 245
 246 struct sdvo_device_mapping {
 247         u8 initialized;
 248         u8 dvo_port;
 249         u8 slave_addr;
 250         u8 dvo_wiring;
 251         u8 i2c_pin;
 252         u8 ddc_pin;
 253 };
 254
 255 struct intel_connector;
 256 struct intel_encoder;
 257 struct intel_atomic_state;
 258 struct intel_crtc_state;
 259 struct intel_initial_plane_config;
 260 struct intel_crtc;
 261 struct intel_limit;
 262 struct dpll;
 263 struct intel_cdclk_state;
 264
 265 struct drm_i915_display_funcs {
 266         void (*get_cdclk)(struct drm_i915_private *dev_priv,
 267                           struct intel_cdclk_state *cdclk_state);
 268         void (*set_cdclk)(struct drm_i915_private *dev_priv,
 269                           const struct intel_cdclk_state *cdclk_state,
 270                           enum pipe pipe);
 271         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 272                              enum i9xx_plane_id i9xx_plane);
 273         int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
 274         int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
 275         void (*initial_watermarks)(struct intel_atomic_state *state,
 276                                    struct intel_crtc *crtc);
 277         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
 278                                          struct intel_crtc *crtc);
 279         void (*optimize_watermarks)(struct intel_atomic_state *state,
 280                                     struct intel_crtc *crtc);
 281         int (*compute_global_watermarks)(struct intel_atomic_state *state);
 282         void (*update_wm)(struct intel_crtc *crtc);
 283         int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 284         u8 (*calc_voltage_level)(int cdclk);
 285         /* Returns the active state of the crtc, and if the crtc is active,
 286          * fills out the pipe-config with the hw state. */
 287         bool (*get_pipe_config)(struct intel_crtc *,
 288                                 struct intel_crtc_state *);
 289         void (*get_initial_plane_config)(struct intel_crtc *,
 290                                          struct intel_initial_plane_config *);
 291         int (*crtc_compute_clock)(struct intel_crtc *crtc,
 292                                   struct intel_crtc_state *crtc_state);
 293         void (*crtc_enable)(struct intel_atomic_state *state,
 294                             struct intel_crtc *crtc);
 295         void (*crtc_disable)(struct intel_atomic_state *state,
 296                              struct intel_crtc *crtc);
 297         void (*commit_modeset_enables)(struct intel_atomic_state *state);
 298         void (*commit_modeset_disables)(struct intel_atomic_state *state);
 299         void (*audio_codec_enable)(struct intel_encoder *encoder,
 300                                    const struct intel_crtc_state *crtc_state,
 301                                    const struct drm_connector_state *conn_state);
 302         void (*audio_codec_disable)(struct intel_encoder *encoder,
 303                                     const struct intel_crtc_state *old_crtc_state,
 304                                     const struct drm_connector_state *old_conn_state);
 305         void (*fdi_link_train)(struct intel_crtc *crtc,
 306                                const struct intel_crtc_state *crtc_state);
 307         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 308         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 309         /* clock updates for mode set */
 310         /* cursor updates */
 311         /* render clock increase/decrease */
 312         /* display clock increase/decrease */
 313         /* pll clock increase/decrease */
 314
 315         int (*color_check)(struct intel_crtc_state *crtc_state);
 316         /*
 317          * Program double buffered color management registers during
 318          * vblank evasion. The registers should then latch during the
 319          * next vblank start, alongside any other double buffered registers
 320          * involved with the same commit.
 321          */
 322         void (*color_commit)(const struct intel_crtc_state *crtc_state);
 323         /*
 324          * Load LUTs (and other single buffered color management
 325          * registers). Will (hopefully) be called during the vblank
 326          * following the latching of any double buffered registers
 327          * involved with the same commit.
 328          */
 329         void (*load_luts)(const struct intel_crtc_state *crtc_state);
 330         void (*read_luts)(struct intel_crtc_state *crtc_state);
 331 };
 332
 333 struct intel_csr {
 334         struct work_struct work;
 335         const char *fw_path;
 336         u32 required_version;
 337         u32 max_fw_size; /* bytes */
 338         u32 *dmc_payload;
 339         u32 dmc_fw_size; /* dwords */
 340         u32 version;
 341         u32 mmio_count;
 342         i915_reg_t mmioaddr[20];
 343         u32 mmiodata[20];
 344         u32 dc_state;
 345         u32 target_dc_state;
 346         u32 allowed_dc_mask;
 347         intel_wakeref_t wakeref;
 348 };
 349
 350 enum i915_cache_level {
 351         I915_CACHE_NONE = 0,
 352         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 353         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 354                               caches, eg sampler/render caches, and the
 355                               large Last-Level-Cache. LLC is coherent with
 356                               the CPU, but L3 is only visible to the GPU. */
 357         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 358 };
 359
 360 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
 361
 362 struct intel_fbc {
 363         /* This is always the inner lock when overlapping with struct_mutex and
 364          * it's the outer lock when overlapping with stolen_lock. */
 365         struct mutex lock;
 366         unsigned threshold;
 367         unsigned int possible_framebuffer_bits;
 368         unsigned int busy_bits;
 369         struct intel_crtc *crtc;
 370
 371         struct drm_mm_node compressed_fb;
 372         struct drm_mm_node *compressed_llb;
 373
 374         bool false_color;
 375
 376         bool active;
 377         bool activated;
 378         bool flip_pending;
 379
 380         bool underrun_detected;
 381         struct work_struct underrun_work;
 382
 383         /*
 384          * Due to the atomic rules we can't access some structures without the
 385          * appropriate locking, so we cache information here in order to avoid
 386          * these problems.
 387          */
 388         struct intel_fbc_state_cache {
 389                 struct {
 390                         unsigned int mode_flags;
 391                         u32 hsw_bdw_pixel_rate;
 392                 } crtc;
 393
 394                 struct {
 395                         unsigned int rotation;
 396                         int src_w;
 397                         int src_h;
 398                         bool visible;
 399                         /*
 400                          * Display surface base address adjustement for
 401                          * pageflips. Note that on gen4+ this only adjusts up
 402                          * to a tile, offsets within a tile are handled in
 403                          * the hw itself (with the TILEOFF register).
 404                          */
 405                         int adjusted_x;
 406                         int adjusted_y;
 407
 408                         int y;
 409
 410                         u16 pixel_blend_mode;
 411                 } plane;
 412
 413                 struct {
 414                         const struct drm_format_info *format;
 415                         unsigned int stride;
 416                 } fb;
 417                 u16 gen9_wa_cfb_stride;
 418                 s8 fence_id;
 419         } state_cache;
 420
 421         /*
 422          * This structure contains everything that's relevant to program the
 423          * hardware registers. When we want to figure out if we need to disable
 424          * and re-enable FBC for a new configuration we just check if there's
 425          * something different in the struct. The genx_fbc_activate functions
 426          * are supposed to read from it in order to program the registers.
 427          */
 428         struct intel_fbc_reg_params {
 429                 struct {
 430                         enum pipe pipe;
 431                         enum i9xx_plane_id i9xx_plane;
 432                         unsigned int fence_y_offset;
 433                 } crtc;
 434
 435                 struct {
 436                         const struct drm_format_info *format;
 437                         unsigned int stride;
 438                 } fb;
 439
 440                 int cfb_size;
 441                 u16 gen9_wa_cfb_stride;
 442                 s8 fence_id;
 443                 bool plane_visible;
 444         } params;
 445
 446         const char *no_fbc_reason;
 447 };
 448
 449 /*
 450  * HIGH_RR is the highest eDP panel refresh rate read from EDID
 451  * LOW_RR is the lowest eDP panel refresh rate found from EDID
 452  * parsing for same resolution.
 453  */
 454 enum drrs_refresh_rate_type {
 455         DRRS_HIGH_RR,
 456         DRRS_LOW_RR,
 457         DRRS_MAX_RR, /* RR count */
 458 };
 459
 460 enum drrs_support_type {
 461         DRRS_NOT_SUPPORTED = 0,
 462         STATIC_DRRS_SUPPORT = 1,
 463         SEAMLESS_DRRS_SUPPORT = 2
 464 };
 465
 466 struct intel_dp;
 467 struct i915_drrs {
 468         struct mutex mutex;
 469         struct delayed_work work;
 470         struct intel_dp *dp;
 471         unsigned busy_frontbuffer_bits;
 472         enum drrs_refresh_rate_type refresh_rate_type;
 473         enum drrs_support_type type;
 474 };
 475
 476 struct i915_psr {
 477         struct mutex lock;
 478
 479 #define I915_PSR_DEBUG_MODE_MASK        0x0f
 480 #define I915_PSR_DEBUG_DEFAULT          0x00
 481 #define I915_PSR_DEBUG_DISABLE          0x01
 482 #define I915_PSR_DEBUG_ENABLE           0x02
 483 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
 484 #define I915_PSR_DEBUG_IRQ              0x10
 485
 486         u32 debug;
 487         bool sink_support;
 488         bool enabled;
 489         struct intel_dp *dp;
 490         enum pipe pipe;
 491         enum transcoder transcoder;
 492         bool active;
 493         struct work_struct work;
 494         unsigned busy_frontbuffer_bits;
 495         bool sink_psr2_support;
 496         bool link_standby;
 497         bool colorimetry_support;
 498         bool psr2_enabled;
 499         u8 sink_sync_latency;
 500         ktime_t last_entry_attempt;
 501         ktime_t last_exit;
 502         bool sink_not_reliable;
 503         bool irq_aux_error;
 504         u16 su_x_granularity;
 505         bool dc3co_enabled;
 506         u32 dc3co_exit_delay;
 507         struct delayed_work idle_work;
 508         bool initially_probed;
 509 };
 510
 511 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 512 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 513 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 514 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
 515 #define QUIRK_INCREASE_T12_DELAY (1<<6)
 516 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
 517
 518 struct intel_fbdev;
 519 struct intel_fbc_work;
 520
 521 struct intel_gmbus {
 522         struct i2c_adapter adapter;
 523 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
 524         u32 force_bit;
 525         u32 reg0;
 526         i915_reg_t gpio_reg;
 527         struct i2c_algo_bit_data bit_algo;
 528         struct drm_i915_private *dev_priv;
 529 };
 530
 531 struct i915_suspend_saved_registers {
 532         u32 saveDSPARB;
 533         u32 saveFBC_CONTROL;
 534         u32 saveCACHE_MODE_0;
 535         u32 saveMI_ARB_STATE;
 536         u32 saveSWF0[16];
 537         u32 saveSWF1[16];
 538         u32 saveSWF3[3];
 539         u64 saveFENCE[I915_MAX_NUM_FENCES];
 540         u32 savePCH_PORT_HOTPLUG;
 541         u16 saveGCDGMBUS;
 542 };
 543
 544 struct vlv_s0ix_state;
 545
 546 #define MAX_L3_SLICES 2
 547 struct intel_l3_parity {
 548         u32 *remap_info[MAX_L3_SLICES];
 549         struct work_struct error_work;
 550         int which_slice;
 551 };
 552
 553 struct i915_gem_mm {
 554         /** Memory allocator for GTT stolen memory */
 555         struct drm_mm stolen;
 556         /** Protects the usage of the GTT stolen memory allocator. This is
 557          * always the inner lock when overlapping with struct_mutex. */
 558         struct mutex stolen_lock;
 559
 560         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 561         spinlock_t obj_lock;
 562
 563         /**
 564          * List of objects which are purgeable.
 565          */
 566         struct list_head purge_list;
 567
 568         /**
 569          * List of objects which have allocated pages and are shrinkable.
 570          */
 571         struct list_head shrink_list;
 572
 573         /**
 574          * List of objects which are pending destruction.
 575          */
 576         struct llist_head free_list;
 577         struct work_struct free_work;
 578         /**
 579          * Count of objects pending destructions. Used to skip needlessly
 580          * waiting on an RCU barrier if no objects are waiting to be freed.
 581          */
 582         atomic_t free_count;
 583
 584         /**
 585          * Small stash of WC pages
 586          */
 587         struct pagestash wc_stash;
 588
 589         /**
 590          * tmpfs instance used for shmem backed objects
 591          */
 592         struct vfsmount *gemfs;
 593
 594         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 595
 596         struct notifier_block oom_notifier;
 597         struct notifier_block vmap_notifier;
 598         struct shrinker shrinker;
 599
 600         /**
 601          * Workqueue to fault in userptr pages, flushed by the execbuf
 602          * when required but otherwise left to userspace to try again
 603          * on EAGAIN.
 604          */
 605         struct workqueue_struct *userptr_wq;
 606
 607         /* shrinker accounting, also useful for userland debugging */
 608         u64 shrink_memory;
 609         u32 shrink_count;
 610 };
 611
 612 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 613
 614 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
 615 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
 616
 617 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
 618 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
 619
 620 #define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */
 621
 622 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 623 #define I915_NUM_QGV_POINTS 8
 624
 625 struct ddi_vbt_port_info {
 626         /* Non-NULL if port present. */
 627         const struct child_device_config *child;
 628
 629         int max_tmds_clock;
 630
 631         /* This is an index in the HDMI/DVI DDI buffer translation table. */
 632         u8 hdmi_level_shift;
 633         u8 hdmi_level_shift_set:1;
 634
 635         u8 supports_dvi:1;
 636         u8 supports_hdmi:1;
 637         u8 supports_dp:1;
 638         u8 supports_edp:1;
 639         u8 supports_typec_usb:1;
 640         u8 supports_tbt:1;
 641
 642         u8 alternate_aux_channel;
 643         u8 alternate_ddc_pin;
 644
 645         u8 dp_boost_level;
 646         u8 hdmi_boost_level;
 647         int dp_max_link_rate;           /* 0 for not limited by VBT */
 648 };
 649
 650 enum psr_lines_to_wait {
 651         PSR_0_LINES_TO_WAIT = 0,
 652         PSR_1_LINE_TO_WAIT,
 653         PSR_4_LINES_TO_WAIT,
 654         PSR_8_LINES_TO_WAIT
 655 };
 656
 657 struct intel_vbt_data {
 658         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 659         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 660
 661         /* Feature bits */
 662         unsigned int int_tv_support:1;
 663         unsigned int lvds_dither:1;
 664         unsigned int int_crt_support:1;
 665         unsigned int lvds_use_ssc:1;
 666         unsigned int int_lvds_support:1;
 667         unsigned int display_clock_mode:1;
 668         unsigned int fdi_rx_polarity_inverted:1;
 669         unsigned int panel_type:4;
 670         int lvds_ssc_freq;
 671         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 672         enum drm_panel_orientation orientation;
 673
 674         enum drrs_support_type drrs_type;
 675
 676         struct {
 677                 int rate;
 678                 int lanes;
 679                 int preemphasis;
 680                 int vswing;
 681                 bool low_vswing;
 682                 bool initialized;
 683                 int bpp;
 684                 struct edp_power_seq pps;
 685         } edp;
 686
 687         struct {
 688                 bool enable;
 689                 bool full_link;
 690                 bool require_aux_wakeup;
 691                 int idle_frames;
 692                 enum psr_lines_to_wait lines_to_wait;
 693                 int tp1_wakeup_time_us;
 694                 int tp2_tp3_wakeup_time_us;
 695                 int psr2_tp2_tp3_wakeup_time_us;
 696         } psr;
 697
 698         struct {
 699                 u16 pwm_freq_hz;
 700                 bool present;
 701                 bool active_low_pwm;
 702                 u8 min_brightness;      /* min_brightness/255 of max */
 703                 u8 controller;          /* brightness controller number */
 704                 enum intel_backlight_type type;
 705         } backlight;
 706
 707         /* MIPI DSI */
 708         struct {
 709                 u16 panel_id;
 710                 struct mipi_config *config;
 711                 struct mipi_pps_data *pps;
 712                 u16 bl_ports;
 713                 u16 cabc_ports;
 714                 u8 seq_version;
 715                 u32 size;
 716                 u8 *data;
 717                 const u8 *sequence[MIPI_SEQ_MAX];
 718                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
 719                 enum drm_panel_orientation orientation;
 720         } dsi;
 721
 722         int crt_ddc_pin;
 723
 724         struct list_head display_devices;
 725
 726         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
 727         struct sdvo_device_mapping sdvo_mappings[2];
 728 };
 729
 730 enum intel_ddb_partitioning {
 731         INTEL_DDB_PART_1_2,
 732         INTEL_DDB_PART_5_6, /* IVB+ */
 733 };
 734
 735 struct intel_wm_level {
 736         bool enable;
 737         u32 pri_val;
 738         u32 spr_val;
 739         u32 cur_val;
 740         u32 fbc_val;
 741 };
 742
 743 struct ilk_wm_values {
 744         u32 wm_pipe[3];
 745         u32 wm_lp[3];
 746         u32 wm_lp_spr[3];
 747         u32 wm_linetime[3];
 748         bool enable_fbc_wm;
 749         enum intel_ddb_partitioning partitioning;
 750 };
 751
 752 struct g4x_pipe_wm {
 753         u16 plane[I915_MAX_PLANES];
 754         u16 fbc;
 755 };
 756
 757 struct g4x_sr_wm {
 758         u16 plane;
 759         u16 cursor;
 760         u16 fbc;
 761 };
 762
 763 struct vlv_wm_ddl_values {
 764         u8 plane[I915_MAX_PLANES];
 765 };
 766
 767 struct vlv_wm_values {
 768         struct g4x_pipe_wm pipe[3];
 769         struct g4x_sr_wm sr;
 770         struct vlv_wm_ddl_values ddl[3];
 771         u8 level;
 772         bool cxsr;
 773 };
 774
 775 struct g4x_wm_values {
 776         struct g4x_pipe_wm pipe[2];
 777         struct g4x_sr_wm sr;
 778         struct g4x_sr_wm hpll;
 779         bool cxsr;
 780         bool hpll_en;
 781         bool fbc_en;
 782 };
 783
 784 struct skl_ddb_entry {
 785         u16 start, end; /* in number of blocks, 'end' is exclusive */
 786 };
 787
 788 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
 789 {
 790         return entry->end - entry->start;
 791 }
 792
 793 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 794                                        const struct skl_ddb_entry *e2)
 795 {
 796         if (e1->start == e2->start && e1->end == e2->end)
 797                 return true;
 798
 799         return false;
 800 }
 801
 802 struct skl_ddb_allocation {
 803         u8 enabled_slices; /* GEN11 has configurable 2 slices */
 804 };
 805
 806 struct skl_ddb_values {
 807         unsigned dirty_pipes;
 808         struct skl_ddb_allocation ddb;
 809 };
 810
 811 struct skl_wm_level {
 812         u16 min_ddb_alloc;
 813         u16 plane_res_b;
 814         u8 plane_res_l;
 815         bool plane_en;
 816         bool ignore_lines;
 817 };
 818
 819 /* Stores plane specific WM parameters */
 820 struct skl_wm_params {
 821         bool x_tiled, y_tiled;
 822         bool rc_surface;
 823         bool is_planar;
 824         u32 width;
 825         u8 cpp;
 826         u32 plane_pixel_rate;
 827         u32 y_min_scanlines;
 828         u32 plane_bytes_per_line;
 829         uint_fixed_16_16_t plane_blocks_per_line;
 830         uint_fixed_16_16_t y_tile_minimum;
 831         u32 linetime_us;
 832         u32 dbuf_block_size;
 833 };
 834
 835 enum intel_pipe_crc_source {
 836         INTEL_PIPE_CRC_SOURCE_NONE,
 837         INTEL_PIPE_CRC_SOURCE_PLANE1,
 838         INTEL_PIPE_CRC_SOURCE_PLANE2,
 839         INTEL_PIPE_CRC_SOURCE_PLANE3,
 840         INTEL_PIPE_CRC_SOURCE_PLANE4,
 841         INTEL_PIPE_CRC_SOURCE_PLANE5,
 842         INTEL_PIPE_CRC_SOURCE_PLANE6,
 843         INTEL_PIPE_CRC_SOURCE_PLANE7,
 844         INTEL_PIPE_CRC_SOURCE_PIPE,
 845         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
 846         INTEL_PIPE_CRC_SOURCE_TV,
 847         INTEL_PIPE_CRC_SOURCE_DP_B,
 848         INTEL_PIPE_CRC_SOURCE_DP_C,
 849         INTEL_PIPE_CRC_SOURCE_DP_D,
 850         INTEL_PIPE_CRC_SOURCE_AUTO,
 851         INTEL_PIPE_CRC_SOURCE_MAX,
 852 };
 853
 854 #define INTEL_PIPE_CRC_ENTRIES_NR       128
 855 struct intel_pipe_crc {
 856         spinlock_t lock;
 857         int skipped;
 858         enum intel_pipe_crc_source source;
 859 };
 860
 861 struct i915_frontbuffer_tracking {
 862         spinlock_t lock;
 863
 864         /*
 865          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
 866          * scheduled flips.
 867          */
 868         unsigned busy_bits;
 869         unsigned flip_bits;
 870 };
 871
 872 struct i915_virtual_gpu {
 873         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 874         bool active;
 875         u32 caps;
 876 };
 877
 878 /* used in computing the new watermarks state */
 879 struct intel_wm_config {
 880         unsigned int num_pipes_active;
 881         bool sprites_enabled;
 882         bool sprites_scaled;
 883 };
 884
 885 struct intel_cdclk_state {
 886         unsigned int cdclk, vco, ref, bypass;
 887         u8 voltage_level;
 888 };
 889
 890 struct i915_selftest_stash {
 891         atomic_t counter;
 892 };
 893
 894 struct drm_i915_private {
 895         struct drm_device drm;
 896
 897         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 898         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 899         struct intel_driver_caps caps;
 900
 901         /**
 902          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 903          * end of stolen which we can optionally use to create GEM objects
 904          * backed by stolen memory. Note that stolen_usable_size tells us
 905          * exactly how much of this we are actually allowed to use, given that
 906          * some portion of it is in fact reserved for use by hardware functions.
 907          */
 908         struct resource dsm;
 909         /**
 910          * Reseved portion of Data Stolen Memory
 911          */
 912         struct resource dsm_reserved;
 913
 914         /*
 915          * Stolen memory is segmented in hardware with different portions
 916          * offlimits to certain functions.
 917          *
 918          * The drm_mm is initialised to the total accessible range, as found
 919          * from the PCI config. On Broadwell+, this is further restricted to
 920          * avoid the first page! The upper end of stolen memory is reserved for
 921          * hardware functions and similarly removed from the accessible range.
 922          */
 923         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 924
 925         struct intel_uncore uncore;
 926         struct intel_uncore_mmio_debug mmio_debug;
 927
 928         struct i915_virtual_gpu vgpu;
 929
 930         struct intel_gvt *gvt;
 931
 932         struct intel_wopcm wopcm;
 933
 934         struct intel_csr csr;
 935
 936         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
 937
 938         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 939          * controller on different i2c buses. */
 940         struct mutex gmbus_mutex;
 941
 942         /**
 943          * Base address of where the gmbus and gpio blocks are located (either
 944          * on PCH or on SoC for platforms without PCH).
 945          */
 946         u32 gpio_mmio_base;
 947
 948         u32 hsw_psr_mmio_adjust;
 949
 950         /* MMIO base address for MIPI regs */
 951         u32 mipi_mmio_base;
 952
 953         u32 pps_mmio_base;
 954
 955         wait_queue_head_t gmbus_wait_queue;
 956
 957         struct pci_dev *bridge_dev;
 958
 959         struct intel_engine_cs *engine[I915_NUM_ENGINES];
 960         struct rb_root uabi_engines;
 961
 962         struct resource mch_res;
 963
 964         /* protects the irq masks */
 965         spinlock_t irq_lock;
 966
 967         bool display_irqs_enabled;
 968
 969         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
 970         struct pm_qos_request pm_qos;
 971
 972         /* Sideband mailbox protection */
 973         struct mutex sb_lock;
 974         struct pm_qos_request sb_qos;
 975
 976         /** Cached value of IMR to avoid reads in updating the bitfield */
 977         union {
 978                 u32 irq_mask;
 979                 u32 de_irq_mask[I915_MAX_PIPES];
 980         };
 981         u32 pipestat_irq_mask[I915_MAX_PIPES];
 982
 983         struct i915_hotplug hotplug;
 984         struct intel_fbc fbc;
 985         struct i915_drrs drrs;
 986         struct intel_opregion opregion;
 987         struct intel_vbt_data vbt;
 988
 989         bool preserve_bios_swizzle;
 990
 991         /* overlay */
 992         struct intel_overlay *overlay;
 993
 994         /* backlight registers and fields in struct intel_panel */
 995         struct mutex backlight_lock;
 996
 997         /* protects panel power sequencer state */
 998         struct mutex pps_mutex;
 999
1000         unsigned int fsb_freq, mem_freq, is_ddr3;
1001         unsigned int skl_preferred_vco_freq;
1002         unsigned int max_cdclk_freq;
1003
1004         unsigned int max_dotclk_freq;
1005         unsigned int rawclk_freq;
1006         unsigned int hpll_freq;
1007         unsigned int fdi_pll_freq;
1008         unsigned int czclk_freq;
1009
1010         /*
1011          * For reading holding any crtc lock is sufficient,
1012          * for writing must hold all of them.
1013          */
1014         struct {
1015                 /*
1016                  * The current logical cdclk state.
1017                  * See intel_atomic_state.cdclk.logical
1018                  */
1019                 struct intel_cdclk_state logical;
1020                 /*
1021                  * The current actual cdclk state.
1022                  * See intel_atomic_state.cdclk.actual
1023                  */
1024                 struct intel_cdclk_state actual;
1025                 /* The current hardware cdclk state */
1026                 struct intel_cdclk_state hw;
1027
1028                 /* cdclk, divider, and ratio table from bspec */
1029                 const struct intel_cdclk_vals *table;
1030
1031                 int force_min_cdclk;
1032         } cdclk;
1033
1034         /**
1035          * wq - Driver workqueue for GEM.
1036          *
1037          * NOTE: Work items scheduled here are not allowed to grab any modeset
1038          * locks, for otherwise the flushing done in the pageflip code will
1039          * result in deadlocks.
1040          */
1041         struct workqueue_struct *wq;
1042
1043         /* ordered wq for modesets */
1044         struct workqueue_struct *modeset_wq;
1045         /* unbound hipri wq for page flips/plane updates */
1046         struct workqueue_struct *flip_wq;
1047
1048         /* Display functions */
1049         struct drm_i915_display_funcs display;
1050
1051         /* PCH chipset type */
1052         enum intel_pch pch_type;
1053         unsigned short pch_id;
1054
1055         unsigned long quirks;
1056
1057         struct drm_atomic_state *modeset_restore_state;
1058         struct drm_modeset_acquire_ctx reset_ctx;
1059
1060         struct i915_ggtt ggtt; /* VM representing the global address space */
1061
1062         struct i915_gem_mm mm;
1063         DECLARE_HASHTABLE(mm_structs, 7);
1064         struct mutex mm_lock;
1065
1066         /* Kernel Modesetting */
1067
1068         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1069         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1070
1071 #ifdef CONFIG_DEBUG_FS
1072         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1073 #endif
1074
1075         /* dpll and cdclk state is protected by connection_mutex */
1076         int num_shared_dpll;
1077         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1078         const struct intel_dpll_mgr *dpll_mgr;
1079
1080         /*
1081          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1082          * Must be global rather than per dpll, because on some platforms
1083          * plls share registers.
1084          */
1085         struct mutex dpll_lock;
1086
1087         /*
1088          * For reading active_pipes, min_cdclk, min_voltage_level holding
1089          * any crtc lock is sufficient, for writing must hold all of them.
1090          */
1091         u8 active_pipes;
1092         /* minimum acceptable cdclk for each pipe */
1093         int min_cdclk[I915_MAX_PIPES];
1094         /* minimum acceptable voltage level for each pipe */
1095         u8 min_voltage_level[I915_MAX_PIPES];
1096
1097         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1098
1099         struct i915_wa_list gt_wa_list;
1100
1101         struct i915_frontbuffer_tracking fb_tracking;
1102
1103         struct intel_atomic_helper {
1104                 struct llist_head free_list;
1105                 struct work_struct free_work;
1106         } atomic_helper;
1107
1108         u16 orig_clock;
1109
1110         bool mchbar_need_disable;
1111
1112         struct intel_l3_parity l3_parity;
1113
1114         /*
1115          * edram size in MB.
1116          * Cannot be determined by PCIID. You must always read a register.
1117          */
1118         u32 edram_size_mb;
1119
1120         struct i915_power_domains power_domains;
1121
1122         struct i915_psr psr;
1123
1124         struct i915_gpu_error gpu_error;
1125
1126         struct drm_i915_gem_object *vlv_pctx;
1127
1128         /* list of fbdev register on this device */
1129         struct intel_fbdev *fbdev;
1130         struct work_struct fbdev_suspend_work;
1131
1132         struct drm_property *broadcast_rgb_property;
1133         struct drm_property *force_audio_property;
1134
1135         /* hda/i915 audio component */
1136         struct i915_audio_component *audio_component;
1137         bool audio_component_registered;
1138         /**
1139          * av_mutex - mutex for audio/video sync
1140          *
1141          */
1142         struct mutex av_mutex;
1143         int audio_power_refcount;
1144         u32 audio_freq_cntrl;
1145
1146         u32 fdi_rx_config;
1147
1148         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1149         u32 chv_phy_control;
1150         /*
1151          * Shadows for CHV DPLL_MD regs to keep the state
1152          * checker somewhat working in the presence hardware
1153          * crappiness (can't read out DPLL_MD for pipes B & C).
1154          */
1155         u32 chv_dpll_md[I915_MAX_PIPES];
1156         u32 bxt_phy_grc;
1157
1158         u32 suspend_count;
1159         bool power_domains_suspended;
1160         struct i915_suspend_saved_registers regfile;
1161         struct vlv_s0ix_state *vlv_s0ix_state;
1162
1163         enum {
1164                 I915_SAGV_UNKNOWN = 0,
1165                 I915_SAGV_DISABLED,
1166                 I915_SAGV_ENABLED,
1167                 I915_SAGV_NOT_CONTROLLED
1168         } sagv_status;
1169
1170         u32 sagv_block_time_us;
1171
1172         struct {
1173                 /*
1174                  * Raw watermark latency values:
1175                  * in 0.1us units for WM0,
1176                  * in 0.5us units for WM1+.
1177                  */
1178                 /* primary */
1179                 u16 pri_latency[5];
1180                 /* sprite */
1181                 u16 spr_latency[5];
1182                 /* cursor */
1183                 u16 cur_latency[5];
1184                 /*
1185                  * Raw watermark memory latency values
1186                  * for SKL for all 8 levels
1187                  * in 1us units.
1188                  */
1189                 u16 skl_latency[8];
1190
1191                 /* current hardware state */
1192                 union {
1193                         struct ilk_wm_values hw;
1194                         struct skl_ddb_values skl_hw;
1195                         struct vlv_wm_values vlv;
1196                         struct g4x_wm_values g4x;
1197                 };
1198
1199                 u8 max_level;
1200
1201                 /*
1202                  * Should be held around atomic WM register writing; also
1203                  * protects * intel_crtc->wm.active and
1204                  * crtc_state->wm.need_postvbl_update.
1205                  */
1206                 struct mutex wm_mutex;
1207
1208                 /*
1209                  * Set during HW readout of watermarks/DDB.  Some platforms
1210                  * need to know when we're still using BIOS-provided values
1211                  * (which we don't fully trust).
1212                  */
1213                 bool distrust_bios_wm;
1214         } wm;
1215
1216         struct dram_info {
1217                 bool valid;
1218                 bool is_16gb_dimm;
1219                 u8 num_channels;
1220                 u8 ranks;
1221                 u32 bandwidth_kbps;
1222                 bool symmetric_memory;
1223                 enum intel_dram_type {
1224                         INTEL_DRAM_UNKNOWN,
1225                         INTEL_DRAM_DDR3,
1226                         INTEL_DRAM_DDR4,
1227                         INTEL_DRAM_LPDDR3,
1228                         INTEL_DRAM_LPDDR4
1229                 } type;
1230         } dram_info;
1231
1232         struct intel_bw_info {
1233                 /* for each QGV point */
1234                 unsigned int deratedbw[I915_NUM_QGV_POINTS];
1235                 u8 num_qgv_points;
1236                 u8 num_planes;
1237         } max_bw[6];
1238
1239         struct drm_private_obj bw_obj;
1240
1241         struct intel_runtime_pm runtime_pm;
1242
1243         struct i915_perf perf;
1244
1245         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1246         struct intel_gt gt;
1247
1248         struct {
1249                 struct i915_gem_contexts {
1250                         spinlock_t lock; /* locks list */
1251                         struct list_head list;
1252
1253                         struct llist_head free_list;
1254                         struct work_struct free_work;
1255                 } contexts;
1256
1257                 /*
1258                  * We replace the local file with a global mappings as the
1259                  * backing storage for the mmap is on the device and not
1260                  * on the struct file, and we do not want to prolong the
1261                  * lifetime of the local fd. To minimise the number of
1262                  * anonymous inodes we create, we use a global singleton to
1263                  * share the global mapping.
1264                  */
1265                 struct file *mmap_singleton;
1266         } gem;
1267
1268         u8 pch_ssc_use;
1269
1270         /* For i915gm/i945gm vblank irq workaround */
1271         u8 vblank_enabled;
1272
1273         /* perform PHY state sanity checks? */
1274         bool chv_phy_assert[2];
1275
1276         bool ipc_enabled;
1277
1278         /* Used to save the pipe-to-encoder mapping for audio */
1279         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1280
1281         /* necessary resource sharing with HDMI LPE audio driver. */
1282         struct {
1283                 struct platform_device *platdev;
1284                 int     irq;
1285         } lpe_audio;
1286
1287         struct i915_pmu pmu;
1288
1289         struct i915_hdcp_comp_master *hdcp_master;
1290         bool hdcp_comp_added;
1291
1292         /* Mutex to protect the above hdcp component related values. */
1293         struct mutex hdcp_comp_mutex;
1294
1295         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
1296
1297         /*
1298          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1299          * will be rejected. Instead look for a better place.
1300          */
1301 };
1302
1303 struct dram_dimm_info {
1304         u8 size, width, ranks;
1305 };
1306
1307 struct dram_channel_info {
1308         struct dram_dimm_info dimm_l, dimm_s;
1309         u8 ranks;
1310         bool is_16gb_dimm;
1311 };
1312
1313 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1314 {
1315         return container_of(dev, struct drm_i915_private, drm);
1316 }
1317
1318 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1319 {
1320         return dev_get_drvdata(kdev);
1321 }
1322
1323 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1324 {
1325         return pci_get_drvdata(pdev);
1326 }
1327
1328 /* Simple iterator over all initialised engines */
1329 #define for_each_engine(engine__, dev_priv__, id__) \
1330         for ((id__) = 0; \
1331              (id__) < I915_NUM_ENGINES; \
1332              (id__)++) \
1333                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1334
1335 /* Iterator over subset of engines selected by mask */
1336 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
1337         for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1338              (tmp__) ? \
1339              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
1340              0;)
1341
1342 #define rb_to_uabi_engine(rb) \
1343         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1344
1345 #define for_each_uabi_engine(engine__, i915__) \
1346         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1347              (engine__); \
1348              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1349
1350 #define I915_GTT_OFFSET_NONE ((u32)-1)
1351
1352 /*
1353  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1354  * considered to be the frontbuffer for the given plane interface-wise. This
1355  * doesn't mean that the hw necessarily already scans it out, but that any
1356  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1357  *
1358  * We have one bit per pipe and per scanout plane type.
1359  */
1360 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1361 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1362         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1363         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1364         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1365 })
1366 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1367         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1368 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1369         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1370                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1371
1372 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
1373 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
1374 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
1375
1376 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
1377 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
1378
1379 #define REVID_FOREVER           0xff
1380 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
1381
1382 #define INTEL_GEN_MASK(s, e) ( \
1383         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1384         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1385         GENMASK((e) - 1, (s) - 1))
1386
1387 /* Returns true if Gen is in inclusive range [Start, End] */
1388 #define IS_GEN_RANGE(dev_priv, s, e) \
1389         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1390
1391 #define IS_GEN(dev_priv, n) \
1392         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1393          INTEL_INFO(dev_priv)->gen == (n))
1394
1395 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
1396
1397 /*
1398  * Return true if revision is in range [since,until] inclusive.
1399  *
1400  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1401  */
1402 #define IS_REVID(p, since, until) \
1403         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1404
1405 static __always_inline unsigned int
1406 __platform_mask_index(const struct intel_runtime_info *info,
1407                       enum intel_platform p)
1408 {
1409         const unsigned int pbits =
1410                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1411
1412         /* Expand the platform_mask array if this fails. */
1413         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1414                      pbits * ARRAY_SIZE(info->platform_mask));
1415
1416         return p / pbits;
1417 }
1418
1419 static __always_inline unsigned int
1420 __platform_mask_bit(const struct intel_runtime_info *info,
1421                     enum intel_platform p)
1422 {
1423         const unsigned int pbits =
1424                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1425
1426         return p % pbits + INTEL_SUBPLATFORM_BITS;
1427 }
1428
1429 static inline u32
1430 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1431 {
1432         const unsigned int pi = __platform_mask_index(info, p);
1433
1434         return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1435 }
1436
1437 static __always_inline bool
1438 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1439 {
1440         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1441         const unsigned int pi = __platform_mask_index(info, p);
1442         const unsigned int pb = __platform_mask_bit(info, p);
1443
1444         BUILD_BUG_ON(!__builtin_constant_p(p));
1445
1446         return info->platform_mask[pi] & BIT(pb);
1447 }
1448
1449 static __always_inline bool
1450 IS_SUBPLATFORM(const struct drm_i915_private *i915,
1451                enum intel_platform p, unsigned int s)
1452 {
1453         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1454         const unsigned int pi = __platform_mask_index(info, p);
1455         const unsigned int pb = __platform_mask_bit(info, p);
1456         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1457         const u32 mask = info->platform_mask[pi];
1458
1459         BUILD_BUG_ON(!__builtin_constant_p(p));
1460         BUILD_BUG_ON(!__builtin_constant_p(s));
1461         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1462
1463         /* Shift and test on the MSB position so sign flag can be used. */
1464         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1465 }
1466
1467 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
1468 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
1469
1470 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
1471 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
1472 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
1473 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
1474 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
1475 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
1476 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
1477 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
1478 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
1479 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
1480 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
1481 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
1482 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
1483 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1484 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
1485 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1486 #define IS_IRONLAKE_M(dev_priv) \
1487         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1488 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1489 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
1490                                  INTEL_INFO(dev_priv)->gt == 1)
1491 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1492 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1493 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
1494 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1495 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1496 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
1497 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1498 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1499 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1500 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1501 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1502 #define IS_ELKHARTLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1503 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1504 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1505                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1506 #define IS_BDW_ULT(dev_priv) \
1507         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1508 #define IS_BDW_ULX(dev_priv) \
1509         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1510 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
1511                                  INTEL_INFO(dev_priv)->gt == 3)
1512 #define IS_HSW_ULT(dev_priv) \
1513         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1514 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
1515                                  INTEL_INFO(dev_priv)->gt == 3)
1516 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
1517                                  INTEL_INFO(dev_priv)->gt == 1)
1518 /* ULX machines are also considered ULT. */
1519 #define IS_HSW_ULX(dev_priv) \
1520         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1521 #define IS_SKL_ULT(dev_priv) \
1522         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1523 #define IS_SKL_ULX(dev_priv) \
1524         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1525 #define IS_KBL_ULT(dev_priv) \
1526         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1527 #define IS_KBL_ULX(dev_priv) \
1528         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1529 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1530                                  INTEL_INFO(dev_priv)->gt == 2)
1531 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1532                                  INTEL_INFO(dev_priv)->gt == 3)
1533 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
1534                                  INTEL_INFO(dev_priv)->gt == 4)
1535 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1536                                  INTEL_INFO(dev_priv)->gt == 2)
1537 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
1538                                  INTEL_INFO(dev_priv)->gt == 3)
1539 #define IS_CFL_ULT(dev_priv) \
1540         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1541 #define IS_CFL_ULX(dev_priv) \
1542         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1543 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1544                                  INTEL_INFO(dev_priv)->gt == 2)
1545 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
1546                                  INTEL_INFO(dev_priv)->gt == 3)
1547 #define IS_CNL_WITH_PORT_F(dev_priv) \
1548         IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1549 #define IS_ICL_WITH_PORT_F(dev_priv) \
1550         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1551
1552 #define SKL_REVID_A0            0x0
1553 #define SKL_REVID_B0            0x1
1554 #define SKL_REVID_C0            0x2
1555 #define SKL_REVID_D0            0x3
1556 #define SKL_REVID_E0            0x4
1557 #define SKL_REVID_F0            0x5
1558 #define SKL_REVID_G0            0x6
1559 #define SKL_REVID_H0            0x7
1560
1561 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
1562
1563 #define BXT_REVID_A0            0x0
1564 #define BXT_REVID_A1            0x1
1565 #define BXT_REVID_B0            0x3
1566 #define BXT_REVID_B_LAST        0x8
1567 #define BXT_REVID_C0            0x9
1568
1569 #define IS_BXT_REVID(dev_priv, since, until) \
1570         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1571
1572 #define KBL_REVID_A0            0x0
1573 #define KBL_REVID_B0            0x1
1574 #define KBL_REVID_C0            0x2
1575 #define KBL_REVID_D0            0x3
1576 #define KBL_REVID_E0            0x4
1577
1578 #define IS_KBL_REVID(dev_priv, since, until) \
1579         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1580
1581 #define GLK_REVID_A0            0x0
1582 #define GLK_REVID_A1            0x1
1583
1584 #define IS_GLK_REVID(dev_priv, since, until) \
1585         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1586
1587 #define CNL_REVID_A0            0x0
1588 #define CNL_REVID_B0            0x1
1589 #define CNL_REVID_C0            0x2
1590
1591 #define IS_CNL_REVID(p, since, until) \
1592         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
1593
1594 #define ICL_REVID_A0            0x0
1595 #define ICL_REVID_A2            0x1
1596 #define ICL_REVID_B0            0x3
1597 #define ICL_REVID_B2            0x4
1598 #define ICL_REVID_C0            0x5
1599
1600 #define IS_ICL_REVID(p, since, until) \
1601         (IS_ICELAKE(p) && IS_REVID(p, since, until))
1602
1603 #define TGL_REVID_A0            0x0
1604
1605 #define IS_TGL_REVID(p, since, until) \
1606         (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
1607
1608 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
1609 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
1610 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
1611
1612 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1613
1614 #define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({                \
1615         unsigned int first__ = (first);                                 \
1616         unsigned int count__ = (count);                                 \
1617         (INTEL_INFO(dev_priv)->engine_mask &                            \
1618          GENMASK(first__ + count__ - 1, first__)) >> first__;           \
1619 })
1620 #define VDBOX_MASK(dev_priv) \
1621         ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
1622 #define VEBOX_MASK(dev_priv) \
1623         ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
1624
1625 /*
1626  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
1627  * All later gens can run the final buffer from the ppgtt
1628  */
1629 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
1630
1631 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
1632 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
1633 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
1634 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
1635 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
1636                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1637
1638 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
1639
1640 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
1641                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1642 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
1643                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1644 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
1645                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1646
1647 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
1648
1649 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
1650 #define HAS_PPGTT(dev_priv) \
1651         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1652 #define HAS_FULL_PPGTT(dev_priv) \
1653         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1654
1655 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
1656         GEM_BUG_ON((sizes) == 0); \
1657         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1658 })
1659
1660 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
1661 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
1662                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1663
1664 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1665 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
1666
1667 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
1668         (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1669
1670 /* WaRsDisableCoarsePowerGating:skl,cnl */
1671 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
1672         (IS_CANNONLAKE(dev_priv) ||                                     \
1673          IS_SKL_GT3(dev_priv) ||                                        \
1674          IS_SKL_GT4(dev_priv))
1675
1676 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
1677 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
1678                                         IS_GEMINILAKE(dev_priv) || \
1679                                         IS_KABYLAKE(dev_priv))
1680
1681 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1682  * rows, which changed the alignment requirements and fence programming.
1683  */
1684 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
1685                                          !(IS_I915G(dev_priv) || \
1686                                          IS_I915GM(dev_priv)))
1687 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
1688 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
1689
1690 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
1691 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
1692 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
1693
1694 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
1695
1696 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
1697
1698 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
1699 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
1700 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
1701 #define HAS_TRANSCODER_EDP(dev_priv)     (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
1702
1703 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
1704 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
1705 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
1706
1707 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
1708
1709 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
1710
1711 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
1712 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
1713
1714 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
1715
1716 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
1717 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
1718
1719 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
1720
1721 /* Having GuC is not the same as using GuC */
1722 #define USES_GUC(dev_priv)              intel_uc_uses_guc(&(dev_priv)->gt.uc)
1723 #define USES_GUC_SUBMISSION(dev_priv)   intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
1724
1725 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
1726
1727 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
1728
1729
1730 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
1731
1732 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
1733
1734 /* DPF == dynamic parity feature */
1735 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
1736 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
1737                                  2 : HAS_L3_DPF(dev_priv))
1738
1739 #define GT_FREQUENCY_MULTIPLIER 50
1740 #define GEN9_FREQ_SCALER 3
1741
1742 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
1743
1744 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
1745
1746 /* Only valid when HAS_DISPLAY() is true */
1747 #define INTEL_DISPLAY_ENABLED(dev_priv) (WARN_ON(!HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display)
1748
1749 static inline bool intel_vtd_active(void)
1750 {
1751 #ifdef CONFIG_INTEL_IOMMU
1752         if (intel_iommu_gfx_mapped)
1753                 return true;
1754 #endif
1755         return false;
1756 }
1757
1758 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
1759 {
1760         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
1761 }
1762
1763 static inline bool
1764 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
1765 {
1766         return IS_BROXTON(dev_priv) && intel_vtd_active();
1767 }
1768
1769 /* i915_drv.c */
1770 #ifdef CONFIG_COMPAT
1771 long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
1772 #else
1773 #define i915_compat_ioctl NULL
1774 #endif
1775 extern const struct dev_pm_ops i915_pm_ops;
1776
1777 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
1778 void i915_driver_remove(struct drm_i915_private *i915);
1779
1780 int i915_resume_switcheroo(struct drm_i915_private *i915);
1781 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
1782
1783 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
1784
1785 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
1786 {
1787         return dev_priv->gvt;
1788 }
1789
1790 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
1791 {
1792         return dev_priv->vgpu.active;
1793 }
1794
1795 int i915_getparam_ioctl(struct drm_device *dev, void *data,
1796                         struct drm_file *file_priv);
1797
1798 /* i915_gem.c */
1799 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1800 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1801 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1802 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1803 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1804 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1805
1806 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915);
1807
1808 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1809 {
1810         /*
1811          * A single pass should suffice to release all the freed objects (along
1812          * most call paths) , but be a little more paranoid in that freeing
1813          * the objects does take a little amount of time, during which the rcu
1814          * callbacks could have added new objects into the freed list, and
1815          * armed the work again.
1816          */
1817         while (atomic_read(&i915->mm.free_count)) {
1818                 flush_work(&i915->mm.free_work);
1819                 rcu_barrier();
1820         }
1821 }
1822
1823 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1824 {
1825         /*
1826          * Similar to objects above (see i915_gem_drain_freed-objects), in
1827          * general we have workers that are armed by RCU and then rearm
1828          * themselves in their callbacks. To be paranoid, we need to
1829          * drain the workqueue a second time after waiting for the RCU
1830          * grace period so that we catch work queued via RCU from the first
1831          * pass. As neither drain_workqueue() nor flush_workqueue() report
1832          * a result, we make an assumption that we only don't require more
1833          * than 3 passes to catch all _recursive_ RCU delayed work.
1834          *
1835          */
1836         int pass = 3;
1837         do {
1838                 flush_workqueue(i915->wq);
1839                 rcu_barrier();
1840                 i915_gem_drain_freed_objects(i915);
1841         } while (--pass);
1842         drain_workqueue(i915->wq);
1843 }
1844
1845 struct i915_vma * __must_check
1846 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1847                          const struct i915_ggtt_view *view,
1848                          u64 size,
1849                          u64 alignment,
1850                          u64 flags);
1851
1852 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
1853                            unsigned long flags);
1854 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
1855 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1)
1856
1857 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1858
1859 static inline int __must_check
1860 i915_mutex_lock_interruptible(struct drm_device *dev)
1861 {
1862         return mutex_lock_interruptible(&dev->struct_mutex);
1863 }
1864
1865 int i915_gem_dumb_create(struct drm_file *file_priv,
1866                          struct drm_device *dev,
1867                          struct drm_mode_create_dumb *args);
1868
1869 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
1870
1871 static inline u32 i915_reset_count(struct i915_gpu_error *error)
1872 {
1873         return atomic_read(&error->reset_count);
1874 }
1875
1876 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
1877                                           const struct intel_engine_cs *engine)
1878 {
1879         return atomic_read(&error->reset_engine_count[engine->uabi_class]);
1880 }
1881
1882 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1883 void i915_gem_driver_register(struct drm_i915_private *i915);
1884 void i915_gem_driver_unregister(struct drm_i915_private *i915);
1885 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1886 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1887 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1888 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1889 void i915_gem_resume(struct drm_i915_private *dev_priv);
1890
1891 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
1892 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1893
1894 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1895                                     enum i915_cache_level cache_level);
1896
1897 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1898                                 struct dma_buf *dma_buf);
1899
1900 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
1901
1902 static inline struct i915_gem_context *
1903 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
1904 {
1905         return xa_load(&file_priv->context_xa, id);
1906 }
1907
1908 static inline struct i915_gem_context *
1909 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
1910 {
1911         struct i915_gem_context *ctx;
1912
1913         rcu_read_lock();
1914         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
1915         if (ctx && !kref_get_unless_zero(&ctx->ref))
1916                 ctx = NULL;
1917         rcu_read_unlock();
1918
1919         return ctx;
1920 }
1921
1922 /* i915_gem_evict.c */
1923 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
1924                                           u64 min_size, u64 alignment,
1925                                           unsigned long color,
1926                                           u64 start, u64 end,
1927                                           unsigned flags);
1928 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
1929                                          struct drm_mm_node *node,
1930                                          unsigned int flags);
1931 int i915_gem_evict_vm(struct i915_address_space *vm);
1932
1933 /* i915_gem_internal.c */
1934 struct drm_i915_gem_object *
1935 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1936                                 phys_addr_t size);
1937
1938 /* i915_gem_tiling.c */
1939 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1940 {
1941         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1942
1943         return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1944                 i915_gem_object_is_tiled(obj);
1945 }
1946
1947 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1948                         unsigned int tiling, unsigned int stride);
1949 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1950                              unsigned int tiling, unsigned int stride);
1951
1952 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
1953
1954 /* i915_cmd_parser.c */
1955 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1956 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
1957 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
1958 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1959                             struct i915_vma *batch,
1960                             u32 batch_offset,
1961                             u32 batch_length,
1962                             struct i915_vma *shadow,
1963                             bool trampoline);
1964 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8
1965
1966 /* intel_device_info.c */
1967 static inline struct intel_device_info *
1968 mkwrite_device_info(struct drm_i915_private *dev_priv)
1969 {
1970         return (struct intel_device_info *)INTEL_INFO(dev_priv);
1971 }
1972
1973 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1974                         struct drm_file *file);
1975
1976 #define __I915_REG_OP(op__, dev_priv__, ...) \
1977         intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
1978
1979 #define I915_READ(reg__)         __I915_REG_OP(read, dev_priv, (reg__))
1980 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1981
1982 #define POSTING_READ(reg__)     __I915_REG_OP(posting_read, dev_priv, (reg__))
1983
1984 /* These are untraced mmio-accessors that are only valid to be used inside
1985  * critical sections, such as inside IRQ handlers, where forcewake is explicitly
1986  * controlled.
1987  *
1988  * Think twice, and think again, before using these.
1989  *
1990  * As an example, these accessors can possibly be used between:
1991  *
1992  * spin_lock_irq(&dev_priv->uncore.lock);
1993  * intel_uncore_forcewake_get__locked();
1994  *
1995  * and
1996  *
1997  * intel_uncore_forcewake_put__locked();
1998  * spin_unlock_irq(&dev_priv->uncore.lock);
1999  *
2000  *
2001  * Note: some registers may not need forcewake held, so
2002  * intel_uncore_forcewake_{get,put} can be omitted, see
2003  * intel_uncore_forcewake_for_reg().
2004  *
2005  * Certain architectures will die if the same cacheline is concurrently accessed
2006  * by different clients (e.g. on Ivybridge). Access to registers should
2007  * therefore generally be serialised, by either the dev_priv->uncore.lock or
2008  * a more localised lock guarding all access to that bank of registers.
2009  */
2010 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2011 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2012
2013 /* register wait wrappers for display regs */
2014 #define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2015         intel_wait_for_register(&(dev_priv_)->uncore, \
2016                                 (reg_), (mask_), (value_), (timeout_))
2017
2018 #define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({      \
2019         u32 mask__ = (mask_);                                           \
2020         intel_de_wait_for_register((dev_priv_), (reg_),                 \
2021                                    mask__, mask__, (timeout_)); \
2022 })
2023
2024 #define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2025         intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2026
2027 /* i915_mm.c */
2028 int remap_io_mapping(struct vm_area_struct *vma,
2029                      unsigned long addr, unsigned long pfn, unsigned long size,
2030                      struct io_mapping *iomap);
2031 int remap_io_sg(struct vm_area_struct *vma,
2032                 unsigned long addr, unsigned long size,
2033                 struct scatterlist *sgl, resource_size_t iobase);
2034
2035 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2036 {
2037         if (INTEL_GEN(i915) >= 10)
2038                 return CNL_HWS_CSB_WRITE_INDEX;
2039         else
2040                 return I915_HWS_CSB_WRITE_INDEX;
2041 }
2042
2043 static inline enum i915_map_type
2044 i915_coherent_map_type(struct drm_i915_private *i915)
2045 {
2046         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2047 }
2048
2049 static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc)
2050 {
2051         return intel_guc_is_submission_supported(guc) &&
2052                 intel_guc_is_running(guc);
2053 }
2054
2055 #endif