1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/perf_event.h>
44 #include <linux/pm_qos.h>
45 #include <linux/reservation.h>
46 #include <linux/shmem_fs.h>
49 #include <drm/intel-gtt.h>
50 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
51 #include <drm/drm_gem.h>
52 #include <drm/drm_auth.h>
53 #include <drm/drm_cache.h>
55 #include "i915_params.h"
57 #include "i915_utils.h"
59 #include "intel_bios.h"
60 #include "intel_device_info.h"
61 #include "intel_display.h"
62 #include "intel_dpll_mgr.h"
63 #include "intel_lrc.h"
64 #include "intel_opregion.h"
65 #include "intel_ringbuffer.h"
66 #include "intel_uncore.h"
70 #include "i915_gem_context.h"
71 #include "i915_gem_fence_reg.h"
72 #include "i915_gem_object.h"
73 #include "i915_gem_gtt.h"
74 #include "i915_gem_request.h"
75 #include "i915_gem_timeline.h"
79 #include "intel_gvt.h"
81 /* General customization:
84 #define DRIVER_NAME "i915"
85 #define DRIVER_DESC "Intel Graphics"
86 #define DRIVER_DATE "20180207"
87 #define DRIVER_TIMESTAMP 1517988364
89 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
90 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
91 * which may not necessarily be a user visible problem. This will either
92 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
93 * enable distros and users to tailor their preferred amount of i915 abrt
96 #define I915_STATE_WARN(condition, format...) ({ \
97 int __ret_warn_on = !!(condition); \
98 if (unlikely(__ret_warn_on)) \
99 if (!WARN(i915_modparams.verbose_state_checks, format)) \
101 unlikely(__ret_warn_on); \
104 #define I915_STATE_WARN_ON(x) \
105 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
107 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
108 bool __i915_inject_load_failure(const char *func, int line);
109 #define i915_inject_load_failure() \
110 __i915_inject_load_failure(__func__, __LINE__)
112 #define i915_inject_load_failure() false
117 } uint_fixed_16_16_t;
119 #define FP_16_16_MAX ({ \
120 uint_fixed_16_16_t fp; \
125 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
132 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
134 uint_fixed_16_16_t fp;
136 WARN_ON(val > U16_MAX);
142 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
144 return DIV_ROUND_UP(fp.val, 1 << 16);
147 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
152 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
153 uint_fixed_16_16_t min2)
155 uint_fixed_16_16_t min;
157 min.val = min(min1.val, min2.val);
161 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
162 uint_fixed_16_16_t max2)
164 uint_fixed_16_16_t max;
166 max.val = max(max1.val, max2.val);
170 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
172 uint_fixed_16_16_t fp;
173 WARN_ON(val > U32_MAX);
174 fp.val = (uint32_t) val;
178 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
179 uint_fixed_16_16_t d)
181 return DIV_ROUND_UP(val.val, d.val);
184 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
185 uint_fixed_16_16_t mul)
187 uint64_t intermediate_val;
189 intermediate_val = (uint64_t) val * mul.val;
190 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
191 WARN_ON(intermediate_val > U32_MAX);
192 return (uint32_t) intermediate_val;
195 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
196 uint_fixed_16_16_t mul)
198 uint64_t intermediate_val;
200 intermediate_val = (uint64_t) val.val * mul.val;
201 intermediate_val = intermediate_val >> 16;
202 return clamp_u64_to_fixed16(intermediate_val);
205 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
209 interm_val = (uint64_t)val << 16;
210 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
211 return clamp_u64_to_fixed16(interm_val);
214 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
215 uint_fixed_16_16_t d)
219 interm_val = (uint64_t)val << 16;
220 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
221 WARN_ON(interm_val > U32_MAX);
222 return (uint32_t) interm_val;
225 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
226 uint_fixed_16_16_t mul)
228 uint64_t intermediate_val;
230 intermediate_val = (uint64_t) val * mul.val;
231 return clamp_u64_to_fixed16(intermediate_val);
234 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
235 uint_fixed_16_16_t add2)
239 interm_sum = (uint64_t) add1.val + add2.val;
240 return clamp_u64_to_fixed16(interm_sum);
243 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
247 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
249 interm_sum = (uint64_t) add1.val + interm_add2.val;
250 return clamp_u64_to_fixed16(interm_sum);
255 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
267 #define for_each_hpd_pin(__pin) \
268 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
270 #define HPD_STORM_DEFAULT_THRESHOLD 5
272 struct i915_hotplug {
273 struct work_struct hotplug_work;
276 unsigned long last_jiffies;
281 HPD_MARK_DISABLED = 2
283 } stats[HPD_NUM_PINS];
285 struct delayed_work reenable_work;
287 struct intel_digital_port *irq_port[I915_MAX_PORTS];
290 struct work_struct dig_port_work;
292 struct work_struct poll_init_work;
295 unsigned int hpd_storm_threshold;
298 * if we get a HPD irq from DP and a HPD irq from non-DP
299 * the non-DP HPD could block the workqueue on a mode config
300 * mutex getting, that userspace may have taken. However
301 * userspace is waiting on the DP workqueue to run which is
302 * blocked behind the non-DP one.
304 struct workqueue_struct *dp_wq;
307 #define I915_GEM_GPU_DOMAINS \
308 (I915_GEM_DOMAIN_RENDER | \
309 I915_GEM_DOMAIN_SAMPLER | \
310 I915_GEM_DOMAIN_COMMAND | \
311 I915_GEM_DOMAIN_INSTRUCTION | \
312 I915_GEM_DOMAIN_VERTEX)
314 struct drm_i915_private;
315 struct i915_mm_struct;
316 struct i915_mmu_object;
318 struct drm_i915_file_private {
319 struct drm_i915_private *dev_priv;
320 struct drm_file *file;
324 struct list_head request_list;
325 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
326 * chosen to prevent the CPU getting more than a frame ahead of the GPU
327 * (when using lax throttling for the frontbuffer). We also use it to
328 * offer free GPU waitboosts for severely congested workloads.
330 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
332 struct idr context_idr;
334 struct intel_rps_client {
338 unsigned int bsd_engine;
340 /* Client can have a maximum of 3 contexts banned before
341 * it is denied of creating new contexts. As one context
342 * ban needs 4 consecutive hangs, and more if there is
343 * progress in between, this is a last resort stop gap measure
344 * to limit the badly behaving clients access to gpu.
346 #define I915_MAX_CLIENT_CONTEXT_BANS 3
347 atomic_t context_bans;
350 /* Interface history:
353 * 1.2: Add Power Management
354 * 1.3: Add vblank support
355 * 1.4: Fix cmdbuffer path, add heap destroy
356 * 1.5: Add vblank pipe configuration
357 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
358 * - Support vertical blank on secondary display pipe
360 #define DRIVER_MAJOR 1
361 #define DRIVER_MINOR 6
362 #define DRIVER_PATCHLEVEL 0
364 struct intel_overlay;
365 struct intel_overlay_error_state;
367 struct sdvo_device_mapping {
376 struct intel_connector;
377 struct intel_encoder;
378 struct intel_atomic_state;
379 struct intel_crtc_state;
380 struct intel_initial_plane_config;
384 struct intel_cdclk_state;
386 struct drm_i915_display_funcs {
387 void (*get_cdclk)(struct drm_i915_private *dev_priv,
388 struct intel_cdclk_state *cdclk_state);
389 void (*set_cdclk)(struct drm_i915_private *dev_priv,
390 const struct intel_cdclk_state *cdclk_state);
391 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
392 enum i9xx_plane_id i9xx_plane);
393 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
394 int (*compute_intermediate_wm)(struct drm_device *dev,
395 struct intel_crtc *intel_crtc,
396 struct intel_crtc_state *newstate);
397 void (*initial_watermarks)(struct intel_atomic_state *state,
398 struct intel_crtc_state *cstate);
399 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
400 struct intel_crtc_state *cstate);
401 void (*optimize_watermarks)(struct intel_atomic_state *state,
402 struct intel_crtc_state *cstate);
403 int (*compute_global_watermarks)(struct drm_atomic_state *state);
404 void (*update_wm)(struct intel_crtc *crtc);
405 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
406 /* Returns the active state of the crtc, and if the crtc is active,
407 * fills out the pipe-config with the hw state. */
408 bool (*get_pipe_config)(struct intel_crtc *,
409 struct intel_crtc_state *);
410 void (*get_initial_plane_config)(struct intel_crtc *,
411 struct intel_initial_plane_config *);
412 int (*crtc_compute_clock)(struct intel_crtc *crtc,
413 struct intel_crtc_state *crtc_state);
414 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
415 struct drm_atomic_state *old_state);
416 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
417 struct drm_atomic_state *old_state);
418 void (*update_crtcs)(struct drm_atomic_state *state);
419 void (*audio_codec_enable)(struct intel_encoder *encoder,
420 const struct intel_crtc_state *crtc_state,
421 const struct drm_connector_state *conn_state);
422 void (*audio_codec_disable)(struct intel_encoder *encoder,
423 const struct intel_crtc_state *old_crtc_state,
424 const struct drm_connector_state *old_conn_state);
425 void (*fdi_link_train)(struct intel_crtc *crtc,
426 const struct intel_crtc_state *crtc_state);
427 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
428 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
429 /* clock updates for mode set */
431 /* render clock increase/decrease */
432 /* display clock increase/decrease */
433 /* pll clock increase/decrease */
435 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
436 void (*load_luts)(struct drm_crtc_state *crtc_state);
439 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
440 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
441 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
444 struct work_struct work;
446 uint32_t *dmc_payload;
447 uint32_t dmc_fw_size;
450 i915_reg_t mmioaddr[8];
451 uint32_t mmiodata[8];
453 uint32_t allowed_dc_mask;
456 struct intel_display_error_state;
458 struct i915_gpu_state {
464 struct drm_i915_private *i915;
474 struct intel_device_info device_info;
475 struct intel_driver_caps driver_caps;
476 struct i915_params params;
478 struct i915_error_uc {
479 struct intel_uc_fw guc_fw;
480 struct intel_uc_fw huc_fw;
481 struct drm_i915_error_object *guc_log;
484 /* Generic register state */
488 u32 gtier[4], ngtier;
492 u32 error; /* gen6+ */
493 u32 err_int; /* gen7 */
494 u32 fault_data0; /* gen8, gen9 */
495 u32 fault_data1; /* gen8, gen9 */
503 u64 fence[I915_MAX_NUM_FENCES];
504 struct intel_overlay_error_state *overlay;
505 struct intel_display_error_state *display;
507 struct drm_i915_error_engine {
509 /* Software tracked state */
513 unsigned long hangcheck_timestamp;
514 bool hangcheck_stalled;
515 enum intel_engine_hangcheck_action hangcheck_action;
516 struct i915_address_space *vm;
520 /* position of active request inside the ring */
521 u32 rq_head, rq_post, rq_tail;
523 /* our own tracking of ring head and tail */
546 u32 rc_psmi; /* sleep state */
547 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
548 struct intel_instdone instdone;
550 struct drm_i915_error_context {
551 char comm[TASK_COMM_LEN];
562 struct drm_i915_error_object {
568 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
570 struct drm_i915_error_object **user_bo;
573 struct drm_i915_error_object *wa_ctx;
574 struct drm_i915_error_object *default_state;
576 struct drm_i915_error_request {
585 } *requests, execlist[EXECLIST_MAX_PORTS];
586 unsigned int num_ports;
588 struct drm_i915_error_waiter {
589 char comm[TASK_COMM_LEN];
601 } engine[I915_NUM_ENGINES];
603 struct drm_i915_error_buffer {
606 u32 rseqno[I915_NUM_ENGINES], wseqno;
610 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
617 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
618 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
619 struct i915_address_space *active_vm[I915_NUM_ENGINES];
622 enum i915_cache_level {
624 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
625 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
626 caches, eg sampler/render caches, and the
627 large Last-Level-Cache. LLC is coherent with
628 the CPU, but L3 is only visible to the GPU. */
629 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
632 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
643 /* This is always the inner lock when overlapping with struct_mutex and
644 * it's the outer lock when overlapping with stolen_lock. */
647 unsigned int possible_framebuffer_bits;
648 unsigned int busy_bits;
649 unsigned int visible_pipes_mask;
650 struct intel_crtc *crtc;
652 struct drm_mm_node compressed_fb;
653 struct drm_mm_node *compressed_llb;
660 bool underrun_detected;
661 struct work_struct underrun_work;
664 * Due to the atomic rules we can't access some structures without the
665 * appropriate locking, so we cache information here in order to avoid
668 struct intel_fbc_state_cache {
669 struct i915_vma *vma;
672 unsigned int mode_flags;
673 uint32_t hsw_bdw_pixel_rate;
677 unsigned int rotation;
682 * Display surface base address adjustement for
683 * pageflips. Note that on gen4+ this only adjusts up
684 * to a tile, offsets within a tile are handled in
685 * the hw itself (with the TILEOFF register).
694 const struct drm_format_info *format;
700 * This structure contains everything that's relevant to program the
701 * hardware registers. When we want to figure out if we need to disable
702 * and re-enable FBC for a new configuration we just check if there's
703 * something different in the struct. The genx_fbc_activate functions
704 * are supposed to read from it in order to program the registers.
706 struct intel_fbc_reg_params {
707 struct i915_vma *vma;
711 enum i9xx_plane_id i9xx_plane;
712 unsigned int fence_y_offset;
716 const struct drm_format_info *format;
721 unsigned int gen9_wa_cfb_stride;
724 struct intel_fbc_work {
726 u32 scheduled_vblank;
727 struct work_struct work;
730 const char *no_fbc_reason;
734 * HIGH_RR is the highest eDP panel refresh rate read from EDID
735 * LOW_RR is the lowest eDP panel refresh rate found from EDID
736 * parsing for same resolution.
738 enum drrs_refresh_rate_type {
741 DRRS_MAX_RR, /* RR count */
744 enum drrs_support_type {
745 DRRS_NOT_SUPPORTED = 0,
746 STATIC_DRRS_SUPPORT = 1,
747 SEAMLESS_DRRS_SUPPORT = 2
753 struct delayed_work work;
755 unsigned busy_frontbuffer_bits;
756 enum drrs_refresh_rate_type refresh_rate_type;
757 enum drrs_support_type type;
763 struct intel_dp *enabled;
765 struct delayed_work work;
766 unsigned busy_frontbuffer_bits;
771 bool colorimetry_support;
774 void (*enable_source)(struct intel_dp *,
775 const struct intel_crtc_state *);
776 void (*disable_source)(struct intel_dp *,
777 const struct intel_crtc_state *);
778 void (*enable_sink)(struct intel_dp *);
779 void (*activate)(struct intel_dp *);
780 void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
784 PCH_NONE = 0, /* No PCH present */
785 PCH_IBX, /* Ibexpeak PCH */
786 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
787 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
788 PCH_SPT, /* Sunrisepoint PCH */
789 PCH_KBP, /* Kaby Lake PCH */
790 PCH_CNP, /* Cannon Lake PCH */
791 PCH_ICP, /* Ice Lake PCH */
795 enum intel_sbi_destination {
800 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
801 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
802 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
803 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
804 #define QUIRK_INCREASE_T12_DELAY (1<<6)
807 struct intel_fbc_work;
810 struct i2c_adapter adapter;
811 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
815 struct i2c_algo_bit_data bit_algo;
816 struct drm_i915_private *dev_priv;
819 struct i915_suspend_saved_registers {
822 u32 saveCACHE_MODE_0;
823 u32 saveMI_ARB_STATE;
827 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
828 u32 savePCH_PORT_HOTPLUG;
832 struct vlv_s0ix_state {
839 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
840 u32 media_max_req_count;
841 u32 gfx_max_req_count;
873 /* Display 1 CZ domain */
878 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
880 /* GT SA CZ domain */
887 /* Display 2 CZ domain */
894 struct intel_rps_ei {
902 * work, interrupts_enabled and pm_iir are protected by
905 struct work_struct work;
906 bool interrupts_enabled;
909 /* PM interrupt bits that should never be masked */
912 /* Frequencies are stored in potentially platform dependent multiples.
913 * In other words, *_freq needs to be multiplied by X to be interesting.
914 * Soft limits are those which are used for the dynamic reclocking done
915 * by the driver (raise frequencies under heavy loads, and lower for
916 * lighter loads). Hard limits are those imposed by the hardware.
918 * A distinction is made for overclocking, which is never enabled by
919 * default, and is considered to be above the hard limit if it's
922 u8 cur_freq; /* Current frequency (cached, may not == HW) */
923 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
924 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
925 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
926 u8 min_freq; /* AKA RPn. Minimum frequency */
927 u8 boost_freq; /* Frequency to request when wait boosting */
928 u8 idle_freq; /* Frequency to request when we are idle */
929 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
930 u8 rp1_freq; /* "less than" RP0 power/freqency */
931 u8 rp0_freq; /* Non-overclocked max frequency. */
932 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
934 u8 up_threshold; /* Current %busy required to uplock */
935 u8 down_threshold; /* Current %busy required to downclock */
938 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
941 atomic_t num_waiters;
944 /* manual wa residency calculations */
945 struct intel_rps_ei ei;
952 struct intel_llc_pstate {
956 struct intel_gen6_power_mgmt {
957 struct intel_rps rps;
958 struct intel_rc6 rc6;
959 struct intel_llc_pstate llc_pstate;
962 /* defined intel_pm.c */
963 extern spinlock_t mchdev_lock;
965 struct intel_ilk_power_mgmt {
973 unsigned long last_time1;
974 unsigned long chipset_power;
977 unsigned long gfx_power;
984 struct drm_i915_private;
985 struct i915_power_well;
987 struct i915_power_well_ops {
989 * Synchronize the well's hw state to match the current sw state, for
990 * example enable/disable it based on the current refcount. Called
991 * during driver init and resume time, possibly after first calling
992 * the enable/disable handlers.
994 void (*sync_hw)(struct drm_i915_private *dev_priv,
995 struct i915_power_well *power_well);
997 * Enable the well and resources that depend on it (for example
998 * interrupts located on the well). Called after the 0->1 refcount
1001 void (*enable)(struct drm_i915_private *dev_priv,
1002 struct i915_power_well *power_well);
1004 * Disable the well and resources that depend on it. Called after
1005 * the 1->0 refcount transition.
1007 void (*disable)(struct drm_i915_private *dev_priv,
1008 struct i915_power_well *power_well);
1009 /* Returns the hw enabled state. */
1010 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1011 struct i915_power_well *power_well);
1014 /* Power well structure for haswell */
1015 struct i915_power_well {
1018 /* power well enable/disable usage count */
1020 /* cached hw enabled state */
1023 /* unique identifier for this power well */
1024 enum i915_power_well_id id;
1026 * Arbitraty data associated with this power well. Platform and power
1034 /* Mask of pipes whose IRQ logic is backed by the pw */
1036 /* The pw is backing the VGA functionality */
1041 const struct i915_power_well_ops *ops;
1044 struct i915_power_domains {
1046 * Power wells needed for initialization at driver init and suspend
1047 * time are on. They are kept on until after the first modeset.
1051 int power_well_count;
1054 int domain_use_count[POWER_DOMAIN_NUM];
1055 struct i915_power_well *power_wells;
1058 #define MAX_L3_SLICES 2
1059 struct intel_l3_parity {
1060 u32 *remap_info[MAX_L3_SLICES];
1061 struct work_struct error_work;
1065 struct i915_gem_mm {
1066 /** Memory allocator for GTT stolen memory */
1067 struct drm_mm stolen;
1068 /** Protects the usage of the GTT stolen memory allocator. This is
1069 * always the inner lock when overlapping with struct_mutex. */
1070 struct mutex stolen_lock;
1072 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
1073 spinlock_t obj_lock;
1075 /** List of all objects in gtt_space. Used to restore gtt
1076 * mappings on resume */
1077 struct list_head bound_list;
1079 * List of objects which are not bound to the GTT (thus
1080 * are idle and not used by the GPU). These objects may or may
1081 * not actually have any pages attached.
1083 struct list_head unbound_list;
1085 /** List of all objects in gtt_space, currently mmaped by userspace.
1086 * All objects within this list must also be on bound_list.
1088 struct list_head userfault_list;
1091 * List of objects which are pending destruction.
1093 struct llist_head free_list;
1094 struct work_struct free_work;
1095 spinlock_t free_lock;
1098 * Small stash of WC pages
1100 struct pagevec wc_stash;
1103 * tmpfs instance used for shmem backed objects
1105 struct vfsmount *gemfs;
1107 /** PPGTT used for aliasing the PPGTT with the GTT */
1108 struct i915_hw_ppgtt *aliasing_ppgtt;
1110 struct notifier_block oom_notifier;
1111 struct notifier_block vmap_notifier;
1112 struct shrinker shrinker;
1114 /** LRU list of objects with fence regs on them. */
1115 struct list_head fence_list;
1118 * Workqueue to fault in userptr pages, flushed by the execbuf
1119 * when required but otherwise left to userspace to try again
1122 struct workqueue_struct *userptr_wq;
1124 u64 unordered_timeline;
1126 /* the indicator for dispatch video commands on two BSD rings */
1127 atomic_t bsd_engine_dispatch_index;
1129 /** Bit 6 swizzling required for X tiling */
1130 uint32_t bit_6_swizzle_x;
1131 /** Bit 6 swizzling required for Y tiling */
1132 uint32_t bit_6_swizzle_y;
1134 /* accounting, useful for userland debugging */
1135 spinlock_t object_stat_lock;
1140 struct drm_i915_error_state_buf {
1141 struct drm_i915_private *i915;
1150 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1152 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1153 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1155 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1156 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1158 struct i915_gpu_error {
1159 /* For hangcheck timer */
1160 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1161 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1163 struct delayed_work hangcheck_work;
1165 /* For reset and error_state handling. */
1167 /* Protected by the above dev->gpu_error.lock. */
1168 struct i915_gpu_state *first_error;
1170 atomic_t pending_fb_pin;
1172 unsigned long missed_irq_rings;
1175 * State variable controlling the reset flow and count
1177 * This is a counter which gets incremented when reset is triggered,
1179 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1180 * meaning that any waiters holding onto the struct_mutex should
1181 * relinquish the lock immediately in order for the reset to start.
1183 * If reset is not completed succesfully, the I915_WEDGE bit is
1184 * set meaning that hardware is terminally sour and there is no
1185 * recovery. All waiters on the reset_queue will be woken when
1188 * This counter is used by the wait_seqno code to notice that reset
1189 * event happened and it needs to restart the entire ioctl (since most
1190 * likely the seqno it waited for won't ever signal anytime soon).
1192 * This is important for lock-free wait paths, where no contended lock
1193 * naturally enforces the correct ordering between the bail-out of the
1194 * waiter and the gpu reset work code.
1196 unsigned long reset_count;
1199 * flags: Control various stages of the GPU reset
1201 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1202 * other users acquiring the struct_mutex. To do this we set the
1203 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1204 * and then check for that bit before acquiring the struct_mutex (in
1205 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1206 * secondary role in preventing two concurrent global reset attempts.
1208 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1209 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1210 * but it may be held by some long running waiter (that we cannot
1211 * interrupt without causing trouble). Once we are ready to do the GPU
1212 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1213 * they already hold the struct_mutex and want to participate they can
1214 * inspect the bit and do the reset directly, otherwise the worker
1215 * waits for the struct_mutex.
1217 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1218 * acquire the struct_mutex to reset an engine, we need an explicit
1219 * flag to prevent two concurrent reset attempts in the same engine.
1220 * As the number of engines continues to grow, allocate the flags from
1221 * the most significant bits.
1223 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1224 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1225 * i915_gem_request_alloc(), this bit is checked and the sequence
1226 * aborted (with -EIO reported to userspace) if set.
1228 unsigned long flags;
1229 #define I915_RESET_BACKOFF 0
1230 #define I915_RESET_HANDOFF 1
1231 #define I915_RESET_MODESET 2
1232 #define I915_WEDGED (BITS_PER_LONG - 1)
1233 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1235 /** Number of times an engine has been reset */
1236 u32 reset_engine_count[I915_NUM_ENGINES];
1239 * Waitqueue to signal when a hang is detected. Used to for waiters
1240 * to release the struct_mutex for the reset to procede.
1242 wait_queue_head_t wait_queue;
1245 * Waitqueue to signal when the reset has completed. Used by clients
1246 * that wait for dev_priv->mm.wedged to settle.
1248 wait_queue_head_t reset_queue;
1250 /* For missed irq/seqno simulation. */
1251 unsigned long test_irq_rings;
1254 enum modeset_restore {
1255 MODESET_ON_LID_OPEN,
1260 #define DP_AUX_A 0x40
1261 #define DP_AUX_B 0x10
1262 #define DP_AUX_C 0x20
1263 #define DP_AUX_D 0x30
1264 #define DP_AUX_F 0x60
1266 #define DDC_PIN_B 0x05
1267 #define DDC_PIN_C 0x04
1268 #define DDC_PIN_D 0x06
1270 struct ddi_vbt_port_info {
1274 * This is an index in the HDMI/DVI DDI buffer translation table.
1275 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1276 * populate this field.
1278 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1279 uint8_t hdmi_level_shift;
1281 uint8_t supports_dvi:1;
1282 uint8_t supports_hdmi:1;
1283 uint8_t supports_dp:1;
1284 uint8_t supports_edp:1;
1286 uint8_t alternate_aux_channel;
1287 uint8_t alternate_ddc_pin;
1289 uint8_t dp_boost_level;
1290 uint8_t hdmi_boost_level;
1291 int dp_max_link_rate; /* 0 for not limited by VBT */
1294 enum psr_lines_to_wait {
1295 PSR_0_LINES_TO_WAIT = 0,
1297 PSR_4_LINES_TO_WAIT,
1301 struct intel_vbt_data {
1302 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1303 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1306 unsigned int int_tv_support:1;
1307 unsigned int lvds_dither:1;
1308 unsigned int lvds_vbt:1;
1309 unsigned int int_crt_support:1;
1310 unsigned int lvds_use_ssc:1;
1311 unsigned int display_clock_mode:1;
1312 unsigned int fdi_rx_polarity_inverted:1;
1313 unsigned int panel_type:4;
1315 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1317 enum drrs_support_type drrs_type;
1328 struct edp_power_seq pps;
1333 bool require_aux_wakeup;
1335 enum psr_lines_to_wait lines_to_wait;
1336 int tp1_wakeup_time;
1337 int tp2_tp3_wakeup_time;
1343 bool active_low_pwm;
1344 u8 min_brightness; /* min_brightness/255 of max */
1345 u8 controller; /* brightness controller number */
1346 enum intel_backlight_type type;
1352 struct mipi_config *config;
1353 struct mipi_pps_data *pps;
1359 const u8 *sequence[MIPI_SEQ_MAX];
1365 struct child_device_config *child_dev;
1367 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1368 struct sdvo_device_mapping sdvo_mappings[2];
1371 enum intel_ddb_partitioning {
1373 INTEL_DDB_PART_5_6, /* IVB+ */
1376 struct intel_wm_level {
1384 struct ilk_wm_values {
1385 uint32_t wm_pipe[3];
1387 uint32_t wm_lp_spr[3];
1388 uint32_t wm_linetime[3];
1390 enum intel_ddb_partitioning partitioning;
1393 struct g4x_pipe_wm {
1394 uint16_t plane[I915_MAX_PLANES];
1404 struct vlv_wm_ddl_values {
1405 uint8_t plane[I915_MAX_PLANES];
1408 struct vlv_wm_values {
1409 struct g4x_pipe_wm pipe[3];
1410 struct g4x_sr_wm sr;
1411 struct vlv_wm_ddl_values ddl[3];
1416 struct g4x_wm_values {
1417 struct g4x_pipe_wm pipe[2];
1418 struct g4x_sr_wm sr;
1419 struct g4x_sr_wm hpll;
1425 struct skl_ddb_entry {
1426 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1429 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1431 return entry->end - entry->start;
1434 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1435 const struct skl_ddb_entry *e2)
1437 if (e1->start == e2->start && e1->end == e2->end)
1443 struct skl_ddb_allocation {
1444 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1445 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1448 struct skl_wm_values {
1449 unsigned dirty_pipes;
1450 struct skl_ddb_allocation ddb;
1453 struct skl_wm_level {
1455 uint16_t plane_res_b;
1456 uint8_t plane_res_l;
1459 /* Stores plane specific WM parameters */
1460 struct skl_wm_params {
1461 bool x_tiled, y_tiled;
1465 uint32_t plane_pixel_rate;
1466 uint32_t y_min_scanlines;
1467 uint32_t plane_bytes_per_line;
1468 uint_fixed_16_16_t plane_blocks_per_line;
1469 uint_fixed_16_16_t y_tile_minimum;
1470 uint32_t linetime_us;
1471 uint32_t dbuf_block_size;
1475 * This struct helps tracking the state needed for runtime PM, which puts the
1476 * device in PCI D3 state. Notice that when this happens, nothing on the
1477 * graphics device works, even register access, so we don't get interrupts nor
1480 * Every piece of our code that needs to actually touch the hardware needs to
1481 * either call intel_runtime_pm_get or call intel_display_power_get with the
1482 * appropriate power domain.
1484 * Our driver uses the autosuspend delay feature, which means we'll only really
1485 * suspend if we stay with zero refcount for a certain amount of time. The
1486 * default value is currently very conservative (see intel_runtime_pm_enable), but
1487 * it can be changed with the standard runtime PM files from sysfs.
1489 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1490 * goes back to false exactly before we reenable the IRQs. We use this variable
1491 * to check if someone is trying to enable/disable IRQs while they're supposed
1492 * to be disabled. This shouldn't happen and we'll print some error messages in
1495 * For more, read the Documentation/power/runtime_pm.txt.
1497 struct i915_runtime_pm {
1498 atomic_t wakeref_count;
1503 enum intel_pipe_crc_source {
1504 INTEL_PIPE_CRC_SOURCE_NONE,
1505 INTEL_PIPE_CRC_SOURCE_PLANE1,
1506 INTEL_PIPE_CRC_SOURCE_PLANE2,
1507 INTEL_PIPE_CRC_SOURCE_PF,
1508 INTEL_PIPE_CRC_SOURCE_PIPE,
1509 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1510 INTEL_PIPE_CRC_SOURCE_TV,
1511 INTEL_PIPE_CRC_SOURCE_DP_B,
1512 INTEL_PIPE_CRC_SOURCE_DP_C,
1513 INTEL_PIPE_CRC_SOURCE_DP_D,
1514 INTEL_PIPE_CRC_SOURCE_AUTO,
1515 INTEL_PIPE_CRC_SOURCE_MAX,
1518 struct intel_pipe_crc_entry {
1523 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1524 struct intel_pipe_crc {
1526 bool opened; /* exclusive access to the result file */
1527 struct intel_pipe_crc_entry *entries;
1528 enum intel_pipe_crc_source source;
1530 wait_queue_head_t wq;
1534 struct i915_frontbuffer_tracking {
1538 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1545 struct i915_wa_reg {
1548 /* bitmask representing WA bits */
1552 #define I915_MAX_WA_REGS 16
1554 struct i915_workarounds {
1555 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1557 u32 hw_whitelist_count[I915_NUM_ENGINES];
1560 struct i915_virtual_gpu {
1565 /* used in computing the new watermarks state */
1566 struct intel_wm_config {
1567 unsigned int num_pipes_active;
1568 bool sprites_enabled;
1569 bool sprites_scaled;
1572 struct i915_oa_format {
1577 struct i915_oa_reg {
1582 struct i915_oa_config {
1583 char uuid[UUID_STRING_LEN + 1];
1586 const struct i915_oa_reg *mux_regs;
1588 const struct i915_oa_reg *b_counter_regs;
1589 u32 b_counter_regs_len;
1590 const struct i915_oa_reg *flex_regs;
1593 struct attribute_group sysfs_metric;
1594 struct attribute *attrs[2];
1595 struct device_attribute sysfs_metric_id;
1600 struct i915_perf_stream;
1603 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1605 struct i915_perf_stream_ops {
1607 * @enable: Enables the collection of HW samples, either in response to
1608 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1609 * without `I915_PERF_FLAG_DISABLED`.
1611 void (*enable)(struct i915_perf_stream *stream);
1614 * @disable: Disables the collection of HW samples, either in response
1615 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1618 void (*disable)(struct i915_perf_stream *stream);
1621 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1622 * once there is something ready to read() for the stream
1624 void (*poll_wait)(struct i915_perf_stream *stream,
1629 * @wait_unlocked: For handling a blocking read, wait until there is
1630 * something to ready to read() for the stream. E.g. wait on the same
1631 * wait queue that would be passed to poll_wait().
1633 int (*wait_unlocked)(struct i915_perf_stream *stream);
1636 * @read: Copy buffered metrics as records to userspace
1637 * **buf**: the userspace, destination buffer
1638 * **count**: the number of bytes to copy, requested by userspace
1639 * **offset**: zero at the start of the read, updated as the read
1640 * proceeds, it represents how many bytes have been copied so far and
1641 * the buffer offset for copying the next record.
1643 * Copy as many buffered i915 perf samples and records for this stream
1644 * to userspace as will fit in the given buffer.
1646 * Only write complete records; returning -%ENOSPC if there isn't room
1647 * for a complete record.
1649 * Return any error condition that results in a short read such as
1650 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1651 * returning to userspace.
1653 int (*read)(struct i915_perf_stream *stream,
1659 * @destroy: Cleanup any stream specific resources.
1661 * The stream will always be disabled before this is called.
1663 void (*destroy)(struct i915_perf_stream *stream);
1667 * struct i915_perf_stream - state for a single open stream FD
1669 struct i915_perf_stream {
1671 * @dev_priv: i915 drm device
1673 struct drm_i915_private *dev_priv;
1676 * @link: Links the stream into ``&drm_i915_private->streams``
1678 struct list_head link;
1681 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1682 * properties given when opening a stream, representing the contents
1683 * of a single sample as read() by userspace.
1688 * @sample_size: Considering the configured contents of a sample
1689 * combined with the required header size, this is the total size
1690 * of a single sample record.
1695 * @ctx: %NULL if measuring system-wide across all contexts or a
1696 * specific context that is being monitored.
1698 struct i915_gem_context *ctx;
1701 * @enabled: Whether the stream is currently enabled, considering
1702 * whether the stream was opened in a disabled state and based
1703 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1708 * @ops: The callbacks providing the implementation of this specific
1709 * type of configured stream.
1711 const struct i915_perf_stream_ops *ops;
1714 * @oa_config: The OA configuration used by the stream.
1716 struct i915_oa_config *oa_config;
1720 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1722 struct i915_oa_ops {
1724 * @is_valid_b_counter_reg: Validates register's address for
1725 * programming boolean counters for a particular platform.
1727 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1731 * @is_valid_mux_reg: Validates register's address for programming mux
1732 * for a particular platform.
1734 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1737 * @is_valid_flex_reg: Validates register's address for programming
1738 * flex EU filtering for a particular platform.
1740 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1743 * @init_oa_buffer: Resets the head and tail pointers of the
1744 * circular buffer for periodic OA reports.
1746 * Called when first opening a stream for OA metrics, but also may be
1747 * called in response to an OA buffer overflow or other error
1750 * Note it may be necessary to clear the full OA buffer here as part of
1751 * maintaining the invariable that new reports must be written to
1752 * zeroed memory for us to be able to reliable detect if an expected
1753 * report has not yet landed in memory. (At least on Haswell the OA
1754 * buffer tail pointer is not synchronized with reports being visible
1757 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1760 * @enable_metric_set: Selects and applies any MUX configuration to set
1761 * up the Boolean and Custom (B/C) counters that are part of the
1762 * counter reports being sampled. May apply system constraints such as
1763 * disabling EU clock gating as required.
1765 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1766 const struct i915_oa_config *oa_config);
1769 * @disable_metric_set: Remove system constraints associated with using
1772 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1775 * @oa_enable: Enable periodic sampling
1777 void (*oa_enable)(struct drm_i915_private *dev_priv);
1780 * @oa_disable: Disable periodic sampling
1782 void (*oa_disable)(struct drm_i915_private *dev_priv);
1785 * @read: Copy data from the circular OA buffer into a given userspace
1788 int (*read)(struct i915_perf_stream *stream,
1794 * @oa_hw_tail_read: read the OA tail pointer register
1796 * In particular this enables us to share all the fiddly code for
1797 * handling the OA unit tail pointer race that affects multiple
1800 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1803 struct intel_cdclk_state {
1804 unsigned int cdclk, vco, ref, bypass;
1808 struct drm_i915_private {
1809 struct drm_device drm;
1811 struct kmem_cache *objects;
1812 struct kmem_cache *vmas;
1813 struct kmem_cache *luts;
1814 struct kmem_cache *requests;
1815 struct kmem_cache *dependencies;
1816 struct kmem_cache *priorities;
1818 const struct intel_device_info info;
1819 struct intel_driver_caps caps;
1822 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1823 * end of stolen which we can optionally use to create GEM objects
1824 * backed by stolen memory. Note that stolen_usable_size tells us
1825 * exactly how much of this we are actually allowed to use, given that
1826 * some portion of it is in fact reserved for use by hardware functions.
1828 struct resource dsm;
1830 * Reseved portion of Data Stolen Memory
1832 struct resource dsm_reserved;
1835 * Stolen memory is segmented in hardware with different portions
1836 * offlimits to certain functions.
1838 * The drm_mm is initialised to the total accessible range, as found
1839 * from the PCI config. On Broadwell+, this is further restricted to
1840 * avoid the first page! The upper end of stolen memory is reserved for
1841 * hardware functions and similarly removed from the accessible range.
1843 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1847 struct intel_uncore uncore;
1849 struct i915_virtual_gpu vgpu;
1851 struct intel_gvt *gvt;
1853 struct intel_huc huc;
1854 struct intel_guc guc;
1856 struct intel_csr csr;
1858 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1860 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1861 * controller on different i2c buses. */
1862 struct mutex gmbus_mutex;
1865 * Base address of the gmbus and gpio block.
1867 uint32_t gpio_mmio_base;
1869 /* MMIO base address for MIPI regs */
1870 uint32_t mipi_mmio_base;
1872 uint32_t psr_mmio_base;
1874 uint32_t pps_mmio_base;
1876 wait_queue_head_t gmbus_wait_queue;
1878 struct pci_dev *bridge_dev;
1879 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1880 /* Context used internally to idle the GPU and setup initial state */
1881 struct i915_gem_context *kernel_context;
1882 /* Context only to be used for injecting preemption commands */
1883 struct i915_gem_context *preempt_context;
1884 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1885 [MAX_ENGINE_INSTANCE + 1];
1887 struct drm_dma_handle *status_page_dmah;
1888 struct resource mch_res;
1890 /* protects the irq masks */
1891 spinlock_t irq_lock;
1893 bool display_irqs_enabled;
1895 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1896 struct pm_qos_request pm_qos;
1898 /* Sideband mailbox protection */
1899 struct mutex sb_lock;
1901 /** Cached value of IMR to avoid reads in updating the bitfield */
1904 u32 de_irq_mask[I915_MAX_PIPES];
1911 u32 pipestat_irq_mask[I915_MAX_PIPES];
1913 struct i915_hotplug hotplug;
1914 struct intel_fbc fbc;
1915 struct i915_drrs drrs;
1916 struct intel_opregion opregion;
1917 struct intel_vbt_data vbt;
1919 bool preserve_bios_swizzle;
1922 struct intel_overlay *overlay;
1924 /* backlight registers and fields in struct intel_panel */
1925 struct mutex backlight_lock;
1928 bool no_aux_handshake;
1930 /* protects panel power sequencer state */
1931 struct mutex pps_mutex;
1933 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1934 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1936 unsigned int fsb_freq, mem_freq, is_ddr3;
1937 unsigned int skl_preferred_vco_freq;
1938 unsigned int max_cdclk_freq;
1940 unsigned int max_dotclk_freq;
1941 unsigned int rawclk_freq;
1942 unsigned int hpll_freq;
1943 unsigned int fdi_pll_freq;
1944 unsigned int czclk_freq;
1948 * The current logical cdclk state.
1949 * See intel_atomic_state.cdclk.logical
1951 * For reading holding any crtc lock is sufficient,
1952 * for writing must hold all of them.
1954 struct intel_cdclk_state logical;
1956 * The current actual cdclk state.
1957 * See intel_atomic_state.cdclk.actual
1959 struct intel_cdclk_state actual;
1960 /* The current hardware cdclk state */
1961 struct intel_cdclk_state hw;
1965 * wq - Driver workqueue for GEM.
1967 * NOTE: Work items scheduled here are not allowed to grab any modeset
1968 * locks, for otherwise the flushing done in the pageflip code will
1969 * result in deadlocks.
1971 struct workqueue_struct *wq;
1973 /* ordered wq for modesets */
1974 struct workqueue_struct *modeset_wq;
1976 /* Display functions */
1977 struct drm_i915_display_funcs display;
1979 /* PCH chipset type */
1980 enum intel_pch pch_type;
1981 unsigned short pch_id;
1983 unsigned long quirks;
1985 enum modeset_restore modeset_restore;
1986 struct mutex modeset_restore_lock;
1987 struct drm_atomic_state *modeset_restore_state;
1988 struct drm_modeset_acquire_ctx reset_ctx;
1990 struct list_head vm_list; /* Global list of all address spaces */
1991 struct i915_ggtt ggtt; /* VM representing the global address space */
1993 struct i915_gem_mm mm;
1994 DECLARE_HASHTABLE(mm_structs, 7);
1995 struct mutex mm_lock;
1997 struct intel_ppat ppat;
1999 /* Kernel Modesetting */
2001 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
2002 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2004 #ifdef CONFIG_DEBUG_FS
2005 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
2008 /* dpll and cdclk state is protected by connection_mutex */
2009 int num_shared_dpll;
2010 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2011 const struct intel_dpll_mgr *dpll_mgr;
2014 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2015 * Must be global rather than per dpll, because on some platforms
2016 * plls share registers.
2018 struct mutex dpll_lock;
2020 unsigned int active_crtcs;
2021 /* minimum acceptable cdclk for each pipe */
2022 int min_cdclk[I915_MAX_PIPES];
2023 /* minimum acceptable voltage level for each pipe */
2024 u8 min_voltage_level[I915_MAX_PIPES];
2026 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2028 struct i915_workarounds workarounds;
2030 struct i915_frontbuffer_tracking fb_tracking;
2032 struct intel_atomic_helper {
2033 struct llist_head free_list;
2034 struct work_struct free_work;
2039 bool mchbar_need_disable;
2041 struct intel_l3_parity l3_parity;
2043 /* Cannot be determined by PCIID. You must always read a register. */
2047 * Protects RPS/RC6 register access and PCU communication.
2048 * Must be taken after struct_mutex if nested. Note that
2049 * this lock may be held for long periods of time when
2050 * talking to hw - so only take it when talking to hw!
2052 struct mutex pcu_lock;
2054 /* gen6+ GT PM state */
2055 struct intel_gen6_power_mgmt gt_pm;
2057 /* ilk-only ips/rps state. Everything in here is protected by the global
2058 * mchdev_lock in intel_pm.c */
2059 struct intel_ilk_power_mgmt ips;
2061 struct i915_power_domains power_domains;
2063 struct i915_psr psr;
2065 struct i915_gpu_error gpu_error;
2067 struct drm_i915_gem_object *vlv_pctx;
2069 /* list of fbdev register on this device */
2070 struct intel_fbdev *fbdev;
2071 struct work_struct fbdev_suspend_work;
2073 struct drm_property *broadcast_rgb_property;
2074 struct drm_property *force_audio_property;
2076 /* hda/i915 audio component */
2077 struct i915_audio_component *audio_component;
2078 bool audio_component_registered;
2080 * av_mutex - mutex for audio/video sync
2083 struct mutex av_mutex;
2086 struct list_head list;
2087 struct llist_head free_list;
2088 struct work_struct free_work;
2090 /* The hw wants to have a stable context identifier for the
2091 * lifetime of the context (for OA, PASID, faults, etc).
2092 * This is limited in execlists to 21 bits.
2095 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2100 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2101 u32 chv_phy_control;
2103 * Shadows for CHV DPLL_MD regs to keep the state
2104 * checker somewhat working in the presence hardware
2105 * crappiness (can't read out DPLL_MD for pipes B & C).
2107 u32 chv_dpll_md[I915_MAX_PIPES];
2111 bool suspended_to_idle;
2112 struct i915_suspend_saved_registers regfile;
2113 struct vlv_s0ix_state vlv_s0ix_state;
2116 I915_SAGV_UNKNOWN = 0,
2119 I915_SAGV_NOT_CONTROLLED
2124 * Raw watermark latency values:
2125 * in 0.1us units for WM0,
2126 * in 0.5us units for WM1+.
2129 uint16_t pri_latency[5];
2131 uint16_t spr_latency[5];
2133 uint16_t cur_latency[5];
2135 * Raw watermark memory latency values
2136 * for SKL for all 8 levels
2139 uint16_t skl_latency[8];
2141 /* current hardware state */
2143 struct ilk_wm_values hw;
2144 struct skl_wm_values skl_hw;
2145 struct vlv_wm_values vlv;
2146 struct g4x_wm_values g4x;
2152 * Should be held around atomic WM register writing; also
2153 * protects * intel_crtc->wm.active and
2154 * cstate->wm.need_postvbl_update.
2156 struct mutex wm_mutex;
2159 * Set during HW readout of watermarks/DDB. Some platforms
2160 * need to know when we're still using BIOS-provided values
2161 * (which we don't fully trust).
2163 bool distrust_bios_wm;
2166 struct i915_runtime_pm runtime_pm;
2171 struct kobject *metrics_kobj;
2172 struct ctl_table_header *sysctl_header;
2175 * Lock associated with adding/modifying/removing OA configs
2176 * in dev_priv->perf.metrics_idr.
2178 struct mutex metrics_lock;
2181 * List of dynamic configurations, you need to hold
2182 * dev_priv->perf.metrics_lock to access it.
2184 struct idr metrics_idr;
2187 * Lock associated with anything below within this structure
2188 * except exclusive_stream.
2191 struct list_head streams;
2195 * The stream currently using the OA unit. If accessed
2196 * outside a syscall associated to its file
2197 * descriptor, you need to hold
2198 * dev_priv->drm.struct_mutex.
2200 struct i915_perf_stream *exclusive_stream;
2202 u32 specific_ctx_id;
2204 struct hrtimer poll_check_timer;
2205 wait_queue_head_t poll_wq;
2209 * For rate limiting any notifications of spurious
2210 * invalid OA reports
2212 struct ratelimit_state spurious_report_rs;
2215 int period_exponent;
2217 struct i915_oa_config test_config;
2220 struct i915_vma *vma;
2227 * Locks reads and writes to all head/tail state
2229 * Consider: the head and tail pointer state
2230 * needs to be read consistently from a hrtimer
2231 * callback (atomic context) and read() fop
2232 * (user context) with tail pointer updates
2233 * happening in atomic context and head updates
2234 * in user context and the (unlikely)
2235 * possibility of read() errors needing to
2236 * reset all head/tail state.
2238 * Note: Contention or performance aren't
2239 * currently a significant concern here
2240 * considering the relatively low frequency of
2241 * hrtimer callbacks (5ms period) and that
2242 * reads typically only happen in response to a
2243 * hrtimer event and likely complete before the
2246 * Note: This lock is not held *while* reading
2247 * and copying data to userspace so the value
2248 * of head observed in htrimer callbacks won't
2249 * represent any partial consumption of data.
2251 spinlock_t ptr_lock;
2254 * One 'aging' tail pointer and one 'aged'
2255 * tail pointer ready to used for reading.
2257 * Initial values of 0xffffffff are invalid
2258 * and imply that an update is required
2259 * (and should be ignored by an attempted
2267 * Index for the aged tail ready to read()
2270 unsigned int aged_tail_idx;
2273 * A monotonic timestamp for when the current
2274 * aging tail pointer was read; used to
2275 * determine when it is old enough to trust.
2277 u64 aging_timestamp;
2280 * Although we can always read back the head
2281 * pointer register, we prefer to avoid
2282 * trusting the HW state, just to avoid any
2283 * risk that some hardware condition could
2284 * somehow bump the head pointer unpredictably
2285 * and cause us to forward the wrong OA buffer
2286 * data to userspace.
2291 u32 gen7_latched_oastatus1;
2292 u32 ctx_oactxctrl_offset;
2293 u32 ctx_flexeu0_offset;
2296 * The RPT_ID/reason field for Gen8+ includes a bit
2297 * to determine if the CTX ID in the report is valid
2298 * but the specific bit differs between Gen 8 and 9
2300 u32 gen8_valid_ctx_bit;
2302 struct i915_oa_ops ops;
2303 const struct i915_oa_format *oa_formats;
2307 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2309 void (*resume)(struct drm_i915_private *);
2310 void (*cleanup_engine)(struct intel_engine_cs *engine);
2312 struct list_head timelines;
2313 struct i915_gem_timeline global_timeline;
2314 u32 active_requests;
2317 * Is the GPU currently considered idle, or busy executing
2318 * userspace requests? Whilst idle, we allow runtime power
2319 * management to power down the hardware and display clocks.
2320 * In order to reduce the effect on performance, there
2321 * is a slight delay before we do so.
2326 * The number of times we have woken up.
2329 #define I915_EPOCH_INVALID 0
2332 * We leave the user IRQ off as much as possible,
2333 * but this means that requests will finish and never
2334 * be retired once the system goes idle. Set a timer to
2335 * fire periodically while the ring is running. When it
2336 * fires, go retire requests.
2338 struct delayed_work retire_work;
2341 * When we detect an idle GPU, we want to turn on
2342 * powersaving features. So once we see that there
2343 * are no more requests outstanding and no more
2344 * arrive within a small period of time, we fire
2345 * off the idle_work.
2347 struct delayed_work idle_work;
2349 ktime_t last_init_time;
2352 /* perform PHY state sanity checks? */
2353 bool chv_phy_assert[2];
2357 /* Used to save the pipe-to-encoder mapping for audio */
2358 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2360 /* necessary resource sharing with HDMI LPE audio driver. */
2362 struct platform_device *platdev;
2366 struct i915_pmu pmu;
2369 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2370 * will be rejected. Instead look for a better place.
2374 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2376 return container_of(dev, struct drm_i915_private, drm);
2379 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2381 return to_i915(dev_get_drvdata(kdev));
2384 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2386 return container_of(guc, struct drm_i915_private, guc);
2389 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2391 return container_of(huc, struct drm_i915_private, huc);
2394 /* Simple iterator over all initialised engines */
2395 #define for_each_engine(engine__, dev_priv__, id__) \
2397 (id__) < I915_NUM_ENGINES; \
2399 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2401 /* Iterator over subset of engines selected by mask */
2402 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2403 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2404 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2406 enum hdmi_force_audio {
2407 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2408 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2409 HDMI_AUDIO_AUTO, /* trust EDID */
2410 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2413 #define I915_GTT_OFFSET_NONE ((u32)-1)
2416 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2417 * considered to be the frontbuffer for the given plane interface-wise. This
2418 * doesn't mean that the hw necessarily already scans it out, but that any
2419 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2421 * We have one bit per pipe and per scanout plane type.
2423 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2424 #define INTEL_FRONTBUFFER(pipe, plane_id) \
2425 (1 << ((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2426 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2427 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2428 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2429 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2432 * Optimised SGL iterator for GEM objects
2434 static __always_inline struct sgt_iter {
2435 struct scatterlist *sgp;
2442 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2443 struct sgt_iter s = { .sgp = sgl };
2446 s.max = s.curr = s.sgp->offset;
2447 s.max += s.sgp->length;
2449 s.dma = sg_dma_address(s.sgp);
2451 s.pfn = page_to_pfn(sg_page(s.sgp));
2457 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2460 if (unlikely(sg_is_chain(sg)))
2461 sg = sg_chain_ptr(sg);
2466 * __sg_next - return the next scatterlist entry in a list
2467 * @sg: The current sg entry
2470 * If the entry is the last, return NULL; otherwise, step to the next
2471 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2472 * otherwise just return the pointer to the current element.
2474 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2476 #ifdef CONFIG_DEBUG_SG
2477 BUG_ON(sg->sg_magic != SG_MAGIC);
2479 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2483 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2484 * @__dmap: DMA address (output)
2485 * @__iter: 'struct sgt_iter' (iterator state, internal)
2486 * @__sgt: sg_table to iterate over (input)
2488 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2489 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2490 ((__dmap) = (__iter).dma + (__iter).curr); \
2491 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2492 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2495 * for_each_sgt_page - iterate over the pages of the given sg_table
2496 * @__pp: page pointer (output)
2497 * @__iter: 'struct sgt_iter' (iterator state, internal)
2498 * @__sgt: sg_table to iterate over (input)
2500 #define for_each_sgt_page(__pp, __iter, __sgt) \
2501 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2502 ((__pp) = (__iter).pfn == 0 ? NULL : \
2503 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2504 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2505 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2507 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2509 unsigned int page_sizes;
2513 GEM_BUG_ON(sg->offset);
2514 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2515 page_sizes |= sg->length;
2522 static inline unsigned int i915_sg_segment_size(void)
2524 unsigned int size = swiotlb_max_segment();
2527 return SCATTERLIST_MAX_SEGMENT;
2529 size = rounddown(size, PAGE_SIZE);
2530 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2531 if (size < PAGE_SIZE)
2537 static inline const struct intel_device_info *
2538 intel_info(const struct drm_i915_private *dev_priv)
2540 return &dev_priv->info;
2543 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2545 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2546 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2548 #define REVID_FOREVER 0xff
2549 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2551 #define GEN_FOREVER (0)
2553 #define INTEL_GEN_MASK(s, e) ( \
2554 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2555 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2556 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2557 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2561 * Returns true if Gen is in inclusive range [Start, End].
2563 * Use GEN_FOREVER for unbound start and or end.
2565 #define IS_GEN(dev_priv, s, e) \
2566 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2569 * Return true if revision is in range [since,until] inclusive.
2571 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2573 #define IS_REVID(p, since, until) \
2574 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2576 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2578 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2579 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2580 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2581 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2582 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2583 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2584 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2585 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2586 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2587 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2588 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2589 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2590 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2591 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2592 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2593 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2594 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2595 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2596 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2597 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2598 (dev_priv)->info.gt == 1)
2599 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2600 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2601 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2602 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2603 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2604 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2605 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2606 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2607 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2608 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2609 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2610 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2611 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2612 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2613 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2614 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2615 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2616 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2617 /* ULX machines are also considered ULT. */
2618 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2619 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2620 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2621 (dev_priv)->info.gt == 3)
2622 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2623 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2624 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2625 (dev_priv)->info.gt == 3)
2626 /* ULX machines are also considered ULT. */
2627 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2628 INTEL_DEVID(dev_priv) == 0x0A1E)
2629 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2630 INTEL_DEVID(dev_priv) == 0x1913 || \
2631 INTEL_DEVID(dev_priv) == 0x1916 || \
2632 INTEL_DEVID(dev_priv) == 0x1921 || \
2633 INTEL_DEVID(dev_priv) == 0x1926)
2634 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2635 INTEL_DEVID(dev_priv) == 0x1915 || \
2636 INTEL_DEVID(dev_priv) == 0x191E)
2637 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2638 INTEL_DEVID(dev_priv) == 0x5913 || \
2639 INTEL_DEVID(dev_priv) == 0x5916 || \
2640 INTEL_DEVID(dev_priv) == 0x5921 || \
2641 INTEL_DEVID(dev_priv) == 0x5926)
2642 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2643 INTEL_DEVID(dev_priv) == 0x5915 || \
2644 INTEL_DEVID(dev_priv) == 0x591E)
2645 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2646 (dev_priv)->info.gt == 2)
2647 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2648 (dev_priv)->info.gt == 3)
2649 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2650 (dev_priv)->info.gt == 4)
2651 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2652 (dev_priv)->info.gt == 2)
2653 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2654 (dev_priv)->info.gt == 3)
2655 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2656 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2657 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2658 (dev_priv)->info.gt == 2)
2659 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2660 (dev_priv)->info.gt == 3)
2661 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2662 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2664 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2666 #define SKL_REVID_A0 0x0
2667 #define SKL_REVID_B0 0x1
2668 #define SKL_REVID_C0 0x2
2669 #define SKL_REVID_D0 0x3
2670 #define SKL_REVID_E0 0x4
2671 #define SKL_REVID_F0 0x5
2672 #define SKL_REVID_G0 0x6
2673 #define SKL_REVID_H0 0x7
2675 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2677 #define BXT_REVID_A0 0x0
2678 #define BXT_REVID_A1 0x1
2679 #define BXT_REVID_B0 0x3
2680 #define BXT_REVID_B_LAST 0x8
2681 #define BXT_REVID_C0 0x9
2683 #define IS_BXT_REVID(dev_priv, since, until) \
2684 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2686 #define KBL_REVID_A0 0x0
2687 #define KBL_REVID_B0 0x1
2688 #define KBL_REVID_C0 0x2
2689 #define KBL_REVID_D0 0x3
2690 #define KBL_REVID_E0 0x4
2692 #define IS_KBL_REVID(dev_priv, since, until) \
2693 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2695 #define GLK_REVID_A0 0x0
2696 #define GLK_REVID_A1 0x1
2698 #define IS_GLK_REVID(dev_priv, since, until) \
2699 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2701 #define CNL_REVID_A0 0x0
2702 #define CNL_REVID_B0 0x1
2703 #define CNL_REVID_C0 0x2
2705 #define IS_CNL_REVID(p, since, until) \
2706 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2709 * The genX designation typically refers to the render engine, so render
2710 * capability related checks should use IS_GEN, while display and other checks
2711 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2714 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2715 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2716 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2717 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2718 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2719 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2720 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2721 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2722 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2723 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2725 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2726 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2727 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2729 #define ENGINE_MASK(id) BIT(id)
2730 #define RENDER_RING ENGINE_MASK(RCS)
2731 #define BSD_RING ENGINE_MASK(VCS)
2732 #define BLT_RING ENGINE_MASK(BCS)
2733 #define VEBOX_RING ENGINE_MASK(VECS)
2734 #define BSD2_RING ENGINE_MASK(VCS2)
2735 #define ALL_ENGINES (~0)
2737 #define HAS_ENGINE(dev_priv, id) \
2738 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2740 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2741 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2742 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2743 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2745 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2747 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2748 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2749 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2750 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2751 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2753 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2755 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2756 ((dev_priv)->info.has_logical_ring_contexts)
2757 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2758 ((dev_priv)->info.has_logical_ring_preemption)
2760 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2762 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2763 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2764 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2765 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2766 GEM_BUG_ON((sizes) == 0); \
2767 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2770 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2771 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2772 ((dev_priv)->info.overlay_needs_physical)
2774 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2775 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2777 /* WaRsDisableCoarsePowerGating:skl,bxt */
2778 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2779 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2782 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2783 * even when in MSI mode. This results in spurious interrupt warnings if the
2784 * legacy irq no. is shared with another device. The kernel then disables that
2785 * interrupt source and so prevents the other device from working properly.
2787 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
2790 #define HAS_AUX_IRQ(dev_priv) true
2791 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2793 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2794 * rows, which changed the alignment requirements and fence programming.
2796 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2797 !(IS_I915G(dev_priv) || \
2798 IS_I915GM(dev_priv)))
2799 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2800 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2802 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2803 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2804 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2806 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2808 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2810 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2811 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2812 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2814 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2815 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2816 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2818 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2820 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2821 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2823 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2826 * For now, anything with a GuC requires uCode loading, and then supports
2827 * command submission once loaded. But these are logically independent
2828 * properties, so we have separate macros to test them.
2830 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2831 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2832 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2833 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2835 /* For now, anything with a GuC has also HuC */
2836 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2837 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2839 /* Having a GuC is not the same as using a GuC */
2840 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2841 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2842 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2844 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2846 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2848 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2849 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2850 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2851 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2852 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2853 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2854 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2855 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2856 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2857 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2858 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2859 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2860 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2861 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2862 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2863 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2864 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2866 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2867 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2868 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2869 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2870 #define HAS_PCH_CNP_LP(dev_priv) \
2871 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2872 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2873 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2874 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2875 #define HAS_PCH_LPT_LP(dev_priv) \
2876 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2877 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2878 #define HAS_PCH_LPT_H(dev_priv) \
2879 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2880 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2881 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2882 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2883 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2884 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2886 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2888 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2890 /* DPF == dynamic parity feature */
2891 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2892 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2893 2 : HAS_L3_DPF(dev_priv))
2895 #define GT_FREQUENCY_MULTIPLIER 50
2896 #define GEN9_FREQ_SCALER 3
2898 #include "i915_trace.h"
2900 static inline bool intel_vtd_active(void)
2902 #ifdef CONFIG_INTEL_IOMMU
2903 if (intel_iommu_gfx_mapped)
2909 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2911 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2915 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2917 return IS_BROXTON(dev_priv) && intel_vtd_active();
2920 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2925 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2926 const char *fmt, ...);
2928 #define i915_report_error(dev_priv, fmt, ...) \
2929 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2931 #ifdef CONFIG_COMPAT
2932 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2935 #define i915_compat_ioctl NULL
2937 extern const struct dev_pm_ops i915_pm_ops;
2939 extern int i915_driver_load(struct pci_dev *pdev,
2940 const struct pci_device_id *ent);
2941 extern void i915_driver_unload(struct drm_device *dev);
2942 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2943 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2945 #define I915_RESET_QUIET BIT(0)
2946 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
2947 extern int i915_reset_engine(struct intel_engine_cs *engine,
2948 unsigned int flags);
2950 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2951 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2952 extern int intel_guc_reset_engine(struct intel_guc *guc,
2953 struct intel_engine_cs *engine);
2954 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2955 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2956 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2957 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2958 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2959 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2960 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2962 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2963 int intel_engines_init(struct drm_i915_private *dev_priv);
2965 /* intel_hotplug.c */
2966 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2967 u32 pin_mask, u32 long_mask);
2968 void intel_hpd_init(struct drm_i915_private *dev_priv);
2969 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2970 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2971 enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv,
2973 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2975 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2976 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2979 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2981 unsigned long delay;
2983 if (unlikely(!i915_modparams.enable_hangcheck))
2986 /* Don't continually defer the hangcheck so that it is always run at
2987 * least once after work has been scheduled on any ring. Otherwise,
2988 * we will ignore a hung ring if a second ring is kept busy.
2991 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2992 queue_delayed_work(system_long_wq,
2993 &dev_priv->gpu_error.hangcheck_work, delay);
2997 void i915_handle_error(struct drm_i915_private *dev_priv,
2999 const char *fmt, ...);
3001 extern void intel_irq_init(struct drm_i915_private *dev_priv);
3002 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3003 int intel_irq_install(struct drm_i915_private *dev_priv);
3004 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3006 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3008 return dev_priv->gvt;
3011 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3013 return dev_priv->vgpu.active;
3016 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
3019 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3023 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3026 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3027 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3028 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3031 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3032 uint32_t interrupt_mask,
3033 uint32_t enabled_irq_mask);
3035 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3037 ilk_update_display_irq(dev_priv, bits, bits);
3040 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3042 ilk_update_display_irq(dev_priv, bits, 0);
3044 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3046 uint32_t interrupt_mask,
3047 uint32_t enabled_irq_mask);
3048 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3049 enum pipe pipe, uint32_t bits)
3051 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3053 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3054 enum pipe pipe, uint32_t bits)
3056 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3058 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3059 uint32_t interrupt_mask,
3060 uint32_t enabled_irq_mask);
3062 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3064 ibx_display_interrupt_update(dev_priv, bits, bits);
3067 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3069 ibx_display_interrupt_update(dev_priv, bits, 0);
3073 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3074 struct drm_file *file_priv);
3075 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3076 struct drm_file *file_priv);
3077 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3078 struct drm_file *file_priv);
3079 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3080 struct drm_file *file_priv);
3081 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3082 struct drm_file *file_priv);
3083 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3084 struct drm_file *file_priv);
3085 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3086 struct drm_file *file_priv);
3087 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
3088 struct drm_file *file_priv);
3089 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3090 struct drm_file *file_priv);
3091 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3092 struct drm_file *file_priv);
3093 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3094 struct drm_file *file);
3095 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3096 struct drm_file *file);
3097 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3098 struct drm_file *file_priv);
3099 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3100 struct drm_file *file_priv);
3101 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3102 struct drm_file *file_priv);
3103 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3104 struct drm_file *file_priv);
3105 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3106 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
3107 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3108 struct drm_file *file);
3109 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3110 struct drm_file *file_priv);
3111 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3112 struct drm_file *file_priv);
3113 void i915_gem_sanitize(struct drm_i915_private *i915);
3114 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3115 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3116 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3117 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3118 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3120 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3121 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3122 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3123 const struct drm_i915_gem_object_ops *ops);
3124 struct drm_i915_gem_object *
3125 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3126 struct drm_i915_gem_object *
3127 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3128 const void *data, size_t size);
3129 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3130 void i915_gem_free_object(struct drm_gem_object *obj);
3132 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3134 /* A single pass should suffice to release all the freed objects (along
3135 * most call paths) , but be a little more paranoid in that freeing
3136 * the objects does take a little amount of time, during which the rcu
3137 * callbacks could have added new objects into the freed list, and
3138 * armed the work again.
3142 } while (flush_work(&i915->mm.free_work));
3145 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
3148 * Similar to objects above (see i915_gem_drain_freed-objects), in
3149 * general we have workers that are armed by RCU and then rearm
3150 * themselves in their callbacks. To be paranoid, we need to
3151 * drain the workqueue a second time after waiting for the RCU
3152 * grace period so that we catch work queued via RCU from the first
3153 * pass. As neither drain_workqueue() nor flush_workqueue() report
3154 * a result, we make an assumption that we only don't require more
3155 * than 2 passes to catch all recursive RCU delayed work.
3161 drain_workqueue(i915->wq);
3165 struct i915_vma * __must_check
3166 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3167 const struct i915_ggtt_view *view,
3172 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3173 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3175 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3177 static inline int __sg_page_count(const struct scatterlist *sg)
3179 return sg->length >> PAGE_SHIFT;
3182 struct scatterlist *
3183 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3184 unsigned int n, unsigned int *offset);
3187 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3191 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3195 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3198 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3199 struct sg_table *pages,
3200 unsigned int sg_page_sizes);
3201 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3203 static inline int __must_check
3204 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3206 might_lock(&obj->mm.lock);
3208 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3211 return __i915_gem_object_get_pages(obj);
3215 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
3217 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
3221 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3223 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3225 atomic_inc(&obj->mm.pages_pin_count);
3229 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3231 return atomic_read(&obj->mm.pages_pin_count);
3235 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3237 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3238 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3240 atomic_dec(&obj->mm.pages_pin_count);
3244 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3246 __i915_gem_object_unpin_pages(obj);
3249 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3254 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3255 enum i915_mm_subclass subclass);
3256 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3258 enum i915_map_type {
3261 #define I915_MAP_OVERRIDE BIT(31)
3262 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3263 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3267 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3268 * @obj: the object to map into kernel address space
3269 * @type: the type of mapping, used to select pgprot_t
3271 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3272 * pages and then returns a contiguous mapping of the backing storage into
3273 * the kernel address space. Based on the @type of mapping, the PTE will be
3274 * set to either WriteBack or WriteCombine (via pgprot_t).
3276 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3277 * mapping is no longer required.
3279 * Returns the pointer through which to access the mapped object, or an
3280 * ERR_PTR() on error.
3282 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3283 enum i915_map_type type);
3286 * i915_gem_object_unpin_map - releases an earlier mapping
3287 * @obj: the object to unmap
3289 * After pinning the object and mapping its pages, once you are finished
3290 * with your access, call i915_gem_object_unpin_map() to release the pin
3291 * upon the mapping. Once the pin count reaches zero, that mapping may be
3294 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3296 i915_gem_object_unpin_pages(obj);
3299 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3300 unsigned int *needs_clflush);
3301 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3302 unsigned int *needs_clflush);
3303 #define CLFLUSH_BEFORE BIT(0)
3304 #define CLFLUSH_AFTER BIT(1)
3305 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3308 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3310 i915_gem_object_unpin_pages(obj);
3313 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3314 void i915_vma_move_to_active(struct i915_vma *vma,
3315 struct drm_i915_gem_request *req,
3316 unsigned int flags);
3317 int i915_gem_dumb_create(struct drm_file *file_priv,
3318 struct drm_device *dev,
3319 struct drm_mode_create_dumb *args);
3320 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3321 uint32_t handle, uint64_t *offset);
3322 int i915_gem_mmap_gtt_version(void);
3324 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3325 struct drm_i915_gem_object *new,
3326 unsigned frontbuffer_bits);
3328 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3330 struct drm_i915_gem_request *
3331 i915_gem_find_active_request(struct intel_engine_cs *engine);
3333 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3335 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3337 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3340 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3342 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3345 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3347 return unlikely(test_bit(I915_WEDGED, &error->flags));
3350 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3352 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3355 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3357 return READ_ONCE(error->reset_count);
3360 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3361 struct intel_engine_cs *engine)
3363 return READ_ONCE(error->reset_engine_count[engine->id]);
3366 struct drm_i915_gem_request *
3367 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3368 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3369 void i915_gem_reset(struct drm_i915_private *dev_priv);
3370 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3371 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3372 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3373 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3374 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3375 struct drm_i915_gem_request *request);
3377 void i915_gem_init_mmio(struct drm_i915_private *i915);
3378 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3379 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3380 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3381 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3382 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3383 unsigned int flags);
3384 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3385 void i915_gem_resume(struct drm_i915_private *dev_priv);
3386 int i915_gem_fault(struct vm_fault *vmf);
3387 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3390 struct intel_rps_client *rps);
3391 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3394 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3397 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3399 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3401 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3402 struct i915_vma * __must_check
3403 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3405 const struct i915_ggtt_view *view);
3406 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3407 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3409 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3410 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3412 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3413 enum i915_cache_level cache_level);
3415 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3416 struct dma_buf *dma_buf);
3418 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3419 struct drm_gem_object *gem_obj, int flags);
3421 static inline struct i915_hw_ppgtt *
3422 i915_vm_to_ppgtt(struct i915_address_space *vm)
3424 return container_of(vm, struct i915_hw_ppgtt, base);
3427 /* i915_gem_fence_reg.c */
3428 struct drm_i915_fence_reg *
3429 i915_reserve_fence(struct drm_i915_private *dev_priv);
3430 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3432 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3433 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3435 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3436 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3437 struct sg_table *pages);
3438 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3439 struct sg_table *pages);
3441 static inline struct i915_gem_context *
3442 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3444 return idr_find(&file_priv->context_idr, id);
3447 static inline struct i915_gem_context *
3448 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3450 struct i915_gem_context *ctx;
3453 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3454 if (ctx && !kref_get_unless_zero(&ctx->ref))
3461 static inline struct intel_timeline *
3462 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3463 struct intel_engine_cs *engine)
3465 struct i915_address_space *vm;
3467 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3468 return &vm->timeline.engine[engine->id];
3471 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3472 struct drm_file *file);
3473 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3474 struct drm_file *file);
3475 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3476 struct drm_file *file);
3477 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3478 struct i915_gem_context *ctx,
3479 uint32_t *reg_state);
3481 /* i915_gem_evict.c */
3482 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3483 u64 min_size, u64 alignment,
3484 unsigned cache_level,
3487 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3488 struct drm_mm_node *node,
3489 unsigned int flags);
3490 int i915_gem_evict_vm(struct i915_address_space *vm);
3492 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3494 /* belongs in i915_gem_gtt.h */
3495 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3498 if (INTEL_GEN(dev_priv) < 6)
3499 intel_gtt_chipset_flush();
3502 /* i915_gem_stolen.c */
3503 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3504 struct drm_mm_node *node, u64 size,
3505 unsigned alignment);
3506 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3507 struct drm_mm_node *node, u64 size,
3508 unsigned alignment, u64 start,
3510 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3511 struct drm_mm_node *node);
3512 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3513 void i915_gem_cleanup_stolen(struct drm_device *dev);
3514 struct drm_i915_gem_object *
3515 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3516 resource_size_t size);
3517 struct drm_i915_gem_object *
3518 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3519 resource_size_t stolen_offset,
3520 resource_size_t gtt_offset,
3521 resource_size_t size);
3523 /* i915_gem_internal.c */
3524 struct drm_i915_gem_object *
3525 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3528 /* i915_gem_shrinker.c */
3529 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3530 unsigned long target,
3531 unsigned long *nr_scanned,
3533 #define I915_SHRINK_PURGEABLE 0x1
3534 #define I915_SHRINK_UNBOUND 0x2
3535 #define I915_SHRINK_BOUND 0x4
3536 #define I915_SHRINK_ACTIVE 0x8
3537 #define I915_SHRINK_VMAPS 0x10
3538 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3539 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3540 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3543 /* i915_gem_tiling.c */
3544 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3546 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3548 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3549 i915_gem_object_is_tiled(obj);
3552 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3553 unsigned int tiling, unsigned int stride);
3554 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3555 unsigned int tiling, unsigned int stride);
3557 /* i915_debugfs.c */
3558 #ifdef CONFIG_DEBUG_FS
3559 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3560 int i915_debugfs_connector_add(struct drm_connector *connector);
3561 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3563 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3564 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3566 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3569 /* i915_gpu_error.c */
3570 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3573 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3574 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3575 const struct i915_gpu_state *gpu);
3576 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3577 struct drm_i915_private *i915,
3578 size_t count, loff_t pos);
3579 static inline void i915_error_state_buf_release(
3580 struct drm_i915_error_state_buf *eb)
3585 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3586 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3588 const char *error_msg);
3590 static inline struct i915_gpu_state *
3591 i915_gpu_state_get(struct i915_gpu_state *gpu)
3593 kref_get(&gpu->ref);
3597 void __i915_gpu_state_free(struct kref *kref);
3598 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3601 kref_put(&gpu->ref, __i915_gpu_state_free);
3604 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3605 void i915_reset_error_state(struct drm_i915_private *i915);
3609 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3611 const char *error_msg)
3615 static inline struct i915_gpu_state *
3616 i915_first_error_state(struct drm_i915_private *i915)
3621 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3627 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3629 /* i915_cmd_parser.c */
3630 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3631 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3632 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3633 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3634 struct drm_i915_gem_object *batch_obj,
3635 struct drm_i915_gem_object *shadow_batch_obj,
3636 u32 batch_start_offset,
3641 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3642 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3643 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3644 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3646 /* i915_suspend.c */
3647 extern int i915_save_state(struct drm_i915_private *dev_priv);
3648 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3651 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3652 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3654 /* intel_lpe_audio.c */
3655 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3656 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3657 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3658 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3659 enum pipe pipe, enum port port,
3660 const void *eld, int ls_clock, bool dp_output);
3663 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3664 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3665 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3668 extern struct i2c_adapter *
3669 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3670 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3671 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3672 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3674 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3676 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3679 void intel_bios_init(struct drm_i915_private *dev_priv);
3680 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3681 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3682 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3683 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3684 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3685 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3686 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3687 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3689 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3694 extern void intel_register_dsm_handler(void);
3695 extern void intel_unregister_dsm_handler(void);
3697 static inline void intel_register_dsm_handler(void) { return; }
3698 static inline void intel_unregister_dsm_handler(void) { return; }
3699 #endif /* CONFIG_ACPI */
3701 /* intel_device_info.c */
3702 static inline struct intel_device_info *
3703 mkwrite_device_info(struct drm_i915_private *dev_priv)
3705 return (struct intel_device_info *)&dev_priv->info;
3709 extern void intel_modeset_init_hw(struct drm_device *dev);
3710 extern int intel_modeset_init(struct drm_device *dev);
3711 extern void intel_modeset_cleanup(struct drm_device *dev);
3712 extern int intel_connector_register(struct drm_connector *);
3713 extern void intel_connector_unregister(struct drm_connector *);
3714 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3716 extern void intel_display_resume(struct drm_device *dev);
3717 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3718 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3719 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3720 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3721 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3722 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3725 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3726 struct drm_file *file);
3729 extern struct intel_overlay_error_state *
3730 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3731 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3732 struct intel_overlay_error_state *error);
3734 extern struct intel_display_error_state *
3735 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3736 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3737 struct intel_display_error_state *error);
3739 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3740 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3741 u32 val, int fast_timeout_us,
3742 int slow_timeout_ms);
3743 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3744 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3746 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3747 u32 reply_mask, u32 reply, int timeout_base_ms);
3749 /* intel_sideband.c */
3750 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3751 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3752 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3753 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3754 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3755 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3756 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3757 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3758 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3759 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3760 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3761 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3762 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3763 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3764 enum intel_sbi_destination destination);
3765 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3766 enum intel_sbi_destination destination);
3767 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3768 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3770 /* intel_dpio_phy.c */
3771 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3772 enum dpio_phy *phy, enum dpio_channel *ch);
3773 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3774 enum port port, u32 margin, u32 scale,
3775 u32 enable, u32 deemphasis);
3776 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3777 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3778 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3780 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3782 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3783 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3784 uint8_t lane_lat_optim_mask);
3785 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3787 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3788 u32 deemph_reg_value, u32 margin_reg_value,
3789 bool uniq_trans_scale);
3790 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3791 const struct intel_crtc_state *crtc_state,
3793 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3794 const struct intel_crtc_state *crtc_state);
3795 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3796 const struct intel_crtc_state *crtc_state);
3797 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3798 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3799 const struct intel_crtc_state *old_crtc_state);
3801 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3802 u32 demph_reg_value, u32 preemph_reg_value,
3803 u32 uniqtranscale_reg_value, u32 tx3_demph);
3804 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3805 const struct intel_crtc_state *crtc_state);
3806 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3807 const struct intel_crtc_state *crtc_state);
3808 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3809 const struct intel_crtc_state *old_crtc_state);
3811 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3812 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3813 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3814 const i915_reg_t reg);
3816 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3818 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3819 const i915_reg_t reg)
3821 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3824 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3825 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3827 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3828 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3829 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3830 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3832 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3833 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3834 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3835 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3837 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3838 * will be implemented using 2 32-bit writes in an arbitrary order with
3839 * an arbitrary delay between them. This can cause the hardware to
3840 * act upon the intermediate value, possibly leading to corruption and
3841 * machine death. For this reason we do not support I915_WRITE64, or
3842 * dev_priv->uncore.funcs.mmio_writeq.
3844 * When reading a 64-bit value as two 32-bit values, the delay may cause
3845 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3846 * occasionally a 64-bit register does not actualy support a full readq
3847 * and must be read using two 32-bit reads.
3849 * You have been warned.
3851 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3853 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3854 u32 upper, lower, old_upper, loop = 0; \
3855 upper = I915_READ(upper_reg); \
3857 old_upper = upper; \
3858 lower = I915_READ(lower_reg); \
3859 upper = I915_READ(upper_reg); \
3860 } while (upper != old_upper && loop++ < 2); \
3861 (u64)upper << 32 | lower; })
3863 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3864 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3866 #define __raw_read(x, s) \
3867 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3870 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3873 #define __raw_write(x, s) \
3874 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3875 i915_reg_t reg, uint##x##_t val) \
3877 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3892 /* These are untraced mmio-accessors that are only valid to be used inside
3893 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3896 * Think twice, and think again, before using these.
3898 * As an example, these accessors can possibly be used between:
3900 * spin_lock_irq(&dev_priv->uncore.lock);
3901 * intel_uncore_forcewake_get__locked();
3905 * intel_uncore_forcewake_put__locked();
3906 * spin_unlock_irq(&dev_priv->uncore.lock);
3909 * Note: some registers may not need forcewake held, so
3910 * intel_uncore_forcewake_{get,put} can be omitted, see
3911 * intel_uncore_forcewake_for_reg().
3913 * Certain architectures will die if the same cacheline is concurrently accessed
3914 * by different clients (e.g. on Ivybridge). Access to registers should
3915 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3916 * a more localised lock guarding all access to that bank of registers.
3918 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3919 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3920 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3921 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3923 /* "Broadcast RGB" property */
3924 #define INTEL_BROADCAST_RGB_AUTO 0
3925 #define INTEL_BROADCAST_RGB_FULL 1
3926 #define INTEL_BROADCAST_RGB_LIMITED 2
3928 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3930 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3931 return VLV_VGACNTRL;
3932 else if (INTEL_GEN(dev_priv) >= 5)
3933 return CPU_VGACNTRL;
3938 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3940 unsigned long j = msecs_to_jiffies(m);
3942 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3945 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3947 /* nsecs_to_jiffies64() does not guard against overflow */
3948 if (NSEC_PER_SEC % HZ &&
3949 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3950 return MAX_JIFFY_OFFSET;
3952 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3955 static inline unsigned long
3956 timespec_to_jiffies_timeout(const struct timespec *value)
3958 unsigned long j = timespec_to_jiffies(value);
3960 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3964 * If you need to wait X milliseconds between events A and B, but event B
3965 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3966 * when event A happened, then just before event B you call this function and
3967 * pass the timestamp as the first argument, and X as the second argument.
3970 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3972 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3975 * Don't re-read the value of "jiffies" every time since it may change
3976 * behind our back and break the math.
3978 tmp_jiffies = jiffies;
3979 target_jiffies = timestamp_jiffies +
3980 msecs_to_jiffies_timeout(to_wait_ms);
3982 if (time_after(target_jiffies, tmp_jiffies)) {
3983 remaining_jiffies = target_jiffies - tmp_jiffies;
3984 while (remaining_jiffies)
3986 schedule_timeout_uninterruptible(remaining_jiffies);
3991 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
3993 struct intel_engine_cs *engine = req->engine;
3996 /* Note that the engine may have wrapped around the seqno, and
3997 * so our request->global_seqno will be ahead of the hardware,
3998 * even though it completed the request before wrapping. We catch
3999 * this by kicking all the waiters before resetting the seqno
4000 * in hardware, and also signal the fence.
4002 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
4005 /* The request was dequeued before we were awoken. We check after
4006 * inspecting the hw to confirm that this was the same request
4007 * that generated the HWS update. The memory barriers within
4008 * the request execution are sufficient to ensure that a check
4009 * after reading the value from hw matches this request.
4011 seqno = i915_gem_request_global_seqno(req);
4015 /* Before we do the heavier coherent read of the seqno,
4016 * check the value (hopefully) in the CPU cacheline.
4018 if (__i915_gem_request_completed(req, seqno))
4021 /* Ensure our read of the seqno is coherent so that we
4022 * do not "miss an interrupt" (i.e. if this is the last
4023 * request and the seqno write from the GPU is not visible
4024 * by the time the interrupt fires, we will see that the
4025 * request is incomplete and go back to sleep awaiting
4026 * another interrupt that will never come.)
4028 * Strictly, we only need to do this once after an interrupt,
4029 * but it is easier and safer to do it every time the waiter
4032 if (engine->irq_seqno_barrier &&
4033 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4034 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4036 /* The ordering of irq_posted versus applying the barrier
4037 * is crucial. The clearing of the current irq_posted must
4038 * be visible before we perform the barrier operation,
4039 * such that if a subsequent interrupt arrives, irq_posted
4040 * is reasserted and our task rewoken (which causes us to
4041 * do another __i915_request_irq_complete() immediately
4042 * and reapply the barrier). Conversely, if the clear
4043 * occurs after the barrier, then an interrupt that arrived
4044 * whilst we waited on the barrier would not trigger a
4045 * barrier on the next pass, and the read may not see the
4048 engine->irq_seqno_barrier(engine);
4050 /* If we consume the irq, but we are no longer the bottom-half,
4051 * the real bottom-half may not have serialised their own
4052 * seqno check with the irq-barrier (i.e. may have inspected
4053 * the seqno before we believe it coherent since they see
4054 * irq_posted == false but we are still running).
4056 spin_lock_irq(&b->irq_lock);
4057 if (b->irq_wait && b->irq_wait->tsk != current)
4058 /* Note that if the bottom-half is changed as we
4059 * are sending the wake-up, the new bottom-half will
4060 * be woken by whomever made the change. We only have
4061 * to worry about when we steal the irq-posted for
4064 wake_up_process(b->irq_wait->tsk);
4065 spin_unlock_irq(&b->irq_lock);
4067 if (__i915_gem_request_completed(req, seqno))
4074 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4075 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4077 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4078 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4079 * perform the operation. To check beforehand, pass in the parameters to
4080 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4081 * you only need to pass in the minor offsets, page-aligned pointers are
4084 * For just checking for SSE4.1, in the foreknowledge that the future use
4085 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4087 #define i915_can_memcpy_from_wc(dst, src, len) \
4088 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4090 #define i915_has_memcpy_from_wc() \
4091 i915_memcpy_from_wc(NULL, NULL, 0)
4094 int remap_io_mapping(struct vm_area_struct *vma,
4095 unsigned long addr, unsigned long pfn, unsigned long size,
4096 struct io_mapping *iomap);
4098 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
4100 if (INTEL_GEN(i915) >= 10)
4101 return CNL_HWS_CSB_WRITE_INDEX;
4103 return I915_HWS_CSB_WRITE_INDEX;