2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
46 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
48 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
50 static bool cpu_cache_is_coherent(struct drm_device *dev,
51 enum i915_cache_level level)
53 return HAS_LLC(dev) || level != I915_CACHE_NONE;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
58 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
61 return obj->pin_display;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
68 spin_lock(&dev_priv->mm.object_stat_lock);
69 dev_priv->mm.object_count++;
70 dev_priv->mm.object_memory += size;
71 spin_unlock(&dev_priv->mm.object_stat_lock);
74 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
77 spin_lock(&dev_priv->mm.object_stat_lock);
78 dev_priv->mm.object_count--;
79 dev_priv->mm.object_memory -= size;
80 spin_unlock(&dev_priv->mm.object_stat_lock);
84 i915_gem_wait_for_error(struct i915_gpu_error *error)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret = wait_event_interruptible_timeout(error->reset_queue,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret < 0) {
112 int i915_mutex_lock_interruptible(struct drm_device *dev)
114 struct drm_i915_private *dev_priv = dev->dev_private;
117 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
121 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 WARN_ON(i915_verify_lists(dev));
130 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
131 struct drm_file *file)
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 struct drm_i915_gem_get_aperture *args = data;
135 struct i915_gtt *ggtt = &dev_priv->gtt;
136 struct i915_vma *vma;
140 mutex_lock(&dev->struct_mutex);
141 list_for_each_entry(vma, &ggtt->base.active_list, mm_list)
143 pinned += vma->node.size;
144 list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list)
146 pinned += vma->node.size;
147 mutex_unlock(&dev->struct_mutex);
149 args->aper_size = dev_priv->gtt.base.total;
150 args->aper_available_size = args->aper_size - pinned;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
158 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
159 char *vaddr = obj->phys_handle->vaddr;
161 struct scatterlist *sg;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
167 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
171 page = shmem_read_mapping_page(mapping, i);
173 return PTR_ERR(page);
175 src = kmap_atomic(page);
176 memcpy(vaddr, src, PAGE_SIZE);
177 drm_clflush_virt_range(vaddr, PAGE_SIZE);
180 page_cache_release(page);
184 i915_gem_chipset_flush(obj->base.dev);
186 st = kmalloc(sizeof(*st), GFP_KERNEL);
190 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
197 sg->length = obj->base.size;
199 sg_dma_address(sg) = obj->phys_handle->busaddr;
200 sg_dma_len(sg) = obj->base.size;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
211 BUG_ON(obj->madv == __I915_MADV_PURGED);
213 ret = i915_gem_object_set_to_cpu_domain(obj, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret != -EIO);
219 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
222 if (obj->madv == I915_MADV_DONTNEED)
226 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
227 char *vaddr = obj->phys_handle->vaddr;
230 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
234 page = shmem_read_mapping_page(mapping, i);
238 dst = kmap_atomic(page);
239 drm_clflush_virt_range(vaddr, PAGE_SIZE);
240 memcpy(dst, vaddr, PAGE_SIZE);
243 set_page_dirty(page);
244 if (obj->madv == I915_MADV_WILLNEED)
245 mark_page_accessed(page);
246 page_cache_release(page);
252 sg_free_table(obj->pages);
257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
259 drm_pci_free(obj->base.dev, obj->phys_handle);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
263 .get_pages = i915_gem_object_get_pages_phys,
264 .put_pages = i915_gem_object_put_pages_phys,
265 .release = i915_gem_object_release_phys,
269 drop_pages(struct drm_i915_gem_object *obj)
271 struct i915_vma *vma, *next;
274 drm_gem_object_reference(&obj->base);
275 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
276 if (i915_vma_unbind(vma))
279 ret = i915_gem_object_put_pages(obj);
280 drm_gem_object_unreference(&obj->base);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
289 drm_dma_handle_t *phys;
292 if (obj->phys_handle) {
293 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
299 if (obj->madv != I915_MADV_WILLNEED)
302 if (obj->base.filp == NULL)
305 ret = drop_pages(obj);
309 /* create a new object */
310 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
314 obj->phys_handle = phys;
315 obj->ops = &i915_gem_phys_ops;
317 return i915_gem_object_get_pages(obj);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
322 struct drm_i915_gem_pwrite *args,
323 struct drm_file *file_priv)
325 struct drm_device *dev = obj->base.dev;
326 void *vaddr = obj->phys_handle->vaddr + args->offset;
327 char __user *user_data = to_user_ptr(args->data_ptr);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret = i915_gem_object_wait_rendering(obj, false);
337 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
338 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
339 unsigned long unwritten;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev->struct_mutex);
346 unwritten = copy_from_user(vaddr, user_data, args->size);
347 mutex_lock(&dev->struct_mutex);
354 drm_clflush_virt_range(vaddr, args->size);
355 i915_gem_chipset_flush(dev);
358 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
362 void *i915_gem_object_alloc(struct drm_device *dev)
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
368 void i915_gem_object_free(struct drm_i915_gem_object *obj)
370 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
371 kmem_cache_free(dev_priv->objects, obj);
375 i915_gem_create(struct drm_file *file,
376 struct drm_device *dev,
380 struct drm_i915_gem_object *obj;
384 size = roundup(size, PAGE_SIZE);
388 /* Allocate the new object */
389 obj = i915_gem_alloc_object(dev, size);
393 ret = drm_gem_handle_create(file, &obj->base, &handle);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj->base);
404 i915_gem_dumb_create(struct drm_file *file,
405 struct drm_device *dev,
406 struct drm_mode_create_dumb *args)
408 /* have to work out size/pitch and return them */
409 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
410 args->size = args->pitch * args->height;
411 return i915_gem_create(file, dev,
412 args->size, &args->handle);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device *dev, void *data,
420 struct drm_file *file)
422 struct drm_i915_gem_create *args = data;
424 return i915_gem_create(file, dev,
425 args->size, &args->handle);
429 __copy_to_user_swizzled(char __user *cpu_vaddr,
430 const char *gpu_vaddr, int gpu_offset,
433 int ret, cpu_offset = 0;
436 int cacheline_end = ALIGN(gpu_offset + 1, 64);
437 int this_length = min(cacheline_end - gpu_offset, length);
438 int swizzled_gpu_offset = gpu_offset ^ 64;
440 ret = __copy_to_user(cpu_vaddr + cpu_offset,
441 gpu_vaddr + swizzled_gpu_offset,
446 cpu_offset += this_length;
447 gpu_offset += this_length;
448 length -= this_length;
455 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
456 const char __user *cpu_vaddr,
459 int ret, cpu_offset = 0;
462 int cacheline_end = ALIGN(gpu_offset + 1, 64);
463 int this_length = min(cacheline_end - gpu_offset, length);
464 int swizzled_gpu_offset = gpu_offset ^ 64;
466 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
467 cpu_vaddr + cpu_offset,
472 cpu_offset += this_length;
473 gpu_offset += this_length;
474 length -= this_length;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
495 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
502 ret = i915_gem_object_wait_rendering(obj, true);
507 ret = i915_gem_object_get_pages(obj);
511 i915_gem_object_pin_pages(obj);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
521 char __user *user_data,
522 bool page_do_bit17_swizzling, bool needs_clflush)
527 if (unlikely(page_do_bit17_swizzling))
530 vaddr = kmap_atomic(page);
532 drm_clflush_virt_range(vaddr + shmem_page_offset,
534 ret = __copy_to_user_inatomic(user_data,
535 vaddr + shmem_page_offset,
537 kunmap_atomic(vaddr);
539 return ret ? -EFAULT : 0;
543 shmem_clflush_swizzled_range(char *addr, unsigned long length,
546 if (unlikely(swizzled)) {
547 unsigned long start = (unsigned long) addr;
548 unsigned long end = (unsigned long) addr + length;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start = round_down(start, 128);
555 end = round_up(end, 128);
557 drm_clflush_virt_range((void *)start, end - start);
559 drm_clflush_virt_range(addr, length);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
568 char __user *user_data,
569 bool page_do_bit17_swizzling, bool needs_clflush)
576 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
578 page_do_bit17_swizzling);
580 if (page_do_bit17_swizzling)
581 ret = __copy_to_user_swizzled(user_data,
582 vaddr, shmem_page_offset,
585 ret = __copy_to_user(user_data,
586 vaddr + shmem_page_offset,
590 return ret ? - EFAULT : 0;
594 i915_gem_shmem_pread(struct drm_device *dev,
595 struct drm_i915_gem_object *obj,
596 struct drm_i915_gem_pread *args,
597 struct drm_file *file)
599 char __user *user_data;
602 int shmem_page_offset, page_length, ret = 0;
603 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
605 int needs_clflush = 0;
606 struct sg_page_iter sg_iter;
608 user_data = to_user_ptr(args->data_ptr);
611 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
613 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
617 offset = args->offset;
619 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
620 offset >> PAGE_SHIFT) {
621 struct page *page = sg_page_iter_page(&sg_iter);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((shmem_page_offset + page_length) > PAGE_SIZE)
634 page_length = PAGE_SIZE - shmem_page_offset;
636 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
637 (page_to_phys(page) & (1 << 17)) != 0;
639 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
640 user_data, page_do_bit17_swizzling,
645 mutex_unlock(&dev->struct_mutex);
647 if (likely(!i915.prefault_disable) && !prefaulted) {
648 ret = fault_in_multipages_writeable(user_data, remain);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
658 user_data, page_do_bit17_swizzling,
661 mutex_lock(&dev->struct_mutex);
667 remain -= page_length;
668 user_data += page_length;
669 offset += page_length;
673 i915_gem_object_unpin_pages(obj);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
685 struct drm_file *file)
687 struct drm_i915_gem_pread *args = data;
688 struct drm_i915_gem_object *obj;
694 if (!access_ok(VERIFY_WRITE,
695 to_user_ptr(args->data_ptr),
699 ret = i915_mutex_lock_interruptible(dev);
703 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
704 if (&obj->base == NULL) {
709 /* Bounds check source. */
710 if (args->offset > obj->base.size ||
711 args->size > obj->base.size - args->offset) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj->base.filp) {
724 trace_i915_gem_object_pread(obj, args->offset, args->size);
726 ret = i915_gem_shmem_pread(dev, obj, args, file);
729 drm_gem_object_unreference(&obj->base);
731 mutex_unlock(&dev->struct_mutex);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping *mapping,
741 loff_t page_base, int page_offset,
742 char __user *user_data,
745 void __iomem *vaddr_atomic;
747 unsigned long unwritten;
749 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr = (void __force*)vaddr_atomic + page_offset;
752 unwritten = __copy_from_user_inatomic_nocache(vaddr,
754 io_mapping_unmap_atomic(vaddr_atomic);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
764 struct drm_i915_gem_object *obj,
765 struct drm_i915_gem_pwrite *args,
766 struct drm_file *file)
768 struct drm_i915_private *dev_priv = dev->dev_private;
770 loff_t offset, page_base;
771 char __user *user_data;
772 int page_offset, page_length, ret;
774 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
778 ret = i915_gem_object_set_to_gtt_domain(obj, true);
782 ret = i915_gem_object_put_fence(obj);
786 user_data = to_user_ptr(args->data_ptr);
789 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
791 intel_fb_obj_invalidate(obj, ORIGIN_GTT);
794 /* Operation in this page
796 * page_base = page offset within aperture
797 * page_offset = offset within page
798 * page_length = bytes to copy for this page
800 page_base = offset & PAGE_MASK;
801 page_offset = offset_in_page(offset);
802 page_length = remain;
803 if ((page_offset + remain) > PAGE_SIZE)
804 page_length = PAGE_SIZE - page_offset;
806 /* If we get a fault while copying data, then (presumably) our
807 * source page isn't available. Return the error and we'll
808 * retry in the slow path.
810 if (fast_user_write(dev_priv->gtt.mappable, page_base,
811 page_offset, user_data, page_length)) {
816 remain -= page_length;
817 user_data += page_length;
818 offset += page_length;
822 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
824 i915_gem_object_ggtt_unpin(obj);
829 /* Per-page copy function for the shmem pwrite fastpath.
830 * Flushes invalid cachelines before writing to the target if
831 * needs_clflush_before is set and flushes out any written cachelines after
832 * writing if needs_clflush is set. */
834 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
835 char __user *user_data,
836 bool page_do_bit17_swizzling,
837 bool needs_clflush_before,
838 bool needs_clflush_after)
843 if (unlikely(page_do_bit17_swizzling))
846 vaddr = kmap_atomic(page);
847 if (needs_clflush_before)
848 drm_clflush_virt_range(vaddr + shmem_page_offset,
850 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
851 user_data, page_length);
852 if (needs_clflush_after)
853 drm_clflush_virt_range(vaddr + shmem_page_offset,
855 kunmap_atomic(vaddr);
857 return ret ? -EFAULT : 0;
860 /* Only difference to the fast-path function is that this can handle bit17
861 * and uses non-atomic copy and kmap functions. */
863 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
864 char __user *user_data,
865 bool page_do_bit17_swizzling,
866 bool needs_clflush_before,
867 bool needs_clflush_after)
873 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
874 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
876 page_do_bit17_swizzling);
877 if (page_do_bit17_swizzling)
878 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
882 ret = __copy_from_user(vaddr + shmem_page_offset,
885 if (needs_clflush_after)
886 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
888 page_do_bit17_swizzling);
891 return ret ? -EFAULT : 0;
895 i915_gem_shmem_pwrite(struct drm_device *dev,
896 struct drm_i915_gem_object *obj,
897 struct drm_i915_gem_pwrite *args,
898 struct drm_file *file)
902 char __user *user_data;
903 int shmem_page_offset, page_length, ret = 0;
904 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
905 int hit_slowpath = 0;
906 int needs_clflush_after = 0;
907 int needs_clflush_before = 0;
908 struct sg_page_iter sg_iter;
910 user_data = to_user_ptr(args->data_ptr);
913 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
915 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
916 /* If we're not in the cpu write domain, set ourself into the gtt
917 * write domain and manually flush cachelines (if required). This
918 * optimizes for the case when the gpu will use the data
919 * right away and we therefore have to clflush anyway. */
920 needs_clflush_after = cpu_write_needs_clflush(obj);
921 ret = i915_gem_object_wait_rendering(obj, false);
925 /* Same trick applies to invalidate partially written cachelines read
927 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
928 needs_clflush_before =
929 !cpu_cache_is_coherent(dev, obj->cache_level);
931 ret = i915_gem_object_get_pages(obj);
935 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
937 i915_gem_object_pin_pages(obj);
939 offset = args->offset;
942 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
943 offset >> PAGE_SHIFT) {
944 struct page *page = sg_page_iter_page(&sg_iter);
945 int partial_cacheline_write;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset = offset_in_page(offset);
957 page_length = remain;
958 if ((shmem_page_offset + page_length) > PAGE_SIZE)
959 page_length = PAGE_SIZE - shmem_page_offset;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write = needs_clflush_before &&
965 ((shmem_page_offset | page_length)
966 & (boot_cpu_data.x86_clflush_size - 1));
968 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
969 (page_to_phys(page) & (1 << 17)) != 0;
971 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
972 user_data, page_do_bit17_swizzling,
973 partial_cacheline_write,
974 needs_clflush_after);
979 mutex_unlock(&dev->struct_mutex);
980 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
981 user_data, page_do_bit17_swizzling,
982 partial_cacheline_write,
983 needs_clflush_after);
985 mutex_lock(&dev->struct_mutex);
991 remain -= page_length;
992 user_data += page_length;
993 offset += page_length;
997 i915_gem_object_unpin_pages(obj);
1001 * Fixup: Flush cpu caches in case we didn't flush the dirty
1002 * cachelines in-line while writing and the object moved
1003 * out of the cpu write domain while we've dropped the lock.
1005 if (!needs_clflush_after &&
1006 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1007 if (i915_gem_clflush_object(obj, obj->pin_display))
1008 needs_clflush_after = true;
1012 if (needs_clflush_after)
1013 i915_gem_chipset_flush(dev);
1015 obj->cache_dirty = true;
1017 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1028 struct drm_file *file)
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct drm_i915_gem_pwrite *args = data;
1032 struct drm_i915_gem_object *obj;
1035 if (args->size == 0)
1038 if (!access_ok(VERIFY_READ,
1039 to_user_ptr(args->data_ptr),
1043 if (likely(!i915.prefault_disable)) {
1044 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1050 intel_runtime_pm_get(dev_priv);
1052 ret = i915_mutex_lock_interruptible(dev);
1056 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1057 if (&obj->base == NULL) {
1062 /* Bounds check destination. */
1063 if (args->offset > obj->base.size ||
1064 args->size > obj->base.size - args->offset) {
1069 /* prime objects have no backing filp to GEM pread/pwrite
1072 if (!obj->base.filp) {
1077 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1081 * it would end up going through the fenced access, and we'll get
1082 * different detiling behavior between reading and writing.
1083 * pread/pwrite currently are reading and writing from the CPU
1084 * perspective, requiring manual detiling by the client.
1086 if (obj->tiling_mode == I915_TILING_NONE &&
1087 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1088 cpu_write_needs_clflush(obj)) {
1089 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1090 /* Note that the gtt paths might fail with non-page-backed user
1091 * pointers (e.g. gtt mappings when moving data between
1092 * textures). Fallback to the shmem path in that case. */
1095 if (ret == -EFAULT || ret == -ENOSPC) {
1096 if (obj->phys_handle)
1097 ret = i915_gem_phys_pwrite(obj, args, file);
1099 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1103 drm_gem_object_unreference(&obj->base);
1105 mutex_unlock(&dev->struct_mutex);
1107 intel_runtime_pm_put(dev_priv);
1113 i915_gem_check_wedge(struct i915_gpu_error *error,
1116 if (i915_reset_in_progress(error)) {
1117 /* Non-interruptible callers can't handle -EAGAIN, hence return
1118 * -EIO unconditionally for these. */
1122 /* Recovery complete, but the reset failed ... */
1123 if (i915_terminally_wedged(error))
1127 * Check if GPU Reset is in progress - we need intel_ring_begin
1128 * to work properly to reinit the hw state while the gpu is
1129 * still marked as reset-in-progress. Handle this with a flag.
1131 if (!error->reload_in_reset)
1138 static void fake_irq(unsigned long data)
1140 wake_up_process((struct task_struct *)data);
1143 static bool missed_irq(struct drm_i915_private *dev_priv,
1144 struct intel_engine_cs *ring)
1146 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1149 static unsigned long local_clock_us(unsigned *cpu)
1153 /* Cheaply and approximately convert from nanoseconds to microseconds.
1154 * The result and subsequent calculations are also defined in the same
1155 * approximate microseconds units. The principal source of timing
1156 * error here is from the simple truncation.
1158 * Note that local_clock() is only defined wrt to the current CPU;
1159 * the comparisons are no longer valid if we switch CPUs. Instead of
1160 * blocking preemption for the entire busywait, we can detect the CPU
1161 * switch and use that as indicator of system load and a reason to
1162 * stop busywaiting, see busywait_stop().
1165 t = local_clock() >> 10;
1171 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1175 if (time_after(local_clock_us(&this_cpu), timeout))
1178 return this_cpu != cpu;
1181 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1183 unsigned long timeout;
1186 /* When waiting for high frequency requests, e.g. during synchronous
1187 * rendering split between the CPU and GPU, the finite amount of time
1188 * required to set up the irq and wait upon it limits the response
1189 * rate. By busywaiting on the request completion for a short while we
1190 * can service the high frequency waits as quick as possible. However,
1191 * if it is a slow request, we want to sleep as quickly as possible.
1192 * The tradeoff between waiting and sleeping is roughly the time it
1193 * takes to sleep on a request, on the order of a microsecond.
1196 if (i915_gem_request_get_ring(req)->irq_refcount)
1199 timeout = local_clock_us(&cpu) + 5;
1200 while (!need_resched()) {
1201 if (i915_gem_request_completed(req, true))
1204 if (signal_pending_state(state, current))
1207 if (busywait_stop(timeout, cpu))
1210 cpu_relax_lowlatency();
1212 if (i915_gem_request_completed(req, false))
1219 * __i915_wait_request - wait until execution of request has finished
1221 * @reset_counter: reset sequence associated with the given request
1222 * @interruptible: do an interruptible wait (normally yes)
1223 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1225 * Note: It is of utmost importance that the passed in seqno and reset_counter
1226 * values have been read by the caller in an smp safe manner. Where read-side
1227 * locks are involved, it is sufficient to read the reset_counter before
1228 * unlocking the lock that protects the seqno. For lockless tricks, the
1229 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1232 * Returns 0 if the request was found within the alloted time. Else returns the
1233 * errno with remaining time filled in timeout argument.
1235 int __i915_wait_request(struct drm_i915_gem_request *req,
1236 unsigned reset_counter,
1239 struct intel_rps_client *rps)
1241 struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1242 struct drm_device *dev = ring->dev;
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 const bool irq_test_in_progress =
1245 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1246 int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1248 unsigned long timeout_expire;
1252 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1254 if (list_empty(&req->list))
1257 if (i915_gem_request_completed(req, true))
1262 if (WARN_ON(*timeout < 0))
1268 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1271 if (INTEL_INFO(dev_priv)->gen >= 6)
1272 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1274 /* Record current time in case interrupted by signal, or wedged */
1275 trace_i915_gem_request_wait_begin(req);
1276 before = ktime_get_raw_ns();
1278 /* Optimistic spin for the next jiffie before touching IRQs */
1279 ret = __i915_spin_request(req, state);
1283 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1289 struct timer_list timer;
1291 prepare_to_wait(&ring->irq_queue, &wait, state);
1293 /* We need to check whether any gpu reset happened in between
1294 * the caller grabbing the seqno and now ... */
1295 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1296 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1297 * is truely gone. */
1298 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1304 if (i915_gem_request_completed(req, false)) {
1309 if (signal_pending_state(state, current)) {
1314 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1319 timer.function = NULL;
1320 if (timeout || missed_irq(dev_priv, ring)) {
1321 unsigned long expire;
1323 setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1324 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1325 mod_timer(&timer, expire);
1330 if (timer.function) {
1331 del_singleshot_timer_sync(&timer);
1332 destroy_timer_on_stack(&timer);
1335 if (!irq_test_in_progress)
1336 ring->irq_put(ring);
1338 finish_wait(&ring->irq_queue, &wait);
1341 now = ktime_get_raw_ns();
1342 trace_i915_gem_request_wait_end(req);
1345 s64 tres = *timeout - (now - before);
1347 *timeout = tres < 0 ? 0 : tres;
1350 * Apparently ktime isn't accurate enough and occasionally has a
1351 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1352 * things up to make the test happy. We allow up to 1 jiffy.
1354 * This is a regrssion from the timespec->ktime conversion.
1356 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1363 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1364 struct drm_file *file)
1366 struct drm_i915_private *dev_private;
1367 struct drm_i915_file_private *file_priv;
1369 WARN_ON(!req || !file || req->file_priv);
1377 dev_private = req->ring->dev->dev_private;
1378 file_priv = file->driver_priv;
1380 spin_lock(&file_priv->mm.lock);
1381 req->file_priv = file_priv;
1382 list_add_tail(&req->client_list, &file_priv->mm.request_list);
1383 spin_unlock(&file_priv->mm.lock);
1385 req->pid = get_pid(task_pid(current));
1391 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1393 struct drm_i915_file_private *file_priv = request->file_priv;
1398 spin_lock(&file_priv->mm.lock);
1399 list_del(&request->client_list);
1400 request->file_priv = NULL;
1401 spin_unlock(&file_priv->mm.lock);
1403 put_pid(request->pid);
1404 request->pid = NULL;
1407 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1409 trace_i915_gem_request_retire(request);
1411 /* We know the GPU must have read the request to have
1412 * sent us the seqno + interrupt, so use the position
1413 * of tail of the request to update the last known position
1416 * Note this requires that we are always called in request
1419 request->ringbuf->last_retired_head = request->postfix;
1421 list_del_init(&request->list);
1422 i915_gem_request_remove_from_client(request);
1424 i915_gem_request_unreference(request);
1428 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1430 struct intel_engine_cs *engine = req->ring;
1431 struct drm_i915_gem_request *tmp;
1433 lockdep_assert_held(&engine->dev->struct_mutex);
1435 if (list_empty(&req->list))
1439 tmp = list_first_entry(&engine->request_list,
1440 typeof(*tmp), list);
1442 i915_gem_request_retire(tmp);
1443 } while (tmp != req);
1445 WARN_ON(i915_verify_lists(engine->dev));
1449 * Waits for a request to be signaled, and cleans up the
1450 * request and object lists appropriately for that event.
1453 i915_wait_request(struct drm_i915_gem_request *req)
1455 struct drm_device *dev;
1456 struct drm_i915_private *dev_priv;
1460 BUG_ON(req == NULL);
1462 dev = req->ring->dev;
1463 dev_priv = dev->dev_private;
1464 interruptible = dev_priv->mm.interruptible;
1466 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1468 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1472 ret = __i915_wait_request(req,
1473 atomic_read(&dev_priv->gpu_error.reset_counter),
1474 interruptible, NULL, NULL);
1478 __i915_gem_request_retire__upto(req);
1483 * Ensures that all rendering to the object has completed and the object is
1484 * safe to unbind from the GTT or access from the CPU.
1487 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1496 if (obj->last_write_req != NULL) {
1497 ret = i915_wait_request(obj->last_write_req);
1501 i = obj->last_write_req->ring->id;
1502 if (obj->last_read_req[i] == obj->last_write_req)
1503 i915_gem_object_retire__read(obj, i);
1505 i915_gem_object_retire__write(obj);
1508 for (i = 0; i < I915_NUM_RINGS; i++) {
1509 if (obj->last_read_req[i] == NULL)
1512 ret = i915_wait_request(obj->last_read_req[i]);
1516 i915_gem_object_retire__read(obj, i);
1518 RQ_BUG_ON(obj->active);
1525 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1526 struct drm_i915_gem_request *req)
1528 int ring = req->ring->id;
1530 if (obj->last_read_req[ring] == req)
1531 i915_gem_object_retire__read(obj, ring);
1532 else if (obj->last_write_req == req)
1533 i915_gem_object_retire__write(obj);
1535 __i915_gem_request_retire__upto(req);
1538 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1539 * as the object state may change during this call.
1541 static __must_check int
1542 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1543 struct intel_rps_client *rps,
1546 struct drm_device *dev = obj->base.dev;
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548 struct drm_i915_gem_request *requests[I915_NUM_RINGS];
1549 unsigned reset_counter;
1552 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1553 BUG_ON(!dev_priv->mm.interruptible);
1558 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1562 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1565 struct drm_i915_gem_request *req;
1567 req = obj->last_write_req;
1571 requests[n++] = i915_gem_request_reference(req);
1573 for (i = 0; i < I915_NUM_RINGS; i++) {
1574 struct drm_i915_gem_request *req;
1576 req = obj->last_read_req[i];
1580 requests[n++] = i915_gem_request_reference(req);
1584 mutex_unlock(&dev->struct_mutex);
1585 for (i = 0; ret == 0 && i < n; i++)
1586 ret = __i915_wait_request(requests[i], reset_counter, true,
1588 mutex_lock(&dev->struct_mutex);
1590 for (i = 0; i < n; i++) {
1592 i915_gem_object_retire_request(obj, requests[i]);
1593 i915_gem_request_unreference(requests[i]);
1599 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1601 struct drm_i915_file_private *fpriv = file->driver_priv;
1606 * Called when user space prepares to use an object with the CPU, either
1607 * through the mmap ioctl's mapping or a GTT mapping.
1610 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1611 struct drm_file *file)
1613 struct drm_i915_gem_set_domain *args = data;
1614 struct drm_i915_gem_object *obj;
1615 uint32_t read_domains = args->read_domains;
1616 uint32_t write_domain = args->write_domain;
1619 /* Only handle setting domains to types used by the CPU. */
1620 if (write_domain & I915_GEM_GPU_DOMAINS)
1623 if (read_domains & I915_GEM_GPU_DOMAINS)
1626 /* Having something in the write domain implies it's in the read
1627 * domain, and only that read domain. Enforce that in the request.
1629 if (write_domain != 0 && read_domains != write_domain)
1632 ret = i915_mutex_lock_interruptible(dev);
1636 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1637 if (&obj->base == NULL) {
1642 /* Try to flush the object off the GPU without holding the lock.
1643 * We will repeat the flush holding the lock in the normal manner
1644 * to catch cases where we are gazumped.
1646 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1647 to_rps_client(file),
1652 if (read_domains & I915_GEM_DOMAIN_GTT)
1653 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1655 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1657 if (write_domain != 0)
1658 intel_fb_obj_invalidate(obj,
1659 write_domain == I915_GEM_DOMAIN_GTT ?
1660 ORIGIN_GTT : ORIGIN_CPU);
1663 drm_gem_object_unreference(&obj->base);
1665 mutex_unlock(&dev->struct_mutex);
1670 * Called when user space has done writes to this buffer
1673 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file)
1676 struct drm_i915_gem_sw_finish *args = data;
1677 struct drm_i915_gem_object *obj;
1680 ret = i915_mutex_lock_interruptible(dev);
1684 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1685 if (&obj->base == NULL) {
1690 /* Pinned buffers may be scanout, so flush the cache */
1691 if (obj->pin_display)
1692 i915_gem_object_flush_cpu_write_domain(obj);
1694 drm_gem_object_unreference(&obj->base);
1696 mutex_unlock(&dev->struct_mutex);
1701 * Maps the contents of an object, returning the address it is mapped
1704 * While the mapping holds a reference on the contents of the object, it doesn't
1705 * imply a ref on the object itself.
1709 * DRM driver writers who look a this function as an example for how to do GEM
1710 * mmap support, please don't implement mmap support like here. The modern way
1711 * to implement DRM mmap support is with an mmap offset ioctl (like
1712 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1713 * That way debug tooling like valgrind will understand what's going on, hiding
1714 * the mmap call in a driver private ioctl will break that. The i915 driver only
1715 * does cpu mmaps this way because we didn't know better.
1718 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1719 struct drm_file *file)
1721 struct drm_i915_gem_mmap *args = data;
1722 struct drm_gem_object *obj;
1725 if (args->flags & ~(I915_MMAP_WC))
1728 if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1731 obj = drm_gem_object_lookup(dev, file, args->handle);
1735 /* prime objects have no backing filp to GEM mmap
1739 drm_gem_object_unreference_unlocked(obj);
1743 addr = vm_mmap(obj->filp, 0, args->size,
1744 PROT_READ | PROT_WRITE, MAP_SHARED,
1746 if (args->flags & I915_MMAP_WC) {
1747 struct mm_struct *mm = current->mm;
1748 struct vm_area_struct *vma;
1750 down_write(&mm->mmap_sem);
1751 vma = find_vma(mm, addr);
1754 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1757 up_write(&mm->mmap_sem);
1759 drm_gem_object_unreference_unlocked(obj);
1760 if (IS_ERR((void *)addr))
1763 args->addr_ptr = (uint64_t) addr;
1769 * i915_gem_fault - fault a page into the GTT
1770 * @vma: VMA in question
1773 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1774 * from userspace. The fault handler takes care of binding the object to
1775 * the GTT (if needed), allocating and programming a fence register (again,
1776 * only if needed based on whether the old reg is still valid or the object
1777 * is tiled) and inserting a new PTE into the faulting process.
1779 * Note that the faulting process may involve evicting existing objects
1780 * from the GTT and/or fence registers to make room. So performance may
1781 * suffer if the GTT working set is large or there are few fence registers
1784 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1786 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1787 struct drm_device *dev = obj->base.dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 struct i915_ggtt_view view = i915_ggtt_view_normal;
1790 pgoff_t page_offset;
1793 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1795 intel_runtime_pm_get(dev_priv);
1797 /* We don't use vmf->pgoff since that has the fake offset */
1798 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1801 ret = i915_mutex_lock_interruptible(dev);
1805 trace_i915_gem_object_fault(obj, page_offset, true, write);
1807 /* Try to flush the object off the GPU first without holding the lock.
1808 * Upon reacquiring the lock, we will perform our sanity checks and then
1809 * repeat the flush holding the lock in the normal manner to catch cases
1810 * where we are gazumped.
1812 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1816 /* Access to snoopable pages through the GTT is incoherent. */
1817 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1822 /* Use a partial view if the object is bigger than the aperture. */
1823 if (obj->base.size >= dev_priv->gtt.mappable_end &&
1824 obj->tiling_mode == I915_TILING_NONE) {
1825 static const unsigned int chunk_size = 256; // 1 MiB
1827 memset(&view, 0, sizeof(view));
1828 view.type = I915_GGTT_VIEW_PARTIAL;
1829 view.params.partial.offset = rounddown(page_offset, chunk_size);
1830 view.params.partial.size =
1833 (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1834 view.params.partial.offset);
1837 /* Now pin it into the GTT if needed */
1838 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1842 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1846 ret = i915_gem_object_get_fence(obj);
1850 /* Finally, remap it using the new GTT offset */
1851 pfn = dev_priv->gtt.mappable_base +
1852 i915_gem_obj_ggtt_offset_view(obj, &view);
1855 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1856 /* Overriding existing pages in partial view does not cause
1857 * us any trouble as TLBs are still valid because the fault
1858 * is due to userspace losing part of the mapping or never
1859 * having accessed it before (at this partials' range).
1861 unsigned long base = vma->vm_start +
1862 (view.params.partial.offset << PAGE_SHIFT);
1865 for (i = 0; i < view.params.partial.size; i++) {
1866 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1871 obj->fault_mappable = true;
1873 if (!obj->fault_mappable) {
1874 unsigned long size = min_t(unsigned long,
1875 vma->vm_end - vma->vm_start,
1879 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1880 ret = vm_insert_pfn(vma,
1881 (unsigned long)vma->vm_start + i * PAGE_SIZE,
1887 obj->fault_mappable = true;
1889 ret = vm_insert_pfn(vma,
1890 (unsigned long)vmf->virtual_address,
1894 i915_gem_object_ggtt_unpin_view(obj, &view);
1896 mutex_unlock(&dev->struct_mutex);
1901 * We eat errors when the gpu is terminally wedged to avoid
1902 * userspace unduly crashing (gl has no provisions for mmaps to
1903 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1904 * and so needs to be reported.
1906 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1907 ret = VM_FAULT_SIGBUS;
1912 * EAGAIN means the gpu is hung and we'll wait for the error
1913 * handler to reset everything when re-faulting in
1914 * i915_mutex_lock_interruptible.
1921 * EBUSY is ok: this just means that another thread
1922 * already did the job.
1924 ret = VM_FAULT_NOPAGE;
1931 ret = VM_FAULT_SIGBUS;
1934 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1935 ret = VM_FAULT_SIGBUS;
1939 intel_runtime_pm_put(dev_priv);
1944 * i915_gem_release_mmap - remove physical page mappings
1945 * @obj: obj in question
1947 * Preserve the reservation of the mmapping with the DRM core code, but
1948 * relinquish ownership of the pages back to the system.
1950 * It is vital that we remove the page mapping if we have mapped a tiled
1951 * object through the GTT and then lose the fence register due to
1952 * resource pressure. Similarly if the object has been moved out of the
1953 * aperture, than pages mapped into userspace must be revoked. Removing the
1954 * mapping will then trigger a page fault on the next user access, allowing
1955 * fixup by i915_gem_fault().
1958 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1960 if (!obj->fault_mappable)
1963 drm_vma_node_unmap(&obj->base.vma_node,
1964 obj->base.dev->anon_inode->i_mapping);
1965 obj->fault_mappable = false;
1969 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1971 struct drm_i915_gem_object *obj;
1973 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1974 i915_gem_release_mmap(obj);
1978 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1982 if (INTEL_INFO(dev)->gen >= 4 ||
1983 tiling_mode == I915_TILING_NONE)
1986 /* Previous chips need a power-of-two fence region when tiling */
1987 if (INTEL_INFO(dev)->gen == 3)
1988 gtt_size = 1024*1024;
1990 gtt_size = 512*1024;
1992 while (gtt_size < size)
1999 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2000 * @obj: object to check
2002 * Return the required GTT alignment for an object, taking into account
2003 * potential fence register mapping.
2006 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2007 int tiling_mode, bool fenced)
2010 * Minimum alignment is 4k (GTT page size), but might be greater
2011 * if a fence register is needed for the object.
2013 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2014 tiling_mode == I915_TILING_NONE)
2018 * Previous chips need to be aligned to the size of the smallest
2019 * fence register that can contain the object.
2021 return i915_gem_get_gtt_size(dev, size, tiling_mode);
2024 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2026 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2029 if (drm_vma_node_has_offset(&obj->base.vma_node))
2032 dev_priv->mm.shrinker_no_lock_stealing = true;
2034 ret = drm_gem_create_mmap_offset(&obj->base);
2038 /* Badly fragmented mmap space? The only way we can recover
2039 * space is by destroying unwanted objects. We can't randomly release
2040 * mmap_offsets as userspace expects them to be persistent for the
2041 * lifetime of the objects. The closest we can is to release the
2042 * offsets on purgeable objects by truncating it and marking it purged,
2043 * which prevents userspace from ever using that object again.
2045 i915_gem_shrink(dev_priv,
2046 obj->base.size >> PAGE_SHIFT,
2048 I915_SHRINK_UNBOUND |
2049 I915_SHRINK_PURGEABLE);
2050 ret = drm_gem_create_mmap_offset(&obj->base);
2054 i915_gem_shrink_all(dev_priv);
2055 ret = drm_gem_create_mmap_offset(&obj->base);
2057 dev_priv->mm.shrinker_no_lock_stealing = false;
2062 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2064 drm_gem_free_mmap_offset(&obj->base);
2068 i915_gem_mmap_gtt(struct drm_file *file,
2069 struct drm_device *dev,
2073 struct drm_i915_gem_object *obj;
2076 ret = i915_mutex_lock_interruptible(dev);
2080 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2081 if (&obj->base == NULL) {
2086 if (obj->madv != I915_MADV_WILLNEED) {
2087 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2092 ret = i915_gem_object_create_mmap_offset(obj);
2096 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2099 drm_gem_object_unreference(&obj->base);
2101 mutex_unlock(&dev->struct_mutex);
2106 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2108 * @data: GTT mapping ioctl data
2109 * @file: GEM object info
2111 * Simply returns the fake offset to userspace so it can mmap it.
2112 * The mmap call will end up in drm_gem_mmap(), which will set things
2113 * up so we can get faults in the handler above.
2115 * The fault handler will take care of binding the object into the GTT
2116 * (since it may have been evicted to make room for something), allocating
2117 * a fence register, and mapping the appropriate aperture address into
2121 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *file)
2124 struct drm_i915_gem_mmap_gtt *args = data;
2126 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2129 /* Immediately discard the backing storage */
2131 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2133 i915_gem_object_free_mmap_offset(obj);
2135 if (obj->base.filp == NULL)
2138 /* Our goal here is to return as much of the memory as
2139 * is possible back to the system as we are called from OOM.
2140 * To do this we must instruct the shmfs to drop all of its
2141 * backing pages, *now*.
2143 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2144 obj->madv = __I915_MADV_PURGED;
2147 /* Try to discard unwanted pages */
2149 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2151 struct address_space *mapping;
2153 switch (obj->madv) {
2154 case I915_MADV_DONTNEED:
2155 i915_gem_object_truncate(obj);
2156 case __I915_MADV_PURGED:
2160 if (obj->base.filp == NULL)
2163 mapping = file_inode(obj->base.filp)->i_mapping,
2164 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2168 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2170 struct sg_page_iter sg_iter;
2173 BUG_ON(obj->madv == __I915_MADV_PURGED);
2175 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2177 /* In the event of a disaster, abandon all caches and
2178 * hope for the best.
2180 WARN_ON(ret != -EIO);
2181 i915_gem_clflush_object(obj, true);
2182 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2185 i915_gem_gtt_finish_object(obj);
2187 if (i915_gem_object_needs_bit17_swizzle(obj))
2188 i915_gem_object_save_bit_17_swizzle(obj);
2190 if (obj->madv == I915_MADV_DONTNEED)
2193 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2194 struct page *page = sg_page_iter_page(&sg_iter);
2197 set_page_dirty(page);
2199 if (obj->madv == I915_MADV_WILLNEED)
2200 mark_page_accessed(page);
2202 page_cache_release(page);
2206 sg_free_table(obj->pages);
2211 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2213 const struct drm_i915_gem_object_ops *ops = obj->ops;
2215 if (obj->pages == NULL)
2218 if (obj->pages_pin_count)
2221 BUG_ON(i915_gem_obj_bound_any(obj));
2223 /* ->put_pages might need to allocate memory for the bit17 swizzle
2224 * array, hence protect them from being reaped by removing them from gtt
2226 list_del(&obj->global_list);
2228 ops->put_pages(obj);
2231 i915_gem_object_invalidate(obj);
2237 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2239 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 struct address_space *mapping;
2242 struct sg_table *st;
2243 struct scatterlist *sg;
2244 struct sg_page_iter sg_iter;
2246 unsigned long last_pfn = 0; /* suppress gcc warning */
2250 /* Assert that the object is not currently in any GPU domain. As it
2251 * wasn't in the GTT, there shouldn't be any way it could have been in
2254 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2255 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2257 st = kmalloc(sizeof(*st), GFP_KERNEL);
2261 page_count = obj->base.size / PAGE_SIZE;
2262 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2267 /* Get the list of pages out of our struct file. They'll be pinned
2268 * at this point until we release them.
2270 * Fail silently without starting the shrinker
2272 mapping = file_inode(obj->base.filp)->i_mapping;
2273 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2274 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2277 for (i = 0; i < page_count; i++) {
2278 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2280 i915_gem_shrink(dev_priv,
2283 I915_SHRINK_UNBOUND |
2284 I915_SHRINK_PURGEABLE);
2285 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2288 /* We've tried hard to allocate the memory by reaping
2289 * our own buffer, now let the real VM do its job and
2290 * go down in flames if truly OOM.
2292 i915_gem_shrink_all(dev_priv);
2293 page = shmem_read_mapping_page(mapping, i);
2295 ret = PTR_ERR(page);
2299 #ifdef CONFIG_SWIOTLB
2300 if (swiotlb_nr_tbl()) {
2302 sg_set_page(sg, page, PAGE_SIZE, 0);
2307 if (!i || page_to_pfn(page) != last_pfn + 1) {
2311 sg_set_page(sg, page, PAGE_SIZE, 0);
2313 sg->length += PAGE_SIZE;
2315 last_pfn = page_to_pfn(page);
2317 /* Check that the i965g/gm workaround works. */
2318 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2320 #ifdef CONFIG_SWIOTLB
2321 if (!swiotlb_nr_tbl())
2326 ret = i915_gem_gtt_prepare_object(obj);
2330 if (i915_gem_object_needs_bit17_swizzle(obj))
2331 i915_gem_object_do_bit_17_swizzle(obj);
2333 if (obj->tiling_mode != I915_TILING_NONE &&
2334 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2335 i915_gem_object_pin_pages(obj);
2341 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2342 page_cache_release(sg_page_iter_page(&sg_iter));
2346 /* shmemfs first checks if there is enough memory to allocate the page
2347 * and reports ENOSPC should there be insufficient, along with the usual
2348 * ENOMEM for a genuine allocation failure.
2350 * We use ENOSPC in our driver to mean that we have run out of aperture
2351 * space and so want to translate the error from shmemfs back to our
2352 * usual understanding of ENOMEM.
2360 /* Ensure that the associated pages are gathered from the backing storage
2361 * and pinned into our object. i915_gem_object_get_pages() may be called
2362 * multiple times before they are released by a single call to
2363 * i915_gem_object_put_pages() - once the pages are no longer referenced
2364 * either as a result of memory pressure (reaping pages under the shrinker)
2365 * or as the object is itself released.
2368 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2370 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2371 const struct drm_i915_gem_object_ops *ops = obj->ops;
2377 if (obj->madv != I915_MADV_WILLNEED) {
2378 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2382 BUG_ON(obj->pages_pin_count);
2384 ret = ops->get_pages(obj);
2388 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2390 obj->get_page.sg = obj->pages->sgl;
2391 obj->get_page.last = 0;
2396 void i915_vma_move_to_active(struct i915_vma *vma,
2397 struct drm_i915_gem_request *req)
2399 struct drm_i915_gem_object *obj = vma->obj;
2400 struct intel_engine_cs *ring;
2402 ring = i915_gem_request_get_ring(req);
2404 /* Add a reference if we're newly entering the active list. */
2405 if (obj->active == 0)
2406 drm_gem_object_reference(&obj->base);
2407 obj->active |= intel_ring_flag(ring);
2409 list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
2410 i915_gem_request_assign(&obj->last_read_req[ring->id], req);
2412 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2416 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2418 RQ_BUG_ON(obj->last_write_req == NULL);
2419 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
2421 i915_gem_request_assign(&obj->last_write_req, NULL);
2422 intel_fb_obj_flush(obj, true, ORIGIN_CS);
2426 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2428 struct i915_vma *vma;
2430 RQ_BUG_ON(obj->last_read_req[ring] == NULL);
2431 RQ_BUG_ON(!(obj->active & (1 << ring)));
2433 list_del_init(&obj->ring_list[ring]);
2434 i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2436 if (obj->last_write_req && obj->last_write_req->ring->id == ring)
2437 i915_gem_object_retire__write(obj);
2439 obj->active &= ~(1 << ring);
2443 /* Bump our place on the bound list to keep it roughly in LRU order
2444 * so that we don't steal from recently used but inactive objects
2445 * (unless we are forced to ofc!)
2447 list_move_tail(&obj->global_list,
2448 &to_i915(obj->base.dev)->mm.bound_list);
2450 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2451 if (!list_empty(&vma->mm_list))
2452 list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2455 i915_gem_request_assign(&obj->last_fenced_req, NULL);
2456 drm_gem_object_unreference(&obj->base);
2460 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 struct intel_engine_cs *ring;
2466 /* Carefully retire all requests without writing to the rings */
2467 for_each_ring(ring, dev_priv, i) {
2468 ret = intel_ring_idle(ring);
2472 i915_gem_retire_requests(dev);
2474 /* Finally reset hw state */
2475 for_each_ring(ring, dev_priv, i) {
2476 intel_ring_init_seqno(ring, seqno);
2478 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2479 ring->semaphore.sync_seqno[j] = 0;
2485 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2493 /* HWS page needs to be set less than what we
2494 * will inject to ring
2496 ret = i915_gem_init_seqno(dev, seqno - 1);
2500 /* Carefully set the last_seqno value so that wrap
2501 * detection still works
2503 dev_priv->next_seqno = seqno;
2504 dev_priv->last_seqno = seqno - 1;
2505 if (dev_priv->last_seqno == 0)
2506 dev_priv->last_seqno--;
2512 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2516 /* reserve 0 for non-seqno */
2517 if (dev_priv->next_seqno == 0) {
2518 int ret = i915_gem_init_seqno(dev, 0);
2522 dev_priv->next_seqno = 1;
2525 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2530 * NB: This function is not allowed to fail. Doing so would mean the the
2531 * request is not being tracked for completion but the work itself is
2532 * going to happen on the hardware. This would be a Bad Thing(tm).
2534 void __i915_add_request(struct drm_i915_gem_request *request,
2535 struct drm_i915_gem_object *obj,
2538 struct intel_engine_cs *ring;
2539 struct drm_i915_private *dev_priv;
2540 struct intel_ringbuffer *ringbuf;
2544 if (WARN_ON(request == NULL))
2547 ring = request->ring;
2548 dev_priv = ring->dev->dev_private;
2549 ringbuf = request->ringbuf;
2552 * To ensure that this call will not fail, space for its emissions
2553 * should already have been reserved in the ring buffer. Let the ring
2554 * know that it is time to use that space up.
2556 intel_ring_reserved_space_use(ringbuf);
2558 request_start = intel_ring_get_tail(ringbuf);
2560 * Emit any outstanding flushes - execbuf can fail to emit the flush
2561 * after having emitted the batchbuffer command. Hence we need to fix
2562 * things up similar to emitting the lazy request. The difference here
2563 * is that the flush _must_ happen before the next request, no matter
2567 if (i915.enable_execlists)
2568 ret = logical_ring_flush_all_caches(request);
2570 ret = intel_ring_flush_all_caches(request);
2571 /* Not allowed to fail! */
2572 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2575 /* Record the position of the start of the request so that
2576 * should we detect the updated seqno part-way through the
2577 * GPU processing the request, we never over-estimate the
2578 * position of the head.
2580 request->postfix = intel_ring_get_tail(ringbuf);
2582 if (i915.enable_execlists)
2583 ret = ring->emit_request(request);
2585 ret = ring->add_request(request);
2587 request->tail = intel_ring_get_tail(ringbuf);
2589 /* Not allowed to fail! */
2590 WARN(ret, "emit|add_request failed: %d!\n", ret);
2592 request->head = request_start;
2594 /* Whilst this request exists, batch_obj will be on the
2595 * active_list, and so will hold the active reference. Only when this
2596 * request is retired will the the batch_obj be moved onto the
2597 * inactive_list and lose its active reference. Hence we do not need
2598 * to explicitly hold another reference here.
2600 request->batch_obj = obj;
2602 request->emitted_jiffies = jiffies;
2603 ring->last_submitted_seqno = request->seqno;
2604 list_add_tail(&request->list, &ring->request_list);
2606 trace_i915_gem_request_add(request);
2608 i915_queue_hangcheck(ring->dev);
2610 queue_delayed_work(dev_priv->wq,
2611 &dev_priv->mm.retire_work,
2612 round_jiffies_up_relative(HZ));
2613 intel_mark_busy(dev_priv->dev);
2615 /* Sanity check that the reserved size was large enough. */
2616 intel_ring_reserved_space_end(ringbuf);
2619 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2620 const struct intel_context *ctx)
2622 unsigned long elapsed;
2624 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2626 if (ctx->hang_stats.banned)
2629 if (ctx->hang_stats.ban_period_seconds &&
2630 elapsed <= ctx->hang_stats.ban_period_seconds) {
2631 if (!i915_gem_context_is_default(ctx)) {
2632 DRM_DEBUG("context hanging too fast, banning!\n");
2634 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2635 if (i915_stop_ring_allow_warn(dev_priv))
2636 DRM_ERROR("gpu hanging too fast, banning!\n");
2644 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2645 struct intel_context *ctx,
2648 struct i915_ctx_hang_stats *hs;
2653 hs = &ctx->hang_stats;
2656 hs->banned = i915_context_is_banned(dev_priv, ctx);
2658 hs->guilty_ts = get_seconds();
2660 hs->batch_pending++;
2664 void i915_gem_request_free(struct kref *req_ref)
2666 struct drm_i915_gem_request *req = container_of(req_ref,
2668 struct intel_context *ctx = req->ctx;
2671 i915_gem_request_remove_from_client(req);
2674 if (i915.enable_execlists) {
2675 if (ctx != req->ring->default_context)
2676 intel_lr_context_unpin(req);
2679 i915_gem_context_unreference(ctx);
2682 kmem_cache_free(req->i915->requests, req);
2685 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2686 struct intel_context *ctx,
2687 struct drm_i915_gem_request **req_out)
2689 struct drm_i915_private *dev_priv = to_i915(ring->dev);
2690 struct drm_i915_gem_request *req;
2698 req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2702 ret = i915_gem_get_seqno(ring->dev, &req->seqno);
2706 kref_init(&req->ref);
2707 req->i915 = dev_priv;
2710 i915_gem_context_reference(req->ctx);
2712 if (i915.enable_execlists)
2713 ret = intel_logical_ring_alloc_request_extras(req);
2715 ret = intel_ring_alloc_request_extras(req);
2717 i915_gem_context_unreference(req->ctx);
2722 * Reserve space in the ring buffer for all the commands required to
2723 * eventually emit this request. This is to guarantee that the
2724 * i915_add_request() call can't fail. Note that the reserve may need
2725 * to be redone if the request is not actually submitted straight
2726 * away, e.g. because a GPU scheduler has deferred it.
2728 if (i915.enable_execlists)
2729 ret = intel_logical_ring_reserve_space(req);
2731 ret = intel_ring_reserve_space(req);
2734 * At this point, the request is fully allocated even if not
2735 * fully prepared. Thus it can be cleaned up using the proper
2738 i915_gem_request_cancel(req);
2746 kmem_cache_free(dev_priv->requests, req);
2750 void i915_gem_request_cancel(struct drm_i915_gem_request *req)
2752 intel_ring_reserved_space_cancel(req->ringbuf);
2754 i915_gem_request_unreference(req);
2757 struct drm_i915_gem_request *
2758 i915_gem_find_active_request(struct intel_engine_cs *ring)
2760 struct drm_i915_gem_request *request;
2762 list_for_each_entry(request, &ring->request_list, list) {
2763 if (i915_gem_request_completed(request, false))
2772 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2773 struct intel_engine_cs *ring)
2775 struct drm_i915_gem_request *request;
2778 request = i915_gem_find_active_request(ring);
2780 if (request == NULL)
2783 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2785 i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2787 list_for_each_entry_continue(request, &ring->request_list, list)
2788 i915_set_reset_status(dev_priv, request->ctx, false);
2791 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2792 struct intel_engine_cs *ring)
2794 while (!list_empty(&ring->active_list)) {
2795 struct drm_i915_gem_object *obj;
2797 obj = list_first_entry(&ring->active_list,
2798 struct drm_i915_gem_object,
2799 ring_list[ring->id]);
2801 i915_gem_object_retire__read(obj, ring->id);
2805 * Clear the execlists queue up before freeing the requests, as those
2806 * are the ones that keep the context and ringbuffer backing objects
2809 while (!list_empty(&ring->execlist_queue)) {
2810 struct drm_i915_gem_request *submit_req;
2812 submit_req = list_first_entry(&ring->execlist_queue,
2813 struct drm_i915_gem_request,
2815 list_del(&submit_req->execlist_link);
2817 if (submit_req->ctx != ring->default_context)
2818 intel_lr_context_unpin(submit_req);
2820 i915_gem_request_unreference(submit_req);
2824 * We must free the requests after all the corresponding objects have
2825 * been moved off active lists. Which is the same order as the normal
2826 * retire_requests function does. This is important if object hold
2827 * implicit references on things like e.g. ppgtt address spaces through
2830 while (!list_empty(&ring->request_list)) {
2831 struct drm_i915_gem_request *request;
2833 request = list_first_entry(&ring->request_list,
2834 struct drm_i915_gem_request,
2837 i915_gem_request_retire(request);
2841 void i915_gem_reset(struct drm_device *dev)
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844 struct intel_engine_cs *ring;
2848 * Before we free the objects from the requests, we need to inspect
2849 * them for finding the guilty party. As the requests only borrow
2850 * their reference to the objects, the inspection must be done first.
2852 for_each_ring(ring, dev_priv, i)
2853 i915_gem_reset_ring_status(dev_priv, ring);
2855 for_each_ring(ring, dev_priv, i)
2856 i915_gem_reset_ring_cleanup(dev_priv, ring);
2858 i915_gem_context_reset(dev);
2860 i915_gem_restore_fences(dev);
2862 WARN_ON(i915_verify_lists(dev));
2866 * This function clears the request list as sequence numbers are passed.
2869 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2871 WARN_ON(i915_verify_lists(ring->dev));
2873 /* Retire requests first as we use it above for the early return.
2874 * If we retire requests last, we may use a later seqno and so clear
2875 * the requests lists without clearing the active list, leading to
2878 while (!list_empty(&ring->request_list)) {
2879 struct drm_i915_gem_request *request;
2881 request = list_first_entry(&ring->request_list,
2882 struct drm_i915_gem_request,
2885 if (!i915_gem_request_completed(request, true))
2888 i915_gem_request_retire(request);
2891 /* Move any buffers on the active list that are no longer referenced
2892 * by the ringbuffer to the flushing/inactive lists as appropriate,
2893 * before we free the context associated with the requests.
2895 while (!list_empty(&ring->active_list)) {
2896 struct drm_i915_gem_object *obj;
2898 obj = list_first_entry(&ring->active_list,
2899 struct drm_i915_gem_object,
2900 ring_list[ring->id]);
2902 if (!list_empty(&obj->last_read_req[ring->id]->list))
2905 i915_gem_object_retire__read(obj, ring->id);
2908 if (unlikely(ring->trace_irq_req &&
2909 i915_gem_request_completed(ring->trace_irq_req, true))) {
2910 ring->irq_put(ring);
2911 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2914 WARN_ON(i915_verify_lists(ring->dev));
2918 i915_gem_retire_requests(struct drm_device *dev)
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 struct intel_engine_cs *ring;
2925 for_each_ring(ring, dev_priv, i) {
2926 i915_gem_retire_requests_ring(ring);
2927 idle &= list_empty(&ring->request_list);
2928 if (i915.enable_execlists) {
2929 unsigned long flags;
2931 spin_lock_irqsave(&ring->execlist_lock, flags);
2932 idle &= list_empty(&ring->execlist_queue);
2933 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2935 intel_execlists_retire_requests(ring);
2940 mod_delayed_work(dev_priv->wq,
2941 &dev_priv->mm.idle_work,
2942 msecs_to_jiffies(100));
2948 i915_gem_retire_work_handler(struct work_struct *work)
2950 struct drm_i915_private *dev_priv =
2951 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2952 struct drm_device *dev = dev_priv->dev;
2955 /* Come back later if the device is busy... */
2957 if (mutex_trylock(&dev->struct_mutex)) {
2958 idle = i915_gem_retire_requests(dev);
2959 mutex_unlock(&dev->struct_mutex);
2962 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2963 round_jiffies_up_relative(HZ));
2967 i915_gem_idle_work_handler(struct work_struct *work)
2969 struct drm_i915_private *dev_priv =
2970 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2971 struct drm_device *dev = dev_priv->dev;
2972 struct intel_engine_cs *ring;
2975 for_each_ring(ring, dev_priv, i)
2976 if (!list_empty(&ring->request_list))
2979 intel_mark_idle(dev);
2981 if (mutex_trylock(&dev->struct_mutex)) {
2982 struct intel_engine_cs *ring;
2985 for_each_ring(ring, dev_priv, i)
2986 i915_gem_batch_pool_fini(&ring->batch_pool);
2988 mutex_unlock(&dev->struct_mutex);
2993 * Ensures that an object will eventually get non-busy by flushing any required
2994 * write domains, emitting any outstanding lazy request and retiring and
2995 * completed requests.
2998 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3005 for (i = 0; i < I915_NUM_RINGS; i++) {
3006 struct drm_i915_gem_request *req;
3008 req = obj->last_read_req[i];
3012 if (list_empty(&req->list))
3015 if (i915_gem_request_completed(req, true)) {
3016 __i915_gem_request_retire__upto(req);
3018 i915_gem_object_retire__read(obj, i);
3026 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3027 * @DRM_IOCTL_ARGS: standard ioctl arguments
3029 * Returns 0 if successful, else an error is returned with the remaining time in
3030 * the timeout parameter.
3031 * -ETIME: object is still busy after timeout
3032 * -ERESTARTSYS: signal interrupted the wait
3033 * -ENONENT: object doesn't exist
3034 * Also possible, but rare:
3035 * -EAGAIN: GPU wedged
3037 * -ENODEV: Internal IRQ fail
3038 * -E?: The add request failed
3040 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3041 * non-zero timeout parameter the wait ioctl will wait for the given number of
3042 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3043 * without holding struct_mutex the object may become re-busied before this
3044 * function completes. A similar but shorter * race condition exists in the busy
3048 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct drm_i915_gem_wait *args = data;
3052 struct drm_i915_gem_object *obj;
3053 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3054 unsigned reset_counter;
3058 if (args->flags != 0)
3061 ret = i915_mutex_lock_interruptible(dev);
3065 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
3066 if (&obj->base == NULL) {
3067 mutex_unlock(&dev->struct_mutex);
3071 /* Need to make sure the object gets inactive eventually. */
3072 ret = i915_gem_object_flush_active(obj);
3079 /* Do this after OLR check to make sure we make forward progress polling
3080 * on this IOCTL with a timeout == 0 (like busy ioctl)
3082 if (args->timeout_ns == 0) {
3087 drm_gem_object_unreference(&obj->base);
3088 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3090 for (i = 0; i < I915_NUM_RINGS; i++) {
3091 if (obj->last_read_req[i] == NULL)
3094 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3097 mutex_unlock(&dev->struct_mutex);
3099 for (i = 0; i < n; i++) {
3101 ret = __i915_wait_request(req[i], reset_counter, true,
3102 args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3104 i915_gem_request_unreference__unlocked(req[i]);
3109 drm_gem_object_unreference(&obj->base);
3110 mutex_unlock(&dev->struct_mutex);
3115 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3116 struct intel_engine_cs *to,
3117 struct drm_i915_gem_request *from_req,
3118 struct drm_i915_gem_request **to_req)
3120 struct intel_engine_cs *from;
3123 from = i915_gem_request_get_ring(from_req);
3127 if (i915_gem_request_completed(from_req, true))
3130 if (!i915_semaphore_is_enabled(obj->base.dev)) {
3131 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3132 ret = __i915_wait_request(from_req,
3133 atomic_read(&i915->gpu_error.reset_counter),
3134 i915->mm.interruptible,
3136 &i915->rps.semaphores);
3140 i915_gem_object_retire_request(obj, from_req);
3142 int idx = intel_ring_sync_index(from, to);
3143 u32 seqno = i915_gem_request_get_seqno(from_req);
3147 if (seqno <= from->semaphore.sync_seqno[idx])
3150 if (*to_req == NULL) {
3151 ret = i915_gem_request_alloc(to, to->default_context, to_req);
3156 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3157 ret = to->semaphore.sync_to(*to_req, from, seqno);
3161 /* We use last_read_req because sync_to()
3162 * might have just caused seqno wrap under
3165 from->semaphore.sync_seqno[idx] =
3166 i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3173 * i915_gem_object_sync - sync an object to a ring.
3175 * @obj: object which may be in use on another ring.
3176 * @to: ring we wish to use the object on. May be NULL.
3177 * @to_req: request we wish to use the object for. See below.
3178 * This will be allocated and returned if a request is
3179 * required but not passed in.
3181 * This code is meant to abstract object synchronization with the GPU.
3182 * Calling with NULL implies synchronizing the object with the CPU
3183 * rather than a particular GPU ring. Conceptually we serialise writes
3184 * between engines inside the GPU. We only allow one engine to write
3185 * into a buffer at any time, but multiple readers. To ensure each has
3186 * a coherent view of memory, we must:
3188 * - If there is an outstanding write request to the object, the new
3189 * request must wait for it to complete (either CPU or in hw, requests
3190 * on the same ring will be naturally ordered).
3192 * - If we are a write request (pending_write_domain is set), the new
3193 * request must wait for outstanding read requests to complete.
3195 * For CPU synchronisation (NULL to) no request is required. For syncing with
3196 * rings to_req must be non-NULL. However, a request does not have to be
3197 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3198 * request will be allocated automatically and returned through *to_req. Note
3199 * that it is not guaranteed that commands will be emitted (because the system
3200 * might already be idle). Hence there is no need to create a request that
3201 * might never have any work submitted. Note further that if a request is
3202 * returned in *to_req, it is the responsibility of the caller to submit
3203 * that request (after potentially adding more work to it).
3205 * Returns 0 if successful, else propagates up the lower layer error.
3208 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3209 struct intel_engine_cs *to,
3210 struct drm_i915_gem_request **to_req)
3212 const bool readonly = obj->base.pending_write_domain == 0;
3213 struct drm_i915_gem_request *req[I915_NUM_RINGS];
3220 return i915_gem_object_wait_rendering(obj, readonly);
3224 if (obj->last_write_req)
3225 req[n++] = obj->last_write_req;
3227 for (i = 0; i < I915_NUM_RINGS; i++)
3228 if (obj->last_read_req[i])
3229 req[n++] = obj->last_read_req[i];
3231 for (i = 0; i < n; i++) {
3232 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3240 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3242 u32 old_write_domain, old_read_domains;
3244 /* Force a pagefault for domain tracking on next user access */
3245 i915_gem_release_mmap(obj);
3247 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3250 /* Wait for any direct GTT access to complete */
3253 old_read_domains = obj->base.read_domains;
3254 old_write_domain = obj->base.write_domain;
3256 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3257 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3259 trace_i915_gem_object_change_domain(obj,
3264 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3266 struct drm_i915_gem_object *obj = vma->obj;
3267 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3270 if (list_empty(&vma->vma_link))
3273 if (!drm_mm_node_allocated(&vma->node)) {
3274 i915_gem_vma_destroy(vma);
3281 BUG_ON(obj->pages == NULL);
3284 ret = i915_gem_object_wait_rendering(obj, false);
3289 if (i915_is_ggtt(vma->vm) &&
3290 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3291 i915_gem_object_finish_gtt(obj);
3293 /* release the fence reg _after_ flushing */
3294 ret = i915_gem_object_put_fence(obj);
3299 trace_i915_vma_unbind(vma);
3301 vma->vm->unbind_vma(vma);
3304 list_del_init(&vma->mm_list);
3305 if (i915_is_ggtt(vma->vm)) {
3306 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3307 obj->map_and_fenceable = false;
3308 } else if (vma->ggtt_view.pages) {
3309 sg_free_table(vma->ggtt_view.pages);
3310 kfree(vma->ggtt_view.pages);
3312 vma->ggtt_view.pages = NULL;
3315 drm_mm_remove_node(&vma->node);
3316 i915_gem_vma_destroy(vma);
3318 /* Since the unbound list is global, only move to that list if
3319 * no more VMAs exist. */
3320 if (list_empty(&obj->vma_list))
3321 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3323 /* And finally now the object is completely decoupled from this vma,
3324 * we can drop its hold on the backing storage and allow it to be
3325 * reaped by the shrinker.
3327 i915_gem_object_unpin_pages(obj);
3332 int i915_vma_unbind(struct i915_vma *vma)
3334 return __i915_vma_unbind(vma, true);
3337 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3339 return __i915_vma_unbind(vma, false);
3342 int i915_gpu_idle(struct drm_device *dev)
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_engine_cs *ring;
3348 /* Flush everything onto the inactive list. */
3349 for_each_ring(ring, dev_priv, i) {
3350 if (!i915.enable_execlists) {
3351 struct drm_i915_gem_request *req;
3353 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
3357 ret = i915_switch_context(req);
3359 i915_gem_request_cancel(req);
3363 i915_add_request_no_flush(req);
3366 ret = intel_ring_idle(ring);
3371 WARN_ON(i915_verify_lists(dev));
3375 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3376 unsigned long cache_level)
3378 struct drm_mm_node *gtt_space = &vma->node;
3379 struct drm_mm_node *other;
3382 * On some machines we have to be careful when putting differing types
3383 * of snoopable memory together to avoid the prefetcher crossing memory
3384 * domains and dying. During vm initialisation, we decide whether or not
3385 * these constraints apply and set the drm_mm.color_adjust
3388 if (vma->vm->mm.color_adjust == NULL)
3391 if (!drm_mm_node_allocated(gtt_space))
3394 if (list_empty(>t_space->node_list))
3397 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3398 if (other->allocated && !other->hole_follows && other->color != cache_level)
3401 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3402 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3409 * Finds free space in the GTT aperture and binds the object or a view of it
3412 static struct i915_vma *
3413 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3414 struct i915_address_space *vm,
3415 const struct i915_ggtt_view *ggtt_view,
3419 struct drm_device *dev = obj->base.dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 u32 fence_alignment, unfenced_alignment;
3422 u32 search_flag, alloc_flag;
3424 u64 size, fence_size;
3425 struct i915_vma *vma;
3428 if (i915_is_ggtt(vm)) {
3431 if (WARN_ON(!ggtt_view))
3432 return ERR_PTR(-EINVAL);
3434 view_size = i915_ggtt_view_size(obj, ggtt_view);
3436 fence_size = i915_gem_get_gtt_size(dev,
3439 fence_alignment = i915_gem_get_gtt_alignment(dev,
3443 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3447 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3449 fence_size = i915_gem_get_gtt_size(dev,
3452 fence_alignment = i915_gem_get_gtt_alignment(dev,
3456 unfenced_alignment =
3457 i915_gem_get_gtt_alignment(dev,
3461 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3464 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3466 if (flags & PIN_MAPPABLE)
3467 end = min_t(u64, end, dev_priv->gtt.mappable_end);
3468 if (flags & PIN_ZONE_4G)
3469 end = min_t(u64, end, (1ULL << 32));
3472 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3474 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3475 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3476 ggtt_view ? ggtt_view->type : 0,
3478 return ERR_PTR(-EINVAL);
3481 /* If binding the object/GGTT view requires more space than the entire
3482 * aperture has, reject it early before evicting everything in a vain
3483 * attempt to find space.
3486 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3487 ggtt_view ? ggtt_view->type : 0,
3489 flags & PIN_MAPPABLE ? "mappable" : "total",
3491 return ERR_PTR(-E2BIG);
3494 ret = i915_gem_object_get_pages(obj);
3496 return ERR_PTR(ret);
3498 i915_gem_object_pin_pages(obj);
3500 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3501 i915_gem_obj_lookup_or_create_vma(obj, vm);
3506 if (flags & PIN_HIGH) {
3507 search_flag = DRM_MM_SEARCH_BELOW;
3508 alloc_flag = DRM_MM_CREATE_TOP;
3510 search_flag = DRM_MM_SEARCH_DEFAULT;
3511 alloc_flag = DRM_MM_CREATE_DEFAULT;
3515 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3522 ret = i915_gem_evict_something(dev, vm, size, alignment,
3531 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3533 goto err_remove_node;
3536 trace_i915_vma_bind(vma, flags);
3537 ret = i915_vma_bind(vma, obj->cache_level, flags);
3539 goto err_remove_node;
3541 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3542 list_add_tail(&vma->mm_list, &vm->inactive_list);
3547 drm_mm_remove_node(&vma->node);
3549 i915_gem_vma_destroy(vma);
3552 i915_gem_object_unpin_pages(obj);
3557 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3560 /* If we don't have a page list set up, then we're not pinned
3561 * to GPU, and we can ignore the cache flush because it'll happen
3562 * again at bind time.
3564 if (obj->pages == NULL)
3568 * Stolen memory is always coherent with the GPU as it is explicitly
3569 * marked as wc by the system, or the system is cache-coherent.
3571 if (obj->stolen || obj->phys_handle)
3574 /* If the GPU is snooping the contents of the CPU cache,
3575 * we do not need to manually clear the CPU cache lines. However,
3576 * the caches are only snooped when the render cache is
3577 * flushed/invalidated. As we always have to emit invalidations
3578 * and flushes when moving into and out of the RENDER domain, correct
3579 * snooping behaviour occurs naturally as the result of our domain
3582 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3583 obj->cache_dirty = true;
3587 trace_i915_gem_object_clflush(obj);
3588 drm_clflush_sg(obj->pages);
3589 obj->cache_dirty = false;
3594 /** Flushes the GTT write domain for the object if it's dirty. */
3596 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3598 uint32_t old_write_domain;
3600 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3603 /* No actual flushing is required for the GTT write domain. Writes
3604 * to it immediately go to main memory as far as we know, so there's
3605 * no chipset flush. It also doesn't land in render cache.
3607 * However, we do have to enforce the order so that all writes through
3608 * the GTT land before any writes to the device, such as updates to
3613 old_write_domain = obj->base.write_domain;
3614 obj->base.write_domain = 0;
3616 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3618 trace_i915_gem_object_change_domain(obj,
3619 obj->base.read_domains,
3623 /** Flushes the CPU write domain for the object if it's dirty. */
3625 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3627 uint32_t old_write_domain;
3629 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3632 if (i915_gem_clflush_object(obj, obj->pin_display))
3633 i915_gem_chipset_flush(obj->base.dev);
3635 old_write_domain = obj->base.write_domain;
3636 obj->base.write_domain = 0;
3638 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3640 trace_i915_gem_object_change_domain(obj,
3641 obj->base.read_domains,
3646 * Moves a single object to the GTT read, and possibly write domain.
3648 * This function returns when the move is complete, including waiting on
3652 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3654 uint32_t old_write_domain, old_read_domains;
3655 struct i915_vma *vma;
3658 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3661 ret = i915_gem_object_wait_rendering(obj, !write);
3665 /* Flush and acquire obj->pages so that we are coherent through
3666 * direct access in memory with previous cached writes through
3667 * shmemfs and that our cache domain tracking remains valid.
3668 * For example, if the obj->filp was moved to swap without us
3669 * being notified and releasing the pages, we would mistakenly
3670 * continue to assume that the obj remained out of the CPU cached
3673 ret = i915_gem_object_get_pages(obj);
3677 i915_gem_object_flush_cpu_write_domain(obj);
3679 /* Serialise direct access to this object with the barriers for
3680 * coherent writes from the GPU, by effectively invalidating the
3681 * GTT domain upon first access.
3683 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3686 old_write_domain = obj->base.write_domain;
3687 old_read_domains = obj->base.read_domains;
3689 /* It should now be out of any other write domains, and we can update
3690 * the domain values for our changes.
3692 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3693 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3695 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3696 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3700 trace_i915_gem_object_change_domain(obj,
3704 /* And bump the LRU for this access */
3705 vma = i915_gem_obj_to_ggtt(obj);
3706 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3707 list_move_tail(&vma->mm_list,
3708 &to_i915(obj->base.dev)->gtt.base.inactive_list);
3714 * Changes the cache-level of an object across all VMA.
3716 * After this function returns, the object will be in the new cache-level
3717 * across all GTT and the contents of the backing storage will be coherent,
3718 * with respect to the new cache-level. In order to keep the backing storage
3719 * coherent for all users, we only allow a single cache level to be set
3720 * globally on the object and prevent it from being changed whilst the
3721 * hardware is reading from the object. That is if the object is currently
3722 * on the scanout it will be set to uncached (or equivalent display
3723 * cache coherency) and all non-MOCS GPU access will also be uncached so
3724 * that all direct access to the scanout remains coherent.
3726 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3727 enum i915_cache_level cache_level)
3729 struct drm_device *dev = obj->base.dev;
3730 struct i915_vma *vma, *next;
3734 if (obj->cache_level == cache_level)
3737 /* Inspect the list of currently bound VMA and unbind any that would
3738 * be invalid given the new cache-level. This is principally to
3739 * catch the issue of the CS prefetch crossing page boundaries and
3740 * reading an invalid PTE on older architectures.
3742 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3743 if (!drm_mm_node_allocated(&vma->node))
3746 if (vma->pin_count) {
3747 DRM_DEBUG("can not change the cache level of pinned objects\n");
3751 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3752 ret = i915_vma_unbind(vma);
3759 /* We can reuse the existing drm_mm nodes but need to change the
3760 * cache-level on the PTE. We could simply unbind them all and
3761 * rebind with the correct cache-level on next use. However since
3762 * we already have a valid slot, dma mapping, pages etc, we may as
3763 * rewrite the PTE in the belief that doing so tramples upon less
3764 * state and so involves less work.
3767 /* Before we change the PTE, the GPU must not be accessing it.
3768 * If we wait upon the object, we know that all the bound
3769 * VMA are no longer active.
3771 ret = i915_gem_object_wait_rendering(obj, false);
3775 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3776 /* Access to snoopable pages through the GTT is
3777 * incoherent and on some machines causes a hard
3778 * lockup. Relinquish the CPU mmaping to force
3779 * userspace to refault in the pages and we can
3780 * then double check if the GTT mapping is still
3781 * valid for that pointer access.
3783 i915_gem_release_mmap(obj);
3785 /* As we no longer need a fence for GTT access,
3786 * we can relinquish it now (and so prevent having
3787 * to steal a fence from someone else on the next
3788 * fence request). Note GPU activity would have
3789 * dropped the fence as all snoopable access is
3790 * supposed to be linear.
3792 ret = i915_gem_object_put_fence(obj);
3796 /* We either have incoherent backing store and
3797 * so no GTT access or the architecture is fully
3798 * coherent. In such cases, existing GTT mmaps
3799 * ignore the cache bit in the PTE and we can
3800 * rewrite it without confusing the GPU or having
3801 * to force userspace to fault back in its mmaps.
3805 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3806 if (!drm_mm_node_allocated(&vma->node))
3809 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3815 list_for_each_entry(vma, &obj->vma_list, vma_link)
3816 vma->node.color = cache_level;
3817 obj->cache_level = cache_level;
3820 /* Flush the dirty CPU caches to the backing storage so that the
3821 * object is now coherent at its new cache level (with respect
3822 * to the access domain).
3824 if (obj->cache_dirty &&
3825 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3826 cpu_write_needs_clflush(obj)) {
3827 if (i915_gem_clflush_object(obj, true))
3828 i915_gem_chipset_flush(obj->base.dev);
3834 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3835 struct drm_file *file)
3837 struct drm_i915_gem_caching *args = data;
3838 struct drm_i915_gem_object *obj;
3840 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3841 if (&obj->base == NULL)
3844 switch (obj->cache_level) {
3845 case I915_CACHE_LLC:
3846 case I915_CACHE_L3_LLC:
3847 args->caching = I915_CACHING_CACHED;
3851 args->caching = I915_CACHING_DISPLAY;
3855 args->caching = I915_CACHING_NONE;
3859 drm_gem_object_unreference_unlocked(&obj->base);
3863 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3864 struct drm_file *file)
3866 struct drm_i915_private *dev_priv = dev->dev_private;
3867 struct drm_i915_gem_caching *args = data;
3868 struct drm_i915_gem_object *obj;
3869 enum i915_cache_level level;
3872 switch (args->caching) {
3873 case I915_CACHING_NONE:
3874 level = I915_CACHE_NONE;
3876 case I915_CACHING_CACHED:
3878 * Due to a HW issue on BXT A stepping, GPU stores via a
3879 * snooped mapping may leave stale data in a corresponding CPU
3880 * cacheline, whereas normally such cachelines would get
3883 if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)
3886 level = I915_CACHE_LLC;
3888 case I915_CACHING_DISPLAY:
3889 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3895 intel_runtime_pm_get(dev_priv);
3897 ret = i915_mutex_lock_interruptible(dev);
3901 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3902 if (&obj->base == NULL) {
3907 ret = i915_gem_object_set_cache_level(obj, level);
3909 drm_gem_object_unreference(&obj->base);
3911 mutex_unlock(&dev->struct_mutex);
3913 intel_runtime_pm_put(dev_priv);
3919 * Prepare buffer for display plane (scanout, cursors, etc).
3920 * Can be called from an uninterruptible phase (modesetting) and allows
3921 * any flushes to be pipelined (for pageflips).
3924 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3926 struct intel_engine_cs *pipelined,
3927 struct drm_i915_gem_request **pipelined_request,
3928 const struct i915_ggtt_view *view)
3930 u32 old_read_domains, old_write_domain;
3933 ret = i915_gem_object_sync(obj, pipelined, pipelined_request);
3937 /* Mark the pin_display early so that we account for the
3938 * display coherency whilst setting up the cache domains.
3942 /* The display engine is not coherent with the LLC cache on gen6. As
3943 * a result, we make sure that the pinning that is about to occur is
3944 * done with uncached PTEs. This is lowest common denominator for all
3947 * However for gen6+, we could do better by using the GFDT bit instead
3948 * of uncaching, which would allow us to flush all the LLC-cached data
3949 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3951 ret = i915_gem_object_set_cache_level(obj,
3952 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3954 goto err_unpin_display;
3956 /* As the user may map the buffer once pinned in the display plane
3957 * (e.g. libkms for the bootup splash), we have to ensure that we
3958 * always use map_and_fenceable for all scanout buffers.
3960 ret = i915_gem_object_ggtt_pin(obj, view, alignment,
3961 view->type == I915_GGTT_VIEW_NORMAL ?
3964 goto err_unpin_display;
3966 i915_gem_object_flush_cpu_write_domain(obj);
3968 old_write_domain = obj->base.write_domain;
3969 old_read_domains = obj->base.read_domains;
3971 /* It should now be out of any other write domains, and we can update
3972 * the domain values for our changes.
3974 obj->base.write_domain = 0;
3975 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3977 trace_i915_gem_object_change_domain(obj,
3989 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3990 const struct i915_ggtt_view *view)
3992 if (WARN_ON(obj->pin_display == 0))
3995 i915_gem_object_ggtt_unpin_view(obj, view);
4001 * Moves a single object to the CPU read, and possibly write domain.
4003 * This function returns when the move is complete, including waiting on
4007 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4009 uint32_t old_write_domain, old_read_domains;
4012 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4015 ret = i915_gem_object_wait_rendering(obj, !write);
4019 i915_gem_object_flush_gtt_write_domain(obj);
4021 old_write_domain = obj->base.write_domain;
4022 old_read_domains = obj->base.read_domains;
4024 /* Flush the CPU cache if it's still invalid. */
4025 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4026 i915_gem_clflush_object(obj, false);
4028 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4031 /* It should now be out of any other write domains, and we can update
4032 * the domain values for our changes.
4034 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4036 /* If we're writing through the CPU, then the GPU read domains will
4037 * need to be invalidated at next use.
4040 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4041 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4044 trace_i915_gem_object_change_domain(obj,
4051 /* Throttle our rendering by waiting until the ring has completed our requests
4052 * emitted over 20 msec ago.
4054 * Note that if we were to use the current jiffies each time around the loop,
4055 * we wouldn't escape the function with any frames outstanding if the time to
4056 * render a frame was over 20ms.
4058 * This should get us reasonable parallelism between CPU and GPU but also
4059 * relatively low latency when blocking on a particular request to finish.
4062 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4064 struct drm_i915_private *dev_priv = dev->dev_private;
4065 struct drm_i915_file_private *file_priv = file->driver_priv;
4066 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4067 struct drm_i915_gem_request *request, *target = NULL;
4068 unsigned reset_counter;
4071 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4075 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4079 spin_lock(&file_priv->mm.lock);
4080 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4081 if (time_after_eq(request->emitted_jiffies, recent_enough))
4085 * Note that the request might not have been submitted yet.
4086 * In which case emitted_jiffies will be zero.
4088 if (!request->emitted_jiffies)
4093 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4095 i915_gem_request_reference(target);
4096 spin_unlock(&file_priv->mm.lock);
4101 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4103 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4105 i915_gem_request_unreference__unlocked(target);
4111 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4113 struct drm_i915_gem_object *obj = vma->obj;
4116 vma->node.start & (alignment - 1))
4119 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4122 if (flags & PIN_OFFSET_BIAS &&
4123 vma->node.start < (flags & PIN_OFFSET_MASK))
4129 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4131 struct drm_i915_gem_object *obj = vma->obj;
4132 bool mappable, fenceable;
4133 u32 fence_size, fence_alignment;
4135 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4138 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4143 fenceable = (vma->node.size == fence_size &&
4144 (vma->node.start & (fence_alignment - 1)) == 0);
4146 mappable = (vma->node.start + fence_size <=
4147 to_i915(obj->base.dev)->gtt.mappable_end);
4149 obj->map_and_fenceable = mappable && fenceable;
4153 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4154 struct i915_address_space *vm,
4155 const struct i915_ggtt_view *ggtt_view,
4159 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4160 struct i915_vma *vma;
4164 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4167 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4170 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4173 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4176 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4177 i915_gem_obj_to_vma(obj, vm);
4180 return PTR_ERR(vma);
4183 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4186 if (i915_vma_misplaced(vma, alignment, flags)) {
4187 WARN(vma->pin_count,
4188 "bo is already pinned in %s with incorrect alignment:"
4189 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4190 " obj->map_and_fenceable=%d\n",
4191 ggtt_view ? "ggtt" : "ppgtt",
4192 upper_32_bits(vma->node.start),
4193 lower_32_bits(vma->node.start),
4195 !!(flags & PIN_MAPPABLE),
4196 obj->map_and_fenceable);
4197 ret = i915_vma_unbind(vma);
4205 bound = vma ? vma->bound : 0;
4206 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4207 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4210 return PTR_ERR(vma);
4212 ret = i915_vma_bind(vma, obj->cache_level, flags);
4217 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4218 (bound ^ vma->bound) & GLOBAL_BIND) {
4219 __i915_vma_set_map_and_fenceable(vma);
4220 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4228 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4229 struct i915_address_space *vm,
4233 return i915_gem_object_do_pin(obj, vm,
4234 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4239 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4240 const struct i915_ggtt_view *view,
4244 if (WARN_ONCE(!view, "no view specified"))
4247 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4248 alignment, flags | PIN_GLOBAL);
4252 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4253 const struct i915_ggtt_view *view)
4255 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4258 WARN_ON(vma->pin_count == 0);
4259 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4265 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4266 struct drm_file *file)
4268 struct drm_i915_gem_busy *args = data;
4269 struct drm_i915_gem_object *obj;
4272 ret = i915_mutex_lock_interruptible(dev);
4276 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4277 if (&obj->base == NULL) {
4282 /* Count all active objects as busy, even if they are currently not used
4283 * by the gpu. Users of this interface expect objects to eventually
4284 * become non-busy without any further actions, therefore emit any
4285 * necessary flushes here.
4287 ret = i915_gem_object_flush_active(obj);
4291 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4292 args->busy = obj->active << 16;
4293 if (obj->last_write_req)
4294 args->busy |= obj->last_write_req->ring->id;
4297 drm_gem_object_unreference(&obj->base);
4299 mutex_unlock(&dev->struct_mutex);
4304 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4305 struct drm_file *file_priv)
4307 return i915_gem_ring_throttle(dev, file_priv);
4311 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4312 struct drm_file *file_priv)
4314 struct drm_i915_private *dev_priv = dev->dev_private;
4315 struct drm_i915_gem_madvise *args = data;
4316 struct drm_i915_gem_object *obj;
4319 switch (args->madv) {
4320 case I915_MADV_DONTNEED:
4321 case I915_MADV_WILLNEED:
4327 ret = i915_mutex_lock_interruptible(dev);
4331 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4332 if (&obj->base == NULL) {
4337 if (i915_gem_obj_is_pinned(obj)) {
4343 obj->tiling_mode != I915_TILING_NONE &&
4344 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4345 if (obj->madv == I915_MADV_WILLNEED)
4346 i915_gem_object_unpin_pages(obj);
4347 if (args->madv == I915_MADV_WILLNEED)
4348 i915_gem_object_pin_pages(obj);
4351 if (obj->madv != __I915_MADV_PURGED)
4352 obj->madv = args->madv;
4354 /* if the object is no longer attached, discard its backing storage */
4355 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4356 i915_gem_object_truncate(obj);
4358 args->retained = obj->madv != __I915_MADV_PURGED;
4361 drm_gem_object_unreference(&obj->base);
4363 mutex_unlock(&dev->struct_mutex);
4367 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4368 const struct drm_i915_gem_object_ops *ops)
4372 INIT_LIST_HEAD(&obj->global_list);
4373 for (i = 0; i < I915_NUM_RINGS; i++)
4374 INIT_LIST_HEAD(&obj->ring_list[i]);
4375 INIT_LIST_HEAD(&obj->obj_exec_link);
4376 INIT_LIST_HEAD(&obj->vma_list);
4377 INIT_LIST_HEAD(&obj->batch_pool_link);
4381 obj->fence_reg = I915_FENCE_REG_NONE;
4382 obj->madv = I915_MADV_WILLNEED;
4384 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4387 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4388 .get_pages = i915_gem_object_get_pages_gtt,
4389 .put_pages = i915_gem_object_put_pages_gtt,
4392 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4395 struct drm_i915_gem_object *obj;
4396 struct address_space *mapping;
4399 obj = i915_gem_object_alloc(dev);
4403 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4404 i915_gem_object_free(obj);
4408 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4409 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4410 /* 965gm cannot relocate objects above 4GiB. */
4411 mask &= ~__GFP_HIGHMEM;
4412 mask |= __GFP_DMA32;
4415 mapping = file_inode(obj->base.filp)->i_mapping;
4416 mapping_set_gfp_mask(mapping, mask);
4418 i915_gem_object_init(obj, &i915_gem_object_ops);
4420 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4421 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4424 /* On some devices, we can have the GPU use the LLC (the CPU
4425 * cache) for about a 10% performance improvement
4426 * compared to uncached. Graphics requests other than
4427 * display scanout are coherent with the CPU in
4428 * accessing this cache. This means in this mode we
4429 * don't need to clflush on the CPU side, and on the
4430 * GPU side we only need to flush internal caches to
4431 * get data visible to the CPU.
4433 * However, we maintain the display planes as UC, and so
4434 * need to rebind when first used as such.
4436 obj->cache_level = I915_CACHE_LLC;
4438 obj->cache_level = I915_CACHE_NONE;
4440 trace_i915_gem_object_create(obj);
4445 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4447 /* If we are the last user of the backing storage (be it shmemfs
4448 * pages or stolen etc), we know that the pages are going to be
4449 * immediately released. In this case, we can then skip copying
4450 * back the contents from the GPU.
4453 if (obj->madv != I915_MADV_WILLNEED)
4456 if (obj->base.filp == NULL)
4459 /* At first glance, this looks racy, but then again so would be
4460 * userspace racing mmap against close. However, the first external
4461 * reference to the filp can only be obtained through the
4462 * i915_gem_mmap_ioctl() which safeguards us against the user
4463 * acquiring such a reference whilst we are in the middle of
4464 * freeing the object.
4466 return atomic_long_read(&obj->base.filp->f_count) == 1;
4469 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4471 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4472 struct drm_device *dev = obj->base.dev;
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474 struct i915_vma *vma, *next;
4476 intel_runtime_pm_get(dev_priv);
4478 trace_i915_gem_object_destroy(obj);
4480 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4484 ret = i915_vma_unbind(vma);
4485 if (WARN_ON(ret == -ERESTARTSYS)) {
4486 bool was_interruptible;
4488 was_interruptible = dev_priv->mm.interruptible;
4489 dev_priv->mm.interruptible = false;
4491 WARN_ON(i915_vma_unbind(vma));
4493 dev_priv->mm.interruptible = was_interruptible;
4497 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4498 * before progressing. */
4500 i915_gem_object_unpin_pages(obj);
4502 WARN_ON(obj->frontbuffer_bits);
4504 if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4505 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4506 obj->tiling_mode != I915_TILING_NONE)
4507 i915_gem_object_unpin_pages(obj);
4509 if (WARN_ON(obj->pages_pin_count))
4510 obj->pages_pin_count = 0;
4511 if (discard_backing_storage(obj))
4512 obj->madv = I915_MADV_DONTNEED;
4513 i915_gem_object_put_pages(obj);
4514 i915_gem_object_free_mmap_offset(obj);
4518 if (obj->base.import_attach)
4519 drm_prime_gem_destroy(&obj->base, NULL);
4521 if (obj->ops->release)
4522 obj->ops->release(obj);
4524 drm_gem_object_release(&obj->base);
4525 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4528 i915_gem_object_free(obj);
4530 intel_runtime_pm_put(dev_priv);
4533 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4534 struct i915_address_space *vm)
4536 struct i915_vma *vma;
4537 list_for_each_entry(vma, &obj->vma_list, vma_link) {
4538 if (i915_is_ggtt(vma->vm) &&
4539 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4547 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4548 const struct i915_ggtt_view *view)
4550 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4551 struct i915_vma *vma;
4553 if (WARN_ONCE(!view, "no view specified"))
4554 return ERR_PTR(-EINVAL);
4556 list_for_each_entry(vma, &obj->vma_list, vma_link)
4557 if (vma->vm == ggtt &&
4558 i915_ggtt_view_equal(&vma->ggtt_view, view))
4563 void i915_gem_vma_destroy(struct i915_vma *vma)
4565 struct i915_address_space *vm = NULL;
4566 WARN_ON(vma->node.allocated);
4568 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4569 if (!list_empty(&vma->exec_list))
4574 if (!i915_is_ggtt(vm))
4575 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4577 list_del(&vma->vma_link);
4579 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4583 i915_gem_stop_ringbuffers(struct drm_device *dev)
4585 struct drm_i915_private *dev_priv = dev->dev_private;
4586 struct intel_engine_cs *ring;
4589 for_each_ring(ring, dev_priv, i)
4590 dev_priv->gt.stop_ring(ring);
4594 i915_gem_suspend(struct drm_device *dev)
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4599 mutex_lock(&dev->struct_mutex);
4600 ret = i915_gpu_idle(dev);
4604 i915_gem_retire_requests(dev);
4606 i915_gem_stop_ringbuffers(dev);
4607 mutex_unlock(&dev->struct_mutex);
4609 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4610 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4611 flush_delayed_work(&dev_priv->mm.idle_work);
4613 /* Assert that we sucessfully flushed all the work and
4614 * reset the GPU back to its idle, low power state.
4616 WARN_ON(dev_priv->mm.busy);
4621 mutex_unlock(&dev->struct_mutex);
4625 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4627 struct intel_engine_cs *ring = req->ring;
4628 struct drm_device *dev = ring->dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4631 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4634 if (!HAS_L3_DPF(dev) || !remap_info)
4637 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4642 * Note: We do not worry about the concurrent register cacheline hang
4643 * here because no other code should access these registers other than
4644 * at initialization time.
4646 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4647 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4648 intel_ring_emit(ring, reg_base + i);
4649 intel_ring_emit(ring, remap_info[i/4]);
4652 intel_ring_advance(ring);
4657 void i915_gem_init_swizzling(struct drm_device *dev)
4659 struct drm_i915_private *dev_priv = dev->dev_private;
4661 if (INTEL_INFO(dev)->gen < 5 ||
4662 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4665 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4666 DISP_TILE_SURFACE_SWIZZLING);
4671 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4673 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4674 else if (IS_GEN7(dev))
4675 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4676 else if (IS_GEN8(dev))
4677 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4682 static void init_unused_ring(struct drm_device *dev, u32 base)
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4686 I915_WRITE(RING_CTL(base), 0);
4687 I915_WRITE(RING_HEAD(base), 0);
4688 I915_WRITE(RING_TAIL(base), 0);
4689 I915_WRITE(RING_START(base), 0);
4692 static void init_unused_rings(struct drm_device *dev)
4695 init_unused_ring(dev, PRB1_BASE);
4696 init_unused_ring(dev, SRB0_BASE);
4697 init_unused_ring(dev, SRB1_BASE);
4698 init_unused_ring(dev, SRB2_BASE);
4699 init_unused_ring(dev, SRB3_BASE);
4700 } else if (IS_GEN2(dev)) {
4701 init_unused_ring(dev, SRB0_BASE);
4702 init_unused_ring(dev, SRB1_BASE);
4703 } else if (IS_GEN3(dev)) {
4704 init_unused_ring(dev, PRB1_BASE);
4705 init_unused_ring(dev, PRB2_BASE);
4709 int i915_gem_init_rings(struct drm_device *dev)
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4714 ret = intel_init_render_ring_buffer(dev);
4719 ret = intel_init_bsd_ring_buffer(dev);
4721 goto cleanup_render_ring;
4725 ret = intel_init_blt_ring_buffer(dev);
4727 goto cleanup_bsd_ring;
4730 if (HAS_VEBOX(dev)) {
4731 ret = intel_init_vebox_ring_buffer(dev);
4733 goto cleanup_blt_ring;
4736 if (HAS_BSD2(dev)) {
4737 ret = intel_init_bsd2_ring_buffer(dev);
4739 goto cleanup_vebox_ring;
4745 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4747 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4749 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4750 cleanup_render_ring:
4751 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4757 i915_gem_init_hw(struct drm_device *dev)
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 struct intel_engine_cs *ring;
4763 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4766 /* Double layer security blanket, see i915_gem_init() */
4767 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4769 if (dev_priv->ellc_size)
4770 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4772 if (IS_HASWELL(dev))
4773 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4774 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4776 if (HAS_PCH_NOP(dev)) {
4777 if (IS_IVYBRIDGE(dev)) {
4778 u32 temp = I915_READ(GEN7_MSG_CTL);
4779 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4780 I915_WRITE(GEN7_MSG_CTL, temp);
4781 } else if (INTEL_INFO(dev)->gen >= 7) {
4782 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4783 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4784 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4788 i915_gem_init_swizzling(dev);
4791 * At least 830 can leave some of the unused rings
4792 * "active" (ie. head != tail) after resume which
4793 * will prevent c3 entry. Makes sure all unused rings
4796 init_unused_rings(dev);
4798 BUG_ON(!dev_priv->ring[RCS].default_context);
4800 ret = i915_ppgtt_init_hw(dev);
4802 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4806 /* Need to do basic initialisation of all rings first: */
4807 for_each_ring(ring, dev_priv, i) {
4808 ret = ring->init_hw(ring);
4813 /* We can't enable contexts until all firmware is loaded */
4814 if (HAS_GUC_UCODE(dev)) {
4815 ret = intel_guc_ucode_load(dev);
4818 * If we got an error and GuC submission is enabled, map
4819 * the error to -EIO so the GPU will be declared wedged.
4820 * OTOH, if we didn't intend to use the GuC anyway, just
4821 * discard the error and carry on.
4823 DRM_ERROR("Failed to initialize GuC, error %d%s\n", ret,
4824 i915.enable_guc_submission ? "" :
4826 ret = i915.enable_guc_submission ? -EIO : 0;
4833 * Increment the next seqno by 0x100 so we have a visible break
4834 * on re-initialisation
4836 ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4840 /* Now it is safe to go back round and do everything else: */
4841 for_each_ring(ring, dev_priv, i) {
4842 struct drm_i915_gem_request *req;
4844 WARN_ON(!ring->default_context);
4846 ret = i915_gem_request_alloc(ring, ring->default_context, &req);
4848 i915_gem_cleanup_ringbuffer(dev);
4852 if (ring->id == RCS) {
4853 for (j = 0; j < NUM_L3_SLICES(dev); j++)
4854 i915_gem_l3_remap(req, j);
4857 ret = i915_ppgtt_init_ring(req);
4858 if (ret && ret != -EIO) {
4859 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
4860 i915_gem_request_cancel(req);
4861 i915_gem_cleanup_ringbuffer(dev);
4865 ret = i915_gem_context_enable(req);
4866 if (ret && ret != -EIO) {
4867 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret);
4868 i915_gem_request_cancel(req);
4869 i915_gem_cleanup_ringbuffer(dev);
4873 i915_add_request_no_flush(req);
4877 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4881 int i915_gem_init(struct drm_device *dev)
4883 struct drm_i915_private *dev_priv = dev->dev_private;
4886 i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4887 i915.enable_execlists);
4889 mutex_lock(&dev->struct_mutex);
4891 if (IS_VALLEYVIEW(dev)) {
4892 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4893 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4894 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4895 VLV_GTLC_ALLOWWAKEACK), 10))
4896 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4899 if (!i915.enable_execlists) {
4900 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4901 dev_priv->gt.init_rings = i915_gem_init_rings;
4902 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4903 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4905 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4906 dev_priv->gt.init_rings = intel_logical_rings_init;
4907 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4908 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4911 /* This is just a security blanket to placate dragons.
4912 * On some systems, we very sporadically observe that the first TLBs
4913 * used by the CS may be stale, despite us poking the TLB reset. If
4914 * we hold the forcewake during initialisation these problems
4915 * just magically go away.
4917 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4919 ret = i915_gem_init_userptr(dev);
4923 i915_gem_init_global_gtt(dev);
4925 ret = i915_gem_context_init(dev);
4929 ret = dev_priv->gt.init_rings(dev);
4933 ret = i915_gem_init_hw(dev);
4935 /* Allow ring initialisation to fail by marking the GPU as
4936 * wedged. But we only want to do this where the GPU is angry,
4937 * for all other failure, such as an allocation failure, bail.
4939 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4940 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4945 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4946 mutex_unlock(&dev->struct_mutex);
4952 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4954 struct drm_i915_private *dev_priv = dev->dev_private;
4955 struct intel_engine_cs *ring;
4958 for_each_ring(ring, dev_priv, i)
4959 dev_priv->gt.cleanup_ring(ring);
4961 if (i915.enable_execlists)
4963 * Neither the BIOS, ourselves or any other kernel
4964 * expects the system to be in execlists mode on startup,
4965 * so we need to reset the GPU back to legacy mode.
4967 intel_gpu_reset(dev);
4971 init_ring_lists(struct intel_engine_cs *ring)
4973 INIT_LIST_HEAD(&ring->active_list);
4974 INIT_LIST_HEAD(&ring->request_list);
4978 i915_gem_load(struct drm_device *dev)
4980 struct drm_i915_private *dev_priv = dev->dev_private;
4984 kmem_cache_create("i915_gem_object",
4985 sizeof(struct drm_i915_gem_object), 0,
4989 kmem_cache_create("i915_gem_vma",
4990 sizeof(struct i915_vma), 0,
4993 dev_priv->requests =
4994 kmem_cache_create("i915_gem_request",
4995 sizeof(struct drm_i915_gem_request), 0,
4999 INIT_LIST_HEAD(&dev_priv->vm_list);
5000 INIT_LIST_HEAD(&dev_priv->context_list);
5001 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5002 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5003 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5004 for (i = 0; i < I915_NUM_RINGS; i++)
5005 init_ring_lists(&dev_priv->ring[i]);
5006 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5007 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5008 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5009 i915_gem_retire_work_handler);
5010 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5011 i915_gem_idle_work_handler);
5012 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5014 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5016 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5017 dev_priv->num_fence_regs = 32;
5018 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5019 dev_priv->num_fence_regs = 16;
5021 dev_priv->num_fence_regs = 8;
5023 if (intel_vgpu_active(dev))
5024 dev_priv->num_fence_regs =
5025 I915_READ(vgtif_reg(avail_rs.fence_num));
5028 * Set initial sequence number for requests.
5029 * Using this number allows the wraparound to happen early,
5030 * catching any obvious problems.
5032 dev_priv->next_seqno = ((u32)~0 - 0x1100);
5033 dev_priv->last_seqno = ((u32)~0 - 0x1101);
5035 /* Initialize fence registers to zero */
5036 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5037 i915_gem_restore_fences(dev);
5039 i915_gem_detect_bit_6_swizzle(dev);
5040 init_waitqueue_head(&dev_priv->pending_flip_queue);
5042 dev_priv->mm.interruptible = true;
5044 i915_gem_shrinker_init(dev_priv);
5046 mutex_init(&dev_priv->fb_tracking.lock);
5049 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5051 struct drm_i915_file_private *file_priv = file->driver_priv;
5053 /* Clean up our request list when the client is going away, so that
5054 * later retire_requests won't dereference our soon-to-be-gone
5057 spin_lock(&file_priv->mm.lock);
5058 while (!list_empty(&file_priv->mm.request_list)) {
5059 struct drm_i915_gem_request *request;
5061 request = list_first_entry(&file_priv->mm.request_list,
5062 struct drm_i915_gem_request,
5064 list_del(&request->client_list);
5065 request->file_priv = NULL;
5067 spin_unlock(&file_priv->mm.lock);
5069 if (!list_empty(&file_priv->rps.link)) {
5070 spin_lock(&to_i915(dev)->rps.client_lock);
5071 list_del(&file_priv->rps.link);
5072 spin_unlock(&to_i915(dev)->rps.client_lock);
5076 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5078 struct drm_i915_file_private *file_priv;
5081 DRM_DEBUG_DRIVER("\n");
5083 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5087 file->driver_priv = file_priv;
5088 file_priv->dev_priv = dev->dev_private;
5089 file_priv->file = file;
5090 INIT_LIST_HEAD(&file_priv->rps.link);
5092 spin_lock_init(&file_priv->mm.lock);
5093 INIT_LIST_HEAD(&file_priv->mm.request_list);
5095 ret = i915_gem_context_open(dev, file);
5103 * i915_gem_track_fb - update frontbuffer tracking
5104 * @old: current GEM buffer for the frontbuffer slots
5105 * @new: new GEM buffer for the frontbuffer slots
5106 * @frontbuffer_bits: bitmask of frontbuffer slots
5108 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5109 * from @old and setting them in @new. Both @old and @new can be NULL.
5111 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5112 struct drm_i915_gem_object *new,
5113 unsigned frontbuffer_bits)
5116 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5117 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5118 old->frontbuffer_bits &= ~frontbuffer_bits;
5122 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5123 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5124 new->frontbuffer_bits |= frontbuffer_bits;
5128 /* All the new VM stuff */
5129 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5130 struct i915_address_space *vm)
5132 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5133 struct i915_vma *vma;
5135 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5137 list_for_each_entry(vma, &o->vma_list, vma_link) {
5138 if (i915_is_ggtt(vma->vm) &&
5139 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5142 return vma->node.start;
5145 WARN(1, "%s vma for this object not found.\n",
5146 i915_is_ggtt(vm) ? "global" : "ppgtt");
5150 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5151 const struct i915_ggtt_view *view)
5153 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5154 struct i915_vma *vma;
5156 list_for_each_entry(vma, &o->vma_list, vma_link)
5157 if (vma->vm == ggtt &&
5158 i915_ggtt_view_equal(&vma->ggtt_view, view))
5159 return vma->node.start;
5161 WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5165 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5166 struct i915_address_space *vm)
5168 struct i915_vma *vma;
5170 list_for_each_entry(vma, &o->vma_list, vma_link) {
5171 if (i915_is_ggtt(vma->vm) &&
5172 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5174 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5181 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5182 const struct i915_ggtt_view *view)
5184 struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5185 struct i915_vma *vma;
5187 list_for_each_entry(vma, &o->vma_list, vma_link)
5188 if (vma->vm == ggtt &&
5189 i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5190 drm_mm_node_allocated(&vma->node))
5196 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5198 struct i915_vma *vma;
5200 list_for_each_entry(vma, &o->vma_list, vma_link)
5201 if (drm_mm_node_allocated(&vma->node))
5207 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5208 struct i915_address_space *vm)
5210 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5211 struct i915_vma *vma;
5213 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5215 BUG_ON(list_empty(&o->vma_list));
5217 list_for_each_entry(vma, &o->vma_list, vma_link) {
5218 if (i915_is_ggtt(vma->vm) &&
5219 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5222 return vma->node.size;
5227 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5229 struct i915_vma *vma;
5230 list_for_each_entry(vma, &obj->vma_list, vma_link)
5231 if (vma->pin_count > 0)
5237 /* Allocate a new GEM object and fill it with the supplied data */
5238 struct drm_i915_gem_object *
5239 i915_gem_object_create_from_data(struct drm_device *dev,
5240 const void *data, size_t size)
5242 struct drm_i915_gem_object *obj;
5243 struct sg_table *sg;
5247 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5248 if (IS_ERR_OR_NULL(obj))
5251 ret = i915_gem_object_set_to_cpu_domain(obj, true);
5255 ret = i915_gem_object_get_pages(obj);
5259 i915_gem_object_pin_pages(obj);
5261 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5262 i915_gem_object_unpin_pages(obj);
5264 if (WARN_ON(bytes != size)) {
5265 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5273 drm_gem_object_unreference(&obj->base);
5274 return ERR_PTR(ret);