drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  64
  65 static bool cpu_cache_is_coherent(struct drm_device *dev,
  66                                   enum i915_cache_level level)
  67 {
  68         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  69 }
  70
  71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  72 {
  73         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  74                 return true;
  75
  76         return obj->pin_display;
  77 }
  78
  79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  80 {
  81         if (obj->tiling_mode)
  82                 i915_gem_release_mmap(obj);
  83
  84         /* As we do not have an associated fence register, we will force
  85          * a tiling change if we ever need to acquire one.
  86          */
  87         obj->fence_dirty = false;
  88         obj->fence_reg = I915_FENCE_REG_NONE;
  89 }
  90
  91 /* some bookkeeping */
  92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  93                                   size_t size)
  94 {
  95         spin_lock(&dev_priv->mm.object_stat_lock);
  96         dev_priv->mm.object_count++;
  97         dev_priv->mm.object_memory += size;
  98         spin_unlock(&dev_priv->mm.object_stat_lock);
  99 }
 100
 101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 102                                      size_t size)
 103 {
 104         spin_lock(&dev_priv->mm.object_stat_lock);
 105         dev_priv->mm.object_count--;
 106         dev_priv->mm.object_memory -= size;
 107         spin_unlock(&dev_priv->mm.object_stat_lock);
 108 }
 109
 110 static int
 111 i915_gem_wait_for_error(struct i915_gpu_error *error)
 112 {
 113         int ret;
 114
 115 #define EXIT_COND (!i915_reset_in_progress(error) || \
 116                    i915_terminally_wedged(error))
 117         if (EXIT_COND)
 118                 return 0;
 119
 120         /*
 121          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 122          * userspace. If it takes that long something really bad is going on and
 123          * we should simply try to bail out and fail as gracefully as possible.
 124          */
 125         ret = wait_event_interruptible_timeout(error->reset_queue,
 126                                                EXIT_COND,
 127                                                10*HZ);
 128         if (ret == 0) {
 129                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 130                 return -EIO;
 131         } else if (ret < 0) {
 132                 return ret;
 133         }
 134 #undef EXIT_COND
 135
 136         return 0;
 137 }
 138
 139 int i915_mutex_lock_interruptible(struct drm_device *dev)
 140 {
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         int ret;
 143
 144         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 145         if (ret)
 146                 return ret;
 147
 148         ret = mutex_lock_interruptible(&dev->struct_mutex);
 149         if (ret)
 150                 return ret;
 151
 152         WARN_ON(i915_verify_lists(dev));
 153         return 0;
 154 }
 155
 156 int
 157 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 158                             struct drm_file *file)
 159 {
 160         struct drm_i915_private *dev_priv = dev->dev_private;
 161         struct drm_i915_gem_get_aperture *args = data;
 162         struct drm_i915_gem_object *obj;
 163         size_t pinned;
 164
 165         pinned = 0;
 166         mutex_lock(&dev->struct_mutex);
 167         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 168                 if (i915_gem_obj_is_pinned(obj))
 169                         pinned += i915_gem_obj_ggtt_size(obj);
 170         mutex_unlock(&dev->struct_mutex);
 171
 172         args->aper_size = dev_priv->gtt.base.total;
 173         args->aper_available_size = args->aper_size - pinned;
 174
 175         return 0;
 176 }
 177
 178 static int
 179 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 180 {
 181         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 182         char *vaddr = obj->phys_handle->vaddr;
 183         struct sg_table *st;
 184         struct scatterlist *sg;
 185         int i;
 186
 187         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 188                 return -EINVAL;
 189
 190         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 191                 struct page *page;
 192                 char *src;
 193
 194                 page = shmem_read_mapping_page(mapping, i);
 195                 if (IS_ERR(page))
 196                         return PTR_ERR(page);
 197
 198                 src = kmap_atomic(page);
 199                 memcpy(vaddr, src, PAGE_SIZE);
 200                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 201                 kunmap_atomic(src);
 202
 203                 page_cache_release(page);
 204                 vaddr += PAGE_SIZE;
 205         }
 206
 207         i915_gem_chipset_flush(obj->base.dev);
 208
 209         st = kmalloc(sizeof(*st), GFP_KERNEL);
 210         if (st == NULL)
 211                 return -ENOMEM;
 212
 213         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 214                 kfree(st);
 215                 return -ENOMEM;
 216         }
 217
 218         sg = st->sgl;
 219         sg->offset = 0;
 220         sg->length = obj->base.size;
 221
 222         sg_dma_address(sg) = obj->phys_handle->busaddr;
 223         sg_dma_len(sg) = obj->base.size;
 224
 225         obj->pages = st;
 226         obj->has_dma_mapping = true;
 227         return 0;
 228 }
 229
 230 static void
 231 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 232 {
 233         int ret;
 234
 235         BUG_ON(obj->madv == __I915_MADV_PURGED);
 236
 237         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 238         if (ret) {
 239                 /* In the event of a disaster, abandon all caches and
 240                  * hope for the best.
 241                  */
 242                 WARN_ON(ret != -EIO);
 243                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 244         }
 245
 246         if (obj->madv == I915_MADV_DONTNEED)
 247                 obj->dirty = 0;
 248
 249         if (obj->dirty) {
 250                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 251                 char *vaddr = obj->phys_handle->vaddr;
 252                 int i;
 253
 254                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 255                         struct page *page;
 256                         char *dst;
 257
 258                         page = shmem_read_mapping_page(mapping, i);
 259                         if (IS_ERR(page))
 260                                 continue;
 261
 262                         dst = kmap_atomic(page);
 263                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 264                         memcpy(dst, vaddr, PAGE_SIZE);
 265                         kunmap_atomic(dst);
 266
 267                         set_page_dirty(page);
 268                         if (obj->madv == I915_MADV_WILLNEED)
 269                                 mark_page_accessed(page);
 270                         page_cache_release(page);
 271                         vaddr += PAGE_SIZE;
 272                 }
 273                 obj->dirty = 0;
 274         }
 275
 276         sg_free_table(obj->pages);
 277         kfree(obj->pages);
 278
 279         obj->has_dma_mapping = false;
 280 }
 281
 282 static void
 283 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 284 {
 285         drm_pci_free(obj->base.dev, obj->phys_handle);
 286 }
 287
 288 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 289         .get_pages = i915_gem_object_get_pages_phys,
 290         .put_pages = i915_gem_object_put_pages_phys,
 291         .release = i915_gem_object_release_phys,
 292 };
 293
 294 static int
 295 drop_pages(struct drm_i915_gem_object *obj)
 296 {
 297         struct i915_vma *vma, *next;
 298         int ret;
 299
 300         drm_gem_object_reference(&obj->base);
 301         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 302                 if (i915_vma_unbind(vma))
 303                         break;
 304
 305         ret = i915_gem_object_put_pages(obj);
 306         drm_gem_object_unreference(&obj->base);
 307
 308         return ret;
 309 }
 310
 311 int
 312 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 313                             int align)
 314 {
 315         drm_dma_handle_t *phys;
 316         int ret;
 317
 318         if (obj->phys_handle) {
 319                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 320                         return -EBUSY;
 321
 322                 return 0;
 323         }
 324
 325         if (obj->madv != I915_MADV_WILLNEED)
 326                 return -EFAULT;
 327
 328         if (obj->base.filp == NULL)
 329                 return -EINVAL;
 330
 331         ret = drop_pages(obj);
 332         if (ret)
 333                 return ret;
 334
 335         /* create a new object */
 336         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 337         if (!phys)
 338                 return -ENOMEM;
 339
 340         obj->phys_handle = phys;
 341         obj->ops = &i915_gem_phys_ops;
 342
 343         return i915_gem_object_get_pages(obj);
 344 }
 345
 346 static int
 347 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 348                      struct drm_i915_gem_pwrite *args,
 349                      struct drm_file *file_priv)
 350 {
 351         struct drm_device *dev = obj->base.dev;
 352         void *vaddr = obj->phys_handle->vaddr + args->offset;
 353         char __user *user_data = to_user_ptr(args->data_ptr);
 354         int ret;
 355
 356         /* We manually control the domain here and pretend that it
 357          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 358          */
 359         ret = i915_gem_object_wait_rendering(obj, false);
 360         if (ret)
 361                 return ret;
 362
 363         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 364                 unsigned long unwritten;
 365
 366                 /* The physical object once assigned is fixed for the lifetime
 367                  * of the obj, so we can safely drop the lock and continue
 368                  * to access vaddr.
 369                  */
 370                 mutex_unlock(&dev->struct_mutex);
 371                 unwritten = copy_from_user(vaddr, user_data, args->size);
 372                 mutex_lock(&dev->struct_mutex);
 373                 if (unwritten)
 374                         return -EFAULT;
 375         }
 376
 377         drm_clflush_virt_range(vaddr, args->size);
 378         i915_gem_chipset_flush(dev);
 379         return 0;
 380 }
 381
 382 void *i915_gem_object_alloc(struct drm_device *dev)
 383 {
 384         struct drm_i915_private *dev_priv = dev->dev_private;
 385         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 386 }
 387
 388 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 389 {
 390         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 391         kmem_cache_free(dev_priv->slab, obj);
 392 }
 393
 394 static int
 395 i915_gem_create(struct drm_file *file,
 396                 struct drm_device *dev,
 397                 uint64_t size,
 398                 bool dumb,
 399                 uint32_t *handle_p)
 400 {
 401         struct drm_i915_gem_object *obj;
 402         int ret;
 403         u32 handle;
 404
 405         size = roundup(size, PAGE_SIZE);
 406         if (size == 0)
 407                 return -EINVAL;
 408
 409         /* Allocate the new object */
 410         obj = i915_gem_alloc_object(dev, size);
 411         if (obj == NULL)
 412                 return -ENOMEM;
 413
 414         obj->base.dumb = dumb;
 415         ret = drm_gem_handle_create(file, &obj->base, &handle);
 416         /* drop reference from allocate - handle holds it now */
 417         drm_gem_object_unreference_unlocked(&obj->base);
 418         if (ret)
 419                 return ret;
 420
 421         *handle_p = handle;
 422         return 0;
 423 }
 424
 425 int
 426 i915_gem_dumb_create(struct drm_file *file,
 427                      struct drm_device *dev,
 428                      struct drm_mode_create_dumb *args)
 429 {
 430         /* have to work out size/pitch and return them */
 431         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 432         args->size = args->pitch * args->height;
 433         return i915_gem_create(file, dev,
 434                                args->size, true, &args->handle);
 435 }
 436
 437 /**
 438  * Creates a new mm object and returns a handle to it.
 439  */
 440 int
 441 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 442                       struct drm_file *file)
 443 {
 444         struct drm_i915_gem_create *args = data;
 445
 446         return i915_gem_create(file, dev,
 447                                args->size, false, &args->handle);
 448 }
 449
 450 static inline int
 451 __copy_to_user_swizzled(char __user *cpu_vaddr,
 452                         const char *gpu_vaddr, int gpu_offset,
 453                         int length)
 454 {
 455         int ret, cpu_offset = 0;
 456
 457         while (length > 0) {
 458                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 459                 int this_length = min(cacheline_end - gpu_offset, length);
 460                 int swizzled_gpu_offset = gpu_offset ^ 64;
 461
 462                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 463                                      gpu_vaddr + swizzled_gpu_offset,
 464                                      this_length);
 465                 if (ret)
 466                         return ret + length;
 467
 468                 cpu_offset += this_length;
 469                 gpu_offset += this_length;
 470                 length -= this_length;
 471         }
 472
 473         return 0;
 474 }
 475
 476 static inline int
 477 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 478                           const char __user *cpu_vaddr,
 479                           int length)
 480 {
 481         int ret, cpu_offset = 0;
 482
 483         while (length > 0) {
 484                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 485                 int this_length = min(cacheline_end - gpu_offset, length);
 486                 int swizzled_gpu_offset = gpu_offset ^ 64;
 487
 488                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 489                                        cpu_vaddr + cpu_offset,
 490                                        this_length);
 491                 if (ret)
 492                         return ret + length;
 493
 494                 cpu_offset += this_length;
 495                 gpu_offset += this_length;
 496                 length -= this_length;
 497         }
 498
 499         return 0;
 500 }
 501
 502 /*
 503  * Pins the specified object's pages and synchronizes the object with
 504  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 505  * flush the object from the CPU cache.
 506  */
 507 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 508                                     int *needs_clflush)
 509 {
 510         int ret;
 511
 512         *needs_clflush = 0;
 513
 514         if (!obj->base.filp)
 515                 return -EINVAL;
 516
 517         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 518                 /* If we're not in the cpu read domain, set ourself into the gtt
 519                  * read domain and manually flush cachelines (if required). This
 520                  * optimizes for the case when the gpu will dirty the data
 521                  * anyway again before the next pread happens. */
 522                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 523                                                         obj->cache_level);
 524                 ret = i915_gem_object_wait_rendering(obj, true);
 525                 if (ret)
 526                         return ret;
 527
 528                 i915_gem_object_retire(obj);
 529         }
 530
 531         ret = i915_gem_object_get_pages(obj);
 532         if (ret)
 533                 return ret;
 534
 535         i915_gem_object_pin_pages(obj);
 536
 537         return ret;
 538 }
 539
 540 /* Per-page copy function for the shmem pread fastpath.
 541  * Flushes invalid cachelines before reading the target if
 542  * needs_clflush is set. */
 543 static int
 544 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 545                  char __user *user_data,
 546                  bool page_do_bit17_swizzling, bool needs_clflush)
 547 {
 548         char *vaddr;
 549         int ret;
 550
 551         if (unlikely(page_do_bit17_swizzling))
 552                 return -EINVAL;
 553
 554         vaddr = kmap_atomic(page);
 555         if (needs_clflush)
 556                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 557                                        page_length);
 558         ret = __copy_to_user_inatomic(user_data,
 559                                       vaddr + shmem_page_offset,
 560                                       page_length);
 561         kunmap_atomic(vaddr);
 562
 563         return ret ? -EFAULT : 0;
 564 }
 565
 566 static void
 567 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 568                              bool swizzled)
 569 {
 570         if (unlikely(swizzled)) {
 571                 unsigned long start = (unsigned long) addr;
 572                 unsigned long end = (unsigned long) addr + length;
 573
 574                 /* For swizzling simply ensure that we always flush both
 575                  * channels. Lame, but simple and it works. Swizzled
 576                  * pwrite/pread is far from a hotpath - current userspace
 577                  * doesn't use it at all. */
 578                 start = round_down(start, 128);
 579                 end = round_up(end, 128);
 580
 581                 drm_clflush_virt_range((void *)start, end - start);
 582         } else {
 583                 drm_clflush_virt_range(addr, length);
 584         }
 585
 586 }
 587
 588 /* Only difference to the fast-path function is that this can handle bit17
 589  * and uses non-atomic copy and kmap functions. */
 590 static int
 591 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 592                  char __user *user_data,
 593                  bool page_do_bit17_swizzling, bool needs_clflush)
 594 {
 595         char *vaddr;
 596         int ret;
 597
 598         vaddr = kmap(page);
 599         if (needs_clflush)
 600                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 601                                              page_length,
 602                                              page_do_bit17_swizzling);
 603
 604         if (page_do_bit17_swizzling)
 605                 ret = __copy_to_user_swizzled(user_data,
 606                                               vaddr, shmem_page_offset,
 607                                               page_length);
 608         else
 609                 ret = __copy_to_user(user_data,
 610                                      vaddr + shmem_page_offset,
 611                                      page_length);
 612         kunmap(page);
 613
 614         return ret ? - EFAULT : 0;
 615 }
 616
 617 static int
 618 i915_gem_shmem_pread(struct drm_device *dev,
 619                      struct drm_i915_gem_object *obj,
 620                      struct drm_i915_gem_pread *args,
 621                      struct drm_file *file)
 622 {
 623         char __user *user_data;
 624         ssize_t remain;
 625         loff_t offset;
 626         int shmem_page_offset, page_length, ret = 0;
 627         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 628         int prefaulted = 0;
 629         int needs_clflush = 0;
 630         struct sg_page_iter sg_iter;
 631
 632         user_data = to_user_ptr(args->data_ptr);
 633         remain = args->size;
 634
 635         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 636
 637         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 638         if (ret)
 639                 return ret;
 640
 641         offset = args->offset;
 642
 643         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 644                          offset >> PAGE_SHIFT) {
 645                 struct page *page = sg_page_iter_page(&sg_iter);
 646
 647                 if (remain <= 0)
 648                         break;
 649
 650                 /* Operation in this page
 651                  *
 652                  * shmem_page_offset = offset within page in shmem file
 653                  * page_length = bytes to copy for this page
 654                  */
 655                 shmem_page_offset = offset_in_page(offset);
 656                 page_length = remain;
 657                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 658                         page_length = PAGE_SIZE - shmem_page_offset;
 659
 660                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 661                         (page_to_phys(page) & (1 << 17)) != 0;
 662
 663                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 664                                        user_data, page_do_bit17_swizzling,
 665                                        needs_clflush);
 666                 if (ret == 0)
 667                         goto next_page;
 668
 669                 mutex_unlock(&dev->struct_mutex);
 670
 671                 if (likely(!i915.prefault_disable) && !prefaulted) {
 672                         ret = fault_in_multipages_writeable(user_data, remain);
 673                         /* Userspace is tricking us, but we've already clobbered
 674                          * its pages with the prefault and promised to write the
 675                          * data up to the first fault. Hence ignore any errors
 676                          * and just continue. */
 677                         (void)ret;
 678                         prefaulted = 1;
 679                 }
 680
 681                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 682                                        user_data, page_do_bit17_swizzling,
 683                                        needs_clflush);
 684
 685                 mutex_lock(&dev->struct_mutex);
 686
 687                 if (ret)
 688                         goto out;
 689
 690 next_page:
 691                 remain -= page_length;
 692                 user_data += page_length;
 693                 offset += page_length;
 694         }
 695
 696 out:
 697         i915_gem_object_unpin_pages(obj);
 698
 699         return ret;
 700 }
 701
 702 /**
 703  * Reads data from the object referenced by handle.
 704  *
 705  * On error, the contents of *data are undefined.
 706  */
 707 int
 708 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 709                      struct drm_file *file)
 710 {
 711         struct drm_i915_gem_pread *args = data;
 712         struct drm_i915_gem_object *obj;
 713         int ret = 0;
 714
 715         if (args->size == 0)
 716                 return 0;
 717
 718         if (!access_ok(VERIFY_WRITE,
 719                        to_user_ptr(args->data_ptr),
 720                        args->size))
 721                 return -EFAULT;
 722
 723         ret = i915_mutex_lock_interruptible(dev);
 724         if (ret)
 725                 return ret;
 726
 727         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 728         if (&obj->base == NULL) {
 729                 ret = -ENOENT;
 730                 goto unlock;
 731         }
 732
 733         /* Bounds check source.  */
 734         if (args->offset > obj->base.size ||
 735             args->size > obj->base.size - args->offset) {
 736                 ret = -EINVAL;
 737                 goto out;
 738         }
 739
 740         /* prime objects have no backing filp to GEM pread/pwrite
 741          * pages from.
 742          */
 743         if (!obj->base.filp) {
 744                 ret = -EINVAL;
 745                 goto out;
 746         }
 747
 748         trace_i915_gem_object_pread(obj, args->offset, args->size);
 749
 750         ret = i915_gem_shmem_pread(dev, obj, args, file);
 751
 752 out:
 753         drm_gem_object_unreference(&obj->base);
 754 unlock:
 755         mutex_unlock(&dev->struct_mutex);
 756         return ret;
 757 }
 758
 759 /* This is the fast write path which cannot handle
 760  * page faults in the source data
 761  */
 762
 763 static inline int
 764 fast_user_write(struct io_mapping *mapping,
 765                 loff_t page_base, int page_offset,
 766                 char __user *user_data,
 767                 int length)
 768 {
 769         void __iomem *vaddr_atomic;
 770         void *vaddr;
 771         unsigned long unwritten;
 772
 773         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 774         /* We can use the cpu mem copy function because this is X86. */
 775         vaddr = (void __force*)vaddr_atomic + page_offset;
 776         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 777                                                       user_data, length);
 778         io_mapping_unmap_atomic(vaddr_atomic);
 779         return unwritten;
 780 }
 781
 782 /**
 783  * This is the fast pwrite path, where we copy the data directly from the
 784  * user into the GTT, uncached.
 785  */
 786 static int
 787 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 788                          struct drm_i915_gem_object *obj,
 789                          struct drm_i915_gem_pwrite *args,
 790                          struct drm_file *file)
 791 {
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793         ssize_t remain;
 794         loff_t offset, page_base;
 795         char __user *user_data;
 796         int page_offset, page_length, ret;
 797
 798         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 799         if (ret)
 800                 goto out;
 801
 802         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 803         if (ret)
 804                 goto out_unpin;
 805
 806         ret = i915_gem_object_put_fence(obj);
 807         if (ret)
 808                 goto out_unpin;
 809
 810         user_data = to_user_ptr(args->data_ptr);
 811         remain = args->size;
 812
 813         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 814
 815         while (remain > 0) {
 816                 /* Operation in this page
 817                  *
 818                  * page_base = page offset within aperture
 819                  * page_offset = offset within page
 820                  * page_length = bytes to copy for this page
 821                  */
 822                 page_base = offset & PAGE_MASK;
 823                 page_offset = offset_in_page(offset);
 824                 page_length = remain;
 825                 if ((page_offset + remain) > PAGE_SIZE)
 826                         page_length = PAGE_SIZE - page_offset;
 827
 828                 /* If we get a fault while copying data, then (presumably) our
 829                  * source page isn't available.  Return the error and we'll
 830                  * retry in the slow path.
 831                  */
 832                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 833                                     page_offset, user_data, page_length)) {
 834                         ret = -EFAULT;
 835                         goto out_unpin;
 836                 }
 837
 838                 remain -= page_length;
 839                 user_data += page_length;
 840                 offset += page_length;
 841         }
 842
 843 out_unpin:
 844         i915_gem_object_ggtt_unpin(obj);
 845 out:
 846         return ret;
 847 }
 848
 849 /* Per-page copy function for the shmem pwrite fastpath.
 850  * Flushes invalid cachelines before writing to the target if
 851  * needs_clflush_before is set and flushes out any written cachelines after
 852  * writing if needs_clflush is set. */
 853 static int
 854 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 855                   char __user *user_data,
 856                   bool page_do_bit17_swizzling,
 857                   bool needs_clflush_before,
 858                   bool needs_clflush_after)
 859 {
 860         char *vaddr;
 861         int ret;
 862
 863         if (unlikely(page_do_bit17_swizzling))
 864                 return -EINVAL;
 865
 866         vaddr = kmap_atomic(page);
 867         if (needs_clflush_before)
 868                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 869                                        page_length);
 870         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 871                                         user_data, page_length);
 872         if (needs_clflush_after)
 873                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 874                                        page_length);
 875         kunmap_atomic(vaddr);
 876
 877         return ret ? -EFAULT : 0;
 878 }
 879
 880 /* Only difference to the fast-path function is that this can handle bit17
 881  * and uses non-atomic copy and kmap functions. */
 882 static int
 883 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 884                   char __user *user_data,
 885                   bool page_do_bit17_swizzling,
 886                   bool needs_clflush_before,
 887                   bool needs_clflush_after)
 888 {
 889         char *vaddr;
 890         int ret;
 891
 892         vaddr = kmap(page);
 893         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 894                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 895                                              page_length,
 896                                              page_do_bit17_swizzling);
 897         if (page_do_bit17_swizzling)
 898                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 899                                                 user_data,
 900                                                 page_length);
 901         else
 902                 ret = __copy_from_user(vaddr + shmem_page_offset,
 903                                        user_data,
 904                                        page_length);
 905         if (needs_clflush_after)
 906                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 907                                              page_length,
 908                                              page_do_bit17_swizzling);
 909         kunmap(page);
 910
 911         return ret ? -EFAULT : 0;
 912 }
 913
 914 static int
 915 i915_gem_shmem_pwrite(struct drm_device *dev,
 916                       struct drm_i915_gem_object *obj,
 917                       struct drm_i915_gem_pwrite *args,
 918                       struct drm_file *file)
 919 {
 920         ssize_t remain;
 921         loff_t offset;
 922         char __user *user_data;
 923         int shmem_page_offset, page_length, ret = 0;
 924         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 925         int hit_slowpath = 0;
 926         int needs_clflush_after = 0;
 927         int needs_clflush_before = 0;
 928         struct sg_page_iter sg_iter;
 929
 930         user_data = to_user_ptr(args->data_ptr);
 931         remain = args->size;
 932
 933         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 934
 935         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 936                 /* If we're not in the cpu write domain, set ourself into the gtt
 937                  * write domain and manually flush cachelines (if required). This
 938                  * optimizes for the case when the gpu will use the data
 939                  * right away and we therefore have to clflush anyway. */
 940                 needs_clflush_after = cpu_write_needs_clflush(obj);
 941                 ret = i915_gem_object_wait_rendering(obj, false);
 942                 if (ret)
 943                         return ret;
 944
 945                 i915_gem_object_retire(obj);
 946         }
 947         /* Same trick applies to invalidate partially written cachelines read
 948          * before writing. */
 949         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 950                 needs_clflush_before =
 951                         !cpu_cache_is_coherent(dev, obj->cache_level);
 952
 953         ret = i915_gem_object_get_pages(obj);
 954         if (ret)
 955                 return ret;
 956
 957         i915_gem_object_pin_pages(obj);
 958
 959         offset = args->offset;
 960         obj->dirty = 1;
 961
 962         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 963                          offset >> PAGE_SHIFT) {
 964                 struct page *page = sg_page_iter_page(&sg_iter);
 965                 int partial_cacheline_write;
 966
 967                 if (remain <= 0)
 968                         break;
 969
 970                 /* Operation in this page
 971                  *
 972                  * shmem_page_offset = offset within page in shmem file
 973                  * page_length = bytes to copy for this page
 974                  */
 975                 shmem_page_offset = offset_in_page(offset);
 976
 977                 page_length = remain;
 978                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 979                         page_length = PAGE_SIZE - shmem_page_offset;
 980
 981                 /* If we don't overwrite a cacheline completely we need to be
 982                  * careful to have up-to-date data by first clflushing. Don't
 983                  * overcomplicate things and flush the entire patch. */
 984                 partial_cacheline_write = needs_clflush_before &&
 985                         ((shmem_page_offset | page_length)
 986                                 & (boot_cpu_data.x86_clflush_size - 1));
 987
 988                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 989                         (page_to_phys(page) & (1 << 17)) != 0;
 990
 991                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 992                                         user_data, page_do_bit17_swizzling,
 993                                         partial_cacheline_write,
 994                                         needs_clflush_after);
 995                 if (ret == 0)
 996                         goto next_page;
 997
 998                 hit_slowpath = 1;
 999                 mutex_unlock(&dev->struct_mutex);
1000                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1001                                         user_data, page_do_bit17_swizzling,
1002                                         partial_cacheline_write,
1003                                         needs_clflush_after);
1004
1005                 mutex_lock(&dev->struct_mutex);
1006
1007                 if (ret)
1008                         goto out;
1009
1010 next_page:
1011                 remain -= page_length;
1012                 user_data += page_length;
1013                 offset += page_length;
1014         }
1015
1016 out:
1017         i915_gem_object_unpin_pages(obj);
1018
1019         if (hit_slowpath) {
1020                 /*
1021                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1022                  * cachelines in-line while writing and the object moved
1023                  * out of the cpu write domain while we've dropped the lock.
1024                  */
1025                 if (!needs_clflush_after &&
1026                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1027                         if (i915_gem_clflush_object(obj, obj->pin_display))
1028                                 i915_gem_chipset_flush(dev);
1029                 }
1030         }
1031
1032         if (needs_clflush_after)
1033                 i915_gem_chipset_flush(dev);
1034
1035         return ret;
1036 }
1037
1038 /**
1039  * Writes data to the object referenced by handle.
1040  *
1041  * On error, the contents of the buffer that were to be modified are undefined.
1042  */
1043 int
1044 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1045                       struct drm_file *file)
1046 {
1047         struct drm_i915_gem_pwrite *args = data;
1048         struct drm_i915_gem_object *obj;
1049         int ret;
1050
1051         if (args->size == 0)
1052                 return 0;
1053
1054         if (!access_ok(VERIFY_READ,
1055                        to_user_ptr(args->data_ptr),
1056                        args->size))
1057                 return -EFAULT;
1058
1059         if (likely(!i915.prefault_disable)) {
1060                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1061                                                    args->size);
1062                 if (ret)
1063                         return -EFAULT;
1064         }
1065
1066         ret = i915_mutex_lock_interruptible(dev);
1067         if (ret)
1068                 return ret;
1069
1070         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1071         if (&obj->base == NULL) {
1072                 ret = -ENOENT;
1073                 goto unlock;
1074         }
1075
1076         /* Bounds check destination. */
1077         if (args->offset > obj->base.size ||
1078             args->size > obj->base.size - args->offset) {
1079                 ret = -EINVAL;
1080                 goto out;
1081         }
1082
1083         /* prime objects have no backing filp to GEM pread/pwrite
1084          * pages from.
1085          */
1086         if (!obj->base.filp) {
1087                 ret = -EINVAL;
1088                 goto out;
1089         }
1090
1091         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1092
1093         ret = -EFAULT;
1094         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095          * it would end up going through the fenced access, and we'll get
1096          * different detiling behavior between reading and writing.
1097          * pread/pwrite currently are reading and writing from the CPU
1098          * perspective, requiring manual detiling by the client.
1099          */
1100         if (obj->tiling_mode == I915_TILING_NONE &&
1101             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1102             cpu_write_needs_clflush(obj)) {
1103                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1104                 /* Note that the gtt paths might fail with non-page-backed user
1105                  * pointers (e.g. gtt mappings when moving data between
1106                  * textures). Fallback to the shmem path in that case. */
1107         }
1108
1109         if (ret == -EFAULT || ret == -ENOSPC) {
1110                 if (obj->phys_handle)
1111                         ret = i915_gem_phys_pwrite(obj, args, file);
1112                 else
1113                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1114         }
1115
1116 out:
1117         drm_gem_object_unreference(&obj->base);
1118 unlock:
1119         mutex_unlock(&dev->struct_mutex);
1120         return ret;
1121 }
1122
1123 int
1124 i915_gem_check_wedge(struct i915_gpu_error *error,
1125                      bool interruptible)
1126 {
1127         if (i915_reset_in_progress(error)) {
1128                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1129                  * -EIO unconditionally for these. */
1130                 if (!interruptible)
1131                         return -EIO;
1132
1133                 /* Recovery complete, but the reset failed ... */
1134                 if (i915_terminally_wedged(error))
1135                         return -EIO;
1136
1137                 /*
1138                  * Check if GPU Reset is in progress - we need intel_ring_begin
1139                  * to work properly to reinit the hw state while the gpu is
1140                  * still marked as reset-in-progress. Handle this with a flag.
1141                  */
1142                 if (!error->reload_in_reset)
1143                         return -EAGAIN;
1144         }
1145
1146         return 0;
1147 }
1148
1149 /*
1150  * Compare arbitrary request against outstanding lazy request. Emit on match.
1151  */
1152 int
1153 i915_gem_check_olr(struct drm_i915_gem_request *req)
1154 {
1155         int ret;
1156
1157         WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1158
1159         ret = 0;
1160         if (req == req->ring->outstanding_lazy_request)
1161                 ret = i915_add_request(req->ring);
1162
1163         return ret;
1164 }
1165
1166 static void fake_irq(unsigned long data)
1167 {
1168         wake_up_process((struct task_struct *)data);
1169 }
1170
1171 static bool missed_irq(struct drm_i915_private *dev_priv,
1172                        struct intel_engine_cs *ring)
1173 {
1174         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1175 }
1176
1177 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1178 {
1179         if (file_priv == NULL)
1180                 return true;
1181
1182         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1183 }
1184
1185 /**
1186  * __i915_wait_request - wait until execution of request has finished
1187  * @req: duh!
1188  * @reset_counter: reset sequence associated with the given request
1189  * @interruptible: do an interruptible wait (normally yes)
1190  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1191  *
1192  * Note: It is of utmost importance that the passed in seqno and reset_counter
1193  * values have been read by the caller in an smp safe manner. Where read-side
1194  * locks are involved, it is sufficient to read the reset_counter before
1195  * unlocking the lock that protects the seqno. For lockless tricks, the
1196  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1197  * inserted.
1198  *
1199  * Returns 0 if the request was found within the alloted time. Else returns the
1200  * errno with remaining time filled in timeout argument.
1201  */
1202 int __i915_wait_request(struct drm_i915_gem_request *req,
1203                         unsigned reset_counter,
1204                         bool interruptible,
1205                         s64 *timeout,
1206                         struct drm_i915_file_private *file_priv)
1207 {
1208         struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1209         struct drm_device *dev = ring->dev;
1210         struct drm_i915_private *dev_priv = dev->dev_private;
1211         const bool irq_test_in_progress =
1212                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1213         DEFINE_WAIT(wait);
1214         unsigned long timeout_expire;
1215         s64 before, now;
1216         int ret;
1217
1218         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1219
1220         if (i915_gem_request_completed(req, true))
1221                 return 0;
1222
1223         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1224
1225         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1226                 gen6_rps_boost(dev_priv);
1227                 if (file_priv)
1228                         mod_delayed_work(dev_priv->wq,
1229                                          &file_priv->mm.idle_work,
1230                                          msecs_to_jiffies(100));
1231         }
1232
1233         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1234                 return -ENODEV;
1235
1236         /* Record current time in case interrupted by signal, or wedged */
1237         trace_i915_gem_request_wait_begin(req);
1238         before = ktime_get_raw_ns();
1239         for (;;) {
1240                 struct timer_list timer;
1241
1242                 prepare_to_wait(&ring->irq_queue, &wait,
1243                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1244
1245                 /* We need to check whether any gpu reset happened in between
1246                  * the caller grabbing the seqno and now ... */
1247                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1248                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1249                          * is truely gone. */
1250                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1251                         if (ret == 0)
1252                                 ret = -EAGAIN;
1253                         break;
1254                 }
1255
1256                 if (i915_gem_request_completed(req, false)) {
1257                         ret = 0;
1258                         break;
1259                 }
1260
1261                 if (interruptible && signal_pending(current)) {
1262                         ret = -ERESTARTSYS;
1263                         break;
1264                 }
1265
1266                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1267                         ret = -ETIME;
1268                         break;
1269                 }
1270
1271                 timer.function = NULL;
1272                 if (timeout || missed_irq(dev_priv, ring)) {
1273                         unsigned long expire;
1274
1275                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1276                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1277                         mod_timer(&timer, expire);
1278                 }
1279
1280                 io_schedule();
1281
1282                 if (timer.function) {
1283                         del_singleshot_timer_sync(&timer);
1284                         destroy_timer_on_stack(&timer);
1285                 }
1286         }
1287         now = ktime_get_raw_ns();
1288         trace_i915_gem_request_wait_end(req);
1289
1290         if (!irq_test_in_progress)
1291                 ring->irq_put(ring);
1292
1293         finish_wait(&ring->irq_queue, &wait);
1294
1295         if (timeout) {
1296                 s64 tres = *timeout - (now - before);
1297
1298                 *timeout = tres < 0 ? 0 : tres;
1299         }
1300
1301         return ret;
1302 }
1303
1304 /**
1305  * Waits for a request to be signaled, and cleans up the
1306  * request and object lists appropriately for that event.
1307  */
1308 int
1309 i915_wait_request(struct drm_i915_gem_request *req)
1310 {
1311         struct drm_device *dev;
1312         struct drm_i915_private *dev_priv;
1313         bool interruptible;
1314         unsigned reset_counter;
1315         int ret;
1316
1317         BUG_ON(req == NULL);
1318
1319         dev = req->ring->dev;
1320         dev_priv = dev->dev_private;
1321         interruptible = dev_priv->mm.interruptible;
1322
1323         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1324
1325         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1326         if (ret)
1327                 return ret;
1328
1329         ret = i915_gem_check_olr(req);
1330         if (ret)
1331                 return ret;
1332
1333         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1334         i915_gem_request_reference(req);
1335         ret = __i915_wait_request(req, reset_counter,
1336                                   interruptible, NULL, NULL);
1337         i915_gem_request_unreference(req);
1338         return ret;
1339 }
1340
1341 static int
1342 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1343 {
1344         if (!obj->active)
1345                 return 0;
1346
1347         /* Manually manage the write flush as we may have not yet
1348          * retired the buffer.
1349          *
1350          * Note that the last_write_req is always the earlier of
1351          * the two (read/write) requests, so if we haved successfully waited,
1352          * we know we have passed the last write.
1353          */
1354         i915_gem_request_assign(&obj->last_write_req, NULL);
1355
1356         return 0;
1357 }
1358
1359 /**
1360  * Ensures that all rendering to the object has completed and the object is
1361  * safe to unbind from the GTT or access from the CPU.
1362  */
1363 static __must_check int
1364 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1365                                bool readonly)
1366 {
1367         struct drm_i915_gem_request *req;
1368         int ret;
1369
1370         req = readonly ? obj->last_write_req : obj->last_read_req;
1371         if (!req)
1372                 return 0;
1373
1374         ret = i915_wait_request(req);
1375         if (ret)
1376                 return ret;
1377
1378         return i915_gem_object_wait_rendering__tail(obj);
1379 }
1380
1381 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1382  * as the object state may change during this call.
1383  */
1384 static __must_check int
1385 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1386                                             struct drm_i915_file_private *file_priv,
1387                                             bool readonly)
1388 {
1389         struct drm_i915_gem_request *req;
1390         struct drm_device *dev = obj->base.dev;
1391         struct drm_i915_private *dev_priv = dev->dev_private;
1392         unsigned reset_counter;
1393         int ret;
1394
1395         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1396         BUG_ON(!dev_priv->mm.interruptible);
1397
1398         req = readonly ? obj->last_write_req : obj->last_read_req;
1399         if (!req)
1400                 return 0;
1401
1402         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1403         if (ret)
1404                 return ret;
1405
1406         ret = i915_gem_check_olr(req);
1407         if (ret)
1408                 return ret;
1409
1410         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1411         i915_gem_request_reference(req);
1412         mutex_unlock(&dev->struct_mutex);
1413         ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1414         mutex_lock(&dev->struct_mutex);
1415         i915_gem_request_unreference(req);
1416         if (ret)
1417                 return ret;
1418
1419         return i915_gem_object_wait_rendering__tail(obj);
1420 }
1421
1422 /**
1423  * Called when user space prepares to use an object with the CPU, either
1424  * through the mmap ioctl's mapping or a GTT mapping.
1425  */
1426 int
1427 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1428                           struct drm_file *file)
1429 {
1430         struct drm_i915_gem_set_domain *args = data;
1431         struct drm_i915_gem_object *obj;
1432         uint32_t read_domains = args->read_domains;
1433         uint32_t write_domain = args->write_domain;
1434         int ret;
1435
1436         /* Only handle setting domains to types used by the CPU. */
1437         if (write_domain & I915_GEM_GPU_DOMAINS)
1438                 return -EINVAL;
1439
1440         if (read_domains & I915_GEM_GPU_DOMAINS)
1441                 return -EINVAL;
1442
1443         /* Having something in the write domain implies it's in the read
1444          * domain, and only that read domain.  Enforce that in the request.
1445          */
1446         if (write_domain != 0 && read_domains != write_domain)
1447                 return -EINVAL;
1448
1449         ret = i915_mutex_lock_interruptible(dev);
1450         if (ret)
1451                 return ret;
1452
1453         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1454         if (&obj->base == NULL) {
1455                 ret = -ENOENT;
1456                 goto unlock;
1457         }
1458
1459         /* Try to flush the object off the GPU without holding the lock.
1460          * We will repeat the flush holding the lock in the normal manner
1461          * to catch cases where we are gazumped.
1462          */
1463         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1464                                                           file->driver_priv,
1465                                                           !write_domain);
1466         if (ret)
1467                 goto unref;
1468
1469         if (read_domains & I915_GEM_DOMAIN_GTT)
1470                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1471         else
1472                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1473
1474 unref:
1475         drm_gem_object_unreference(&obj->base);
1476 unlock:
1477         mutex_unlock(&dev->struct_mutex);
1478         return ret;
1479 }
1480
1481 /**
1482  * Called when user space has done writes to this buffer
1483  */
1484 int
1485 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1486                          struct drm_file *file)
1487 {
1488         struct drm_i915_gem_sw_finish *args = data;
1489         struct drm_i915_gem_object *obj;
1490         int ret = 0;
1491
1492         ret = i915_mutex_lock_interruptible(dev);
1493         if (ret)
1494                 return ret;
1495
1496         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1497         if (&obj->base == NULL) {
1498                 ret = -ENOENT;
1499                 goto unlock;
1500         }
1501
1502         /* Pinned buffers may be scanout, so flush the cache */
1503         if (obj->pin_display)
1504                 i915_gem_object_flush_cpu_write_domain(obj, true);
1505
1506         drm_gem_object_unreference(&obj->base);
1507 unlock:
1508         mutex_unlock(&dev->struct_mutex);
1509         return ret;
1510 }
1511
1512 /**
1513  * Maps the contents of an object, returning the address it is mapped
1514  * into.
1515  *
1516  * While the mapping holds a reference on the contents of the object, it doesn't
1517  * imply a ref on the object itself.
1518  *
1519  * IMPORTANT:
1520  *
1521  * DRM driver writers who look a this function as an example for how to do GEM
1522  * mmap support, please don't implement mmap support like here. The modern way
1523  * to implement DRM mmap support is with an mmap offset ioctl (like
1524  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1525  * That way debug tooling like valgrind will understand what's going on, hiding
1526  * the mmap call in a driver private ioctl will break that. The i915 driver only
1527  * does cpu mmaps this way because we didn't know better.
1528  */
1529 int
1530 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1531                     struct drm_file *file)
1532 {
1533         struct drm_i915_gem_mmap *args = data;
1534         struct drm_gem_object *obj;
1535         unsigned long addr;
1536
1537         obj = drm_gem_object_lookup(dev, file, args->handle);
1538         if (obj == NULL)
1539                 return -ENOENT;
1540
1541         /* prime objects have no backing filp to GEM mmap
1542          * pages from.
1543          */
1544         if (!obj->filp) {
1545                 drm_gem_object_unreference_unlocked(obj);
1546                 return -EINVAL;
1547         }
1548
1549         addr = vm_mmap(obj->filp, 0, args->size,
1550                        PROT_READ | PROT_WRITE, MAP_SHARED,
1551                        args->offset);
1552         drm_gem_object_unreference_unlocked(obj);
1553         if (IS_ERR((void *)addr))
1554                 return addr;
1555
1556         args->addr_ptr = (uint64_t) addr;
1557
1558         return 0;
1559 }
1560
1561 /**
1562  * i915_gem_fault - fault a page into the GTT
1563  * vma: VMA in question
1564  * vmf: fault info
1565  *
1566  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1567  * from userspace.  The fault handler takes care of binding the object to
1568  * the GTT (if needed), allocating and programming a fence register (again,
1569  * only if needed based on whether the old reg is still valid or the object
1570  * is tiled) and inserting a new PTE into the faulting process.
1571  *
1572  * Note that the faulting process may involve evicting existing objects
1573  * from the GTT and/or fence registers to make room.  So performance may
1574  * suffer if the GTT working set is large or there are few fence registers
1575  * left.
1576  */
1577 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1578 {
1579         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1580         struct drm_device *dev = obj->base.dev;
1581         struct drm_i915_private *dev_priv = dev->dev_private;
1582         pgoff_t page_offset;
1583         unsigned long pfn;
1584         int ret = 0;
1585         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1586
1587         intel_runtime_pm_get(dev_priv);
1588
1589         /* We don't use vmf->pgoff since that has the fake offset */
1590         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1591                 PAGE_SHIFT;
1592
1593         ret = i915_mutex_lock_interruptible(dev);
1594         if (ret)
1595                 goto out;
1596
1597         trace_i915_gem_object_fault(obj, page_offset, true, write);
1598
1599         /* Try to flush the object off the GPU first without holding the lock.
1600          * Upon reacquiring the lock, we will perform our sanity checks and then
1601          * repeat the flush holding the lock in the normal manner to catch cases
1602          * where we are gazumped.
1603          */
1604         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1605         if (ret)
1606                 goto unlock;
1607
1608         /* Access to snoopable pages through the GTT is incoherent. */
1609         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1610                 ret = -EFAULT;
1611                 goto unlock;
1612         }
1613
1614         /* Now bind it into the GTT if needed */
1615         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1616         if (ret)
1617                 goto unlock;
1618
1619         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1620         if (ret)
1621                 goto unpin;
1622
1623         ret = i915_gem_object_get_fence(obj);
1624         if (ret)
1625                 goto unpin;
1626
1627         /* Finally, remap it using the new GTT offset */
1628         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1629         pfn >>= PAGE_SHIFT;
1630
1631         if (!obj->fault_mappable) {
1632                 unsigned long size = min_t(unsigned long,
1633                                            vma->vm_end - vma->vm_start,
1634                                            obj->base.size);
1635                 int i;
1636
1637                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1638                         ret = vm_insert_pfn(vma,
1639                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1640                                             pfn + i);
1641                         if (ret)
1642                                 break;
1643                 }
1644
1645                 obj->fault_mappable = true;
1646         } else
1647                 ret = vm_insert_pfn(vma,
1648                                     (unsigned long)vmf->virtual_address,
1649                                     pfn + page_offset);
1650 unpin:
1651         i915_gem_object_ggtt_unpin(obj);
1652 unlock:
1653         mutex_unlock(&dev->struct_mutex);
1654 out:
1655         switch (ret) {
1656         case -EIO:
1657                 /*
1658                  * We eat errors when the gpu is terminally wedged to avoid
1659                  * userspace unduly crashing (gl has no provisions for mmaps to
1660                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1661                  * and so needs to be reported.
1662                  */
1663                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1664                         ret = VM_FAULT_SIGBUS;
1665                         break;
1666                 }
1667         case -EAGAIN:
1668                 /*
1669                  * EAGAIN means the gpu is hung and we'll wait for the error
1670                  * handler to reset everything when re-faulting in
1671                  * i915_mutex_lock_interruptible.
1672                  */
1673         case 0:
1674         case -ERESTARTSYS:
1675         case -EINTR:
1676         case -EBUSY:
1677                 /*
1678                  * EBUSY is ok: this just means that another thread
1679                  * already did the job.
1680                  */
1681                 ret = VM_FAULT_NOPAGE;
1682                 break;
1683         case -ENOMEM:
1684                 ret = VM_FAULT_OOM;
1685                 break;
1686         case -ENOSPC:
1687         case -EFAULT:
1688                 ret = VM_FAULT_SIGBUS;
1689                 break;
1690         default:
1691                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1692                 ret = VM_FAULT_SIGBUS;
1693                 break;
1694         }
1695
1696         intel_runtime_pm_put(dev_priv);
1697         return ret;
1698 }
1699
1700 /**
1701  * i915_gem_release_mmap - remove physical page mappings
1702  * @obj: obj in question
1703  *
1704  * Preserve the reservation of the mmapping with the DRM core code, but
1705  * relinquish ownership of the pages back to the system.
1706  *
1707  * It is vital that we remove the page mapping if we have mapped a tiled
1708  * object through the GTT and then lose the fence register due to
1709  * resource pressure. Similarly if the object has been moved out of the
1710  * aperture, than pages mapped into userspace must be revoked. Removing the
1711  * mapping will then trigger a page fault on the next user access, allowing
1712  * fixup by i915_gem_fault().
1713  */
1714 void
1715 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1716 {
1717         if (!obj->fault_mappable)
1718                 return;
1719
1720         drm_vma_node_unmap(&obj->base.vma_node,
1721                            obj->base.dev->anon_inode->i_mapping);
1722         obj->fault_mappable = false;
1723 }
1724
1725 void
1726 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1727 {
1728         struct drm_i915_gem_object *obj;
1729
1730         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1731                 i915_gem_release_mmap(obj);
1732 }
1733
1734 uint32_t
1735 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1736 {
1737         uint32_t gtt_size;
1738
1739         if (INTEL_INFO(dev)->gen >= 4 ||
1740             tiling_mode == I915_TILING_NONE)
1741                 return size;
1742
1743         /* Previous chips need a power-of-two fence region when tiling */
1744         if (INTEL_INFO(dev)->gen == 3)
1745                 gtt_size = 1024*1024;
1746         else
1747                 gtt_size = 512*1024;
1748
1749         while (gtt_size < size)
1750                 gtt_size <<= 1;
1751
1752         return gtt_size;
1753 }
1754
1755 /**
1756  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1757  * @obj: object to check
1758  *
1759  * Return the required GTT alignment for an object, taking into account
1760  * potential fence register mapping.
1761  */
1762 uint32_t
1763 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1764                            int tiling_mode, bool fenced)
1765 {
1766         /*
1767          * Minimum alignment is 4k (GTT page size), but might be greater
1768          * if a fence register is needed for the object.
1769          */
1770         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1771             tiling_mode == I915_TILING_NONE)
1772                 return 4096;
1773
1774         /*
1775          * Previous chips need to be aligned to the size of the smallest
1776          * fence register that can contain the object.
1777          */
1778         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1779 }
1780
1781 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1782 {
1783         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1784         int ret;
1785
1786         if (drm_vma_node_has_offset(&obj->base.vma_node))
1787                 return 0;
1788
1789         dev_priv->mm.shrinker_no_lock_stealing = true;
1790
1791         ret = drm_gem_create_mmap_offset(&obj->base);
1792         if (ret != -ENOSPC)
1793                 goto out;
1794
1795         /* Badly fragmented mmap space? The only way we can recover
1796          * space is by destroying unwanted objects. We can't randomly release
1797          * mmap_offsets as userspace expects them to be persistent for the
1798          * lifetime of the objects. The closest we can is to release the
1799          * offsets on purgeable objects by truncating it and marking it purged,
1800          * which prevents userspace from ever using that object again.
1801          */
1802         i915_gem_shrink(dev_priv,
1803                         obj->base.size >> PAGE_SHIFT,
1804                         I915_SHRINK_BOUND |
1805                         I915_SHRINK_UNBOUND |
1806                         I915_SHRINK_PURGEABLE);
1807         ret = drm_gem_create_mmap_offset(&obj->base);
1808         if (ret != -ENOSPC)
1809                 goto out;
1810
1811         i915_gem_shrink_all(dev_priv);
1812         ret = drm_gem_create_mmap_offset(&obj->base);
1813 out:
1814         dev_priv->mm.shrinker_no_lock_stealing = false;
1815
1816         return ret;
1817 }
1818
1819 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1820 {
1821         drm_gem_free_mmap_offset(&obj->base);
1822 }
1823
1824 static int
1825 i915_gem_mmap_gtt(struct drm_file *file,
1826                   struct drm_device *dev,
1827                   uint32_t handle, bool dumb,
1828                   uint64_t *offset)
1829 {
1830         struct drm_i915_private *dev_priv = dev->dev_private;
1831         struct drm_i915_gem_object *obj;
1832         int ret;
1833
1834         ret = i915_mutex_lock_interruptible(dev);
1835         if (ret)
1836                 return ret;
1837
1838         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1839         if (&obj->base == NULL) {
1840                 ret = -ENOENT;
1841                 goto unlock;
1842         }
1843
1844         /*
1845          * We don't allow dumb mmaps on objects created using another
1846          * interface.
1847          */
1848         WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach),
1849                   "Illegal dumb map of accelerated buffer.\n");
1850
1851         if (obj->base.size > dev_priv->gtt.mappable_end) {
1852                 ret = -E2BIG;
1853                 goto out;
1854         }
1855
1856         if (obj->madv != I915_MADV_WILLNEED) {
1857                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1858                 ret = -EFAULT;
1859                 goto out;
1860         }
1861
1862         ret = i915_gem_object_create_mmap_offset(obj);
1863         if (ret)
1864                 goto out;
1865
1866         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1867
1868 out:
1869         drm_gem_object_unreference(&obj->base);
1870 unlock:
1871         mutex_unlock(&dev->struct_mutex);
1872         return ret;
1873 }
1874
1875 int
1876 i915_gem_dumb_map_offset(struct drm_file *file,
1877                          struct drm_device *dev,
1878                          uint32_t handle,
1879                          uint64_t *offset)
1880 {
1881         return i915_gem_mmap_gtt(file, dev, handle, true, offset);
1882 }
1883
1884 /**
1885  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1886  * @dev: DRM device
1887  * @data: GTT mapping ioctl data
1888  * @file: GEM object info
1889  *
1890  * Simply returns the fake offset to userspace so it can mmap it.
1891  * The mmap call will end up in drm_gem_mmap(), which will set things
1892  * up so we can get faults in the handler above.
1893  *
1894  * The fault handler will take care of binding the object into the GTT
1895  * (since it may have been evicted to make room for something), allocating
1896  * a fence register, and mapping the appropriate aperture address into
1897  * userspace.
1898  */
1899 int
1900 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1901                         struct drm_file *file)
1902 {
1903         struct drm_i915_gem_mmap_gtt *args = data;
1904
1905         return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset);
1906 }
1907
1908 static inline int
1909 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1910 {
1911         return obj->madv == I915_MADV_DONTNEED;
1912 }
1913
1914 /* Immediately discard the backing storage */
1915 static void
1916 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1917 {
1918         i915_gem_object_free_mmap_offset(obj);
1919
1920         if (obj->base.filp == NULL)
1921                 return;
1922
1923         /* Our goal here is to return as much of the memory as
1924          * is possible back to the system as we are called from OOM.
1925          * To do this we must instruct the shmfs to drop all of its
1926          * backing pages, *now*.
1927          */
1928         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1929         obj->madv = __I915_MADV_PURGED;
1930 }
1931
1932 /* Try to discard unwanted pages */
1933 static void
1934 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1935 {
1936         struct address_space *mapping;
1937
1938         switch (obj->madv) {
1939         case I915_MADV_DONTNEED:
1940                 i915_gem_object_truncate(obj);
1941         case __I915_MADV_PURGED:
1942                 return;
1943         }
1944
1945         if (obj->base.filp == NULL)
1946                 return;
1947
1948         mapping = file_inode(obj->base.filp)->i_mapping,
1949         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1950 }
1951
1952 static void
1953 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1954 {
1955         struct sg_page_iter sg_iter;
1956         int ret;
1957
1958         BUG_ON(obj->madv == __I915_MADV_PURGED);
1959
1960         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1961         if (ret) {
1962                 /* In the event of a disaster, abandon all caches and
1963                  * hope for the best.
1964                  */
1965                 WARN_ON(ret != -EIO);
1966                 i915_gem_clflush_object(obj, true);
1967                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1968         }
1969
1970         if (i915_gem_object_needs_bit17_swizzle(obj))
1971                 i915_gem_object_save_bit_17_swizzle(obj);
1972
1973         if (obj->madv == I915_MADV_DONTNEED)
1974                 obj->dirty = 0;
1975
1976         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1977                 struct page *page = sg_page_iter_page(&sg_iter);
1978
1979                 if (obj->dirty)
1980                         set_page_dirty(page);
1981
1982                 if (obj->madv == I915_MADV_WILLNEED)
1983                         mark_page_accessed(page);
1984
1985                 page_cache_release(page);
1986         }
1987         obj->dirty = 0;
1988
1989         sg_free_table(obj->pages);
1990         kfree(obj->pages);
1991 }
1992
1993 int
1994 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1995 {
1996         const struct drm_i915_gem_object_ops *ops = obj->ops;
1997
1998         if (obj->pages == NULL)
1999                 return 0;
2000
2001         if (obj->pages_pin_count)
2002                 return -EBUSY;
2003
2004         BUG_ON(i915_gem_obj_bound_any(obj));
2005
2006         /* ->put_pages might need to allocate memory for the bit17 swizzle
2007          * array, hence protect them from being reaped by removing them from gtt
2008          * lists early. */
2009         list_del(&obj->global_list);
2010
2011         ops->put_pages(obj);
2012         obj->pages = NULL;
2013
2014         i915_gem_object_invalidate(obj);
2015
2016         return 0;
2017 }
2018
2019 unsigned long
2020 i915_gem_shrink(struct drm_i915_private *dev_priv,
2021                 long target, unsigned flags)
2022 {
2023         const struct {
2024                 struct list_head *list;
2025                 unsigned int bit;
2026         } phases[] = {
2027                 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND },
2028                 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND },
2029                 { NULL, 0 },
2030         }, *phase;
2031         unsigned long count = 0;
2032
2033         /*
2034          * As we may completely rewrite the (un)bound list whilst unbinding
2035          * (due to retiring requests) we have to strictly process only
2036          * one element of the list at the time, and recheck the list
2037          * on every iteration.
2038          *
2039          * In particular, we must hold a reference whilst removing the
2040          * object as we may end up waiting for and/or retiring the objects.
2041          * This might release the final reference (held by the active list)
2042          * and result in the object being freed from under us. This is
2043          * similar to the precautions the eviction code must take whilst
2044          * removing objects.
2045          *
2046          * Also note that although these lists do not hold a reference to
2047          * the object we can safely grab one here: The final object
2048          * unreferencing and the bound_list are both protected by the
2049          * dev->struct_mutex and so we won't ever be able to observe an
2050          * object on the bound_list with a reference count equals 0.
2051          */
2052         for (phase = phases; phase->list; phase++) {
2053                 struct list_head still_in_list;
2054
2055                 if ((flags & phase->bit) == 0)
2056                         continue;
2057
2058                 INIT_LIST_HEAD(&still_in_list);
2059                 while (count < target && !list_empty(phase->list)) {
2060                         struct drm_i915_gem_object *obj;
2061                         struct i915_vma *vma, *v;
2062
2063                         obj = list_first_entry(phase->list,
2064                                                typeof(*obj), global_list);
2065                         list_move_tail(&obj->global_list, &still_in_list);
2066
2067                         if (flags & I915_SHRINK_PURGEABLE &&
2068                             !i915_gem_object_is_purgeable(obj))
2069                                 continue;
2070
2071                         drm_gem_object_reference(&obj->base);
2072
2073                         /* For the unbound phase, this should be a no-op! */
2074                         list_for_each_entry_safe(vma, v,
2075                                                  &obj->vma_list, vma_link)
2076                                 if (i915_vma_unbind(vma))
2077                                         break;
2078
2079                         if (i915_gem_object_put_pages(obj) == 0)
2080                                 count += obj->base.size >> PAGE_SHIFT;
2081
2082                         drm_gem_object_unreference(&obj->base);
2083                 }
2084                 list_splice(&still_in_list, phase->list);
2085         }
2086
2087         return count;
2088 }
2089
2090 static unsigned long
2091 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2092 {
2093         i915_gem_evict_everything(dev_priv->dev);
2094         return i915_gem_shrink(dev_priv, LONG_MAX,
2095                                I915_SHRINK_BOUND | I915_SHRINK_UNBOUND);
2096 }
2097
2098 static int
2099 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2100 {
2101         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2102         int page_count, i;
2103         struct address_space *mapping;
2104         struct sg_table *st;
2105         struct scatterlist *sg;
2106         struct sg_page_iter sg_iter;
2107         struct page *page;
2108         unsigned long last_pfn = 0;     /* suppress gcc warning */
2109         gfp_t gfp;
2110
2111         /* Assert that the object is not currently in any GPU domain. As it
2112          * wasn't in the GTT, there shouldn't be any way it could have been in
2113          * a GPU cache
2114          */
2115         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2116         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2117
2118         st = kmalloc(sizeof(*st), GFP_KERNEL);
2119         if (st == NULL)
2120                 return -ENOMEM;
2121
2122         page_count = obj->base.size / PAGE_SIZE;
2123         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2124                 kfree(st);
2125                 return -ENOMEM;
2126         }
2127
2128         /* Get the list of pages out of our struct file.  They'll be pinned
2129          * at this point until we release them.
2130          *
2131          * Fail silently without starting the shrinker
2132          */
2133         mapping = file_inode(obj->base.filp)->i_mapping;
2134         gfp = mapping_gfp_mask(mapping);
2135         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2136         gfp &= ~(__GFP_IO | __GFP_WAIT);
2137         sg = st->sgl;
2138         st->nents = 0;
2139         for (i = 0; i < page_count; i++) {
2140                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2141                 if (IS_ERR(page)) {
2142                         i915_gem_shrink(dev_priv,
2143                                         page_count,
2144                                         I915_SHRINK_BOUND |
2145                                         I915_SHRINK_UNBOUND |
2146                                         I915_SHRINK_PURGEABLE);
2147                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2148                 }
2149                 if (IS_ERR(page)) {
2150                         /* We've tried hard to allocate the memory by reaping
2151                          * our own buffer, now let the real VM do its job and
2152                          * go down in flames if truly OOM.
2153                          */
2154                         i915_gem_shrink_all(dev_priv);
2155                         page = shmem_read_mapping_page(mapping, i);
2156                         if (IS_ERR(page))
2157                                 goto err_pages;
2158                 }
2159 #ifdef CONFIG_SWIOTLB
2160                 if (swiotlb_nr_tbl()) {
2161                         st->nents++;
2162                         sg_set_page(sg, page, PAGE_SIZE, 0);
2163                         sg = sg_next(sg);
2164                         continue;
2165                 }
2166 #endif
2167                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2168                         if (i)
2169                                 sg = sg_next(sg);
2170                         st->nents++;
2171                         sg_set_page(sg, page, PAGE_SIZE, 0);
2172                 } else {
2173                         sg->length += PAGE_SIZE;
2174                 }
2175                 last_pfn = page_to_pfn(page);
2176
2177                 /* Check that the i965g/gm workaround works. */
2178                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2179         }
2180 #ifdef CONFIG_SWIOTLB
2181         if (!swiotlb_nr_tbl())
2182 #endif
2183                 sg_mark_end(sg);
2184         obj->pages = st;
2185
2186         if (i915_gem_object_needs_bit17_swizzle(obj))
2187                 i915_gem_object_do_bit_17_swizzle(obj);
2188
2189         if (obj->tiling_mode != I915_TILING_NONE &&
2190             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2191                 i915_gem_object_pin_pages(obj);
2192
2193         return 0;
2194
2195 err_pages:
2196         sg_mark_end(sg);
2197         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2198                 page_cache_release(sg_page_iter_page(&sg_iter));
2199         sg_free_table(st);
2200         kfree(st);
2201
2202         /* shmemfs first checks if there is enough memory to allocate the page
2203          * and reports ENOSPC should there be insufficient, along with the usual
2204          * ENOMEM for a genuine allocation failure.
2205          *
2206          * We use ENOSPC in our driver to mean that we have run out of aperture
2207          * space and so want to translate the error from shmemfs back to our
2208          * usual understanding of ENOMEM.
2209          */
2210         if (PTR_ERR(page) == -ENOSPC)
2211                 return -ENOMEM;
2212         else
2213                 return PTR_ERR(page);
2214 }
2215
2216 /* Ensure that the associated pages are gathered from the backing storage
2217  * and pinned into our object. i915_gem_object_get_pages() may be called
2218  * multiple times before they are released by a single call to
2219  * i915_gem_object_put_pages() - once the pages are no longer referenced
2220  * either as a result of memory pressure (reaping pages under the shrinker)
2221  * or as the object is itself released.
2222  */
2223 int
2224 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2225 {
2226         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227         const struct drm_i915_gem_object_ops *ops = obj->ops;
2228         int ret;
2229
2230         if (obj->pages)
2231                 return 0;
2232
2233         if (obj->madv != I915_MADV_WILLNEED) {
2234                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2235                 return -EFAULT;
2236         }
2237
2238         BUG_ON(obj->pages_pin_count);
2239
2240         ret = ops->get_pages(obj);
2241         if (ret)
2242                 return ret;
2243
2244         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2245         return 0;
2246 }
2247
2248 static void
2249 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2250                                struct intel_engine_cs *ring)
2251 {
2252         struct drm_i915_gem_request *req;
2253         struct intel_engine_cs *old_ring;
2254
2255         BUG_ON(ring == NULL);
2256
2257         req = intel_ring_get_request(ring);
2258         old_ring = i915_gem_request_get_ring(obj->last_read_req);
2259
2260         if (old_ring != ring && obj->last_write_req) {
2261                 /* Keep the request relative to the current ring */
2262                 i915_gem_request_assign(&obj->last_write_req, req);
2263         }
2264
2265         /* Add a reference if we're newly entering the active list. */
2266         if (!obj->active) {
2267                 drm_gem_object_reference(&obj->base);
2268                 obj->active = 1;
2269         }
2270
2271         list_move_tail(&obj->ring_list, &ring->active_list);
2272
2273         i915_gem_request_assign(&obj->last_read_req, req);
2274 }
2275
2276 void i915_vma_move_to_active(struct i915_vma *vma,
2277                              struct intel_engine_cs *ring)
2278 {
2279         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2280         return i915_gem_object_move_to_active(vma->obj, ring);
2281 }
2282
2283 static void
2284 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2285 {
2286         struct i915_vma *vma;
2287
2288         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2289         BUG_ON(!obj->active);
2290
2291         list_for_each_entry(vma, &obj->vma_list, vma_link) {
2292                 if (!list_empty(&vma->mm_list))
2293                         list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2294         }
2295
2296         intel_fb_obj_flush(obj, true);
2297
2298         list_del_init(&obj->ring_list);
2299
2300         i915_gem_request_assign(&obj->last_read_req, NULL);
2301         i915_gem_request_assign(&obj->last_write_req, NULL);
2302         obj->base.write_domain = 0;
2303
2304         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2305
2306         obj->active = 0;
2307         drm_gem_object_unreference(&obj->base);
2308
2309         WARN_ON(i915_verify_lists(dev));
2310 }
2311
2312 static void
2313 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2314 {
2315         if (obj->last_read_req == NULL)
2316                 return;
2317
2318         if (i915_gem_request_completed(obj->last_read_req, true))
2319                 i915_gem_object_move_to_inactive(obj);
2320 }
2321
2322 static int
2323 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2324 {
2325         struct drm_i915_private *dev_priv = dev->dev_private;
2326         struct intel_engine_cs *ring;
2327         int ret, i, j;
2328
2329         /* Carefully retire all requests without writing to the rings */
2330         for_each_ring(ring, dev_priv, i) {
2331                 ret = intel_ring_idle(ring);
2332                 if (ret)
2333                         return ret;
2334         }
2335         i915_gem_retire_requests(dev);
2336
2337         /* Finally reset hw state */
2338         for_each_ring(ring, dev_priv, i) {
2339                 intel_ring_init_seqno(ring, seqno);
2340
2341                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2342                         ring->semaphore.sync_seqno[j] = 0;
2343         }
2344
2345         return 0;
2346 }
2347
2348 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2349 {
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         int ret;
2352
2353         if (seqno == 0)
2354                 return -EINVAL;
2355
2356         /* HWS page needs to be set less than what we
2357          * will inject to ring
2358          */
2359         ret = i915_gem_init_seqno(dev, seqno - 1);
2360         if (ret)
2361                 return ret;
2362
2363         /* Carefully set the last_seqno value so that wrap
2364          * detection still works
2365          */
2366         dev_priv->next_seqno = seqno;
2367         dev_priv->last_seqno = seqno - 1;
2368         if (dev_priv->last_seqno == 0)
2369                 dev_priv->last_seqno--;
2370
2371         return 0;
2372 }
2373
2374 int
2375 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2376 {
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378
2379         /* reserve 0 for non-seqno */
2380         if (dev_priv->next_seqno == 0) {
2381                 int ret = i915_gem_init_seqno(dev, 0);
2382                 if (ret)
2383                         return ret;
2384
2385                 dev_priv->next_seqno = 1;
2386         }
2387
2388         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2389         return 0;
2390 }
2391
2392 int __i915_add_request(struct intel_engine_cs *ring,
2393                        struct drm_file *file,
2394                        struct drm_i915_gem_object *obj)
2395 {
2396         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2397         struct drm_i915_gem_request *request;
2398         struct intel_ringbuffer *ringbuf;
2399         u32 request_ring_position, request_start;
2400         int ret;
2401
2402         request = ring->outstanding_lazy_request;
2403         if (WARN_ON(request == NULL))
2404                 return -ENOMEM;
2405
2406         if (i915.enable_execlists) {
2407                 struct intel_context *ctx = request->ctx;
2408                 ringbuf = ctx->engine[ring->id].ringbuf;
2409         } else
2410                 ringbuf = ring->buffer;
2411
2412         request_start = intel_ring_get_tail(ringbuf);
2413         /*
2414          * Emit any outstanding flushes - execbuf can fail to emit the flush
2415          * after having emitted the batchbuffer command. Hence we need to fix
2416          * things up similar to emitting the lazy request. The difference here
2417          * is that the flush _must_ happen before the next request, no matter
2418          * what.
2419          */
2420         if (i915.enable_execlists) {
2421                 ret = logical_ring_flush_all_caches(ringbuf);
2422                 if (ret)
2423                         return ret;
2424         } else {
2425                 ret = intel_ring_flush_all_caches(ring);
2426                 if (ret)
2427                         return ret;
2428         }
2429
2430         /* Record the position of the start of the request so that
2431          * should we detect the updated seqno part-way through the
2432          * GPU processing the request, we never over-estimate the
2433          * position of the head.
2434          */
2435         request_ring_position = intel_ring_get_tail(ringbuf);
2436
2437         if (i915.enable_execlists) {
2438                 ret = ring->emit_request(ringbuf);
2439                 if (ret)
2440                         return ret;
2441         } else {
2442                 ret = ring->add_request(ring);
2443                 if (ret)
2444                         return ret;
2445         }
2446
2447         request->head = request_start;
2448         request->tail = request_ring_position;
2449
2450         /* Whilst this request exists, batch_obj will be on the
2451          * active_list, and so will hold the active reference. Only when this
2452          * request is retired will the the batch_obj be moved onto the
2453          * inactive_list and lose its active reference. Hence we do not need
2454          * to explicitly hold another reference here.
2455          */
2456         request->batch_obj = obj;
2457
2458         if (!i915.enable_execlists) {
2459                 /* Hold a reference to the current context so that we can inspect
2460                  * it later in case a hangcheck error event fires.
2461                  */
2462                 request->ctx = ring->last_context;
2463                 if (request->ctx)
2464                         i915_gem_context_reference(request->ctx);
2465         }
2466
2467         request->emitted_jiffies = jiffies;
2468         list_add_tail(&request->list, &ring->request_list);
2469         request->file_priv = NULL;
2470
2471         if (file) {
2472                 struct drm_i915_file_private *file_priv = file->driver_priv;
2473
2474                 spin_lock(&file_priv->mm.lock);
2475                 request->file_priv = file_priv;
2476                 list_add_tail(&request->client_list,
2477                               &file_priv->mm.request_list);
2478                 spin_unlock(&file_priv->mm.lock);
2479         }
2480
2481         trace_i915_gem_request_add(request);
2482         ring->outstanding_lazy_request = NULL;
2483
2484         i915_queue_hangcheck(ring->dev);
2485
2486         cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2487         queue_delayed_work(dev_priv->wq,
2488                            &dev_priv->mm.retire_work,
2489                            round_jiffies_up_relative(HZ));
2490         intel_mark_busy(dev_priv->dev);
2491
2492         return 0;
2493 }
2494
2495 static inline void
2496 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2497 {
2498         struct drm_i915_file_private *file_priv = request->file_priv;
2499
2500         if (!file_priv)
2501                 return;
2502
2503         spin_lock(&file_priv->mm.lock);
2504         list_del(&request->client_list);
2505         request->file_priv = NULL;
2506         spin_unlock(&file_priv->mm.lock);
2507 }
2508
2509 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2510                                    const struct intel_context *ctx)
2511 {
2512         unsigned long elapsed;
2513
2514         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2515
2516         if (ctx->hang_stats.banned)
2517                 return true;
2518
2519         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2520                 if (!i915_gem_context_is_default(ctx)) {
2521                         DRM_DEBUG("context hanging too fast, banning!\n");
2522                         return true;
2523                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2524                         if (i915_stop_ring_allow_warn(dev_priv))
2525                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2526                         return true;
2527                 }
2528         }
2529
2530         return false;
2531 }
2532
2533 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2534                                   struct intel_context *ctx,
2535                                   const bool guilty)
2536 {
2537         struct i915_ctx_hang_stats *hs;
2538
2539         if (WARN_ON(!ctx))
2540                 return;
2541
2542         hs = &ctx->hang_stats;
2543
2544         if (guilty) {
2545                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2546                 hs->batch_active++;
2547                 hs->guilty_ts = get_seconds();
2548         } else {
2549                 hs->batch_pending++;
2550         }
2551 }
2552
2553 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2554 {
2555         list_del(&request->list);
2556         i915_gem_request_remove_from_client(request);
2557
2558         i915_gem_request_unreference(request);
2559 }
2560
2561 void i915_gem_request_free(struct kref *req_ref)
2562 {
2563         struct drm_i915_gem_request *req = container_of(req_ref,
2564                                                  typeof(*req), ref);
2565         struct intel_context *ctx = req->ctx;
2566
2567         if (ctx) {
2568                 if (i915.enable_execlists) {
2569                         struct intel_engine_cs *ring = req->ring;
2570
2571                         if (ctx != ring->default_context)
2572                                 intel_lr_context_unpin(ring, ctx);
2573                 }
2574
2575                 i915_gem_context_unreference(ctx);
2576         }
2577
2578         kfree(req);
2579 }
2580
2581 struct drm_i915_gem_request *
2582 i915_gem_find_active_request(struct intel_engine_cs *ring)
2583 {
2584         struct drm_i915_gem_request *request;
2585
2586         list_for_each_entry(request, &ring->request_list, list) {
2587                 if (i915_gem_request_completed(request, false))
2588                         continue;
2589
2590                 return request;
2591         }
2592
2593         return NULL;
2594 }
2595
2596 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2597                                        struct intel_engine_cs *ring)
2598 {
2599         struct drm_i915_gem_request *request;
2600         bool ring_hung;
2601
2602         request = i915_gem_find_active_request(ring);
2603
2604         if (request == NULL)
2605                 return;
2606
2607         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2608
2609         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2610
2611         list_for_each_entry_continue(request, &ring->request_list, list)
2612                 i915_set_reset_status(dev_priv, request->ctx, false);
2613 }
2614
2615 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2616                                         struct intel_engine_cs *ring)
2617 {
2618         while (!list_empty(&ring->active_list)) {
2619                 struct drm_i915_gem_object *obj;
2620
2621                 obj = list_first_entry(&ring->active_list,
2622                                        struct drm_i915_gem_object,
2623                                        ring_list);
2624
2625                 i915_gem_object_move_to_inactive(obj);
2626         }
2627
2628         /*
2629          * Clear the execlists queue up before freeing the requests, as those
2630          * are the ones that keep the context and ringbuffer backing objects
2631          * pinned in place.
2632          */
2633         while (!list_empty(&ring->execlist_queue)) {
2634                 struct intel_ctx_submit_request *submit_req;
2635
2636                 submit_req = list_first_entry(&ring->execlist_queue,
2637                                 struct intel_ctx_submit_request,
2638                                 execlist_link);
2639                 list_del(&submit_req->execlist_link);
2640                 intel_runtime_pm_put(dev_priv);
2641                 i915_gem_context_unreference(submit_req->ctx);
2642                 kfree(submit_req);
2643         }
2644
2645         /*
2646          * We must free the requests after all the corresponding objects have
2647          * been moved off active lists. Which is the same order as the normal
2648          * retire_requests function does. This is important if object hold
2649          * implicit references on things like e.g. ppgtt address spaces through
2650          * the request.
2651          */
2652         while (!list_empty(&ring->request_list)) {
2653                 struct drm_i915_gem_request *request;
2654
2655                 request = list_first_entry(&ring->request_list,
2656                                            struct drm_i915_gem_request,
2657                                            list);
2658
2659                 i915_gem_free_request(request);
2660         }
2661
2662         /* This may not have been flushed before the reset, so clean it now */
2663         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2664 }
2665
2666 void i915_gem_restore_fences(struct drm_device *dev)
2667 {
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         int i;
2670
2671         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2672                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2673
2674                 /*
2675                  * Commit delayed tiling changes if we have an object still
2676                  * attached to the fence, otherwise just clear the fence.
2677                  */
2678                 if (reg->obj) {
2679                         i915_gem_object_update_fence(reg->obj, reg,
2680                                                      reg->obj->tiling_mode);
2681                 } else {
2682                         i915_gem_write_fence(dev, i, NULL);
2683                 }
2684         }
2685 }
2686
2687 void i915_gem_reset(struct drm_device *dev)
2688 {
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         struct intel_engine_cs *ring;
2691         int i;
2692
2693         /*
2694          * Before we free the objects from the requests, we need to inspect
2695          * them for finding the guilty party. As the requests only borrow
2696          * their reference to the objects, the inspection must be done first.
2697          */
2698         for_each_ring(ring, dev_priv, i)
2699                 i915_gem_reset_ring_status(dev_priv, ring);
2700
2701         for_each_ring(ring, dev_priv, i)
2702                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2703
2704         i915_gem_context_reset(dev);
2705
2706         i915_gem_restore_fences(dev);
2707 }
2708
2709 /**
2710  * This function clears the request list as sequence numbers are passed.
2711  */
2712 void
2713 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2714 {
2715         if (list_empty(&ring->request_list))
2716                 return;
2717
2718         WARN_ON(i915_verify_lists(ring->dev));
2719
2720         /* Move any buffers on the active list that are no longer referenced
2721          * by the ringbuffer to the flushing/inactive lists as appropriate,
2722          * before we free the context associated with the requests.
2723          */
2724         while (!list_empty(&ring->active_list)) {
2725                 struct drm_i915_gem_object *obj;
2726
2727                 obj = list_first_entry(&ring->active_list,
2728                                       struct drm_i915_gem_object,
2729                                       ring_list);
2730
2731                 if (!i915_gem_request_completed(obj->last_read_req, true))
2732                         break;
2733
2734                 i915_gem_object_move_to_inactive(obj);
2735         }
2736
2737
2738         while (!list_empty(&ring->request_list)) {
2739                 struct drm_i915_gem_request *request;
2740                 struct intel_ringbuffer *ringbuf;
2741
2742                 request = list_first_entry(&ring->request_list,
2743                                            struct drm_i915_gem_request,
2744                                            list);
2745
2746                 if (!i915_gem_request_completed(request, true))
2747                         break;
2748
2749                 trace_i915_gem_request_retire(request);
2750
2751                 /* This is one of the few common intersection points
2752                  * between legacy ringbuffer submission and execlists:
2753                  * we need to tell them apart in order to find the correct
2754                  * ringbuffer to which the request belongs to.
2755                  */
2756                 if (i915.enable_execlists) {
2757                         struct intel_context *ctx = request->ctx;
2758                         ringbuf = ctx->engine[ring->id].ringbuf;
2759                 } else
2760                         ringbuf = ring->buffer;
2761
2762                 /* We know the GPU must have read the request to have
2763                  * sent us the seqno + interrupt, so use the position
2764                  * of tail of the request to update the last known position
2765                  * of the GPU head.
2766                  */
2767                 ringbuf->last_retired_head = request->tail;
2768
2769                 i915_gem_free_request(request);
2770         }
2771
2772         if (unlikely(ring->trace_irq_req &&
2773                      i915_gem_request_completed(ring->trace_irq_req, true))) {
2774                 ring->irq_put(ring);
2775                 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2776         }
2777
2778         WARN_ON(i915_verify_lists(ring->dev));
2779 }
2780
2781 bool
2782 i915_gem_retire_requests(struct drm_device *dev)
2783 {
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct intel_engine_cs *ring;
2786         bool idle = true;
2787         int i;
2788
2789         for_each_ring(ring, dev_priv, i) {
2790                 i915_gem_retire_requests_ring(ring);
2791                 idle &= list_empty(&ring->request_list);
2792                 if (i915.enable_execlists) {
2793                         unsigned long flags;
2794
2795                         spin_lock_irqsave(&ring->execlist_lock, flags);
2796                         idle &= list_empty(&ring->execlist_queue);
2797                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2798
2799                         intel_execlists_retire_requests(ring);
2800                 }
2801         }
2802
2803         if (idle)
2804                 mod_delayed_work(dev_priv->wq,
2805                                    &dev_priv->mm.idle_work,
2806                                    msecs_to_jiffies(100));
2807
2808         return idle;
2809 }
2810
2811 static void
2812 i915_gem_retire_work_handler(struct work_struct *work)
2813 {
2814         struct drm_i915_private *dev_priv =
2815                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2816         struct drm_device *dev = dev_priv->dev;
2817         bool idle;
2818
2819         /* Come back later if the device is busy... */
2820         idle = false;
2821         if (mutex_trylock(&dev->struct_mutex)) {
2822                 idle = i915_gem_retire_requests(dev);
2823                 mutex_unlock(&dev->struct_mutex);
2824         }
2825         if (!idle)
2826                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2827                                    round_jiffies_up_relative(HZ));
2828 }
2829
2830 static void
2831 i915_gem_idle_work_handler(struct work_struct *work)
2832 {
2833         struct drm_i915_private *dev_priv =
2834                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2835
2836         intel_mark_idle(dev_priv->dev);
2837 }
2838
2839 /**
2840  * Ensures that an object will eventually get non-busy by flushing any required
2841  * write domains, emitting any outstanding lazy request and retiring and
2842  * completed requests.
2843  */
2844 static int
2845 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2846 {
2847         struct intel_engine_cs *ring;
2848         int ret;
2849
2850         if (obj->active) {
2851                 ring = i915_gem_request_get_ring(obj->last_read_req);
2852
2853                 ret = i915_gem_check_olr(obj->last_read_req);
2854                 if (ret)
2855                         return ret;
2856
2857                 i915_gem_retire_requests_ring(ring);
2858         }
2859
2860         return 0;
2861 }
2862
2863 /**
2864  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2865  * @DRM_IOCTL_ARGS: standard ioctl arguments
2866  *
2867  * Returns 0 if successful, else an error is returned with the remaining time in
2868  * the timeout parameter.
2869  *  -ETIME: object is still busy after timeout
2870  *  -ERESTARTSYS: signal interrupted the wait
2871  *  -ENONENT: object doesn't exist
2872  * Also possible, but rare:
2873  *  -EAGAIN: GPU wedged
2874  *  -ENOMEM: damn
2875  *  -ENODEV: Internal IRQ fail
2876  *  -E?: The add request failed
2877  *
2878  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2879  * non-zero timeout parameter the wait ioctl will wait for the given number of
2880  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2881  * without holding struct_mutex the object may become re-busied before this
2882  * function completes. A similar but shorter * race condition exists in the busy
2883  * ioctl
2884  */
2885 int
2886 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2887 {
2888         struct drm_i915_private *dev_priv = dev->dev_private;
2889         struct drm_i915_gem_wait *args = data;
2890         struct drm_i915_gem_object *obj;
2891         struct drm_i915_gem_request *req;
2892         unsigned reset_counter;
2893         int ret = 0;
2894
2895         if (args->flags != 0)
2896                 return -EINVAL;
2897
2898         ret = i915_mutex_lock_interruptible(dev);
2899         if (ret)
2900                 return ret;
2901
2902         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2903         if (&obj->base == NULL) {
2904                 mutex_unlock(&dev->struct_mutex);
2905                 return -ENOENT;
2906         }
2907
2908         /* Need to make sure the object gets inactive eventually. */
2909         ret = i915_gem_object_flush_active(obj);
2910         if (ret)
2911                 goto out;
2912
2913         if (!obj->active || !obj->last_read_req)
2914                 goto out;
2915
2916         req = obj->last_read_req;
2917
2918         /* Do this after OLR check to make sure we make forward progress polling
2919          * on this IOCTL with a timeout <=0 (like busy ioctl)
2920          */
2921         if (args->timeout_ns <= 0) {
2922                 ret = -ETIME;
2923                 goto out;
2924         }
2925
2926         drm_gem_object_unreference(&obj->base);
2927         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2928         i915_gem_request_reference(req);
2929         mutex_unlock(&dev->struct_mutex);
2930
2931         ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
2932                                   file->driver_priv);
2933         mutex_lock(&dev->struct_mutex);
2934         i915_gem_request_unreference(req);
2935         mutex_unlock(&dev->struct_mutex);
2936         return ret;
2937
2938 out:
2939         drm_gem_object_unreference(&obj->base);
2940         mutex_unlock(&dev->struct_mutex);
2941         return ret;
2942 }
2943
2944 /**
2945  * i915_gem_object_sync - sync an object to a ring.
2946  *
2947  * @obj: object which may be in use on another ring.
2948  * @to: ring we wish to use the object on. May be NULL.
2949  *
2950  * This code is meant to abstract object synchronization with the GPU.
2951  * Calling with NULL implies synchronizing the object with the CPU
2952  * rather than a particular GPU ring.
2953  *
2954  * Returns 0 if successful, else propagates up the lower layer error.
2955  */
2956 int
2957 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2958                      struct intel_engine_cs *to)
2959 {
2960         struct intel_engine_cs *from;
2961         u32 seqno;
2962         int ret, idx;
2963
2964         from = i915_gem_request_get_ring(obj->last_read_req);
2965
2966         if (from == NULL || to == from)
2967                 return 0;
2968
2969         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2970                 return i915_gem_object_wait_rendering(obj, false);
2971
2972         idx = intel_ring_sync_index(from, to);
2973
2974         seqno = i915_gem_request_get_seqno(obj->last_read_req);
2975         /* Optimization: Avoid semaphore sync when we are sure we already
2976          * waited for an object with higher seqno */
2977         if (seqno <= from->semaphore.sync_seqno[idx])
2978                 return 0;
2979
2980         ret = i915_gem_check_olr(obj->last_read_req);
2981         if (ret)
2982                 return ret;
2983
2984         trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
2985         ret = to->semaphore.sync_to(to, from, seqno);
2986         if (!ret)
2987                 /* We use last_read_req because sync_to()
2988                  * might have just caused seqno wrap under
2989                  * the radar.
2990                  */
2991                 from->semaphore.sync_seqno[idx] =
2992                                 i915_gem_request_get_seqno(obj->last_read_req);
2993
2994         return ret;
2995 }
2996
2997 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2998 {
2999         u32 old_write_domain, old_read_domains;
3000
3001         /* Force a pagefault for domain tracking on next user access */
3002         i915_gem_release_mmap(obj);
3003
3004         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3005                 return;
3006
3007         /* Wait for any direct GTT access to complete */
3008         mb();
3009
3010         old_read_domains = obj->base.read_domains;
3011         old_write_domain = obj->base.write_domain;
3012
3013         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3014         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3015
3016         trace_i915_gem_object_change_domain(obj,
3017                                             old_read_domains,
3018                                             old_write_domain);
3019 }
3020
3021 int i915_vma_unbind(struct i915_vma *vma)
3022 {
3023         struct drm_i915_gem_object *obj = vma->obj;
3024         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3025         int ret;
3026
3027         if (list_empty(&vma->vma_link))
3028                 return 0;
3029
3030         if (!drm_mm_node_allocated(&vma->node)) {
3031                 i915_gem_vma_destroy(vma);
3032                 return 0;
3033         }
3034
3035         if (vma->pin_count)
3036                 return -EBUSY;
3037
3038         BUG_ON(obj->pages == NULL);
3039
3040         ret = i915_gem_object_finish_gpu(obj);
3041         if (ret)
3042                 return ret;
3043         /* Continue on if we fail due to EIO, the GPU is hung so we
3044          * should be safe and we need to cleanup or else we might
3045          * cause memory corruption through use-after-free.
3046          */
3047
3048         if (i915_is_ggtt(vma->vm) &&
3049             vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3050                 i915_gem_object_finish_gtt(obj);
3051
3052                 /* release the fence reg _after_ flushing */
3053                 ret = i915_gem_object_put_fence(obj);
3054                 if (ret)
3055                         return ret;
3056         }
3057
3058         trace_i915_vma_unbind(vma);
3059
3060         vma->unbind_vma(vma);
3061
3062         list_del_init(&vma->mm_list);
3063         if (i915_is_ggtt(vma->vm)) {
3064                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3065                         obj->map_and_fenceable = false;
3066                 } else if (vma->ggtt_view.pages) {
3067                         sg_free_table(vma->ggtt_view.pages);
3068                         kfree(vma->ggtt_view.pages);
3069                         vma->ggtt_view.pages = NULL;
3070                 }
3071         }
3072
3073         drm_mm_remove_node(&vma->node);
3074         i915_gem_vma_destroy(vma);
3075
3076         /* Since the unbound list is global, only move to that list if
3077          * no more VMAs exist. */
3078         if (list_empty(&obj->vma_list)) {
3079                 /* Throw away the active reference before
3080                  * moving to the unbound list. */
3081                 i915_gem_object_retire(obj);
3082
3083                 i915_gem_gtt_finish_object(obj);
3084                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3085         }
3086
3087         /* And finally now the object is completely decoupled from this vma,
3088          * we can drop its hold on the backing storage and allow it to be
3089          * reaped by the shrinker.
3090          */
3091         i915_gem_object_unpin_pages(obj);
3092
3093         return 0;
3094 }
3095
3096 int i915_gpu_idle(struct drm_device *dev)
3097 {
3098         struct drm_i915_private *dev_priv = dev->dev_private;
3099         struct intel_engine_cs *ring;
3100         int ret, i;
3101
3102         /* Flush everything onto the inactive list. */
3103         for_each_ring(ring, dev_priv, i) {
3104                 if (!i915.enable_execlists) {
3105                         ret = i915_switch_context(ring, ring->default_context);
3106                         if (ret)
3107                                 return ret;
3108                 }
3109
3110                 ret = intel_ring_idle(ring);
3111                 if (ret)
3112                         return ret;
3113         }
3114
3115         return 0;
3116 }
3117
3118 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3119                                  struct drm_i915_gem_object *obj)
3120 {
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122         int fence_reg;
3123         int fence_pitch_shift;
3124
3125         if (INTEL_INFO(dev)->gen >= 6) {
3126                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3127                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3128         } else {
3129                 fence_reg = FENCE_REG_965_0;
3130                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3131         }
3132
3133         fence_reg += reg * 8;
3134
3135         /* To w/a incoherency with non-atomic 64-bit register updates,
3136          * we split the 64-bit update into two 32-bit writes. In order
3137          * for a partial fence not to be evaluated between writes, we
3138          * precede the update with write to turn off the fence register,
3139          * and only enable the fence as the last step.
3140          *
3141          * For extra levels of paranoia, we make sure each step lands
3142          * before applying the next step.
3143          */
3144         I915_WRITE(fence_reg, 0);
3145         POSTING_READ(fence_reg);
3146
3147         if (obj) {
3148                 u32 size = i915_gem_obj_ggtt_size(obj);
3149                 uint64_t val;
3150
3151                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3152                                  0xfffff000) << 32;
3153                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3154                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3155                 if (obj->tiling_mode == I915_TILING_Y)
3156                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3157                 val |= I965_FENCE_REG_VALID;
3158
3159                 I915_WRITE(fence_reg + 4, val >> 32);
3160                 POSTING_READ(fence_reg + 4);
3161
3162                 I915_WRITE(fence_reg + 0, val);
3163                 POSTING_READ(fence_reg);
3164         } else {
3165                 I915_WRITE(fence_reg + 4, 0);
3166                 POSTING_READ(fence_reg + 4);
3167         }
3168 }
3169
3170 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3171                                  struct drm_i915_gem_object *obj)
3172 {
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         u32 val;
3175
3176         if (obj) {
3177                 u32 size = i915_gem_obj_ggtt_size(obj);
3178                 int pitch_val;
3179                 int tile_width;
3180
3181                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3182                      (size & -size) != size ||
3183                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3184                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3185                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3186
3187                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3188                         tile_width = 128;
3189                 else
3190                         tile_width = 512;
3191
3192                 /* Note: pitch better be a power of two tile widths */
3193                 pitch_val = obj->stride / tile_width;
3194                 pitch_val = ffs(pitch_val) - 1;
3195
3196                 val = i915_gem_obj_ggtt_offset(obj);
3197                 if (obj->tiling_mode == I915_TILING_Y)
3198                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3199                 val |= I915_FENCE_SIZE_BITS(size);
3200                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3201                 val |= I830_FENCE_REG_VALID;
3202         } else
3203                 val = 0;
3204
3205         if (reg < 8)
3206                 reg = FENCE_REG_830_0 + reg * 4;
3207         else
3208                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3209
3210         I915_WRITE(reg, val);
3211         POSTING_READ(reg);
3212 }
3213
3214 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3215                                 struct drm_i915_gem_object *obj)
3216 {
3217         struct drm_i915_private *dev_priv = dev->dev_private;
3218         uint32_t val;
3219
3220         if (obj) {
3221                 u32 size = i915_gem_obj_ggtt_size(obj);
3222                 uint32_t pitch_val;
3223
3224                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3225                      (size & -size) != size ||
3226                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3227                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3228                      i915_gem_obj_ggtt_offset(obj), size);
3229
3230                 pitch_val = obj->stride / 128;
3231                 pitch_val = ffs(pitch_val) - 1;
3232
3233                 val = i915_gem_obj_ggtt_offset(obj);
3234                 if (obj->tiling_mode == I915_TILING_Y)
3235                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3236                 val |= I830_FENCE_SIZE_BITS(size);
3237                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3238                 val |= I830_FENCE_REG_VALID;
3239         } else
3240                 val = 0;
3241
3242         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3243         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3244 }
3245
3246 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3247 {
3248         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3249 }
3250
3251 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3252                                  struct drm_i915_gem_object *obj)
3253 {
3254         struct drm_i915_private *dev_priv = dev->dev_private;
3255
3256         /* Ensure that all CPU reads are completed before installing a fence
3257          * and all writes before removing the fence.
3258          */
3259         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3260                 mb();
3261
3262         WARN(obj && (!obj->stride || !obj->tiling_mode),
3263              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3264              obj->stride, obj->tiling_mode);
3265
3266         if (IS_GEN2(dev))
3267                 i830_write_fence_reg(dev, reg, obj);
3268         else if (IS_GEN3(dev))
3269                 i915_write_fence_reg(dev, reg, obj);
3270         else if (INTEL_INFO(dev)->gen >= 4)
3271                 i965_write_fence_reg(dev, reg, obj);
3272
3273         /* And similarly be paranoid that no direct access to this region
3274          * is reordered to before the fence is installed.
3275          */
3276         if (i915_gem_object_needs_mb(obj))
3277                 mb();
3278 }
3279
3280 static inline int fence_number(struct drm_i915_private *dev_priv,
3281                                struct drm_i915_fence_reg *fence)
3282 {
3283         return fence - dev_priv->fence_regs;
3284 }
3285
3286 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3287                                          struct drm_i915_fence_reg *fence,
3288                                          bool enable)
3289 {
3290         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3291         int reg = fence_number(dev_priv, fence);
3292
3293         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3294
3295         if (enable) {
3296                 obj->fence_reg = reg;
3297                 fence->obj = obj;
3298                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3299         } else {
3300                 obj->fence_reg = I915_FENCE_REG_NONE;
3301                 fence->obj = NULL;
3302                 list_del_init(&fence->lru_list);
3303         }
3304         obj->fence_dirty = false;
3305 }
3306
3307 static int
3308 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3309 {
3310         if (obj->last_fenced_req) {
3311                 int ret = i915_wait_request(obj->last_fenced_req);
3312                 if (ret)
3313                         return ret;
3314
3315                 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3316         }
3317
3318         return 0;
3319 }
3320
3321 int
3322 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3323 {
3324         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3325         struct drm_i915_fence_reg *fence;
3326         int ret;
3327
3328         ret = i915_gem_object_wait_fence(obj);
3329         if (ret)
3330                 return ret;
3331
3332         if (obj->fence_reg == I915_FENCE_REG_NONE)
3333                 return 0;
3334
3335         fence = &dev_priv->fence_regs[obj->fence_reg];
3336
3337         if (WARN_ON(fence->pin_count))
3338                 return -EBUSY;
3339
3340         i915_gem_object_fence_lost(obj);
3341         i915_gem_object_update_fence(obj, fence, false);
3342
3343         return 0;
3344 }
3345
3346 static struct drm_i915_fence_reg *
3347 i915_find_fence_reg(struct drm_device *dev)
3348 {
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct drm_i915_fence_reg *reg, *avail;
3351         int i;
3352
3353         /* First try to find a free reg */
3354         avail = NULL;
3355         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3356                 reg = &dev_priv->fence_regs[i];
3357                 if (!reg->obj)
3358                         return reg;
3359
3360                 if (!reg->pin_count)
3361                         avail = reg;
3362         }
3363
3364         if (avail == NULL)
3365                 goto deadlock;
3366
3367         /* None available, try to steal one or wait for a user to finish */
3368         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3369                 if (reg->pin_count)
3370                         continue;
3371
3372                 return reg;
3373         }
3374
3375 deadlock:
3376         /* Wait for completion of pending flips which consume fences */
3377         if (intel_has_pending_fb_unpin(dev))
3378                 return ERR_PTR(-EAGAIN);
3379
3380         return ERR_PTR(-EDEADLK);
3381 }
3382
3383 /**
3384  * i915_gem_object_get_fence - set up fencing for an object
3385  * @obj: object to map through a fence reg
3386  *
3387  * When mapping objects through the GTT, userspace wants to be able to write
3388  * to them without having to worry about swizzling if the object is tiled.
3389  * This function walks the fence regs looking for a free one for @obj,
3390  * stealing one if it can't find any.
3391  *
3392  * It then sets up the reg based on the object's properties: address, pitch
3393  * and tiling format.
3394  *
3395  * For an untiled surface, this removes any existing fence.
3396  */
3397 int
3398 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3399 {
3400         struct drm_device *dev = obj->base.dev;
3401         struct drm_i915_private *dev_priv = dev->dev_private;
3402         bool enable = obj->tiling_mode != I915_TILING_NONE;
3403         struct drm_i915_fence_reg *reg;
3404         int ret;
3405
3406         /* Have we updated the tiling parameters upon the object and so
3407          * will need to serialise the write to the associated fence register?
3408          */
3409         if (obj->fence_dirty) {
3410                 ret = i915_gem_object_wait_fence(obj);
3411                 if (ret)
3412                         return ret;
3413         }
3414
3415         /* Just update our place in the LRU if our fence is getting reused. */
3416         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3417                 reg = &dev_priv->fence_regs[obj->fence_reg];
3418                 if (!obj->fence_dirty) {
3419                         list_move_tail(&reg->lru_list,
3420                                        &dev_priv->mm.fence_list);
3421                         return 0;
3422                 }
3423         } else if (enable) {
3424                 if (WARN_ON(!obj->map_and_fenceable))
3425                         return -EINVAL;
3426
3427                 reg = i915_find_fence_reg(dev);
3428                 if (IS_ERR(reg))
3429                         return PTR_ERR(reg);
3430
3431                 if (reg->obj) {
3432                         struct drm_i915_gem_object *old = reg->obj;
3433
3434                         ret = i915_gem_object_wait_fence(old);
3435                         if (ret)
3436                                 return ret;
3437
3438                         i915_gem_object_fence_lost(old);
3439                 }
3440         } else
3441                 return 0;
3442
3443         i915_gem_object_update_fence(obj, reg, enable);
3444
3445         return 0;
3446 }
3447
3448 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3449                                      unsigned long cache_level)
3450 {
3451         struct drm_mm_node *gtt_space = &vma->node;
3452         struct drm_mm_node *other;
3453
3454         /*
3455          * On some machines we have to be careful when putting differing types
3456          * of snoopable memory together to avoid the prefetcher crossing memory
3457          * domains and dying. During vm initialisation, we decide whether or not
3458          * these constraints apply and set the drm_mm.color_adjust
3459          * appropriately.
3460          */
3461         if (vma->vm->mm.color_adjust == NULL)
3462                 return true;
3463
3464         if (!drm_mm_node_allocated(gtt_space))
3465                 return true;
3466
3467         if (list_empty(&gtt_space->node_list))
3468                 return true;
3469
3470         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3471         if (other->allocated && !other->hole_follows && other->color != cache_level)
3472                 return false;
3473
3474         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3475         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3476                 return false;
3477
3478         return true;
3479 }
3480
3481 /**
3482  * Finds free space in the GTT aperture and binds the object there.
3483  */
3484 static struct i915_vma *
3485 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3486                            struct i915_address_space *vm,
3487                            unsigned alignment,
3488                            uint64_t flags,
3489                            const struct i915_ggtt_view *view)
3490 {
3491         struct drm_device *dev = obj->base.dev;
3492         struct drm_i915_private *dev_priv = dev->dev_private;
3493         u32 size, fence_size, fence_alignment, unfenced_alignment;
3494         unsigned long start =
3495                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3496         unsigned long end =
3497                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3498         struct i915_vma *vma;
3499         int ret;
3500
3501         fence_size = i915_gem_get_gtt_size(dev,
3502                                            obj->base.size,
3503                                            obj->tiling_mode);
3504         fence_alignment = i915_gem_get_gtt_alignment(dev,
3505                                                      obj->base.size,
3506                                                      obj->tiling_mode, true);
3507         unfenced_alignment =
3508                 i915_gem_get_gtt_alignment(dev,
3509                                            obj->base.size,
3510                                            obj->tiling_mode, false);
3511
3512         if (alignment == 0)
3513                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3514                                                 unfenced_alignment;
3515         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3516                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3517                 return ERR_PTR(-EINVAL);
3518         }
3519
3520         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3521
3522         /* If the object is bigger than the entire aperture, reject it early
3523          * before evicting everything in a vain attempt to find space.
3524          */
3525         if (obj->base.size > end) {
3526                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3527                           obj->base.size,
3528                           flags & PIN_MAPPABLE ? "mappable" : "total",
3529                           end);
3530                 return ERR_PTR(-E2BIG);
3531         }
3532
3533         ret = i915_gem_object_get_pages(obj);
3534         if (ret)
3535                 return ERR_PTR(ret);
3536
3537         i915_gem_object_pin_pages(obj);
3538
3539         vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view);
3540         if (IS_ERR(vma))
3541                 goto err_unpin;
3542
3543 search_free:
3544         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3545                                                   size, alignment,
3546                                                   obj->cache_level,
3547                                                   start, end,
3548                                                   DRM_MM_SEARCH_DEFAULT,
3549                                                   DRM_MM_CREATE_DEFAULT);
3550         if (ret) {
3551                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3552                                                obj->cache_level,
3553                                                start, end,
3554                                                flags);
3555                 if (ret == 0)
3556                         goto search_free;
3557
3558                 goto err_free_vma;
3559         }
3560         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3561                 ret = -EINVAL;
3562                 goto err_remove_node;
3563         }
3564
3565         ret = i915_gem_gtt_prepare_object(obj);
3566         if (ret)
3567                 goto err_remove_node;
3568
3569         trace_i915_vma_bind(vma, flags);
3570         ret = i915_vma_bind(vma, obj->cache_level,
3571                             flags & PIN_GLOBAL ? GLOBAL_BIND : 0);
3572         if (ret)
3573                 goto err_finish_gtt;
3574
3575         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3576         list_add_tail(&vma->mm_list, &vm->inactive_list);
3577
3578         return vma;
3579
3580 err_finish_gtt:
3581         i915_gem_gtt_finish_object(obj);
3582 err_remove_node:
3583         drm_mm_remove_node(&vma->node);
3584 err_free_vma:
3585         i915_gem_vma_destroy(vma);
3586         vma = ERR_PTR(ret);
3587 err_unpin:
3588         i915_gem_object_unpin_pages(obj);
3589         return vma;
3590 }
3591
3592 bool
3593 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3594                         bool force)
3595 {
3596         /* If we don't have a page list set up, then we're not pinned
3597          * to GPU, and we can ignore the cache flush because it'll happen
3598          * again at bind time.
3599          */
3600         if (obj->pages == NULL)
3601                 return false;
3602
3603         /*
3604          * Stolen memory is always coherent with the GPU as it is explicitly
3605          * marked as wc by the system, or the system is cache-coherent.
3606          */
3607         if (obj->stolen || obj->phys_handle)
3608                 return false;
3609
3610         /* If the GPU is snooping the contents of the CPU cache,
3611          * we do not need to manually clear the CPU cache lines.  However,
3612          * the caches are only snooped when the render cache is
3613          * flushed/invalidated.  As we always have to emit invalidations
3614          * and flushes when moving into and out of the RENDER domain, correct
3615          * snooping behaviour occurs naturally as the result of our domain
3616          * tracking.
3617          */
3618         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3619                 return false;
3620
3621         trace_i915_gem_object_clflush(obj);
3622         drm_clflush_sg(obj->pages);
3623
3624         return true;
3625 }
3626
3627 /** Flushes the GTT write domain for the object if it's dirty. */
3628 static void
3629 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3630 {
3631         uint32_t old_write_domain;
3632
3633         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3634                 return;
3635
3636         /* No actual flushing is required for the GTT write domain.  Writes
3637          * to it immediately go to main memory as far as we know, so there's
3638          * no chipset flush.  It also doesn't land in render cache.
3639          *
3640          * However, we do have to enforce the order so that all writes through
3641          * the GTT land before any writes to the device, such as updates to
3642          * the GATT itself.
3643          */
3644         wmb();
3645
3646         old_write_domain = obj->base.write_domain;
3647         obj->base.write_domain = 0;
3648
3649         intel_fb_obj_flush(obj, false);
3650
3651         trace_i915_gem_object_change_domain(obj,
3652                                             obj->base.read_domains,
3653                                             old_write_domain);
3654 }
3655
3656 /** Flushes the CPU write domain for the object if it's dirty. */
3657 static void
3658 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3659                                        bool force)
3660 {
3661         uint32_t old_write_domain;
3662
3663         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3664                 return;
3665
3666         if (i915_gem_clflush_object(obj, force))
3667                 i915_gem_chipset_flush(obj->base.dev);
3668
3669         old_write_domain = obj->base.write_domain;
3670         obj->base.write_domain = 0;
3671
3672         intel_fb_obj_flush(obj, false);
3673
3674         trace_i915_gem_object_change_domain(obj,
3675                                             obj->base.read_domains,
3676                                             old_write_domain);
3677 }
3678
3679 /**
3680  * Moves a single object to the GTT read, and possibly write domain.
3681  *
3682  * This function returns when the move is complete, including waiting on
3683  * flushes to occur.
3684  */
3685 int
3686 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3687 {
3688         uint32_t old_write_domain, old_read_domains;
3689         struct i915_vma *vma;
3690         int ret;
3691
3692         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3693                 return 0;
3694
3695         ret = i915_gem_object_wait_rendering(obj, !write);
3696         if (ret)
3697                 return ret;
3698
3699         i915_gem_object_retire(obj);
3700
3701         /* Flush and acquire obj->pages so that we are coherent through
3702          * direct access in memory with previous cached writes through
3703          * shmemfs and that our cache domain tracking remains valid.
3704          * For example, if the obj->filp was moved to swap without us
3705          * being notified and releasing the pages, we would mistakenly
3706          * continue to assume that the obj remained out of the CPU cached
3707          * domain.
3708          */
3709         ret = i915_gem_object_get_pages(obj);
3710         if (ret)
3711                 return ret;
3712
3713         i915_gem_object_flush_cpu_write_domain(obj, false);
3714
3715         /* Serialise direct access to this object with the barriers for
3716          * coherent writes from the GPU, by effectively invalidating the
3717          * GTT domain upon first access.
3718          */
3719         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3720                 mb();
3721
3722         old_write_domain = obj->base.write_domain;
3723         old_read_domains = obj->base.read_domains;
3724
3725         /* It should now be out of any other write domains, and we can update
3726          * the domain values for our changes.
3727          */
3728         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3729         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3730         if (write) {
3731                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3732                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3733                 obj->dirty = 1;
3734         }
3735
3736         if (write)
3737                 intel_fb_obj_invalidate(obj, NULL);
3738
3739         trace_i915_gem_object_change_domain(obj,
3740                                             old_read_domains,
3741                                             old_write_domain);
3742
3743         /* And bump the LRU for this access */
3744         vma = i915_gem_obj_to_ggtt(obj);
3745         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3746                 list_move_tail(&vma->mm_list,
3747                                &to_i915(obj->base.dev)->gtt.base.inactive_list);
3748
3749         return 0;
3750 }
3751
3752 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3753                                     enum i915_cache_level cache_level)
3754 {
3755         struct drm_device *dev = obj->base.dev;
3756         struct i915_vma *vma, *next;
3757         int ret;
3758
3759         if (obj->cache_level == cache_level)
3760                 return 0;
3761
3762         if (i915_gem_obj_is_pinned(obj)) {
3763                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3764                 return -EBUSY;
3765         }
3766
3767         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3768                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3769                         ret = i915_vma_unbind(vma);
3770                         if (ret)
3771                                 return ret;
3772                 }
3773         }
3774
3775         if (i915_gem_obj_bound_any(obj)) {
3776                 ret = i915_gem_object_finish_gpu(obj);
3777                 if (ret)
3778                         return ret;
3779
3780                 i915_gem_object_finish_gtt(obj);
3781
3782                 /* Before SandyBridge, you could not use tiling or fence
3783                  * registers with snooped memory, so relinquish any fences
3784                  * currently pointing to our region in the aperture.
3785                  */
3786                 if (INTEL_INFO(dev)->gen < 6) {
3787                         ret = i915_gem_object_put_fence(obj);
3788                         if (ret)
3789                                 return ret;
3790                 }
3791
3792                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3793                         if (drm_mm_node_allocated(&vma->node)) {
3794                                 ret = i915_vma_bind(vma, cache_level,
3795                                                     vma->bound & GLOBAL_BIND);
3796                                 if (ret)
3797                                         return ret;
3798                         }
3799         }
3800
3801         list_for_each_entry(vma, &obj->vma_list, vma_link)
3802                 vma->node.color = cache_level;
3803         obj->cache_level = cache_level;
3804
3805         if (cpu_write_needs_clflush(obj)) {
3806                 u32 old_read_domains, old_write_domain;
3807
3808                 /* If we're coming from LLC cached, then we haven't
3809                  * actually been tracking whether the data is in the
3810                  * CPU cache or not, since we only allow one bit set
3811                  * in obj->write_domain and have been skipping the clflushes.
3812                  * Just set it to the CPU cache for now.
3813                  */
3814                 i915_gem_object_retire(obj);
3815                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3816
3817                 old_read_domains = obj->base.read_domains;
3818                 old_write_domain = obj->base.write_domain;
3819
3820                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3821                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3822
3823                 trace_i915_gem_object_change_domain(obj,
3824                                                     old_read_domains,
3825                                                     old_write_domain);
3826         }
3827
3828         return 0;
3829 }
3830
3831 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3832                                struct drm_file *file)
3833 {
3834         struct drm_i915_gem_caching *args = data;
3835         struct drm_i915_gem_object *obj;
3836         int ret;
3837
3838         ret = i915_mutex_lock_interruptible(dev);
3839         if (ret)
3840                 return ret;
3841
3842         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3843         if (&obj->base == NULL) {
3844                 ret = -ENOENT;
3845                 goto unlock;
3846         }
3847
3848         switch (obj->cache_level) {
3849         case I915_CACHE_LLC:
3850         case I915_CACHE_L3_LLC:
3851                 args->caching = I915_CACHING_CACHED;
3852                 break;
3853
3854         case I915_CACHE_WT:
3855                 args->caching = I915_CACHING_DISPLAY;
3856                 break;
3857
3858         default:
3859                 args->caching = I915_CACHING_NONE;
3860                 break;
3861         }
3862
3863         drm_gem_object_unreference(&obj->base);
3864 unlock:
3865         mutex_unlock(&dev->struct_mutex);
3866         return ret;
3867 }
3868
3869 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3870                                struct drm_file *file)
3871 {
3872         struct drm_i915_gem_caching *args = data;
3873         struct drm_i915_gem_object *obj;
3874         enum i915_cache_level level;
3875         int ret;
3876
3877         switch (args->caching) {
3878         case I915_CACHING_NONE:
3879                 level = I915_CACHE_NONE;
3880                 break;
3881         case I915_CACHING_CACHED:
3882                 level = I915_CACHE_LLC;
3883                 break;
3884         case I915_CACHING_DISPLAY:
3885                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3886                 break;
3887         default:
3888                 return -EINVAL;
3889         }
3890
3891         ret = i915_mutex_lock_interruptible(dev);
3892         if (ret)
3893                 return ret;
3894
3895         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3896         if (&obj->base == NULL) {
3897                 ret = -ENOENT;
3898                 goto unlock;
3899         }
3900
3901         ret = i915_gem_object_set_cache_level(obj, level);
3902
3903         drm_gem_object_unreference(&obj->base);
3904 unlock:
3905         mutex_unlock(&dev->struct_mutex);
3906         return ret;
3907 }
3908
3909 static bool is_pin_display(struct drm_i915_gem_object *obj)
3910 {
3911         struct i915_vma *vma;
3912
3913         vma = i915_gem_obj_to_ggtt(obj);
3914         if (!vma)
3915                 return false;
3916
3917         /* There are 2 sources that pin objects:
3918          *   1. The display engine (scanouts, sprites, cursors);
3919          *   2. Reservations for execbuffer;
3920          *
3921          * We can ignore reservations as we hold the struct_mutex and
3922          * are only called outside of the reservation path.
3923          */
3924         return vma->pin_count;
3925 }
3926
3927 /*
3928  * Prepare buffer for display plane (scanout, cursors, etc).
3929  * Can be called from an uninterruptible phase (modesetting) and allows
3930  * any flushes to be pipelined (for pageflips).
3931  */
3932 int
3933 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3934                                      u32 alignment,
3935                                      struct intel_engine_cs *pipelined)
3936 {
3937         u32 old_read_domains, old_write_domain;
3938         bool was_pin_display;
3939         int ret;
3940
3941         if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3942                 ret = i915_gem_object_sync(obj, pipelined);
3943                 if (ret)
3944                         return ret;
3945         }
3946
3947         /* Mark the pin_display early so that we account for the
3948          * display coherency whilst setting up the cache domains.
3949          */
3950         was_pin_display = obj->pin_display;
3951         obj->pin_display = true;
3952
3953         /* The display engine is not coherent with the LLC cache on gen6.  As
3954          * a result, we make sure that the pinning that is about to occur is
3955          * done with uncached PTEs. This is lowest common denominator for all
3956          * chipsets.
3957          *
3958          * However for gen6+, we could do better by using the GFDT bit instead
3959          * of uncaching, which would allow us to flush all the LLC-cached data
3960          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3961          */
3962         ret = i915_gem_object_set_cache_level(obj,
3963                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3964         if (ret)
3965                 goto err_unpin_display;
3966
3967         /* As the user may map the buffer once pinned in the display plane
3968          * (e.g. libkms for the bootup splash), we have to ensure that we
3969          * always use map_and_fenceable for all scanout buffers.
3970          */
3971         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3972         if (ret)
3973                 goto err_unpin_display;
3974
3975         i915_gem_object_flush_cpu_write_domain(obj, true);
3976
3977         old_write_domain = obj->base.write_domain;
3978         old_read_domains = obj->base.read_domains;
3979
3980         /* It should now be out of any other write domains, and we can update
3981          * the domain values for our changes.
3982          */
3983         obj->base.write_domain = 0;
3984         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3985
3986         trace_i915_gem_object_change_domain(obj,
3987                                             old_read_domains,
3988                                             old_write_domain);
3989
3990         return 0;
3991
3992 err_unpin_display:
3993         WARN_ON(was_pin_display != is_pin_display(obj));
3994         obj->pin_display = was_pin_display;
3995         return ret;
3996 }
3997
3998 void
3999 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
4000 {
4001         i915_gem_object_ggtt_unpin(obj);
4002         obj->pin_display = is_pin_display(obj);
4003 }
4004
4005 int
4006 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4007 {
4008         int ret;
4009
4010         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4011                 return 0;
4012
4013         ret = i915_gem_object_wait_rendering(obj, false);
4014         if (ret)
4015                 return ret;
4016
4017         /* Ensure that we invalidate the GPU's caches and TLBs. */
4018         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4019         return 0;
4020 }
4021
4022 /**
4023  * Moves a single object to the CPU read, and possibly write domain.
4024  *
4025  * This function returns when the move is complete, including waiting on
4026  * flushes to occur.
4027  */
4028 int
4029 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4030 {
4031         uint32_t old_write_domain, old_read_domains;
4032         int ret;
4033
4034         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4035                 return 0;
4036
4037         ret = i915_gem_object_wait_rendering(obj, !write);
4038         if (ret)
4039                 return ret;
4040
4041         i915_gem_object_retire(obj);
4042         i915_gem_object_flush_gtt_write_domain(obj);
4043
4044         old_write_domain = obj->base.write_domain;
4045         old_read_domains = obj->base.read_domains;
4046
4047         /* Flush the CPU cache if it's still invalid. */
4048         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4049                 i915_gem_clflush_object(obj, false);
4050
4051                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4052         }
4053
4054         /* It should now be out of any other write domains, and we can update
4055          * the domain values for our changes.
4056          */
4057         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4058
4059         /* If we're writing through the CPU, then the GPU read domains will
4060          * need to be invalidated at next use.
4061          */
4062         if (write) {
4063                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4064                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4065         }
4066
4067         if (write)
4068                 intel_fb_obj_invalidate(obj, NULL);
4069
4070         trace_i915_gem_object_change_domain(obj,
4071                                             old_read_domains,
4072                                             old_write_domain);
4073
4074         return 0;
4075 }
4076
4077 /* Throttle our rendering by waiting until the ring has completed our requests
4078  * emitted over 20 msec ago.
4079  *
4080  * Note that if we were to use the current jiffies each time around the loop,
4081  * we wouldn't escape the function with any frames outstanding if the time to
4082  * render a frame was over 20ms.
4083  *
4084  * This should get us reasonable parallelism between CPU and GPU but also
4085  * relatively low latency when blocking on a particular request to finish.
4086  */
4087 static int
4088 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4089 {
4090         struct drm_i915_private *dev_priv = dev->dev_private;
4091         struct drm_i915_file_private *file_priv = file->driver_priv;
4092         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4093         struct drm_i915_gem_request *request, *target = NULL;
4094         unsigned reset_counter;
4095         int ret;
4096
4097         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4098         if (ret)
4099                 return ret;
4100
4101         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4102         if (ret)
4103                 return ret;
4104
4105         spin_lock(&file_priv->mm.lock);
4106         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4107                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4108                         break;
4109
4110                 target = request;
4111         }
4112         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4113         if (target)
4114                 i915_gem_request_reference(target);
4115         spin_unlock(&file_priv->mm.lock);
4116
4117         if (target == NULL)
4118                 return 0;
4119
4120         ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4121         if (ret == 0)
4122                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4123
4124         mutex_lock(&dev->struct_mutex);
4125         i915_gem_request_unreference(target);
4126         mutex_unlock(&dev->struct_mutex);
4127
4128         return ret;
4129 }
4130
4131 static bool
4132 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4133 {
4134         struct drm_i915_gem_object *obj = vma->obj;
4135
4136         if (alignment &&
4137             vma->node.start & (alignment - 1))
4138                 return true;
4139
4140         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4141                 return true;
4142
4143         if (flags & PIN_OFFSET_BIAS &&
4144             vma->node.start < (flags & PIN_OFFSET_MASK))
4145                 return true;
4146
4147         return false;
4148 }
4149
4150 int
4151 i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
4152                          struct i915_address_space *vm,
4153                          uint32_t alignment,
4154                          uint64_t flags,
4155                          const struct i915_ggtt_view *view)
4156 {
4157         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4158         struct i915_vma *vma;
4159         unsigned bound;
4160         int ret;
4161
4162         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4163                 return -ENODEV;
4164
4165         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4166                 return -EINVAL;
4167
4168         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4169                 return -EINVAL;
4170
4171         vma = i915_gem_obj_to_vma_view(obj, vm, view);
4172         if (vma) {
4173                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4174                         return -EBUSY;
4175
4176                 if (i915_vma_misplaced(vma, alignment, flags)) {
4177                         WARN(vma->pin_count,
4178                              "bo is already pinned with incorrect alignment:"
4179                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4180                              " obj->map_and_fenceable=%d\n",
4181                              i915_gem_obj_offset_view(obj, vm, view->type),
4182                              alignment,
4183                              !!(flags & PIN_MAPPABLE),
4184                              obj->map_and_fenceable);
4185                         ret = i915_vma_unbind(vma);
4186                         if (ret)
4187                                 return ret;
4188
4189                         vma = NULL;
4190                 }
4191         }
4192
4193         bound = vma ? vma->bound : 0;
4194         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4195                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment,
4196                                                  flags, view);
4197                 if (IS_ERR(vma))
4198                         return PTR_ERR(vma);
4199         }
4200
4201         if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) {
4202                 ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND);
4203                 if (ret)
4204                         return ret;
4205         }
4206
4207         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4208                 bool mappable, fenceable;
4209                 u32 fence_size, fence_alignment;
4210
4211                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4212                                                    obj->base.size,
4213                                                    obj->tiling_mode);
4214                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4215                                                              obj->base.size,
4216                                                              obj->tiling_mode,
4217                                                              true);
4218
4219                 fenceable = (vma->node.size == fence_size &&
4220                              (vma->node.start & (fence_alignment - 1)) == 0);
4221
4222                 mappable = (vma->node.start + obj->base.size <=
4223                             dev_priv->gtt.mappable_end);
4224
4225                 obj->map_and_fenceable = mappable && fenceable;
4226         }
4227
4228         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4229
4230         vma->pin_count++;
4231         if (flags & PIN_MAPPABLE)
4232                 obj->pin_mappable |= true;
4233
4234         return 0;
4235 }
4236
4237 void
4238 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4239 {
4240         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4241
4242         BUG_ON(!vma);
4243         BUG_ON(vma->pin_count == 0);
4244         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4245
4246         if (--vma->pin_count == 0)
4247                 obj->pin_mappable = false;
4248 }
4249
4250 bool
4251 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4252 {
4253         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4254                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4255                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4256
4257                 WARN_ON(!ggtt_vma ||
4258                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4259                         ggtt_vma->pin_count);
4260                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4261                 return true;
4262         } else
4263                 return false;
4264 }
4265
4266 void
4267 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4268 {
4269         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4270                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4271                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4272                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4273         }
4274 }
4275
4276 int
4277 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4278                     struct drm_file *file)
4279 {
4280         struct drm_i915_gem_busy *args = data;
4281         struct drm_i915_gem_object *obj;
4282         int ret;
4283
4284         ret = i915_mutex_lock_interruptible(dev);
4285         if (ret)
4286                 return ret;
4287
4288         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4289         if (&obj->base == NULL) {
4290                 ret = -ENOENT;
4291                 goto unlock;
4292         }
4293
4294         /* Count all active objects as busy, even if they are currently not used
4295          * by the gpu. Users of this interface expect objects to eventually
4296          * become non-busy without any further actions, therefore emit any
4297          * necessary flushes here.
4298          */
4299         ret = i915_gem_object_flush_active(obj);
4300
4301         args->busy = obj->active;
4302         if (obj->last_read_req) {
4303                 struct intel_engine_cs *ring;
4304                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4305                 ring = i915_gem_request_get_ring(obj->last_read_req);
4306                 args->busy |= intel_ring_flag(ring) << 16;
4307         }
4308
4309         drm_gem_object_unreference(&obj->base);
4310 unlock:
4311         mutex_unlock(&dev->struct_mutex);
4312         return ret;
4313 }
4314
4315 int
4316 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4317                         struct drm_file *file_priv)
4318 {
4319         return i915_gem_ring_throttle(dev, file_priv);
4320 }
4321
4322 int
4323 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4324                        struct drm_file *file_priv)
4325 {
4326         struct drm_i915_private *dev_priv = dev->dev_private;
4327         struct drm_i915_gem_madvise *args = data;
4328         struct drm_i915_gem_object *obj;
4329         int ret;
4330
4331         switch (args->madv) {
4332         case I915_MADV_DONTNEED:
4333         case I915_MADV_WILLNEED:
4334             break;
4335         default:
4336             return -EINVAL;
4337         }
4338
4339         ret = i915_mutex_lock_interruptible(dev);
4340         if (ret)
4341                 return ret;
4342
4343         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4344         if (&obj->base == NULL) {
4345                 ret = -ENOENT;
4346                 goto unlock;
4347         }
4348
4349         if (i915_gem_obj_is_pinned(obj)) {
4350                 ret = -EINVAL;
4351                 goto out;
4352         }
4353
4354         if (obj->pages &&
4355             obj->tiling_mode != I915_TILING_NONE &&
4356             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4357                 if (obj->madv == I915_MADV_WILLNEED)
4358                         i915_gem_object_unpin_pages(obj);
4359                 if (args->madv == I915_MADV_WILLNEED)
4360                         i915_gem_object_pin_pages(obj);
4361         }
4362
4363         if (obj->madv != __I915_MADV_PURGED)
4364                 obj->madv = args->madv;
4365
4366         /* if the object is no longer attached, discard its backing storage */
4367         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4368                 i915_gem_object_truncate(obj);
4369
4370         args->retained = obj->madv != __I915_MADV_PURGED;
4371
4372 out:
4373         drm_gem_object_unreference(&obj->base);
4374 unlock:
4375         mutex_unlock(&dev->struct_mutex);
4376         return ret;
4377 }
4378
4379 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4380                           const struct drm_i915_gem_object_ops *ops)
4381 {
4382         INIT_LIST_HEAD(&obj->global_list);
4383         INIT_LIST_HEAD(&obj->ring_list);
4384         INIT_LIST_HEAD(&obj->obj_exec_link);
4385         INIT_LIST_HEAD(&obj->vma_list);
4386         INIT_LIST_HEAD(&obj->batch_pool_list);
4387
4388         obj->ops = ops;
4389
4390         obj->fence_reg = I915_FENCE_REG_NONE;
4391         obj->madv = I915_MADV_WILLNEED;
4392
4393         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4394 }
4395
4396 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4397         .get_pages = i915_gem_object_get_pages_gtt,
4398         .put_pages = i915_gem_object_put_pages_gtt,
4399 };
4400
4401 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4402                                                   size_t size)
4403 {
4404         struct drm_i915_gem_object *obj;
4405         struct address_space *mapping;
4406         gfp_t mask;
4407
4408         obj = i915_gem_object_alloc(dev);
4409         if (obj == NULL)
4410                 return NULL;
4411
4412         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4413                 i915_gem_object_free(obj);
4414                 return NULL;
4415         }
4416
4417         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4418         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4419                 /* 965gm cannot relocate objects above 4GiB. */
4420                 mask &= ~__GFP_HIGHMEM;
4421                 mask |= __GFP_DMA32;
4422         }
4423
4424         mapping = file_inode(obj->base.filp)->i_mapping;
4425         mapping_set_gfp_mask(mapping, mask);
4426
4427         i915_gem_object_init(obj, &i915_gem_object_ops);
4428
4429         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4430         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4431
4432         if (HAS_LLC(dev)) {
4433                 /* On some devices, we can have the GPU use the LLC (the CPU
4434                  * cache) for about a 10% performance improvement
4435                  * compared to uncached.  Graphics requests other than
4436                  * display scanout are coherent with the CPU in
4437                  * accessing this cache.  This means in this mode we
4438                  * don't need to clflush on the CPU side, and on the
4439                  * GPU side we only need to flush internal caches to
4440                  * get data visible to the CPU.
4441                  *
4442                  * However, we maintain the display planes as UC, and so
4443                  * need to rebind when first used as such.
4444                  */
4445                 obj->cache_level = I915_CACHE_LLC;
4446         } else
4447                 obj->cache_level = I915_CACHE_NONE;
4448
4449         trace_i915_gem_object_create(obj);
4450
4451         return obj;
4452 }
4453
4454 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4455 {
4456         /* If we are the last user of the backing storage (be it shmemfs
4457          * pages or stolen etc), we know that the pages are going to be
4458          * immediately released. In this case, we can then skip copying
4459          * back the contents from the GPU.
4460          */
4461
4462         if (obj->madv != I915_MADV_WILLNEED)
4463                 return false;
4464
4465         if (obj->base.filp == NULL)
4466                 return true;
4467
4468         /* At first glance, this looks racy, but then again so would be
4469          * userspace racing mmap against close. However, the first external
4470          * reference to the filp can only be obtained through the
4471          * i915_gem_mmap_ioctl() which safeguards us against the user
4472          * acquiring such a reference whilst we are in the middle of
4473          * freeing the object.
4474          */
4475         return atomic_long_read(&obj->base.filp->f_count) == 1;
4476 }
4477
4478 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4479 {
4480         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4481         struct drm_device *dev = obj->base.dev;
4482         struct drm_i915_private *dev_priv = dev->dev_private;
4483         struct i915_vma *vma, *next;
4484
4485         intel_runtime_pm_get(dev_priv);
4486
4487         trace_i915_gem_object_destroy(obj);
4488
4489         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4490                 int ret;
4491
4492                 vma->pin_count = 0;
4493                 ret = i915_vma_unbind(vma);
4494                 if (WARN_ON(ret == -ERESTARTSYS)) {
4495                         bool was_interruptible;
4496
4497                         was_interruptible = dev_priv->mm.interruptible;
4498                         dev_priv->mm.interruptible = false;
4499
4500                         WARN_ON(i915_vma_unbind(vma));
4501
4502                         dev_priv->mm.interruptible = was_interruptible;
4503                 }
4504         }
4505
4506         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4507          * before progressing. */
4508         if (obj->stolen)
4509                 i915_gem_object_unpin_pages(obj);
4510
4511         WARN_ON(obj->frontbuffer_bits);
4512
4513         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4514             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4515             obj->tiling_mode != I915_TILING_NONE)
4516                 i915_gem_object_unpin_pages(obj);
4517
4518         if (WARN_ON(obj->pages_pin_count))
4519                 obj->pages_pin_count = 0;
4520         if (discard_backing_storage(obj))
4521                 obj->madv = I915_MADV_DONTNEED;
4522         i915_gem_object_put_pages(obj);
4523         i915_gem_object_free_mmap_offset(obj);
4524
4525         BUG_ON(obj->pages);
4526
4527         if (obj->base.import_attach)
4528                 drm_prime_gem_destroy(&obj->base, NULL);
4529
4530         if (obj->ops->release)
4531                 obj->ops->release(obj);
4532
4533         drm_gem_object_release(&obj->base);
4534         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4535
4536         kfree(obj->bit_17);
4537         i915_gem_object_free(obj);
4538
4539         intel_runtime_pm_put(dev_priv);
4540 }
4541
4542 struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj,
4543                                           struct i915_address_space *vm,
4544                                           const struct i915_ggtt_view *view)
4545 {
4546         struct i915_vma *vma;
4547         list_for_each_entry(vma, &obj->vma_list, vma_link)
4548                 if (vma->vm == vm && vma->ggtt_view.type == view->type)
4549                         return vma;
4550
4551         return NULL;
4552 }
4553
4554 void i915_gem_vma_destroy(struct i915_vma *vma)
4555 {
4556         struct i915_address_space *vm = NULL;
4557         WARN_ON(vma->node.allocated);
4558
4559         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4560         if (!list_empty(&vma->exec_list))
4561                 return;
4562
4563         vm = vma->vm;
4564
4565         if (!i915_is_ggtt(vm))
4566                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4567
4568         list_del(&vma->vma_link);
4569
4570         kfree(vma);
4571 }
4572
4573 static void
4574 i915_gem_stop_ringbuffers(struct drm_device *dev)
4575 {
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         struct intel_engine_cs *ring;
4578         int i;
4579
4580         for_each_ring(ring, dev_priv, i)
4581                 dev_priv->gt.stop_ring(ring);
4582 }
4583
4584 int
4585 i915_gem_suspend(struct drm_device *dev)
4586 {
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588         int ret = 0;
4589
4590         mutex_lock(&dev->struct_mutex);
4591         ret = i915_gpu_idle(dev);
4592         if (ret)
4593                 goto err;
4594
4595         i915_gem_retire_requests(dev);
4596
4597         /* Under UMS, be paranoid and evict. */
4598         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4599                 i915_gem_evict_everything(dev);
4600
4601         i915_gem_stop_ringbuffers(dev);
4602         mutex_unlock(&dev->struct_mutex);
4603
4604         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4605         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4606         flush_delayed_work(&dev_priv->mm.idle_work);
4607
4608         /* Assert that we sucessfully flushed all the work and
4609          * reset the GPU back to its idle, low power state.
4610          */
4611         WARN_ON(dev_priv->mm.busy);
4612
4613         return 0;
4614
4615 err:
4616         mutex_unlock(&dev->struct_mutex);
4617         return ret;
4618 }
4619
4620 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4621 {
4622         struct drm_device *dev = ring->dev;
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4625         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4626         int i, ret;
4627
4628         if (!HAS_L3_DPF(dev) || !remap_info)
4629                 return 0;
4630
4631         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4632         if (ret)
4633                 return ret;
4634
4635         /*
4636          * Note: We do not worry about the concurrent register cacheline hang
4637          * here because no other code should access these registers other than
4638          * at initialization time.
4639          */
4640         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4641                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4642                 intel_ring_emit(ring, reg_base + i);
4643                 intel_ring_emit(ring, remap_info[i/4]);
4644         }
4645
4646         intel_ring_advance(ring);
4647
4648         return ret;
4649 }
4650
4651 void i915_gem_init_swizzling(struct drm_device *dev)
4652 {
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654
4655         if (INTEL_INFO(dev)->gen < 5 ||
4656             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4657                 return;
4658
4659         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4660                                  DISP_TILE_SURFACE_SWIZZLING);
4661
4662         if (IS_GEN5(dev))
4663                 return;
4664
4665         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4666         if (IS_GEN6(dev))
4667                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4668         else if (IS_GEN7(dev))
4669                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4670         else if (IS_GEN8(dev))
4671                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4672         else
4673                 BUG();
4674 }
4675
4676 static bool
4677 intel_enable_blt(struct drm_device *dev)
4678 {
4679         if (!HAS_BLT(dev))
4680                 return false;
4681
4682         /* The blitter was dysfunctional on early prototypes */
4683         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4684                 DRM_INFO("BLT not supported on this pre-production hardware;"
4685                          " graphics performance will be degraded.\n");
4686                 return false;
4687         }
4688
4689         return true;
4690 }
4691
4692 static void init_unused_ring(struct drm_device *dev, u32 base)
4693 {
4694         struct drm_i915_private *dev_priv = dev->dev_private;
4695
4696         I915_WRITE(RING_CTL(base), 0);
4697         I915_WRITE(RING_HEAD(base), 0);
4698         I915_WRITE(RING_TAIL(base), 0);
4699         I915_WRITE(RING_START(base), 0);
4700 }
4701
4702 static void init_unused_rings(struct drm_device *dev)
4703 {
4704         if (IS_I830(dev)) {
4705                 init_unused_ring(dev, PRB1_BASE);
4706                 init_unused_ring(dev, SRB0_BASE);
4707                 init_unused_ring(dev, SRB1_BASE);
4708                 init_unused_ring(dev, SRB2_BASE);
4709                 init_unused_ring(dev, SRB3_BASE);
4710         } else if (IS_GEN2(dev)) {
4711                 init_unused_ring(dev, SRB0_BASE);
4712                 init_unused_ring(dev, SRB1_BASE);
4713         } else if (IS_GEN3(dev)) {
4714                 init_unused_ring(dev, PRB1_BASE);
4715                 init_unused_ring(dev, PRB2_BASE);
4716         }
4717 }
4718
4719 int i915_gem_init_rings(struct drm_device *dev)
4720 {
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         int ret;
4723
4724         ret = intel_init_render_ring_buffer(dev);
4725         if (ret)
4726                 return ret;
4727
4728         if (HAS_BSD(dev)) {
4729                 ret = intel_init_bsd_ring_buffer(dev);
4730                 if (ret)
4731                         goto cleanup_render_ring;
4732         }
4733
4734         if (intel_enable_blt(dev)) {
4735                 ret = intel_init_blt_ring_buffer(dev);
4736                 if (ret)
4737                         goto cleanup_bsd_ring;
4738         }
4739
4740         if (HAS_VEBOX(dev)) {
4741                 ret = intel_init_vebox_ring_buffer(dev);
4742                 if (ret)
4743                         goto cleanup_blt_ring;
4744         }
4745
4746         if (HAS_BSD2(dev)) {
4747                 ret = intel_init_bsd2_ring_buffer(dev);
4748                 if (ret)
4749                         goto cleanup_vebox_ring;
4750         }
4751
4752         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4753         if (ret)
4754                 goto cleanup_bsd2_ring;
4755
4756         return 0;
4757
4758 cleanup_bsd2_ring:
4759         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4760 cleanup_vebox_ring:
4761         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4762 cleanup_blt_ring:
4763         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4764 cleanup_bsd_ring:
4765         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4766 cleanup_render_ring:
4767         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4768
4769         return ret;
4770 }
4771
4772 int
4773 i915_gem_init_hw(struct drm_device *dev)
4774 {
4775         struct drm_i915_private *dev_priv = dev->dev_private;
4776         struct intel_engine_cs *ring;
4777         int ret, i;
4778
4779         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4780                 return -EIO;
4781
4782         if (dev_priv->ellc_size)
4783                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4784
4785         if (IS_HASWELL(dev))
4786                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4787                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4788
4789         if (HAS_PCH_NOP(dev)) {
4790                 if (IS_IVYBRIDGE(dev)) {
4791                         u32 temp = I915_READ(GEN7_MSG_CTL);
4792                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4793                         I915_WRITE(GEN7_MSG_CTL, temp);
4794                 } else if (INTEL_INFO(dev)->gen >= 7) {
4795                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4796                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4797                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4798                 }
4799         }
4800
4801         i915_gem_init_swizzling(dev);
4802
4803         /*
4804          * At least 830 can leave some of the unused rings
4805          * "active" (ie. head != tail) after resume which
4806          * will prevent c3 entry. Makes sure all unused rings
4807          * are totally idle.
4808          */
4809         init_unused_rings(dev);
4810
4811         for_each_ring(ring, dev_priv, i) {
4812                 ret = ring->init_hw(ring);
4813                 if (ret)
4814                         return ret;
4815         }
4816
4817         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4818                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4819
4820         /*
4821          * XXX: Contexts should only be initialized once. Doing a switch to the
4822          * default context switch however is something we'd like to do after
4823          * reset or thaw (the latter may not actually be necessary for HW, but
4824          * goes with our code better). Context switching requires rings (for
4825          * the do_switch), but before enabling PPGTT. So don't move this.
4826          */
4827         ret = i915_gem_context_enable(dev_priv);
4828         if (ret && ret != -EIO) {
4829                 DRM_ERROR("Context enable failed %d\n", ret);
4830                 i915_gem_cleanup_ringbuffer(dev);
4831
4832                 return ret;
4833         }
4834
4835         ret = i915_ppgtt_init_hw(dev);
4836         if (ret && ret != -EIO) {
4837                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4838                 i915_gem_cleanup_ringbuffer(dev);
4839         }
4840
4841         return ret;
4842 }
4843
4844 int i915_gem_init(struct drm_device *dev)
4845 {
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         int ret;
4848
4849         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4850                         i915.enable_execlists);
4851
4852         mutex_lock(&dev->struct_mutex);
4853
4854         if (IS_VALLEYVIEW(dev)) {
4855                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4856                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4857                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4858                               VLV_GTLC_ALLOWWAKEACK), 10))
4859                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4860         }
4861
4862         if (!i915.enable_execlists) {
4863                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4864                 dev_priv->gt.init_rings = i915_gem_init_rings;
4865                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4866                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4867         } else {
4868                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4869                 dev_priv->gt.init_rings = intel_logical_rings_init;
4870                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4871                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4872         }
4873
4874         ret = i915_gem_init_userptr(dev);
4875         if (ret)
4876                 goto out_unlock;
4877
4878         i915_gem_init_global_gtt(dev);
4879
4880         ret = i915_gem_context_init(dev);
4881         if (ret)
4882                 goto out_unlock;
4883
4884         ret = dev_priv->gt.init_rings(dev);
4885         if (ret)
4886                 goto out_unlock;
4887
4888         ret = i915_gem_init_hw(dev);
4889         if (ret == -EIO) {
4890                 /* Allow ring initialisation to fail by marking the GPU as
4891                  * wedged. But we only want to do this where the GPU is angry,
4892                  * for all other failure, such as an allocation failure, bail.
4893                  */
4894                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4895                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4896                 ret = 0;
4897         }
4898
4899 out_unlock:
4900         mutex_unlock(&dev->struct_mutex);
4901
4902         return ret;
4903 }
4904
4905 void
4906 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4907 {
4908         struct drm_i915_private *dev_priv = dev->dev_private;
4909         struct intel_engine_cs *ring;
4910         int i;
4911
4912         for_each_ring(ring, dev_priv, i)
4913                 dev_priv->gt.cleanup_ring(ring);
4914 }
4915
4916 static void
4917 init_ring_lists(struct intel_engine_cs *ring)
4918 {
4919         INIT_LIST_HEAD(&ring->active_list);
4920         INIT_LIST_HEAD(&ring->request_list);
4921 }
4922
4923 void i915_init_vm(struct drm_i915_private *dev_priv,
4924                   struct i915_address_space *vm)
4925 {
4926         if (!i915_is_ggtt(vm))
4927                 drm_mm_init(&vm->mm, vm->start, vm->total);
4928         vm->dev = dev_priv->dev;
4929         INIT_LIST_HEAD(&vm->active_list);
4930         INIT_LIST_HEAD(&vm->inactive_list);
4931         INIT_LIST_HEAD(&vm->global_link);
4932         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4933 }
4934
4935 void
4936 i915_gem_load(struct drm_device *dev)
4937 {
4938         struct drm_i915_private *dev_priv = dev->dev_private;
4939         int i;
4940
4941         dev_priv->slab =
4942                 kmem_cache_create("i915_gem_object",
4943                                   sizeof(struct drm_i915_gem_object), 0,
4944                                   SLAB_HWCACHE_ALIGN,
4945                                   NULL);
4946
4947         INIT_LIST_HEAD(&dev_priv->vm_list);
4948         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4949
4950         INIT_LIST_HEAD(&dev_priv->context_list);
4951         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4952         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4953         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4954         for (i = 0; i < I915_NUM_RINGS; i++)
4955                 init_ring_lists(&dev_priv->ring[i]);
4956         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4957                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4958         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4959                           i915_gem_retire_work_handler);
4960         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4961                           i915_gem_idle_work_handler);
4962         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4963
4964         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4965         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4966                 I915_WRITE(MI_ARB_STATE,
4967                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4968         }
4969
4970         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4971
4972         /* Old X drivers will take 0-2 for front, back, depth buffers */
4973         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4974                 dev_priv->fence_reg_start = 3;
4975
4976         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4977                 dev_priv->num_fence_regs = 32;
4978         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4979                 dev_priv->num_fence_regs = 16;
4980         else
4981                 dev_priv->num_fence_regs = 8;
4982
4983         /* Initialize fence registers to zero */
4984         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4985         i915_gem_restore_fences(dev);
4986
4987         i915_gem_detect_bit_6_swizzle(dev);
4988         init_waitqueue_head(&dev_priv->pending_flip_queue);
4989
4990         dev_priv->mm.interruptible = true;
4991
4992         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4993         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4994         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4995         register_shrinker(&dev_priv->mm.shrinker);
4996
4997         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4998         register_oom_notifier(&dev_priv->mm.oom_notifier);
4999
5000         i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool);
5001
5002         mutex_init(&dev_priv->fb_tracking.lock);
5003 }
5004
5005 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5006 {
5007         struct drm_i915_file_private *file_priv = file->driver_priv;
5008
5009         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5010
5011         /* Clean up our request list when the client is going away, so that
5012          * later retire_requests won't dereference our soon-to-be-gone
5013          * file_priv.
5014          */
5015         spin_lock(&file_priv->mm.lock);
5016         while (!list_empty(&file_priv->mm.request_list)) {
5017                 struct drm_i915_gem_request *request;
5018
5019                 request = list_first_entry(&file_priv->mm.request_list,
5020                                            struct drm_i915_gem_request,
5021                                            client_list);
5022                 list_del(&request->client_list);
5023                 request->file_priv = NULL;
5024         }
5025         spin_unlock(&file_priv->mm.lock);
5026 }
5027
5028 static void
5029 i915_gem_file_idle_work_handler(struct work_struct *work)
5030 {
5031         struct drm_i915_file_private *file_priv =
5032                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5033
5034         atomic_set(&file_priv->rps_wait_boost, false);
5035 }
5036
5037 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5038 {
5039         struct drm_i915_file_private *file_priv;
5040         int ret;
5041
5042         DRM_DEBUG_DRIVER("\n");
5043
5044         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5045         if (!file_priv)
5046                 return -ENOMEM;
5047
5048         file->driver_priv = file_priv;
5049         file_priv->dev_priv = dev->dev_private;
5050         file_priv->file = file;
5051
5052         spin_lock_init(&file_priv->mm.lock);
5053         INIT_LIST_HEAD(&file_priv->mm.request_list);
5054         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5055                           i915_gem_file_idle_work_handler);
5056
5057         ret = i915_gem_context_open(dev, file);
5058         if (ret)
5059                 kfree(file_priv);
5060
5061         return ret;
5062 }
5063
5064 /**
5065  * i915_gem_track_fb - update frontbuffer tracking
5066  * old: current GEM buffer for the frontbuffer slots
5067  * new: new GEM buffer for the frontbuffer slots
5068  * frontbuffer_bits: bitmask of frontbuffer slots
5069  *
5070  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5071  * from @old and setting them in @new. Both @old and @new can be NULL.
5072  */
5073 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5074                        struct drm_i915_gem_object *new,
5075                        unsigned frontbuffer_bits)
5076 {
5077         if (old) {
5078                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5079                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5080                 old->frontbuffer_bits &= ~frontbuffer_bits;
5081         }
5082
5083         if (new) {
5084                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5085                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5086                 new->frontbuffer_bits |= frontbuffer_bits;
5087         }
5088 }
5089
5090 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5091 {
5092         if (!mutex_is_locked(mutex))
5093                 return false;
5094
5095 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5096         return mutex->owner == task;
5097 #else
5098         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5099         return false;
5100 #endif
5101 }
5102
5103 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5104 {
5105         if (!mutex_trylock(&dev->struct_mutex)) {
5106                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5107                         return false;
5108
5109                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5110                         return false;
5111
5112                 *unlock = false;
5113         } else
5114                 *unlock = true;
5115
5116         return true;
5117 }
5118
5119 static int num_vma_bound(struct drm_i915_gem_object *obj)
5120 {
5121         struct i915_vma *vma;
5122         int count = 0;
5123
5124         list_for_each_entry(vma, &obj->vma_list, vma_link)
5125                 if (drm_mm_node_allocated(&vma->node))
5126                         count++;
5127
5128         return count;
5129 }
5130
5131 static unsigned long
5132 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5133 {
5134         struct drm_i915_private *dev_priv =
5135                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5136         struct drm_device *dev = dev_priv->dev;
5137         struct drm_i915_gem_object *obj;
5138         unsigned long count;
5139         bool unlock;
5140
5141         if (!i915_gem_shrinker_lock(dev, &unlock))
5142                 return 0;
5143
5144         count = 0;
5145         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5146                 if (obj->pages_pin_count == 0)
5147                         count += obj->base.size >> PAGE_SHIFT;
5148
5149         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5150                 if (!i915_gem_obj_is_pinned(obj) &&
5151                     obj->pages_pin_count == num_vma_bound(obj))
5152                         count += obj->base.size >> PAGE_SHIFT;
5153         }
5154
5155         if (unlock)
5156                 mutex_unlock(&dev->struct_mutex);
5157
5158         return count;
5159 }
5160
5161 /* All the new VM stuff */
5162 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o,
5163                                        struct i915_address_space *vm,
5164                                        enum i915_ggtt_view_type view)
5165 {
5166         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5167         struct i915_vma *vma;
5168
5169         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5170
5171         list_for_each_entry(vma, &o->vma_list, vma_link) {
5172                 if (vma->vm == vm && vma->ggtt_view.type == view)
5173                         return vma->node.start;
5174
5175         }
5176         WARN(1, "%s vma for this object not found.\n",
5177              i915_is_ggtt(vm) ? "global" : "ppgtt");
5178         return -1;
5179 }
5180
5181 bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o,
5182                              struct i915_address_space *vm,
5183                              enum i915_ggtt_view_type view)
5184 {
5185         struct i915_vma *vma;
5186
5187         list_for_each_entry(vma, &o->vma_list, vma_link)
5188                 if (vma->vm == vm &&
5189                     vma->ggtt_view.type == view &&
5190                     drm_mm_node_allocated(&vma->node))
5191                         return true;
5192
5193         return false;
5194 }
5195
5196 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5197 {
5198         struct i915_vma *vma;
5199
5200         list_for_each_entry(vma, &o->vma_list, vma_link)
5201                 if (drm_mm_node_allocated(&vma->node))
5202                         return true;
5203
5204         return false;
5205 }
5206
5207 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5208                                 struct i915_address_space *vm)
5209 {
5210         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5211         struct i915_vma *vma;
5212
5213         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5214
5215         BUG_ON(list_empty(&o->vma_list));
5216
5217         list_for_each_entry(vma, &o->vma_list, vma_link)
5218                 if (vma->vm == vm)
5219                         return vma->node.size;
5220
5221         return 0;
5222 }
5223
5224 static unsigned long
5225 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5226 {
5227         struct drm_i915_private *dev_priv =
5228                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5229         struct drm_device *dev = dev_priv->dev;
5230         unsigned long freed;
5231         bool unlock;
5232
5233         if (!i915_gem_shrinker_lock(dev, &unlock))
5234                 return SHRINK_STOP;
5235
5236         freed = i915_gem_shrink(dev_priv,
5237                                 sc->nr_to_scan,
5238                                 I915_SHRINK_BOUND |
5239                                 I915_SHRINK_UNBOUND |
5240                                 I915_SHRINK_PURGEABLE);
5241         if (freed < sc->nr_to_scan)
5242                 freed += i915_gem_shrink(dev_priv,
5243                                          sc->nr_to_scan - freed,
5244                                          I915_SHRINK_BOUND |
5245                                          I915_SHRINK_UNBOUND);
5246         if (unlock)
5247                 mutex_unlock(&dev->struct_mutex);
5248
5249         return freed;
5250 }
5251
5252 static int
5253 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5254 {
5255         struct drm_i915_private *dev_priv =
5256                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5257         struct drm_device *dev = dev_priv->dev;
5258         struct drm_i915_gem_object *obj;
5259         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5260         unsigned long pinned, bound, unbound, freed_pages;
5261         bool was_interruptible;
5262         bool unlock;
5263
5264         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5265                 schedule_timeout_killable(1);
5266                 if (fatal_signal_pending(current))
5267                         return NOTIFY_DONE;
5268         }
5269         if (timeout == 0) {
5270                 pr_err("Unable to purge GPU memory due lock contention.\n");
5271                 return NOTIFY_DONE;
5272         }
5273
5274         was_interruptible = dev_priv->mm.interruptible;
5275         dev_priv->mm.interruptible = false;
5276
5277         freed_pages = i915_gem_shrink_all(dev_priv);
5278
5279         dev_priv->mm.interruptible = was_interruptible;
5280
5281         /* Because we may be allocating inside our own driver, we cannot
5282          * assert that there are no objects with pinned pages that are not
5283          * being pointed to by hardware.
5284          */
5285         unbound = bound = pinned = 0;
5286         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5287                 if (!obj->base.filp) /* not backed by a freeable object */
5288                         continue;
5289
5290                 if (obj->pages_pin_count)
5291                         pinned += obj->base.size;
5292                 else
5293                         unbound += obj->base.size;
5294         }
5295         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5296                 if (!obj->base.filp)
5297                         continue;
5298
5299                 if (obj->pages_pin_count)
5300                         pinned += obj->base.size;
5301                 else
5302                         bound += obj->base.size;
5303         }
5304
5305         if (unlock)
5306                 mutex_unlock(&dev->struct_mutex);
5307
5308         if (freed_pages || unbound || bound)
5309                 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5310                         freed_pages << PAGE_SHIFT, pinned);
5311         if (unbound || bound)
5312                 pr_err("%lu and %lu bytes still available in the "
5313                        "bound and unbound GPU page lists.\n",
5314                        bound, unbound);
5315
5316         *(unsigned long *)ptr += freed_pages;
5317         return NOTIFY_DONE;
5318 }
5319
5320 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5321 {
5322         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
5323         struct i915_vma *vma;
5324
5325         list_for_each_entry(vma, &obj->vma_list, vma_link)
5326                 if (vma->vm == ggtt &&
5327                     vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5328                         return vma;
5329
5330         return NULL;
5331 }