2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_frontbuffer.h"
36 #include "intel_mocs.h"
37 #include <linux/dma-fence-array.h>
38 #include <linux/kthread.h>
39 #include <linux/reservation.h>
40 #include <linux/shmem_fs.h>
41 #include <linux/slab.h>
42 #include <linux/stop_machine.h>
43 #include <linux/swap.h>
44 #include <linux/pci.h>
45 #include <linux/dma-buf.h>
47 static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
48 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
49 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
51 static bool cpu_cache_is_coherent(struct drm_device *dev,
52 enum i915_cache_level level)
54 return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
57 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
59 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
62 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
65 return obj->pin_display;
69 insert_mappable_node(struct i915_ggtt *ggtt,
70 struct drm_mm_node *node, u32 size)
72 memset(node, 0, sizeof(*node));
73 return drm_mm_insert_node_in_range(&ggtt->base.mm, node,
74 size, 0, I915_COLOR_UNEVICTABLE,
75 0, ggtt->mappable_end,
80 remove_mappable_node(struct drm_mm_node *node)
82 drm_mm_remove_node(node);
85 /* some bookkeeping */
86 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
89 spin_lock(&dev_priv->mm.object_stat_lock);
90 dev_priv->mm.object_count++;
91 dev_priv->mm.object_memory += size;
92 spin_unlock(&dev_priv->mm.object_stat_lock);
95 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
98 spin_lock(&dev_priv->mm.object_stat_lock);
99 dev_priv->mm.object_count--;
100 dev_priv->mm.object_memory -= size;
101 spin_unlock(&dev_priv->mm.object_stat_lock);
105 i915_gem_wait_for_error(struct i915_gpu_error *error)
111 if (!i915_reset_in_progress(error))
115 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
116 * userspace. If it takes that long something really bad is going on and
117 * we should simply try to bail out and fail as gracefully as possible.
119 ret = wait_event_interruptible_timeout(error->reset_queue,
120 !i915_reset_in_progress(error),
123 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
125 } else if (ret < 0) {
132 int i915_mutex_lock_interruptible(struct drm_device *dev)
134 struct drm_i915_private *dev_priv = to_i915(dev);
137 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
141 ret = mutex_lock_interruptible(&dev->struct_mutex);
149 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file)
152 struct drm_i915_private *dev_priv = to_i915(dev);
153 struct i915_ggtt *ggtt = &dev_priv->ggtt;
154 struct drm_i915_gem_get_aperture *args = data;
155 struct i915_vma *vma;
159 mutex_lock(&dev->struct_mutex);
160 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
161 if (i915_vma_is_pinned(vma))
162 pinned += vma->node.size;
163 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
164 if (i915_vma_is_pinned(vma))
165 pinned += vma->node.size;
166 mutex_unlock(&dev->struct_mutex);
168 args->aper_size = ggtt->base.total;
169 args->aper_available_size = args->aper_size - pinned;
174 static struct sg_table *
175 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
177 struct address_space *mapping = obj->base.filp->f_mapping;
178 drm_dma_handle_t *phys;
180 struct scatterlist *sg;
184 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
185 return ERR_PTR(-EINVAL);
187 /* Always aligning to the object size, allows a single allocation
188 * to handle all possible callers, and given typical object sizes,
189 * the alignment of the buddy allocation will naturally match.
191 phys = drm_pci_alloc(obj->base.dev,
193 roundup_pow_of_two(obj->base.size));
195 return ERR_PTR(-ENOMEM);
198 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
202 page = shmem_read_mapping_page(mapping, i);
208 src = kmap_atomic(page);
209 memcpy(vaddr, src, PAGE_SIZE);
210 drm_clflush_virt_range(vaddr, PAGE_SIZE);
217 i915_gem_chipset_flush(to_i915(obj->base.dev));
219 st = kmalloc(sizeof(*st), GFP_KERNEL);
221 st = ERR_PTR(-ENOMEM);
225 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
227 st = ERR_PTR(-ENOMEM);
233 sg->length = obj->base.size;
235 sg_dma_address(sg) = phys->busaddr;
236 sg_dma_len(sg) = obj->base.size;
238 obj->phys_handle = phys;
242 drm_pci_free(obj->base.dev, phys);
247 __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
248 struct sg_table *pages,
251 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
253 if (obj->mm.madv == I915_MADV_DONTNEED)
254 obj->mm.dirty = false;
257 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
258 !cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
259 drm_clflush_sg(pages);
261 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
262 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
266 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
267 struct sg_table *pages)
269 __i915_gem_object_release_shmem(obj, pages, false);
272 struct address_space *mapping = obj->base.filp->f_mapping;
273 char *vaddr = obj->phys_handle->vaddr;
276 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
280 page = shmem_read_mapping_page(mapping, i);
284 dst = kmap_atomic(page);
285 drm_clflush_virt_range(vaddr, PAGE_SIZE);
286 memcpy(dst, vaddr, PAGE_SIZE);
289 set_page_dirty(page);
290 if (obj->mm.madv == I915_MADV_WILLNEED)
291 mark_page_accessed(page);
295 obj->mm.dirty = false;
298 sg_free_table(pages);
301 drm_pci_free(obj->base.dev, obj->phys_handle);
305 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
307 i915_gem_object_unpin_pages(obj);
310 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
311 .get_pages = i915_gem_object_get_pages_phys,
312 .put_pages = i915_gem_object_put_pages_phys,
313 .release = i915_gem_object_release_phys,
316 int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
318 struct i915_vma *vma;
319 LIST_HEAD(still_in_list);
322 lockdep_assert_held(&obj->base.dev->struct_mutex);
324 /* Closed vma are removed from the obj->vma_list - but they may
325 * still have an active binding on the object. To remove those we
326 * must wait for all rendering to complete to the object (as unbinding
327 * must anyway), and retire the requests.
329 ret = i915_gem_object_wait(obj,
330 I915_WAIT_INTERRUPTIBLE |
333 MAX_SCHEDULE_TIMEOUT,
338 i915_gem_retire_requests(to_i915(obj->base.dev));
340 while ((vma = list_first_entry_or_null(&obj->vma_list,
343 list_move_tail(&vma->obj_link, &still_in_list);
344 ret = i915_vma_unbind(vma);
348 list_splice(&still_in_list, &obj->vma_list);
354 i915_gem_object_wait_fence(struct dma_fence *fence,
357 struct intel_rps_client *rps)
359 struct drm_i915_gem_request *rq;
361 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
363 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
366 if (!dma_fence_is_i915(fence))
367 return dma_fence_wait_timeout(fence,
368 flags & I915_WAIT_INTERRUPTIBLE,
371 rq = to_request(fence);
372 if (i915_gem_request_completed(rq))
375 /* This client is about to stall waiting for the GPU. In many cases
376 * this is undesirable and limits the throughput of the system, as
377 * many clients cannot continue processing user input/output whilst
378 * blocked. RPS autotuning may take tens of milliseconds to respond
379 * to the GPU load and thus incurs additional latency for the client.
380 * We can circumvent that by promoting the GPU frequency to maximum
381 * before we wait. This makes the GPU throttle up much more quickly
382 * (good for benchmarks and user experience, e.g. window animations),
383 * but at a cost of spending more power processing the workload
384 * (bad for battery). Not all clients even want their results
385 * immediately and for them we should just let the GPU select its own
386 * frequency to maximise efficiency. To prevent a single client from
387 * forcing the clocks too high for the whole system, we only allow
388 * each client to waitboost once in a busy period.
391 if (INTEL_GEN(rq->i915) >= 6)
392 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
397 timeout = i915_wait_request(rq, flags, timeout);
400 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
401 i915_gem_request_retire_upto(rq);
403 if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
404 /* The GPU is now idle and this client has stalled.
405 * Since no other client has submitted a request in the
406 * meantime, assume that this client is the only one
407 * supplying work to the GPU but is unable to keep that
408 * work supplied because it is waiting. Since the GPU is
409 * then never kept fully busy, RPS autoclocking will
410 * keep the clocks relatively low, causing further delays.
411 * Compensate by giving the synchronous client credit for
412 * a waitboost next time.
414 spin_lock(&rq->i915->rps.client_lock);
415 list_del_init(&rps->link);
416 spin_unlock(&rq->i915->rps.client_lock);
423 i915_gem_object_wait_reservation(struct reservation_object *resv,
426 struct intel_rps_client *rps)
428 struct dma_fence *excl;
430 if (flags & I915_WAIT_ALL) {
431 struct dma_fence **shared;
432 unsigned int count, i;
435 ret = reservation_object_get_fences_rcu(resv,
436 &excl, &count, &shared);
440 for (i = 0; i < count; i++) {
441 timeout = i915_gem_object_wait_fence(shared[i],
447 dma_fence_put(shared[i]);
450 for (; i < count; i++)
451 dma_fence_put(shared[i]);
454 excl = reservation_object_get_excl_rcu(resv);
457 if (excl && timeout > 0)
458 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
465 static void __fence_set_priority(struct dma_fence *fence, int prio)
467 struct drm_i915_gem_request *rq;
468 struct intel_engine_cs *engine;
470 if (!dma_fence_is_i915(fence))
473 rq = to_request(fence);
475 if (!engine->schedule)
478 engine->schedule(rq, prio);
481 static void fence_set_priority(struct dma_fence *fence, int prio)
483 /* Recurse once into a fence-array */
484 if (dma_fence_is_array(fence)) {
485 struct dma_fence_array *array = to_dma_fence_array(fence);
488 for (i = 0; i < array->num_fences; i++)
489 __fence_set_priority(array->fences[i], prio);
491 __fence_set_priority(fence, prio);
496 i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
500 struct dma_fence *excl;
502 if (flags & I915_WAIT_ALL) {
503 struct dma_fence **shared;
504 unsigned int count, i;
507 ret = reservation_object_get_fences_rcu(obj->resv,
508 &excl, &count, &shared);
512 for (i = 0; i < count; i++) {
513 fence_set_priority(shared[i], prio);
514 dma_fence_put(shared[i]);
519 excl = reservation_object_get_excl_rcu(obj->resv);
523 fence_set_priority(excl, prio);
530 * Waits for rendering to the object to be completed
531 * @obj: i915 gem object
532 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
533 * @timeout: how long to wait
534 * @rps: client (user process) to charge for any waitboosting
537 i915_gem_object_wait(struct drm_i915_gem_object *obj,
540 struct intel_rps_client *rps)
543 #if IS_ENABLED(CONFIG_LOCKDEP)
544 GEM_BUG_ON(debug_locks &&
545 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
546 !!(flags & I915_WAIT_LOCKED));
548 GEM_BUG_ON(timeout < 0);
550 timeout = i915_gem_object_wait_reservation(obj->resv,
553 return timeout < 0 ? timeout : 0;
556 static struct intel_rps_client *to_rps_client(struct drm_file *file)
558 struct drm_i915_file_private *fpriv = file->driver_priv;
564 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
569 if (align > obj->base.size)
572 if (obj->ops == &i915_gem_phys_ops)
575 if (obj->mm.madv != I915_MADV_WILLNEED)
578 if (obj->base.filp == NULL)
581 ret = i915_gem_object_unbind(obj);
585 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
589 obj->ops = &i915_gem_phys_ops;
591 return i915_gem_object_pin_pages(obj);
595 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
596 struct drm_i915_gem_pwrite *args,
597 struct drm_file *file)
599 void *vaddr = obj->phys_handle->vaddr + args->offset;
600 char __user *user_data = u64_to_user_ptr(args->data_ptr);
602 /* We manually control the domain here and pretend that it
603 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
605 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
606 if (copy_from_user(vaddr, user_data, args->size))
609 drm_clflush_virt_range(vaddr, args->size);
610 i915_gem_chipset_flush(to_i915(obj->base.dev));
612 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
616 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
618 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
621 void i915_gem_object_free(struct drm_i915_gem_object *obj)
623 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
624 kmem_cache_free(dev_priv->objects, obj);
628 i915_gem_create(struct drm_file *file,
629 struct drm_i915_private *dev_priv,
633 struct drm_i915_gem_object *obj;
637 size = roundup(size, PAGE_SIZE);
641 /* Allocate the new object */
642 obj = i915_gem_object_create(dev_priv, size);
646 ret = drm_gem_handle_create(file, &obj->base, &handle);
647 /* drop reference from allocate - handle holds it now */
648 i915_gem_object_put(obj);
657 i915_gem_dumb_create(struct drm_file *file,
658 struct drm_device *dev,
659 struct drm_mode_create_dumb *args)
661 /* have to work out size/pitch and return them */
662 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
663 args->size = args->pitch * args->height;
664 return i915_gem_create(file, to_i915(dev),
665 args->size, &args->handle);
669 * Creates a new mm object and returns a handle to it.
670 * @dev: drm device pointer
671 * @data: ioctl data blob
672 * @file: drm file pointer
675 i915_gem_create_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file)
678 struct drm_i915_private *dev_priv = to_i915(dev);
679 struct drm_i915_gem_create *args = data;
681 i915_gem_flush_free_objects(dev_priv);
683 return i915_gem_create(file, dev_priv,
684 args->size, &args->handle);
688 __copy_to_user_swizzled(char __user *cpu_vaddr,
689 const char *gpu_vaddr, int gpu_offset,
692 int ret, cpu_offset = 0;
695 int cacheline_end = ALIGN(gpu_offset + 1, 64);
696 int this_length = min(cacheline_end - gpu_offset, length);
697 int swizzled_gpu_offset = gpu_offset ^ 64;
699 ret = __copy_to_user(cpu_vaddr + cpu_offset,
700 gpu_vaddr + swizzled_gpu_offset,
705 cpu_offset += this_length;
706 gpu_offset += this_length;
707 length -= this_length;
714 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
715 const char __user *cpu_vaddr,
718 int ret, cpu_offset = 0;
721 int cacheline_end = ALIGN(gpu_offset + 1, 64);
722 int this_length = min(cacheline_end - gpu_offset, length);
723 int swizzled_gpu_offset = gpu_offset ^ 64;
725 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
726 cpu_vaddr + cpu_offset,
731 cpu_offset += this_length;
732 gpu_offset += this_length;
733 length -= this_length;
740 * Pins the specified object's pages and synchronizes the object with
741 * GPU accesses. Sets needs_clflush to non-zero if the caller should
742 * flush the object from the CPU cache.
744 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
745 unsigned int *needs_clflush)
749 lockdep_assert_held(&obj->base.dev->struct_mutex);
752 if (!i915_gem_object_has_struct_page(obj))
755 ret = i915_gem_object_wait(obj,
756 I915_WAIT_INTERRUPTIBLE |
758 MAX_SCHEDULE_TIMEOUT,
763 ret = i915_gem_object_pin_pages(obj);
767 i915_gem_object_flush_gtt_write_domain(obj);
769 /* If we're not in the cpu read domain, set ourself into the gtt
770 * read domain and manually flush cachelines (if required). This
771 * optimizes for the case when the gpu will dirty the data
772 * anyway again before the next pread happens.
774 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
775 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
778 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
779 ret = i915_gem_object_set_to_cpu_domain(obj, false);
786 /* return with the pages pinned */
790 i915_gem_object_unpin_pages(obj);
794 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
795 unsigned int *needs_clflush)
799 lockdep_assert_held(&obj->base.dev->struct_mutex);
802 if (!i915_gem_object_has_struct_page(obj))
805 ret = i915_gem_object_wait(obj,
806 I915_WAIT_INTERRUPTIBLE |
809 MAX_SCHEDULE_TIMEOUT,
814 ret = i915_gem_object_pin_pages(obj);
818 i915_gem_object_flush_gtt_write_domain(obj);
820 /* If we're not in the cpu write domain, set ourself into the
821 * gtt write domain and manually flush cachelines (as required).
822 * This optimizes for the case when the gpu will use the data
823 * right away and we therefore have to clflush anyway.
825 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
826 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
828 /* Same trick applies to invalidate partially written cachelines read
831 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
832 *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
835 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
836 ret = i915_gem_object_set_to_cpu_domain(obj, true);
843 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
844 obj->cache_dirty = true;
846 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
847 obj->mm.dirty = true;
848 /* return with the pages pinned */
852 i915_gem_object_unpin_pages(obj);
857 shmem_clflush_swizzled_range(char *addr, unsigned long length,
860 if (unlikely(swizzled)) {
861 unsigned long start = (unsigned long) addr;
862 unsigned long end = (unsigned long) addr + length;
864 /* For swizzling simply ensure that we always flush both
865 * channels. Lame, but simple and it works. Swizzled
866 * pwrite/pread is far from a hotpath - current userspace
867 * doesn't use it at all. */
868 start = round_down(start, 128);
869 end = round_up(end, 128);
871 drm_clflush_virt_range((void *)start, end - start);
873 drm_clflush_virt_range(addr, length);
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pread_slow(struct page *page, int offset, int length,
882 char __user *user_data,
883 bool page_do_bit17_swizzling, bool needs_clflush)
890 shmem_clflush_swizzled_range(vaddr + offset, length,
891 page_do_bit17_swizzling);
893 if (page_do_bit17_swizzling)
894 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
896 ret = __copy_to_user(user_data, vaddr + offset, length);
899 return ret ? - EFAULT : 0;
903 shmem_pread(struct page *page, int offset, int length, char __user *user_data,
904 bool page_do_bit17_swizzling, bool needs_clflush)
909 if (!page_do_bit17_swizzling) {
910 char *vaddr = kmap_atomic(page);
913 drm_clflush_virt_range(vaddr + offset, length);
914 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
915 kunmap_atomic(vaddr);
920 return shmem_pread_slow(page, offset, length, user_data,
921 page_do_bit17_swizzling, needs_clflush);
925 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
926 struct drm_i915_gem_pread *args)
928 char __user *user_data;
930 unsigned int obj_do_bit17_swizzling;
931 unsigned int needs_clflush;
932 unsigned int idx, offset;
935 obj_do_bit17_swizzling = 0;
936 if (i915_gem_object_needs_bit17_swizzle(obj))
937 obj_do_bit17_swizzling = BIT(17);
939 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
943 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
944 mutex_unlock(&obj->base.dev->struct_mutex);
949 user_data = u64_to_user_ptr(args->data_ptr);
950 offset = offset_in_page(args->offset);
951 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
952 struct page *page = i915_gem_object_get_page(obj, idx);
956 if (offset + length > PAGE_SIZE)
957 length = PAGE_SIZE - offset;
959 ret = shmem_pread(page, offset, length, user_data,
960 page_to_phys(page) & obj_do_bit17_swizzling,
970 i915_gem_obj_finish_shmem_access(obj);
975 gtt_user_read(struct io_mapping *mapping,
976 loff_t base, int offset,
977 char __user *user_data, int length)
980 unsigned long unwritten;
982 /* We can use the cpu mem copy function because this is X86. */
983 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
984 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
985 io_mapping_unmap_atomic(vaddr);
987 vaddr = (void __force *)
988 io_mapping_map_wc(mapping, base, PAGE_SIZE);
989 unwritten = copy_to_user(user_data, vaddr + offset, length);
990 io_mapping_unmap(vaddr);
996 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
997 const struct drm_i915_gem_pread *args)
999 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1000 struct i915_ggtt *ggtt = &i915->ggtt;
1001 struct drm_mm_node node;
1002 struct i915_vma *vma;
1003 void __user *user_data;
1007 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1011 intel_runtime_pm_get(i915);
1012 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1013 PIN_MAPPABLE | PIN_NONBLOCK);
1015 node.start = i915_ggtt_offset(vma);
1016 node.allocated = false;
1017 ret = i915_vma_put_fence(vma);
1019 i915_vma_unpin(vma);
1024 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1027 GEM_BUG_ON(!node.allocated);
1030 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1034 mutex_unlock(&i915->drm.struct_mutex);
1036 user_data = u64_to_user_ptr(args->data_ptr);
1037 remain = args->size;
1038 offset = args->offset;
1040 while (remain > 0) {
1041 /* Operation in this page
1043 * page_base = page offset within aperture
1044 * page_offset = offset within page
1045 * page_length = bytes to copy for this page
1047 u32 page_base = node.start;
1048 unsigned page_offset = offset_in_page(offset);
1049 unsigned page_length = PAGE_SIZE - page_offset;
1050 page_length = remain < page_length ? remain : page_length;
1051 if (node.allocated) {
1053 ggtt->base.insert_page(&ggtt->base,
1054 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1055 node.start, I915_CACHE_NONE, 0);
1058 page_base += offset & PAGE_MASK;
1061 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1062 user_data, page_length)) {
1067 remain -= page_length;
1068 user_data += page_length;
1069 offset += page_length;
1072 mutex_lock(&i915->drm.struct_mutex);
1074 if (node.allocated) {
1076 ggtt->base.clear_range(&ggtt->base,
1077 node.start, node.size);
1078 remove_mappable_node(&node);
1080 i915_vma_unpin(vma);
1083 intel_runtime_pm_put(i915);
1084 mutex_unlock(&i915->drm.struct_mutex);
1090 * Reads data from the object referenced by handle.
1091 * @dev: drm device pointer
1092 * @data: ioctl data blob
1093 * @file: drm file pointer
1095 * On error, the contents of *data are undefined.
1098 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1099 struct drm_file *file)
1101 struct drm_i915_gem_pread *args = data;
1102 struct drm_i915_gem_object *obj;
1105 if (args->size == 0)
1108 if (!access_ok(VERIFY_WRITE,
1109 u64_to_user_ptr(args->data_ptr),
1113 obj = i915_gem_object_lookup(file, args->handle);
1117 /* Bounds check source. */
1118 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1123 trace_i915_gem_object_pread(obj, args->offset, args->size);
1125 ret = i915_gem_object_wait(obj,
1126 I915_WAIT_INTERRUPTIBLE,
1127 MAX_SCHEDULE_TIMEOUT,
1128 to_rps_client(file));
1132 ret = i915_gem_object_pin_pages(obj);
1136 ret = i915_gem_shmem_pread(obj, args);
1137 if (ret == -EFAULT || ret == -ENODEV)
1138 ret = i915_gem_gtt_pread(obj, args);
1140 i915_gem_object_unpin_pages(obj);
1142 i915_gem_object_put(obj);
1146 /* This is the fast write path which cannot handle
1147 * page faults in the source data
1151 ggtt_write(struct io_mapping *mapping,
1152 loff_t base, int offset,
1153 char __user *user_data, int length)
1156 unsigned long unwritten;
1158 /* We can use the cpu mem copy function because this is X86. */
1159 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1160 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1162 io_mapping_unmap_atomic(vaddr);
1164 vaddr = (void __force *)
1165 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1166 unwritten = copy_from_user(vaddr + offset, user_data, length);
1167 io_mapping_unmap(vaddr);
1174 * This is the fast pwrite path, where we copy the data directly from the
1175 * user into the GTT, uncached.
1176 * @obj: i915 GEM object
1177 * @args: pwrite arguments structure
1180 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1181 const struct drm_i915_gem_pwrite *args)
1183 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1184 struct i915_ggtt *ggtt = &i915->ggtt;
1185 struct drm_mm_node node;
1186 struct i915_vma *vma;
1188 void __user *user_data;
1191 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1195 intel_runtime_pm_get(i915);
1196 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1197 PIN_MAPPABLE | PIN_NONBLOCK);
1199 node.start = i915_ggtt_offset(vma);
1200 node.allocated = false;
1201 ret = i915_vma_put_fence(vma);
1203 i915_vma_unpin(vma);
1208 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1211 GEM_BUG_ON(!node.allocated);
1214 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1218 mutex_unlock(&i915->drm.struct_mutex);
1220 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1222 user_data = u64_to_user_ptr(args->data_ptr);
1223 offset = args->offset;
1224 remain = args->size;
1226 /* Operation in this page
1228 * page_base = page offset within aperture
1229 * page_offset = offset within page
1230 * page_length = bytes to copy for this page
1232 u32 page_base = node.start;
1233 unsigned int page_offset = offset_in_page(offset);
1234 unsigned int page_length = PAGE_SIZE - page_offset;
1235 page_length = remain < page_length ? remain : page_length;
1236 if (node.allocated) {
1237 wmb(); /* flush the write before we modify the GGTT */
1238 ggtt->base.insert_page(&ggtt->base,
1239 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1240 node.start, I915_CACHE_NONE, 0);
1241 wmb(); /* flush modifications to the GGTT (insert_page) */
1243 page_base += offset & PAGE_MASK;
1245 /* If we get a fault while copying data, then (presumably) our
1246 * source page isn't available. Return the error and we'll
1247 * retry in the slow path.
1248 * If the object is non-shmem backed, we retry again with the
1249 * path that handles page fault.
1251 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1252 user_data, page_length)) {
1257 remain -= page_length;
1258 user_data += page_length;
1259 offset += page_length;
1261 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1263 mutex_lock(&i915->drm.struct_mutex);
1265 if (node.allocated) {
1267 ggtt->base.clear_range(&ggtt->base,
1268 node.start, node.size);
1269 remove_mappable_node(&node);
1271 i915_vma_unpin(vma);
1274 intel_runtime_pm_put(i915);
1275 mutex_unlock(&i915->drm.struct_mutex);
1280 shmem_pwrite_slow(struct page *page, int offset, int length,
1281 char __user *user_data,
1282 bool page_do_bit17_swizzling,
1283 bool needs_clflush_before,
1284 bool needs_clflush_after)
1290 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1291 shmem_clflush_swizzled_range(vaddr + offset, length,
1292 page_do_bit17_swizzling);
1293 if (page_do_bit17_swizzling)
1294 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1297 ret = __copy_from_user(vaddr + offset, user_data, length);
1298 if (needs_clflush_after)
1299 shmem_clflush_swizzled_range(vaddr + offset, length,
1300 page_do_bit17_swizzling);
1303 return ret ? -EFAULT : 0;
1306 /* Per-page copy function for the shmem pwrite fastpath.
1307 * Flushes invalid cachelines before writing to the target if
1308 * needs_clflush_before is set and flushes out any written cachelines after
1309 * writing if needs_clflush is set.
1312 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1313 bool page_do_bit17_swizzling,
1314 bool needs_clflush_before,
1315 bool needs_clflush_after)
1320 if (!page_do_bit17_swizzling) {
1321 char *vaddr = kmap_atomic(page);
1323 if (needs_clflush_before)
1324 drm_clflush_virt_range(vaddr + offset, len);
1325 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1326 if (needs_clflush_after)
1327 drm_clflush_virt_range(vaddr + offset, len);
1329 kunmap_atomic(vaddr);
1334 return shmem_pwrite_slow(page, offset, len, user_data,
1335 page_do_bit17_swizzling,
1336 needs_clflush_before,
1337 needs_clflush_after);
1341 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1342 const struct drm_i915_gem_pwrite *args)
1344 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1345 void __user *user_data;
1347 unsigned int obj_do_bit17_swizzling;
1348 unsigned int partial_cacheline_write;
1349 unsigned int needs_clflush;
1350 unsigned int offset, idx;
1353 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1357 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1358 mutex_unlock(&i915->drm.struct_mutex);
1362 obj_do_bit17_swizzling = 0;
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 obj_do_bit17_swizzling = BIT(17);
1366 /* If we don't overwrite a cacheline completely we need to be
1367 * careful to have up-to-date data by first clflushing. Don't
1368 * overcomplicate things and flush the entire patch.
1370 partial_cacheline_write = 0;
1371 if (needs_clflush & CLFLUSH_BEFORE)
1372 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1374 user_data = u64_to_user_ptr(args->data_ptr);
1375 remain = args->size;
1376 offset = offset_in_page(args->offset);
1377 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1378 struct page *page = i915_gem_object_get_page(obj, idx);
1382 if (offset + length > PAGE_SIZE)
1383 length = PAGE_SIZE - offset;
1385 ret = shmem_pwrite(page, offset, length, user_data,
1386 page_to_phys(page) & obj_do_bit17_swizzling,
1387 (offset | length) & partial_cacheline_write,
1388 needs_clflush & CLFLUSH_AFTER);
1393 user_data += length;
1397 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1398 i915_gem_obj_finish_shmem_access(obj);
1403 * Writes data to the object referenced by handle.
1405 * @data: ioctl data blob
1408 * On error, the contents of the buffer that were to be modified are undefined.
1411 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *file)
1414 struct drm_i915_gem_pwrite *args = data;
1415 struct drm_i915_gem_object *obj;
1418 if (args->size == 0)
1421 if (!access_ok(VERIFY_READ,
1422 u64_to_user_ptr(args->data_ptr),
1426 obj = i915_gem_object_lookup(file, args->handle);
1430 /* Bounds check destination. */
1431 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
1436 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1438 ret = i915_gem_object_wait(obj,
1439 I915_WAIT_INTERRUPTIBLE |
1441 MAX_SCHEDULE_TIMEOUT,
1442 to_rps_client(file));
1446 ret = i915_gem_object_pin_pages(obj);
1451 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1452 * it would end up going through the fenced access, and we'll get
1453 * different detiling behavior between reading and writing.
1454 * pread/pwrite currently are reading and writing from the CPU
1455 * perspective, requiring manual detiling by the client.
1457 if (!i915_gem_object_has_struct_page(obj) ||
1458 cpu_write_needs_clflush(obj))
1459 /* Note that the gtt paths might fail with non-page-backed user
1460 * pointers (e.g. gtt mappings when moving data between
1461 * textures). Fallback to the shmem path in that case.
1463 ret = i915_gem_gtt_pwrite_fast(obj, args);
1465 if (ret == -EFAULT || ret == -ENOSPC) {
1466 if (obj->phys_handle)
1467 ret = i915_gem_phys_pwrite(obj, args, file);
1469 ret = i915_gem_shmem_pwrite(obj, args);
1472 i915_gem_object_unpin_pages(obj);
1474 i915_gem_object_put(obj);
1478 static inline enum fb_op_origin
1479 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1481 return (domain == I915_GEM_DOMAIN_GTT ?
1482 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1485 static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1487 struct drm_i915_private *i915;
1488 struct list_head *list;
1489 struct i915_vma *vma;
1491 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1492 if (!i915_vma_is_ggtt(vma))
1495 if (i915_vma_is_active(vma))
1498 if (!drm_mm_node_allocated(&vma->node))
1501 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1504 i915 = to_i915(obj->base.dev);
1505 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1506 list_move_tail(&obj->global_link, list);
1510 * Called when user space prepares to use an object with the CPU, either
1511 * through the mmap ioctl's mapping or a GTT mapping.
1513 * @data: ioctl data blob
1517 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1518 struct drm_file *file)
1520 struct drm_i915_gem_set_domain *args = data;
1521 struct drm_i915_gem_object *obj;
1522 uint32_t read_domains = args->read_domains;
1523 uint32_t write_domain = args->write_domain;
1526 /* Only handle setting domains to types used by the CPU. */
1527 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1530 /* Having something in the write domain implies it's in the read
1531 * domain, and only that read domain. Enforce that in the request.
1533 if (write_domain != 0 && read_domains != write_domain)
1536 obj = i915_gem_object_lookup(file, args->handle);
1540 /* Try to flush the object off the GPU without holding the lock.
1541 * We will repeat the flush holding the lock in the normal manner
1542 * to catch cases where we are gazumped.
1544 err = i915_gem_object_wait(obj,
1545 I915_WAIT_INTERRUPTIBLE |
1546 (write_domain ? I915_WAIT_ALL : 0),
1547 MAX_SCHEDULE_TIMEOUT,
1548 to_rps_client(file));
1552 /* Flush and acquire obj->pages so that we are coherent through
1553 * direct access in memory with previous cached writes through
1554 * shmemfs and that our cache domain tracking remains valid.
1555 * For example, if the obj->filp was moved to swap without us
1556 * being notified and releasing the pages, we would mistakenly
1557 * continue to assume that the obj remained out of the CPU cached
1560 err = i915_gem_object_pin_pages(obj);
1564 err = i915_mutex_lock_interruptible(dev);
1568 if (read_domains & I915_GEM_DOMAIN_GTT)
1569 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1571 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1573 /* And bump the LRU for this access */
1574 i915_gem_object_bump_inactive_ggtt(obj);
1576 mutex_unlock(&dev->struct_mutex);
1578 if (write_domain != 0)
1579 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1582 i915_gem_object_unpin_pages(obj);
1584 i915_gem_object_put(obj);
1589 * Called when user space has done writes to this buffer
1591 * @data: ioctl data blob
1595 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1596 struct drm_file *file)
1598 struct drm_i915_gem_sw_finish *args = data;
1599 struct drm_i915_gem_object *obj;
1602 obj = i915_gem_object_lookup(file, args->handle);
1606 /* Pinned buffers may be scanout, so flush the cache */
1607 if (READ_ONCE(obj->pin_display)) {
1608 err = i915_mutex_lock_interruptible(dev);
1610 i915_gem_object_flush_cpu_write_domain(obj);
1611 mutex_unlock(&dev->struct_mutex);
1615 i915_gem_object_put(obj);
1620 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1623 * @data: ioctl data blob
1626 * While the mapping holds a reference on the contents of the object, it doesn't
1627 * imply a ref on the object itself.
1631 * DRM driver writers who look a this function as an example for how to do GEM
1632 * mmap support, please don't implement mmap support like here. The modern way
1633 * to implement DRM mmap support is with an mmap offset ioctl (like
1634 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1635 * That way debug tooling like valgrind will understand what's going on, hiding
1636 * the mmap call in a driver private ioctl will break that. The i915 driver only
1637 * does cpu mmaps this way because we didn't know better.
1640 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1641 struct drm_file *file)
1643 struct drm_i915_gem_mmap *args = data;
1644 struct drm_i915_gem_object *obj;
1647 if (args->flags & ~(I915_MMAP_WC))
1650 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1653 obj = i915_gem_object_lookup(file, args->handle);
1657 /* prime objects have no backing filp to GEM mmap
1660 if (!obj->base.filp) {
1661 i915_gem_object_put(obj);
1665 addr = vm_mmap(obj->base.filp, 0, args->size,
1666 PROT_READ | PROT_WRITE, MAP_SHARED,
1668 if (args->flags & I915_MMAP_WC) {
1669 struct mm_struct *mm = current->mm;
1670 struct vm_area_struct *vma;
1672 if (down_write_killable(&mm->mmap_sem)) {
1673 i915_gem_object_put(obj);
1676 vma = find_vma(mm, addr);
1679 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1682 up_write(&mm->mmap_sem);
1684 /* This may race, but that's ok, it only gets set */
1685 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1687 i915_gem_object_put(obj);
1688 if (IS_ERR((void *)addr))
1691 args->addr_ptr = (uint64_t) addr;
1696 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1698 return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
1702 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1704 * A history of the GTT mmap interface:
1706 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1707 * aligned and suitable for fencing, and still fit into the available
1708 * mappable space left by the pinned display objects. A classic problem
1709 * we called the page-fault-of-doom where we would ping-pong between
1710 * two objects that could not fit inside the GTT and so the memcpy
1711 * would page one object in at the expense of the other between every
1714 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1715 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1716 * object is too large for the available space (or simply too large
1717 * for the mappable aperture!), a view is created instead and faulted
1718 * into userspace. (This view is aligned and sized appropriately for
1723 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1724 * hangs on some architectures, corruption on others. An attempt to service
1725 * a GTT page fault from a snoopable object will generate a SIGBUS.
1727 * * the object must be able to fit into RAM (physical memory, though no
1728 * limited to the mappable aperture).
1733 * * a new GTT page fault will synchronize rendering from the GPU and flush
1734 * all data to system memory. Subsequent access will not be synchronized.
1736 * * all mappings are revoked on runtime device suspend.
1738 * * there are only 8, 16 or 32 fence registers to share between all users
1739 * (older machines require fence register for display and blitter access
1740 * as well). Contention of the fence registers will cause the previous users
1741 * to be unmapped and any new access will generate new page faults.
1743 * * running out of memory while servicing a fault may generate a SIGBUS,
1744 * rather than the expected SIGSEGV.
1746 int i915_gem_mmap_gtt_version(void)
1751 static inline struct i915_ggtt_view
1752 compute_partial_view(struct drm_i915_gem_object *obj,
1753 pgoff_t page_offset,
1756 struct i915_ggtt_view view;
1758 if (i915_gem_object_is_tiled(obj))
1759 chunk = roundup(chunk, tile_row_pages(obj));
1761 view.type = I915_GGTT_VIEW_PARTIAL;
1762 view.partial.offset = rounddown(page_offset, chunk);
1764 min_t(unsigned int, chunk,
1765 (obj->base.size >> PAGE_SHIFT) - view.partial.offset);
1767 /* If the partial covers the entire object, just create a normal VMA. */
1768 if (chunk >= obj->base.size >> PAGE_SHIFT)
1769 view.type = I915_GGTT_VIEW_NORMAL;
1775 * i915_gem_fault - fault a page into the GTT
1776 * @area: CPU VMA in question
1779 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1780 * from userspace. The fault handler takes care of binding the object to
1781 * the GTT (if needed), allocating and programming a fence register (again,
1782 * only if needed based on whether the old reg is still valid or the object
1783 * is tiled) and inserting a new PTE into the faulting process.
1785 * Note that the faulting process may involve evicting existing objects
1786 * from the GTT and/or fence registers to make room. So performance may
1787 * suffer if the GTT working set is large or there are few fence registers
1790 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1791 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1793 int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
1795 #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1796 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1797 struct drm_device *dev = obj->base.dev;
1798 struct drm_i915_private *dev_priv = to_i915(dev);
1799 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1800 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1801 struct i915_vma *vma;
1802 pgoff_t page_offset;
1806 /* We don't use vmf->pgoff since that has the fake offset */
1807 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1809 trace_i915_gem_object_fault(obj, page_offset, true, write);
1811 /* Try to flush the object off the GPU first without holding the lock.
1812 * Upon acquiring the lock, we will perform our sanity checks and then
1813 * repeat the flush holding the lock in the normal manner to catch cases
1814 * where we are gazumped.
1816 ret = i915_gem_object_wait(obj,
1817 I915_WAIT_INTERRUPTIBLE,
1818 MAX_SCHEDULE_TIMEOUT,
1823 ret = i915_gem_object_pin_pages(obj);
1827 intel_runtime_pm_get(dev_priv);
1829 ret = i915_mutex_lock_interruptible(dev);
1833 /* Access to snoopable pages through the GTT is incoherent. */
1834 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1839 /* If the object is smaller than a couple of partial vma, it is
1840 * not worth only creating a single partial vma - we may as well
1841 * clear enough space for the full object.
1843 flags = PIN_MAPPABLE;
1844 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1845 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1847 /* Now pin it into the GTT as needed */
1848 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1850 /* Use a partial view if it is bigger than available space */
1851 struct i915_ggtt_view view =
1852 compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
1854 /* Userspace is now writing through an untracked VMA, abandon
1855 * all hope that the hardware is able to track future writes.
1857 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1859 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1866 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1870 ret = i915_vma_get_fence(vma);
1874 /* Mark as being mmapped into userspace for later revocation */
1875 assert_rpm_wakelock_held(dev_priv);
1876 if (list_empty(&obj->userfault_link))
1877 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1879 /* Finally, remap it using the new GTT offset */
1880 ret = remap_io_mapping(area,
1881 area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT),
1882 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1883 min_t(u64, vma->size, area->vm_end - area->vm_start),
1887 __i915_vma_unpin(vma);
1889 mutex_unlock(&dev->struct_mutex);
1891 intel_runtime_pm_put(dev_priv);
1892 i915_gem_object_unpin_pages(obj);
1897 * We eat errors when the gpu is terminally wedged to avoid
1898 * userspace unduly crashing (gl has no provisions for mmaps to
1899 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1900 * and so needs to be reported.
1902 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1903 ret = VM_FAULT_SIGBUS;
1908 * EAGAIN means the gpu is hung and we'll wait for the error
1909 * handler to reset everything when re-faulting in
1910 * i915_mutex_lock_interruptible.
1917 * EBUSY is ok: this just means that another thread
1918 * already did the job.
1920 ret = VM_FAULT_NOPAGE;
1927 ret = VM_FAULT_SIGBUS;
1930 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1931 ret = VM_FAULT_SIGBUS;
1938 * i915_gem_release_mmap - remove physical page mappings
1939 * @obj: obj in question
1941 * Preserve the reservation of the mmapping with the DRM core code, but
1942 * relinquish ownership of the pages back to the system.
1944 * It is vital that we remove the page mapping if we have mapped a tiled
1945 * object through the GTT and then lose the fence register due to
1946 * resource pressure. Similarly if the object has been moved out of the
1947 * aperture, than pages mapped into userspace must be revoked. Removing the
1948 * mapping will then trigger a page fault on the next user access, allowing
1949 * fixup by i915_gem_fault().
1952 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1954 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1956 /* Serialisation between user GTT access and our code depends upon
1957 * revoking the CPU's PTE whilst the mutex is held. The next user
1958 * pagefault then has to wait until we release the mutex.
1960 * Note that RPM complicates somewhat by adding an additional
1961 * requirement that operations to the GGTT be made holding the RPM
1964 lockdep_assert_held(&i915->drm.struct_mutex);
1965 intel_runtime_pm_get(i915);
1967 if (list_empty(&obj->userfault_link))
1970 list_del_init(&obj->userfault_link);
1971 drm_vma_node_unmap(&obj->base.vma_node,
1972 obj->base.dev->anon_inode->i_mapping);
1974 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1975 * memory transactions from userspace before we return. The TLB
1976 * flushing implied above by changing the PTE above *should* be
1977 * sufficient, an extra barrier here just provides us with a bit
1978 * of paranoid documentation about our requirement to serialise
1979 * memory writes before touching registers / GSM.
1984 intel_runtime_pm_put(i915);
1987 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
1989 struct drm_i915_gem_object *obj, *on;
1993 * Only called during RPM suspend. All users of the userfault_list
1994 * must be holding an RPM wakeref to ensure that this can not
1995 * run concurrently with themselves (and use the struct_mutex for
1996 * protection between themselves).
1999 list_for_each_entry_safe(obj, on,
2000 &dev_priv->mm.userfault_list, userfault_link) {
2001 list_del_init(&obj->userfault_link);
2002 drm_vma_node_unmap(&obj->base.vma_node,
2003 obj->base.dev->anon_inode->i_mapping);
2006 /* The fence will be lost when the device powers down. If any were
2007 * in use by hardware (i.e. they are pinned), we should not be powering
2008 * down! All other fences will be reacquired by the user upon waking.
2010 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2011 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2013 /* Ideally we want to assert that the fence register is not
2014 * live at this point (i.e. that no piece of code will be
2015 * trying to write through fence + GTT, as that both violates
2016 * our tracking of activity and associated locking/barriers,
2017 * but also is illegal given that the hw is powered down).
2019 * Previously we used reg->pin_count as a "liveness" indicator.
2020 * That is not sufficient, and we need a more fine-grained
2021 * tool if we want to have a sanity check here.
2027 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2032 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2034 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2037 err = drm_gem_create_mmap_offset(&obj->base);
2041 /* Attempt to reap some mmap space from dead objects */
2043 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2047 i915_gem_drain_freed_objects(dev_priv);
2048 err = drm_gem_create_mmap_offset(&obj->base);
2052 } while (flush_delayed_work(&dev_priv->gt.retire_work));
2057 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2059 drm_gem_free_mmap_offset(&obj->base);
2063 i915_gem_mmap_gtt(struct drm_file *file,
2064 struct drm_device *dev,
2068 struct drm_i915_gem_object *obj;
2071 obj = i915_gem_object_lookup(file, handle);
2075 ret = i915_gem_object_create_mmap_offset(obj);
2077 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2079 i915_gem_object_put(obj);
2084 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2086 * @data: GTT mapping ioctl data
2087 * @file: GEM object info
2089 * Simply returns the fake offset to userspace so it can mmap it.
2090 * The mmap call will end up in drm_gem_mmap(), which will set things
2091 * up so we can get faults in the handler above.
2093 * The fault handler will take care of binding the object into the GTT
2094 * (since it may have been evicted to make room for something), allocating
2095 * a fence register, and mapping the appropriate aperture address into
2099 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2100 struct drm_file *file)
2102 struct drm_i915_gem_mmap_gtt *args = data;
2104 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2107 /* Immediately discard the backing storage */
2109 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2111 i915_gem_object_free_mmap_offset(obj);
2113 if (obj->base.filp == NULL)
2116 /* Our goal here is to return as much of the memory as
2117 * is possible back to the system as we are called from OOM.
2118 * To do this we must instruct the shmfs to drop all of its
2119 * backing pages, *now*.
2121 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2122 obj->mm.madv = __I915_MADV_PURGED;
2125 /* Try to discard unwanted pages */
2126 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2128 struct address_space *mapping;
2130 lockdep_assert_held(&obj->mm.lock);
2131 GEM_BUG_ON(obj->mm.pages);
2133 switch (obj->mm.madv) {
2134 case I915_MADV_DONTNEED:
2135 i915_gem_object_truncate(obj);
2136 case __I915_MADV_PURGED:
2140 if (obj->base.filp == NULL)
2143 mapping = obj->base.filp->f_mapping,
2144 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2148 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2149 struct sg_table *pages)
2151 struct sgt_iter sgt_iter;
2154 __i915_gem_object_release_shmem(obj, pages, true);
2156 i915_gem_gtt_finish_pages(obj, pages);
2158 if (i915_gem_object_needs_bit17_swizzle(obj))
2159 i915_gem_object_save_bit_17_swizzle(obj, pages);
2161 for_each_sgt_page(page, sgt_iter, pages) {
2163 set_page_dirty(page);
2165 if (obj->mm.madv == I915_MADV_WILLNEED)
2166 mark_page_accessed(page);
2170 obj->mm.dirty = false;
2172 sg_free_table(pages);
2176 static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2178 struct radix_tree_iter iter;
2181 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2182 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2185 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2186 enum i915_mm_subclass subclass)
2188 struct sg_table *pages;
2190 if (i915_gem_object_has_pinned_pages(obj))
2193 GEM_BUG_ON(obj->bind_count);
2194 if (!READ_ONCE(obj->mm.pages))
2197 /* May be called by shrinker from within get_pages() (on another bo) */
2198 mutex_lock_nested(&obj->mm.lock, subclass);
2199 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2202 /* ->put_pages might need to allocate memory for the bit17 swizzle
2203 * array, hence protect them from being reaped by removing them from gtt
2205 pages = fetch_and_zero(&obj->mm.pages);
2208 if (obj->mm.mapping) {
2211 ptr = ptr_mask_bits(obj->mm.mapping);
2212 if (is_vmalloc_addr(ptr))
2215 kunmap(kmap_to_page(ptr));
2217 obj->mm.mapping = NULL;
2220 __i915_gem_object_reset_page_iter(obj);
2222 obj->ops->put_pages(obj, pages);
2224 mutex_unlock(&obj->mm.lock);
2227 static bool i915_sg_trim(struct sg_table *orig_st)
2229 struct sg_table new_st;
2230 struct scatterlist *sg, *new_sg;
2233 if (orig_st->nents == orig_st->orig_nents)
2236 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2239 new_sg = new_st.sgl;
2240 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2241 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2242 /* called before being DMA mapped, no need to copy sg->dma_* */
2243 new_sg = sg_next(new_sg);
2245 GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */
2247 sg_free_table(orig_st);
2253 static struct sg_table *
2254 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2256 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2257 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2259 struct address_space *mapping;
2260 struct sg_table *st;
2261 struct scatterlist *sg;
2262 struct sgt_iter sgt_iter;
2264 unsigned long last_pfn = 0; /* suppress gcc warning */
2265 unsigned int max_segment;
2269 /* Assert that the object is not currently in any GPU domain. As it
2270 * wasn't in the GTT, there shouldn't be any way it could have been in
2273 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2274 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2276 max_segment = swiotlb_max_segment();
2278 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2280 st = kmalloc(sizeof(*st), GFP_KERNEL);
2282 return ERR_PTR(-ENOMEM);
2285 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2287 return ERR_PTR(-ENOMEM);
2290 /* Get the list of pages out of our struct file. They'll be pinned
2291 * at this point until we release them.
2293 * Fail silently without starting the shrinker
2295 mapping = obj->base.filp->f_mapping;
2296 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2297 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2300 for (i = 0; i < page_count; i++) {
2301 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2303 i915_gem_shrink(dev_priv,
2306 I915_SHRINK_UNBOUND |
2307 I915_SHRINK_PURGEABLE);
2308 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2311 /* We've tried hard to allocate the memory by reaping
2312 * our own buffer, now let the real VM do its job and
2313 * go down in flames if truly OOM.
2315 page = shmem_read_mapping_page(mapping, i);
2317 ret = PTR_ERR(page);
2322 sg->length >= max_segment ||
2323 page_to_pfn(page) != last_pfn + 1) {
2327 sg_set_page(sg, page, PAGE_SIZE, 0);
2329 sg->length += PAGE_SIZE;
2331 last_pfn = page_to_pfn(page);
2333 /* Check that the i965g/gm workaround works. */
2334 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2336 if (sg) /* loop terminated early; short sg table */
2339 /* Trim unused sg entries to avoid wasting memory. */
2342 ret = i915_gem_gtt_prepare_pages(obj, st);
2344 /* DMA remapping failed? One possible cause is that
2345 * it could not reserve enough large entries, asking
2346 * for PAGE_SIZE chunks instead may be helpful.
2348 if (max_segment > PAGE_SIZE) {
2349 for_each_sgt_page(page, sgt_iter, st)
2353 max_segment = PAGE_SIZE;
2356 dev_warn(&dev_priv->drm.pdev->dev,
2357 "Failed to DMA remap %lu pages\n",
2363 if (i915_gem_object_needs_bit17_swizzle(obj))
2364 i915_gem_object_do_bit_17_swizzle(obj, st);
2371 for_each_sgt_page(page, sgt_iter, st)
2376 /* shmemfs first checks if there is enough memory to allocate the page
2377 * and reports ENOSPC should there be insufficient, along with the usual
2378 * ENOMEM for a genuine allocation failure.
2380 * We use ENOSPC in our driver to mean that we have run out of aperture
2381 * space and so want to translate the error from shmemfs back to our
2382 * usual understanding of ENOMEM.
2387 return ERR_PTR(ret);
2390 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2391 struct sg_table *pages)
2393 lockdep_assert_held(&obj->mm.lock);
2395 obj->mm.get_page.sg_pos = pages->sgl;
2396 obj->mm.get_page.sg_idx = 0;
2398 obj->mm.pages = pages;
2400 if (i915_gem_object_is_tiled(obj) &&
2401 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2402 GEM_BUG_ON(obj->mm.quirked);
2403 __i915_gem_object_pin_pages(obj);
2404 obj->mm.quirked = true;
2408 static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2410 struct sg_table *pages;
2412 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2414 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2415 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2419 pages = obj->ops->get_pages(obj);
2420 if (unlikely(IS_ERR(pages)))
2421 return PTR_ERR(pages);
2423 __i915_gem_object_set_pages(obj, pages);
2427 /* Ensure that the associated pages are gathered from the backing storage
2428 * and pinned into our object. i915_gem_object_pin_pages() may be called
2429 * multiple times before they are released by a single call to
2430 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2431 * either as a result of memory pressure (reaping pages under the shrinker)
2432 * or as the object is itself released.
2434 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2438 err = mutex_lock_interruptible(&obj->mm.lock);
2442 if (unlikely(!obj->mm.pages)) {
2443 err = ____i915_gem_object_get_pages(obj);
2447 smp_mb__before_atomic();
2449 atomic_inc(&obj->mm.pages_pin_count);
2452 mutex_unlock(&obj->mm.lock);
2456 /* The 'mapping' part of i915_gem_object_pin_map() below */
2457 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2458 enum i915_map_type type)
2460 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2461 struct sg_table *sgt = obj->mm.pages;
2462 struct sgt_iter sgt_iter;
2464 struct page *stack_pages[32];
2465 struct page **pages = stack_pages;
2466 unsigned long i = 0;
2470 /* A single page can always be kmapped */
2471 if (n_pages == 1 && type == I915_MAP_WB)
2472 return kmap(sg_page(sgt->sgl));
2474 if (n_pages > ARRAY_SIZE(stack_pages)) {
2475 /* Too big for stack -- allocate temporary array instead */
2476 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2481 for_each_sgt_page(page, sgt_iter, sgt)
2484 /* Check that we have the expected number of pages */
2485 GEM_BUG_ON(i != n_pages);
2489 pgprot = PAGE_KERNEL;
2492 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2495 addr = vmap(pages, n_pages, 0, pgprot);
2497 if (pages != stack_pages)
2498 drm_free_large(pages);
2503 /* get, pin, and map the pages of the object into kernel space */
2504 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2505 enum i915_map_type type)
2507 enum i915_map_type has_type;
2512 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2514 ret = mutex_lock_interruptible(&obj->mm.lock);
2516 return ERR_PTR(ret);
2519 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2520 if (unlikely(!obj->mm.pages)) {
2521 ret = ____i915_gem_object_get_pages(obj);
2525 smp_mb__before_atomic();
2527 atomic_inc(&obj->mm.pages_pin_count);
2530 GEM_BUG_ON(!obj->mm.pages);
2532 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2533 if (ptr && has_type != type) {
2539 if (is_vmalloc_addr(ptr))
2542 kunmap(kmap_to_page(ptr));
2544 ptr = obj->mm.mapping = NULL;
2548 ptr = i915_gem_object_map(obj, type);
2554 obj->mm.mapping = ptr_pack_bits(ptr, type);
2558 mutex_unlock(&obj->mm.lock);
2562 atomic_dec(&obj->mm.pages_pin_count);
2568 static bool ban_context(const struct i915_gem_context *ctx)
2570 return (i915_gem_context_is_bannable(ctx) &&
2571 ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD);
2574 static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
2576 ctx->guilty_count++;
2577 ctx->ban_score += CONTEXT_SCORE_GUILTY;
2578 if (ban_context(ctx))
2579 i915_gem_context_set_banned(ctx);
2581 DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n",
2582 ctx->name, ctx->ban_score,
2583 yesno(i915_gem_context_is_banned(ctx)));
2585 if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv))
2588 ctx->file_priv->context_bans++;
2589 DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
2590 ctx->name, ctx->file_priv->context_bans);
2593 static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx)
2595 ctx->active_count++;
2598 struct drm_i915_gem_request *
2599 i915_gem_find_active_request(struct intel_engine_cs *engine)
2601 struct drm_i915_gem_request *request;
2603 /* We are called by the error capture and reset at a random
2604 * point in time. In particular, note that neither is crucially
2605 * ordered with an interrupt. After a hang, the GPU is dead and we
2606 * assume that no more writes can happen (we waited long enough for
2607 * all writes that were in transaction to be flushed) - adding an
2608 * extra delay for a recent interrupt is pointless. Hence, we do
2609 * not need an engine->irq_seqno_barrier() before the seqno reads.
2611 list_for_each_entry(request, &engine->timeline->requests, link) {
2612 if (__i915_gem_request_completed(request))
2615 GEM_BUG_ON(request->engine != engine);
2616 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
2617 &request->fence.flags));
2624 static bool engine_stalled(struct intel_engine_cs *engine)
2626 if (!engine->hangcheck.stalled)
2629 /* Check for possible seqno movement after hang declaration */
2630 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) {
2631 DRM_DEBUG_DRIVER("%s pardoned\n", engine->name);
2638 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
2640 struct intel_engine_cs *engine;
2641 enum intel_engine_id id;
2644 /* Ensure irq handler finishes, and not run again. */
2645 for_each_engine(engine, dev_priv, id) {
2646 struct drm_i915_gem_request *request;
2648 /* Prevent the signaler thread from updating the request
2649 * state (by calling dma_fence_signal) as we are processing
2650 * the reset. The write from the GPU of the seqno is
2651 * asynchronous and the signaler thread may see a different
2652 * value to us and declare the request complete, even though
2653 * the reset routine have picked that request as the active
2654 * (incomplete) request. This conflict is not handled
2657 kthread_park(engine->breadcrumbs.signaler);
2659 /* Prevent request submission to the hardware until we have
2660 * completed the reset in i915_gem_reset_finish(). If a request
2661 * is completed by one engine, it may then queue a request
2662 * to a second via its engine->irq_tasklet *just* as we are
2663 * calling engine->init_hw() and also writing the ELSP.
2664 * Turning off the engine->irq_tasklet until the reset is over
2665 * prevents the race.
2667 tasklet_kill(&engine->irq_tasklet);
2668 tasklet_disable(&engine->irq_tasklet);
2670 if (engine->irq_seqno_barrier)
2671 engine->irq_seqno_barrier(engine);
2673 if (engine_stalled(engine)) {
2674 request = i915_gem_find_active_request(engine);
2675 if (request && request->fence.error == -EIO)
2676 err = -EIO; /* Previous reset failed! */
2680 i915_gem_revoke_fences(dev_priv);
2685 static void skip_request(struct drm_i915_gem_request *request)
2687 void *vaddr = request->ring->vaddr;
2690 /* As this request likely depends on state from the lost
2691 * context, clear out all the user operations leaving the
2692 * breadcrumb at the end (so we get the fence notifications).
2694 head = request->head;
2695 if (request->postfix < head) {
2696 memset(vaddr + head, 0, request->ring->size - head);
2699 memset(vaddr + head, 0, request->postfix - head);
2701 dma_fence_set_error(&request->fence, -EIO);
2704 static void engine_skip_context(struct drm_i915_gem_request *request)
2706 struct intel_engine_cs *engine = request->engine;
2707 struct i915_gem_context *hung_ctx = request->ctx;
2708 struct intel_timeline *timeline;
2709 unsigned long flags;
2711 timeline = i915_gem_context_lookup_timeline(hung_ctx, engine);
2713 spin_lock_irqsave(&engine->timeline->lock, flags);
2714 spin_lock(&timeline->lock);
2716 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2717 if (request->ctx == hung_ctx)
2718 skip_request(request);
2720 list_for_each_entry(request, &timeline->requests, link)
2721 skip_request(request);
2723 spin_unlock(&timeline->lock);
2724 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2727 /* Returns true if the request was guilty of hang */
2728 static bool i915_gem_reset_request(struct drm_i915_gem_request *request)
2730 /* Read once and return the resolution */
2731 const bool guilty = engine_stalled(request->engine);
2733 /* The guilty request will get skipped on a hung engine.
2735 * Users of client default contexts do not rely on logical
2736 * state preserved between batches so it is safe to execute
2737 * queued requests following the hang. Non default contexts
2738 * rely on preserved state, so skipping a batch loses the
2739 * evolution of the state and it needs to be considered corrupted.
2740 * Executing more queued batches on top of corrupted state is
2741 * risky. But we take the risk by trying to advance through
2742 * the queued requests in order to make the client behaviour
2743 * more predictable around resets, by not throwing away random
2744 * amount of batches it has prepared for execution. Sophisticated
2745 * clients can use gem_reset_stats_ioctl and dma fence status
2746 * (exported via sync_file info ioctl on explicit fences) to observe
2747 * when it loses the context state and should rebuild accordingly.
2749 * The context ban, and ultimately the client ban, mechanism are safety
2750 * valves if client submission ends up resulting in nothing more than
2755 i915_gem_context_mark_guilty(request->ctx);
2756 skip_request(request);
2758 i915_gem_context_mark_innocent(request->ctx);
2759 dma_fence_set_error(&request->fence, -EAGAIN);
2765 static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2767 struct drm_i915_gem_request *request;
2769 request = i915_gem_find_active_request(engine);
2770 if (request && i915_gem_reset_request(request)) {
2771 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2772 engine->name, request->global_seqno);
2774 /* If this context is now banned, skip all pending requests. */
2775 if (i915_gem_context_is_banned(request->ctx))
2776 engine_skip_context(request);
2779 /* Setup the CS to resume from the breadcrumb of the hung request */
2780 engine->reset_hw(engine, request);
2783 void i915_gem_reset(struct drm_i915_private *dev_priv)
2785 struct intel_engine_cs *engine;
2786 enum intel_engine_id id;
2788 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2790 i915_gem_retire_requests(dev_priv);
2792 for_each_engine(engine, dev_priv, id) {
2793 struct i915_gem_context *ctx;
2795 i915_gem_reset_engine(engine);
2796 ctx = fetch_and_zero(&engine->last_retired_context);
2798 engine->context_unpin(engine, ctx);
2801 i915_gem_restore_fences(dev_priv);
2803 if (dev_priv->gt.awake) {
2804 intel_sanitize_gt_powersave(dev_priv);
2805 intel_enable_gt_powersave(dev_priv);
2806 if (INTEL_GEN(dev_priv) >= 6)
2807 gen6_rps_busy(dev_priv);
2811 void i915_gem_reset_finish(struct drm_i915_private *dev_priv)
2813 struct intel_engine_cs *engine;
2814 enum intel_engine_id id;
2816 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2818 for_each_engine(engine, dev_priv, id) {
2819 tasklet_enable(&engine->irq_tasklet);
2820 kthread_unpark(engine->breadcrumbs.signaler);
2824 static void nop_submit_request(struct drm_i915_gem_request *request)
2826 dma_fence_set_error(&request->fence, -EIO);
2827 i915_gem_request_submit(request);
2828 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2831 static void engine_set_wedged(struct intel_engine_cs *engine)
2833 struct drm_i915_gem_request *request;
2834 unsigned long flags;
2836 /* We need to be sure that no thread is running the old callback as
2837 * we install the nop handler (otherwise we would submit a request
2838 * to hardware that will never complete). In order to prevent this
2839 * race, we wait until the machine is idle before making the swap
2840 * (using stop_machine()).
2842 engine->submit_request = nop_submit_request;
2844 /* Mark all executing requests as skipped */
2845 spin_lock_irqsave(&engine->timeline->lock, flags);
2846 list_for_each_entry(request, &engine->timeline->requests, link)
2847 dma_fence_set_error(&request->fence, -EIO);
2848 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2850 /* Mark all pending requests as complete so that any concurrent
2851 * (lockless) lookup doesn't try and wait upon the request as we
2854 intel_engine_init_global_seqno(engine,
2855 intel_engine_last_submit(engine));
2858 * Clear the execlists queue up before freeing the requests, as those
2859 * are the ones that keep the context and ringbuffer backing objects
2863 if (i915.enable_execlists) {
2864 unsigned long flags;
2866 spin_lock_irqsave(&engine->timeline->lock, flags);
2868 i915_gem_request_put(engine->execlist_port[0].request);
2869 i915_gem_request_put(engine->execlist_port[1].request);
2870 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2871 engine->execlist_queue = RB_ROOT;
2872 engine->execlist_first = NULL;
2874 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2878 static int __i915_gem_set_wedged_BKL(void *data)
2880 struct drm_i915_private *i915 = data;
2881 struct intel_engine_cs *engine;
2882 enum intel_engine_id id;
2884 for_each_engine(engine, i915, id)
2885 engine_set_wedged(engine);
2890 void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2892 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2893 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2895 stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL);
2897 i915_gem_context_lost(dev_priv);
2898 i915_gem_retire_requests(dev_priv);
2900 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2904 i915_gem_retire_work_handler(struct work_struct *work)
2906 struct drm_i915_private *dev_priv =
2907 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2908 struct drm_device *dev = &dev_priv->drm;
2910 /* Come back later if the device is busy... */
2911 if (mutex_trylock(&dev->struct_mutex)) {
2912 i915_gem_retire_requests(dev_priv);
2913 mutex_unlock(&dev->struct_mutex);
2916 /* Keep the retire handler running until we are finally idle.
2917 * We do not need to do this test under locking as in the worst-case
2918 * we queue the retire worker once too often.
2920 if (READ_ONCE(dev_priv->gt.awake)) {
2921 i915_queue_hangcheck(dev_priv);
2922 queue_delayed_work(dev_priv->wq,
2923 &dev_priv->gt.retire_work,
2924 round_jiffies_up_relative(HZ));
2929 i915_gem_idle_work_handler(struct work_struct *work)
2931 struct drm_i915_private *dev_priv =
2932 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2933 struct drm_device *dev = &dev_priv->drm;
2934 struct intel_engine_cs *engine;
2935 enum intel_engine_id id;
2936 bool rearm_hangcheck;
2938 if (!READ_ONCE(dev_priv->gt.awake))
2942 * Wait for last execlists context complete, but bail out in case a
2943 * new request is submitted.
2945 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
2946 intel_execlists_idle(dev_priv), 10);
2948 if (READ_ONCE(dev_priv->gt.active_requests))
2952 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2954 if (!mutex_trylock(&dev->struct_mutex)) {
2955 /* Currently busy, come back later */
2956 mod_delayed_work(dev_priv->wq,
2957 &dev_priv->gt.idle_work,
2958 msecs_to_jiffies(50));
2963 * New request retired after this work handler started, extend active
2964 * period until next instance of the work.
2966 if (work_pending(work))
2969 if (dev_priv->gt.active_requests)
2972 if (wait_for(intel_execlists_idle(dev_priv), 10))
2973 DRM_ERROR("Timeout waiting for engines to idle\n");
2975 for_each_engine(engine, dev_priv, id)
2976 i915_gem_batch_pool_fini(&engine->batch_pool);
2978 GEM_BUG_ON(!dev_priv->gt.awake);
2979 dev_priv->gt.awake = false;
2980 rearm_hangcheck = false;
2982 if (INTEL_GEN(dev_priv) >= 6)
2983 gen6_rps_idle(dev_priv);
2984 intel_runtime_pm_put(dev_priv);
2986 mutex_unlock(&dev->struct_mutex);
2989 if (rearm_hangcheck) {
2990 GEM_BUG_ON(!dev_priv->gt.awake);
2991 i915_queue_hangcheck(dev_priv);
2995 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
2997 struct drm_i915_gem_object *obj = to_intel_bo(gem);
2998 struct drm_i915_file_private *fpriv = file->driver_priv;
2999 struct i915_vma *vma, *vn;
3001 mutex_lock(&obj->base.dev->struct_mutex);
3002 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
3003 if (vma->vm->file == fpriv)
3004 i915_vma_close(vma);
3006 if (i915_gem_object_is_active(obj) &&
3007 !i915_gem_object_has_active_reference(obj)) {
3008 i915_gem_object_set_active_reference(obj);
3009 i915_gem_object_get(obj);
3011 mutex_unlock(&obj->base.dev->struct_mutex);
3014 static unsigned long to_wait_timeout(s64 timeout_ns)
3017 return MAX_SCHEDULE_TIMEOUT;
3019 if (timeout_ns == 0)
3022 return nsecs_to_jiffies_timeout(timeout_ns);
3026 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3027 * @dev: drm device pointer
3028 * @data: ioctl data blob
3029 * @file: drm file pointer
3031 * Returns 0 if successful, else an error is returned with the remaining time in
3032 * the timeout parameter.
3033 * -ETIME: object is still busy after timeout
3034 * -ERESTARTSYS: signal interrupted the wait
3035 * -ENONENT: object doesn't exist
3036 * Also possible, but rare:
3037 * -EAGAIN: GPU wedged
3039 * -ENODEV: Internal IRQ fail
3040 * -E?: The add request failed
3042 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3043 * non-zero timeout parameter the wait ioctl will wait for the given number of
3044 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3045 * without holding struct_mutex the object may become re-busied before this
3046 * function completes. A similar but shorter * race condition exists in the busy
3050 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3052 struct drm_i915_gem_wait *args = data;
3053 struct drm_i915_gem_object *obj;
3057 if (args->flags != 0)
3060 obj = i915_gem_object_lookup(file, args->bo_handle);
3064 start = ktime_get();
3066 ret = i915_gem_object_wait(obj,
3067 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3068 to_wait_timeout(args->timeout_ns),
3069 to_rps_client(file));
3071 if (args->timeout_ns > 0) {
3072 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3073 if (args->timeout_ns < 0)
3074 args->timeout_ns = 0;
3077 i915_gem_object_put(obj);
3081 static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3085 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3086 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3094 int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3098 if (flags & I915_WAIT_LOCKED) {
3099 struct i915_gem_timeline *tl;
3101 lockdep_assert_held(&i915->drm.struct_mutex);
3103 list_for_each_entry(tl, &i915->gt.timelines, link) {
3104 ret = wait_for_timeline(tl, flags);
3109 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3117 void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3120 /* If we don't have a page list set up, then we're not pinned
3121 * to GPU, and we can ignore the cache flush because it'll happen
3122 * again at bind time.
3128 * Stolen memory is always coherent with the GPU as it is explicitly
3129 * marked as wc by the system, or the system is cache-coherent.
3131 if (obj->stolen || obj->phys_handle)
3134 /* If the GPU is snooping the contents of the CPU cache,
3135 * we do not need to manually clear the CPU cache lines. However,
3136 * the caches are only snooped when the render cache is
3137 * flushed/invalidated. As we always have to emit invalidations
3138 * and flushes when moving into and out of the RENDER domain, correct
3139 * snooping behaviour occurs naturally as the result of our domain
3142 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3143 obj->cache_dirty = true;
3147 trace_i915_gem_object_clflush(obj);
3148 drm_clflush_sg(obj->mm.pages);
3149 obj->cache_dirty = false;
3152 /** Flushes the GTT write domain for the object if it's dirty. */
3154 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3156 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3158 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3161 /* No actual flushing is required for the GTT write domain. Writes
3162 * to it "immediately" go to main memory as far as we know, so there's
3163 * no chipset flush. It also doesn't land in render cache.
3165 * However, we do have to enforce the order so that all writes through
3166 * the GTT land before any writes to the device, such as updates to
3169 * We also have to wait a bit for the writes to land from the GTT.
3170 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3171 * timing. This issue has only been observed when switching quickly
3172 * between GTT writes and CPU reads from inside the kernel on recent hw,
3173 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3174 * system agents we cannot reproduce this behaviour).
3177 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3178 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3180 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3182 obj->base.write_domain = 0;
3183 trace_i915_gem_object_change_domain(obj,
3184 obj->base.read_domains,
3185 I915_GEM_DOMAIN_GTT);
3188 /** Flushes the CPU write domain for the object if it's dirty. */
3190 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3192 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3195 i915_gem_clflush_object(obj, obj->pin_display);
3196 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3198 obj->base.write_domain = 0;
3199 trace_i915_gem_object_change_domain(obj,
3200 obj->base.read_domains,
3201 I915_GEM_DOMAIN_CPU);
3205 * Moves a single object to the GTT read, and possibly write domain.
3206 * @obj: object to act on
3207 * @write: ask for write access or read only
3209 * This function returns when the move is complete, including waiting on
3213 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3215 uint32_t old_write_domain, old_read_domains;
3218 lockdep_assert_held(&obj->base.dev->struct_mutex);
3220 ret = i915_gem_object_wait(obj,
3221 I915_WAIT_INTERRUPTIBLE |
3223 (write ? I915_WAIT_ALL : 0),
3224 MAX_SCHEDULE_TIMEOUT,
3229 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3232 /* Flush and acquire obj->pages so that we are coherent through
3233 * direct access in memory with previous cached writes through
3234 * shmemfs and that our cache domain tracking remains valid.
3235 * For example, if the obj->filp was moved to swap without us
3236 * being notified and releasing the pages, we would mistakenly
3237 * continue to assume that the obj remained out of the CPU cached
3240 ret = i915_gem_object_pin_pages(obj);
3244 i915_gem_object_flush_cpu_write_domain(obj);
3246 /* Serialise direct access to this object with the barriers for
3247 * coherent writes from the GPU, by effectively invalidating the
3248 * GTT domain upon first access.
3250 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3253 old_write_domain = obj->base.write_domain;
3254 old_read_domains = obj->base.read_domains;
3256 /* It should now be out of any other write domains, and we can update
3257 * the domain values for our changes.
3259 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3260 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3262 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3263 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3264 obj->mm.dirty = true;
3267 trace_i915_gem_object_change_domain(obj,
3271 i915_gem_object_unpin_pages(obj);
3276 * Changes the cache-level of an object across all VMA.
3277 * @obj: object to act on
3278 * @cache_level: new cache level to set for the object
3280 * After this function returns, the object will be in the new cache-level
3281 * across all GTT and the contents of the backing storage will be coherent,
3282 * with respect to the new cache-level. In order to keep the backing storage
3283 * coherent for all users, we only allow a single cache level to be set
3284 * globally on the object and prevent it from being changed whilst the
3285 * hardware is reading from the object. That is if the object is currently
3286 * on the scanout it will be set to uncached (or equivalent display
3287 * cache coherency) and all non-MOCS GPU access will also be uncached so
3288 * that all direct access to the scanout remains coherent.
3290 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3291 enum i915_cache_level cache_level)
3293 struct i915_vma *vma;
3296 lockdep_assert_held(&obj->base.dev->struct_mutex);
3298 if (obj->cache_level == cache_level)
3301 /* Inspect the list of currently bound VMA and unbind any that would
3302 * be invalid given the new cache-level. This is principally to
3303 * catch the issue of the CS prefetch crossing page boundaries and
3304 * reading an invalid PTE on older architectures.
3307 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3308 if (!drm_mm_node_allocated(&vma->node))
3311 if (i915_vma_is_pinned(vma)) {
3312 DRM_DEBUG("can not change the cache level of pinned objects\n");
3316 if (i915_gem_valid_gtt_space(vma, cache_level))
3319 ret = i915_vma_unbind(vma);
3323 /* As unbinding may affect other elements in the
3324 * obj->vma_list (due to side-effects from retiring
3325 * an active vma), play safe and restart the iterator.
3330 /* We can reuse the existing drm_mm nodes but need to change the
3331 * cache-level on the PTE. We could simply unbind them all and
3332 * rebind with the correct cache-level on next use. However since
3333 * we already have a valid slot, dma mapping, pages etc, we may as
3334 * rewrite the PTE in the belief that doing so tramples upon less
3335 * state and so involves less work.
3337 if (obj->bind_count) {
3338 /* Before we change the PTE, the GPU must not be accessing it.
3339 * If we wait upon the object, we know that all the bound
3340 * VMA are no longer active.
3342 ret = i915_gem_object_wait(obj,
3343 I915_WAIT_INTERRUPTIBLE |
3346 MAX_SCHEDULE_TIMEOUT,
3351 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3352 cache_level != I915_CACHE_NONE) {
3353 /* Access to snoopable pages through the GTT is
3354 * incoherent and on some machines causes a hard
3355 * lockup. Relinquish the CPU mmaping to force
3356 * userspace to refault in the pages and we can
3357 * then double check if the GTT mapping is still
3358 * valid for that pointer access.
3360 i915_gem_release_mmap(obj);
3362 /* As we no longer need a fence for GTT access,
3363 * we can relinquish it now (and so prevent having
3364 * to steal a fence from someone else on the next
3365 * fence request). Note GPU activity would have
3366 * dropped the fence as all snoopable access is
3367 * supposed to be linear.
3369 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3370 ret = i915_vma_put_fence(vma);
3375 /* We either have incoherent backing store and
3376 * so no GTT access or the architecture is fully
3377 * coherent. In such cases, existing GTT mmaps
3378 * ignore the cache bit in the PTE and we can
3379 * rewrite it without confusing the GPU or having
3380 * to force userspace to fault back in its mmaps.
3384 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3385 if (!drm_mm_node_allocated(&vma->node))
3388 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3394 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3395 cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3396 obj->cache_dirty = true;
3398 list_for_each_entry(vma, &obj->vma_list, obj_link)
3399 vma->node.color = cache_level;
3400 obj->cache_level = cache_level;
3405 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3406 struct drm_file *file)
3408 struct drm_i915_gem_caching *args = data;
3409 struct drm_i915_gem_object *obj;
3413 obj = i915_gem_object_lookup_rcu(file, args->handle);
3419 switch (obj->cache_level) {
3420 case I915_CACHE_LLC:
3421 case I915_CACHE_L3_LLC:
3422 args->caching = I915_CACHING_CACHED;
3426 args->caching = I915_CACHING_DISPLAY;
3430 args->caching = I915_CACHING_NONE;
3438 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3439 struct drm_file *file)
3441 struct drm_i915_private *i915 = to_i915(dev);
3442 struct drm_i915_gem_caching *args = data;
3443 struct drm_i915_gem_object *obj;
3444 enum i915_cache_level level;
3447 switch (args->caching) {
3448 case I915_CACHING_NONE:
3449 level = I915_CACHE_NONE;
3451 case I915_CACHING_CACHED:
3453 * Due to a HW issue on BXT A stepping, GPU stores via a
3454 * snooped mapping may leave stale data in a corresponding CPU
3455 * cacheline, whereas normally such cachelines would get
3458 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3461 level = I915_CACHE_LLC;
3463 case I915_CACHING_DISPLAY:
3464 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3470 obj = i915_gem_object_lookup(file, args->handle);
3474 if (obj->cache_level == level)
3477 ret = i915_gem_object_wait(obj,
3478 I915_WAIT_INTERRUPTIBLE,
3479 MAX_SCHEDULE_TIMEOUT,
3480 to_rps_client(file));
3484 ret = i915_mutex_lock_interruptible(dev);
3488 ret = i915_gem_object_set_cache_level(obj, level);
3489 mutex_unlock(&dev->struct_mutex);
3492 i915_gem_object_put(obj);
3497 * Prepare buffer for display plane (scanout, cursors, etc).
3498 * Can be called from an uninterruptible phase (modesetting) and allows
3499 * any flushes to be pipelined (for pageflips).
3502 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3504 const struct i915_ggtt_view *view)
3506 struct i915_vma *vma;
3507 u32 old_read_domains, old_write_domain;
3510 lockdep_assert_held(&obj->base.dev->struct_mutex);
3512 /* Mark the pin_display early so that we account for the
3513 * display coherency whilst setting up the cache domains.
3517 /* The display engine is not coherent with the LLC cache on gen6. As
3518 * a result, we make sure that the pinning that is about to occur is
3519 * done with uncached PTEs. This is lowest common denominator for all
3522 * However for gen6+, we could do better by using the GFDT bit instead
3523 * of uncaching, which would allow us to flush all the LLC-cached data
3524 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3526 ret = i915_gem_object_set_cache_level(obj,
3527 HAS_WT(to_i915(obj->base.dev)) ?
3528 I915_CACHE_WT : I915_CACHE_NONE);
3531 goto err_unpin_display;
3534 /* As the user may map the buffer once pinned in the display plane
3535 * (e.g. libkms for the bootup splash), we have to ensure that we
3536 * always use map_and_fenceable for all scanout buffers. However,
3537 * it may simply be too big to fit into mappable, in which case
3538 * put it anyway and hope that userspace can cope (but always first
3539 * try to preserve the existing ABI).
3541 vma = ERR_PTR(-ENOSPC);
3542 if (!view || view->type == I915_GGTT_VIEW_NORMAL)
3543 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3544 PIN_MAPPABLE | PIN_NONBLOCK);
3546 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3549 /* Valleyview is definitely limited to scanning out the first
3550 * 512MiB. Lets presume this behaviour was inherited from the
3551 * g4x display engine and that all earlier gen are similarly
3552 * limited. Testing suggests that it is a little more
3553 * complicated than this. For example, Cherryview appears quite
3554 * happy to scanout from anywhere within its global aperture.
3557 if (HAS_GMCH_DISPLAY(i915))
3558 flags = PIN_MAPPABLE;
3559 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3562 goto err_unpin_display;
3564 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3566 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3567 if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3568 i915_gem_clflush_object(obj, true);
3569 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
3572 old_write_domain = obj->base.write_domain;
3573 old_read_domains = obj->base.read_domains;
3575 /* It should now be out of any other write domains, and we can update
3576 * the domain values for our changes.
3578 obj->base.write_domain = 0;
3579 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3581 trace_i915_gem_object_change_domain(obj,
3593 i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3595 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
3597 if (WARN_ON(vma->obj->pin_display == 0))
3600 if (--vma->obj->pin_display == 0)
3601 vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
3603 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3604 i915_gem_object_bump_inactive_ggtt(vma->obj);
3606 i915_vma_unpin(vma);
3610 * Moves a single object to the CPU read, and possibly write domain.
3611 * @obj: object to act on
3612 * @write: requesting write or read-only access
3614 * This function returns when the move is complete, including waiting on
3618 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3620 uint32_t old_write_domain, old_read_domains;
3623 lockdep_assert_held(&obj->base.dev->struct_mutex);
3625 ret = i915_gem_object_wait(obj,
3626 I915_WAIT_INTERRUPTIBLE |
3628 (write ? I915_WAIT_ALL : 0),
3629 MAX_SCHEDULE_TIMEOUT,
3634 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3637 i915_gem_object_flush_gtt_write_domain(obj);
3639 old_write_domain = obj->base.write_domain;
3640 old_read_domains = obj->base.read_domains;
3642 /* Flush the CPU cache if it's still invalid. */
3643 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3644 i915_gem_clflush_object(obj, false);
3646 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3649 /* It should now be out of any other write domains, and we can update
3650 * the domain values for our changes.
3652 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3654 /* If we're writing through the CPU, then the GPU read domains will
3655 * need to be invalidated at next use.
3658 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3659 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3662 trace_i915_gem_object_change_domain(obj,
3669 /* Throttle our rendering by waiting until the ring has completed our requests
3670 * emitted over 20 msec ago.
3672 * Note that if we were to use the current jiffies each time around the loop,
3673 * we wouldn't escape the function with any frames outstanding if the time to
3674 * render a frame was over 20ms.
3676 * This should get us reasonable parallelism between CPU and GPU but also
3677 * relatively low latency when blocking on a particular request to finish.
3680 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3682 struct drm_i915_private *dev_priv = to_i915(dev);
3683 struct drm_i915_file_private *file_priv = file->driver_priv;
3684 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3685 struct drm_i915_gem_request *request, *target = NULL;
3688 /* ABI: return -EIO if already wedged */
3689 if (i915_terminally_wedged(&dev_priv->gpu_error))
3692 spin_lock(&file_priv->mm.lock);
3693 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3694 if (time_after_eq(request->emitted_jiffies, recent_enough))
3698 * Note that the request might not have been submitted yet.
3699 * In which case emitted_jiffies will be zero.
3701 if (!request->emitted_jiffies)
3707 i915_gem_request_get(target);
3708 spin_unlock(&file_priv->mm.lock);
3713 ret = i915_wait_request(target,
3714 I915_WAIT_INTERRUPTIBLE,
3715 MAX_SCHEDULE_TIMEOUT);
3716 i915_gem_request_put(target);
3718 return ret < 0 ? ret : 0;
3722 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3723 const struct i915_ggtt_view *view,
3728 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3729 struct i915_address_space *vm = &dev_priv->ggtt.base;
3730 struct i915_vma *vma;
3733 lockdep_assert_held(&obj->base.dev->struct_mutex);
3735 vma = i915_vma_instance(obj, vm, view);
3736 if (unlikely(IS_ERR(vma)))
3739 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3740 if (flags & PIN_NONBLOCK &&
3741 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3742 return ERR_PTR(-ENOSPC);
3744 if (flags & PIN_MAPPABLE) {
3745 /* If the required space is larger than the available
3746 * aperture, we will not able to find a slot for the
3747 * object and unbinding the object now will be in
3748 * vain. Worse, doing so may cause us to ping-pong
3749 * the object in and out of the Global GTT and
3750 * waste a lot of cycles under the mutex.
3752 if (vma->fence_size > dev_priv->ggtt.mappable_end)
3753 return ERR_PTR(-E2BIG);
3755 /* If NONBLOCK is set the caller is optimistically
3756 * trying to cache the full object within the mappable
3757 * aperture, and *must* have a fallback in place for
3758 * situations where we cannot bind the object. We
3759 * can be a little more lax here and use the fallback
3760 * more often to avoid costly migrations of ourselves
3761 * and other objects within the aperture.
3763 * Half-the-aperture is used as a simple heuristic.
3764 * More interesting would to do search for a free
3765 * block prior to making the commitment to unbind.
3766 * That caters for the self-harm case, and with a
3767 * little more heuristics (e.g. NOFAULT, NOEVICT)
3768 * we could try to minimise harm to others.
3770 if (flags & PIN_NONBLOCK &&
3771 vma->fence_size > dev_priv->ggtt.mappable_end / 2)
3772 return ERR_PTR(-ENOSPC);
3775 WARN(i915_vma_is_pinned(vma),
3776 "bo is already pinned in ggtt with incorrect alignment:"
3777 " offset=%08x, req.alignment=%llx,"
3778 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3779 i915_ggtt_offset(vma), alignment,
3780 !!(flags & PIN_MAPPABLE),
3781 i915_vma_is_map_and_fenceable(vma));
3782 ret = i915_vma_unbind(vma);
3784 return ERR_PTR(ret);
3787 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3789 return ERR_PTR(ret);
3794 static __always_inline unsigned int __busy_read_flag(unsigned int id)
3796 /* Note that we could alias engines in the execbuf API, but
3797 * that would be very unwise as it prevents userspace from
3798 * fine control over engine selection. Ahem.
3800 * This should be something like EXEC_MAX_ENGINE instead of
3803 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3804 return 0x10000 << id;
3807 static __always_inline unsigned int __busy_write_id(unsigned int id)
3809 /* The uABI guarantees an active writer is also amongst the read
3810 * engines. This would be true if we accessed the activity tracking
3811 * under the lock, but as we perform the lookup of the object and
3812 * its activity locklessly we can not guarantee that the last_write
3813 * being active implies that we have set the same engine flag from
3814 * last_read - hence we always set both read and write busy for
3817 return id | __busy_read_flag(id);
3820 static __always_inline unsigned int
3821 __busy_set_if_active(const struct dma_fence *fence,
3822 unsigned int (*flag)(unsigned int id))
3824 struct drm_i915_gem_request *rq;
3826 /* We have to check the current hw status of the fence as the uABI
3827 * guarantees forward progress. We could rely on the idle worker
3828 * to eventually flush us, but to minimise latency just ask the
3831 * Note we only report on the status of native fences.
3833 if (!dma_fence_is_i915(fence))
3836 /* opencode to_request() in order to avoid const warnings */
3837 rq = container_of(fence, struct drm_i915_gem_request, fence);
3838 if (i915_gem_request_completed(rq))
3841 return flag(rq->engine->exec_id);
3844 static __always_inline unsigned int
3845 busy_check_reader(const struct dma_fence *fence)
3847 return __busy_set_if_active(fence, __busy_read_flag);
3850 static __always_inline unsigned int
3851 busy_check_writer(const struct dma_fence *fence)
3856 return __busy_set_if_active(fence, __busy_write_id);
3860 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3861 struct drm_file *file)
3863 struct drm_i915_gem_busy *args = data;
3864 struct drm_i915_gem_object *obj;
3865 struct reservation_object_list *list;
3871 obj = i915_gem_object_lookup_rcu(file, args->handle);
3875 /* A discrepancy here is that we do not report the status of
3876 * non-i915 fences, i.e. even though we may report the object as idle,
3877 * a call to set-domain may still stall waiting for foreign rendering.
3878 * This also means that wait-ioctl may report an object as busy,
3879 * where busy-ioctl considers it idle.
3881 * We trade the ability to warn of foreign fences to report on which
3882 * i915 engines are active for the object.
3884 * Alternatively, we can trade that extra information on read/write
3887 * !reservation_object_test_signaled_rcu(obj->resv, true);
3888 * to report the overall busyness. This is what the wait-ioctl does.
3892 seq = raw_read_seqcount(&obj->resv->seq);
3894 /* Translate the exclusive fence to the READ *and* WRITE engine */
3895 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
3897 /* Translate shared fences to READ set of engines */
3898 list = rcu_dereference(obj->resv->fence);
3900 unsigned int shared_count = list->shared_count, i;
3902 for (i = 0; i < shared_count; ++i) {
3903 struct dma_fence *fence =
3904 rcu_dereference(list->shared[i]);
3906 args->busy |= busy_check_reader(fence);
3910 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
3920 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3921 struct drm_file *file_priv)
3923 return i915_gem_ring_throttle(dev, file_priv);
3927 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3928 struct drm_file *file_priv)
3930 struct drm_i915_private *dev_priv = to_i915(dev);
3931 struct drm_i915_gem_madvise *args = data;
3932 struct drm_i915_gem_object *obj;
3935 switch (args->madv) {
3936 case I915_MADV_DONTNEED:
3937 case I915_MADV_WILLNEED:
3943 obj = i915_gem_object_lookup(file_priv, args->handle);
3947 err = mutex_lock_interruptible(&obj->mm.lock);
3951 if (obj->mm.pages &&
3952 i915_gem_object_is_tiled(obj) &&
3953 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
3954 if (obj->mm.madv == I915_MADV_WILLNEED) {
3955 GEM_BUG_ON(!obj->mm.quirked);
3956 __i915_gem_object_unpin_pages(obj);
3957 obj->mm.quirked = false;
3959 if (args->madv == I915_MADV_WILLNEED) {
3960 GEM_BUG_ON(obj->mm.quirked);
3961 __i915_gem_object_pin_pages(obj);
3962 obj->mm.quirked = true;
3966 if (obj->mm.madv != __I915_MADV_PURGED)
3967 obj->mm.madv = args->madv;
3969 /* if the object is no longer attached, discard its backing storage */
3970 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
3971 i915_gem_object_truncate(obj);
3973 args->retained = obj->mm.madv != __I915_MADV_PURGED;
3974 mutex_unlock(&obj->mm.lock);
3977 i915_gem_object_put(obj);
3982 frontbuffer_retire(struct i915_gem_active *active,
3983 struct drm_i915_gem_request *request)
3985 struct drm_i915_gem_object *obj =
3986 container_of(active, typeof(*obj), frontbuffer_write);
3988 intel_fb_obj_flush(obj, true, ORIGIN_CS);
3991 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3992 const struct drm_i915_gem_object_ops *ops)
3994 mutex_init(&obj->mm.lock);
3996 INIT_LIST_HEAD(&obj->global_link);
3997 INIT_LIST_HEAD(&obj->userfault_link);
3998 INIT_LIST_HEAD(&obj->obj_exec_link);
3999 INIT_LIST_HEAD(&obj->vma_list);
4000 INIT_LIST_HEAD(&obj->batch_pool_link);
4004 reservation_object_init(&obj->__builtin_resv);
4005 obj->resv = &obj->__builtin_resv;
4007 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
4008 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
4010 obj->mm.madv = I915_MADV_WILLNEED;
4011 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
4012 mutex_init(&obj->mm.get_page.lock);
4014 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
4017 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4018 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4019 I915_GEM_OBJECT_IS_SHRINKABLE,
4020 .get_pages = i915_gem_object_get_pages_gtt,
4021 .put_pages = i915_gem_object_put_pages_gtt,
4024 struct drm_i915_gem_object *
4025 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
4027 struct drm_i915_gem_object *obj;
4028 struct address_space *mapping;
4032 /* There is a prevalence of the assumption that we fit the object's
4033 * page count inside a 32bit _signed_ variable. Let's document this and
4034 * catch if we ever need to fix it. In the meantime, if you do spot
4035 * such a local variable, please consider fixing!
4037 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
4038 return ERR_PTR(-E2BIG);
4040 if (overflows_type(size, obj->base.size))
4041 return ERR_PTR(-E2BIG);
4043 obj = i915_gem_object_alloc(dev_priv);
4045 return ERR_PTR(-ENOMEM);
4047 ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size);
4051 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4052 if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
4053 /* 965gm cannot relocate objects above 4GiB. */
4054 mask &= ~__GFP_HIGHMEM;
4055 mask |= __GFP_DMA32;
4058 mapping = obj->base.filp->f_mapping;
4059 mapping_set_gfp_mask(mapping, mask);
4061 i915_gem_object_init(obj, &i915_gem_object_ops);
4063 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4064 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4066 if (HAS_LLC(dev_priv)) {
4067 /* On some devices, we can have the GPU use the LLC (the CPU
4068 * cache) for about a 10% performance improvement
4069 * compared to uncached. Graphics requests other than
4070 * display scanout are coherent with the CPU in
4071 * accessing this cache. This means in this mode we
4072 * don't need to clflush on the CPU side, and on the
4073 * GPU side we only need to flush internal caches to
4074 * get data visible to the CPU.
4076 * However, we maintain the display planes as UC, and so
4077 * need to rebind when first used as such.
4079 obj->cache_level = I915_CACHE_LLC;
4081 obj->cache_level = I915_CACHE_NONE;
4083 trace_i915_gem_object_create(obj);
4088 i915_gem_object_free(obj);
4089 return ERR_PTR(ret);
4092 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4094 /* If we are the last user of the backing storage (be it shmemfs
4095 * pages or stolen etc), we know that the pages are going to be
4096 * immediately released. In this case, we can then skip copying
4097 * back the contents from the GPU.
4100 if (obj->mm.madv != I915_MADV_WILLNEED)
4103 if (obj->base.filp == NULL)
4106 /* At first glance, this looks racy, but then again so would be
4107 * userspace racing mmap against close. However, the first external
4108 * reference to the filp can only be obtained through the
4109 * i915_gem_mmap_ioctl() which safeguards us against the user
4110 * acquiring such a reference whilst we are in the middle of
4111 * freeing the object.
4113 return atomic_long_read(&obj->base.filp->f_count) == 1;
4116 static void __i915_gem_free_objects(struct drm_i915_private *i915,
4117 struct llist_node *freed)
4119 struct drm_i915_gem_object *obj, *on;
4121 mutex_lock(&i915->drm.struct_mutex);
4122 intel_runtime_pm_get(i915);
4123 llist_for_each_entry(obj, freed, freed) {
4124 struct i915_vma *vma, *vn;
4126 trace_i915_gem_object_destroy(obj);
4128 GEM_BUG_ON(i915_gem_object_is_active(obj));
4129 list_for_each_entry_safe(vma, vn,
4130 &obj->vma_list, obj_link) {
4131 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4132 GEM_BUG_ON(i915_vma_is_active(vma));
4133 vma->flags &= ~I915_VMA_PIN_MASK;
4134 i915_vma_close(vma);
4136 GEM_BUG_ON(!list_empty(&obj->vma_list));
4137 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4139 list_del(&obj->global_link);
4141 intel_runtime_pm_put(i915);
4142 mutex_unlock(&i915->drm.struct_mutex);
4144 llist_for_each_entry_safe(obj, on, freed, freed) {
4145 GEM_BUG_ON(obj->bind_count);
4146 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4148 if (obj->ops->release)
4149 obj->ops->release(obj);
4151 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4152 atomic_set(&obj->mm.pages_pin_count, 0);
4153 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4154 GEM_BUG_ON(obj->mm.pages);
4156 if (obj->base.import_attach)
4157 drm_prime_gem_destroy(&obj->base, NULL);
4159 reservation_object_fini(&obj->__builtin_resv);
4160 drm_gem_object_release(&obj->base);
4161 i915_gem_info_remove_obj(i915, obj->base.size);
4164 i915_gem_object_free(obj);
4168 static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4170 struct llist_node *freed;
4172 freed = llist_del_all(&i915->mm.free_list);
4173 if (unlikely(freed))
4174 __i915_gem_free_objects(i915, freed);
4177 static void __i915_gem_free_work(struct work_struct *work)
4179 struct drm_i915_private *i915 =
4180 container_of(work, struct drm_i915_private, mm.free_work);
4181 struct llist_node *freed;
4183 /* All file-owned VMA should have been released by this point through
4184 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4185 * However, the object may also be bound into the global GTT (e.g.
4186 * older GPUs without per-process support, or for direct access through
4187 * the GTT either for the user or for scanout). Those VMA still need to
4191 while ((freed = llist_del_all(&i915->mm.free_list)))
4192 __i915_gem_free_objects(i915, freed);
4195 static void __i915_gem_free_object_rcu(struct rcu_head *head)
4197 struct drm_i915_gem_object *obj =
4198 container_of(head, typeof(*obj), rcu);
4199 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4201 /* We can't simply use call_rcu() from i915_gem_free_object()
4202 * as we need to block whilst unbinding, and the call_rcu
4203 * task may be called from softirq context. So we take a
4204 * detour through a worker.
4206 if (llist_add(&obj->freed, &i915->mm.free_list))
4207 schedule_work(&i915->mm.free_work);
4210 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4212 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4214 if (obj->mm.quirked)
4215 __i915_gem_object_unpin_pages(obj);
4217 if (discard_backing_storage(obj))
4218 obj->mm.madv = I915_MADV_DONTNEED;
4220 /* Before we free the object, make sure any pure RCU-only
4221 * read-side critical sections are complete, e.g.
4222 * i915_gem_busy_ioctl(). For the corresponding synchronized
4223 * lookup see i915_gem_object_lookup_rcu().
4225 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4228 void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4230 lockdep_assert_held(&obj->base.dev->struct_mutex);
4232 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4233 if (i915_gem_object_is_active(obj))
4234 i915_gem_object_set_active_reference(obj);
4236 i915_gem_object_put(obj);
4239 static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4241 struct intel_engine_cs *engine;
4242 enum intel_engine_id id;
4244 for_each_engine(engine, dev_priv, id)
4245 GEM_BUG_ON(engine->last_retired_context &&
4246 !i915_gem_context_is_kernel(engine->last_retired_context));
4249 void i915_gem_sanitize(struct drm_i915_private *i915)
4252 * If we inherit context state from the BIOS or earlier occupants
4253 * of the GPU, the GPU may be in an inconsistent state when we
4254 * try to take over. The only way to remove the earlier state
4255 * is by resetting. However, resetting on earlier gen is tricky as
4256 * it may impact the display and we are uncertain about the stability
4257 * of the reset, so we only reset recent machines with logical
4258 * context support (that must be reset to remove any stray contexts).
4260 if (HAS_HW_CONTEXTS(i915)) {
4261 int reset = intel_gpu_reset(i915, ALL_ENGINES);
4262 WARN_ON(reset && reset != -ENODEV);
4266 int i915_gem_suspend(struct drm_i915_private *dev_priv)
4268 struct drm_device *dev = &dev_priv->drm;
4271 intel_suspend_gt_powersave(dev_priv);
4273 mutex_lock(&dev->struct_mutex);
4275 /* We have to flush all the executing contexts to main memory so
4276 * that they can saved in the hibernation image. To ensure the last
4277 * context image is coherent, we have to switch away from it. That
4278 * leaves the dev_priv->kernel_context still active when
4279 * we actually suspend, and its image in memory may not match the GPU
4280 * state. Fortunately, the kernel_context is disposable and we do
4281 * not rely on its state.
4283 ret = i915_gem_switch_to_kernel_context(dev_priv);
4287 ret = i915_gem_wait_for_idle(dev_priv,
4288 I915_WAIT_INTERRUPTIBLE |
4293 i915_gem_retire_requests(dev_priv);
4294 GEM_BUG_ON(dev_priv->gt.active_requests);
4296 assert_kernel_context_is_current(dev_priv);
4297 i915_gem_context_lost(dev_priv);
4298 mutex_unlock(&dev->struct_mutex);
4300 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4301 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4303 /* As the idle_work is rearming if it detects a race, play safe and
4304 * repeat the flush until it is definitely idle.
4306 while (flush_delayed_work(&dev_priv->gt.idle_work))
4309 i915_gem_drain_freed_objects(dev_priv);
4311 /* Assert that we sucessfully flushed all the work and
4312 * reset the GPU back to its idle, low power state.
4314 WARN_ON(dev_priv->gt.awake);
4315 WARN_ON(!intel_execlists_idle(dev_priv));
4318 * Neither the BIOS, ourselves or any other kernel
4319 * expects the system to be in execlists mode on startup,
4320 * so we need to reset the GPU back to legacy mode. And the only
4321 * known way to disable logical contexts is through a GPU reset.
4323 * So in order to leave the system in a known default configuration,
4324 * always reset the GPU upon unload and suspend. Afterwards we then
4325 * clean up the GEM state tracking, flushing off the requests and
4326 * leaving the system in a known idle state.
4328 * Note that is of the upmost importance that the GPU is idle and
4329 * all stray writes are flushed *before* we dismantle the backing
4330 * storage for the pinned objects.
4332 * However, since we are uncertain that resetting the GPU on older
4333 * machines is a good idea, we don't - just in case it leaves the
4334 * machine in an unusable condition.
4336 i915_gem_sanitize(dev_priv);
4341 mutex_unlock(&dev->struct_mutex);
4345 void i915_gem_resume(struct drm_i915_private *dev_priv)
4347 struct drm_device *dev = &dev_priv->drm;
4349 WARN_ON(dev_priv->gt.awake);
4351 mutex_lock(&dev->struct_mutex);
4352 i915_gem_restore_gtt_mappings(dev_priv);
4354 /* As we didn't flush the kernel context before suspend, we cannot
4355 * guarantee that the context image is complete. So let's just reset
4356 * it and start again.
4358 dev_priv->gt.resume(dev_priv);
4360 mutex_unlock(&dev->struct_mutex);
4363 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4365 if (INTEL_GEN(dev_priv) < 5 ||
4366 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4369 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4370 DISP_TILE_SURFACE_SWIZZLING);
4372 if (IS_GEN5(dev_priv))
4375 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4376 if (IS_GEN6(dev_priv))
4377 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4378 else if (IS_GEN7(dev_priv))
4379 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4380 else if (IS_GEN8(dev_priv))
4381 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4386 static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4388 I915_WRITE(RING_CTL(base), 0);
4389 I915_WRITE(RING_HEAD(base), 0);
4390 I915_WRITE(RING_TAIL(base), 0);
4391 I915_WRITE(RING_START(base), 0);
4394 static void init_unused_rings(struct drm_i915_private *dev_priv)
4396 if (IS_I830(dev_priv)) {
4397 init_unused_ring(dev_priv, PRB1_BASE);
4398 init_unused_ring(dev_priv, SRB0_BASE);
4399 init_unused_ring(dev_priv, SRB1_BASE);
4400 init_unused_ring(dev_priv, SRB2_BASE);
4401 init_unused_ring(dev_priv, SRB3_BASE);
4402 } else if (IS_GEN2(dev_priv)) {
4403 init_unused_ring(dev_priv, SRB0_BASE);
4404 init_unused_ring(dev_priv, SRB1_BASE);
4405 } else if (IS_GEN3(dev_priv)) {
4406 init_unused_ring(dev_priv, PRB1_BASE);
4407 init_unused_ring(dev_priv, PRB2_BASE);
4411 static int __i915_gem_restart_engines(void *data)
4413 struct drm_i915_private *i915 = data;
4414 struct intel_engine_cs *engine;
4415 enum intel_engine_id id;
4418 for_each_engine(engine, i915, id) {
4419 err = engine->init_hw(engine);
4427 int i915_gem_init_hw(struct drm_i915_private *dev_priv)
4431 dev_priv->gt.last_init_time = ktime_get();
4433 /* Double layer security blanket, see i915_gem_init() */
4434 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4436 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4437 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4439 if (IS_HASWELL(dev_priv))
4440 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4441 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4443 if (HAS_PCH_NOP(dev_priv)) {
4444 if (IS_IVYBRIDGE(dev_priv)) {
4445 u32 temp = I915_READ(GEN7_MSG_CTL);
4446 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4447 I915_WRITE(GEN7_MSG_CTL, temp);
4448 } else if (INTEL_GEN(dev_priv) >= 7) {
4449 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4450 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4451 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4455 i915_gem_init_swizzling(dev_priv);
4458 * At least 830 can leave some of the unused rings
4459 * "active" (ie. head != tail) after resume which
4460 * will prevent c3 entry. Makes sure all unused rings
4463 init_unused_rings(dev_priv);
4465 BUG_ON(!dev_priv->kernel_context);
4467 ret = i915_ppgtt_init_hw(dev_priv);
4469 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4473 /* Need to do basic initialisation of all rings first: */
4474 ret = __i915_gem_restart_engines(dev_priv);
4478 intel_mocs_init_l3cc_table(dev_priv);
4480 /* We can't enable contexts until all firmware is loaded */
4481 ret = intel_guc_setup(dev_priv);
4486 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4490 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4492 if (INTEL_INFO(dev_priv)->gen < 6)
4495 /* TODO: make semaphores and Execlists play nicely together */
4496 if (i915.enable_execlists)
4502 #ifdef CONFIG_INTEL_IOMMU
4503 /* Enable semaphores on SNB when IO remapping is off */
4504 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4511 int i915_gem_init(struct drm_i915_private *dev_priv)
4515 mutex_lock(&dev_priv->drm.struct_mutex);
4517 if (!i915.enable_execlists) {
4518 dev_priv->gt.resume = intel_legacy_submission_resume;
4519 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4521 dev_priv->gt.resume = intel_lr_context_resume;
4522 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4525 /* This is just a security blanket to placate dragons.
4526 * On some systems, we very sporadically observe that the first TLBs
4527 * used by the CS may be stale, despite us poking the TLB reset. If
4528 * we hold the forcewake during initialisation these problems
4529 * just magically go away.
4531 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4533 i915_gem_init_userptr(dev_priv);
4535 ret = i915_gem_init_ggtt(dev_priv);
4539 ret = i915_gem_context_init(dev_priv);
4543 ret = intel_engines_init(dev_priv);
4547 ret = i915_gem_init_hw(dev_priv);
4549 /* Allow engine initialisation to fail by marking the GPU as
4550 * wedged. But we only want to do this where the GPU is angry,
4551 * for all other failure, such as an allocation failure, bail.
4553 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4554 i915_gem_set_wedged(dev_priv);
4559 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4560 mutex_unlock(&dev_priv->drm.struct_mutex);
4565 void i915_gem_init_mmio(struct drm_i915_private *i915)
4567 i915_gem_sanitize(i915);
4571 i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
4573 struct intel_engine_cs *engine;
4574 enum intel_engine_id id;
4576 for_each_engine(engine, dev_priv, id)
4577 dev_priv->gt.cleanup_engine(engine);
4581 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4585 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4586 !IS_CHERRYVIEW(dev_priv))
4587 dev_priv->num_fence_regs = 32;
4588 else if (INTEL_INFO(dev_priv)->gen >= 4 ||
4589 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
4590 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
4591 dev_priv->num_fence_regs = 16;
4593 dev_priv->num_fence_regs = 8;
4595 if (intel_vgpu_active(dev_priv))
4596 dev_priv->num_fence_regs =
4597 I915_READ(vgtif_reg(avail_rs.fence_num));
4599 /* Initialize fence registers to zero */
4600 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4601 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4603 fence->i915 = dev_priv;
4605 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4607 i915_gem_restore_fences(dev_priv);
4609 i915_gem_detect_bit_6_swizzle(dev_priv);
4613 i915_gem_load_init(struct drm_i915_private *dev_priv)
4617 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4618 if (!dev_priv->objects)
4621 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4622 if (!dev_priv->vmas)
4625 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4626 SLAB_HWCACHE_ALIGN |
4627 SLAB_RECLAIM_ACCOUNT |
4628 SLAB_DESTROY_BY_RCU);
4629 if (!dev_priv->requests)
4632 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4633 SLAB_HWCACHE_ALIGN |
4634 SLAB_RECLAIM_ACCOUNT);
4635 if (!dev_priv->dependencies)
4638 mutex_lock(&dev_priv->drm.struct_mutex);
4639 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4640 err = i915_gem_timeline_init__global(dev_priv);
4641 mutex_unlock(&dev_priv->drm.struct_mutex);
4643 goto err_dependencies;
4645 INIT_LIST_HEAD(&dev_priv->context_list);
4646 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4647 init_llist_head(&dev_priv->mm.free_list);
4648 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4649 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4650 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4651 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4652 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4653 i915_gem_retire_work_handler);
4654 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4655 i915_gem_idle_work_handler);
4656 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4657 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4659 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4661 init_waitqueue_head(&dev_priv->pending_flip_queue);
4663 dev_priv->mm.interruptible = true;
4665 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4667 spin_lock_init(&dev_priv->fb_tracking.lock);
4672 kmem_cache_destroy(dev_priv->dependencies);
4674 kmem_cache_destroy(dev_priv->requests);
4676 kmem_cache_destroy(dev_priv->vmas);
4678 kmem_cache_destroy(dev_priv->objects);
4683 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv)
4685 i915_gem_drain_freed_objects(dev_priv);
4686 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4687 WARN_ON(dev_priv->mm.object_count);
4689 mutex_lock(&dev_priv->drm.struct_mutex);
4690 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4691 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4692 mutex_unlock(&dev_priv->drm.struct_mutex);
4694 kmem_cache_destroy(dev_priv->dependencies);
4695 kmem_cache_destroy(dev_priv->requests);
4696 kmem_cache_destroy(dev_priv->vmas);
4697 kmem_cache_destroy(dev_priv->objects);
4699 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4703 int i915_gem_freeze(struct drm_i915_private *dev_priv)
4705 mutex_lock(&dev_priv->drm.struct_mutex);
4706 i915_gem_shrink_all(dev_priv);
4707 mutex_unlock(&dev_priv->drm.struct_mutex);
4712 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4714 struct drm_i915_gem_object *obj;
4715 struct list_head *phases[] = {
4716 &dev_priv->mm.unbound_list,
4717 &dev_priv->mm.bound_list,
4721 /* Called just before we write the hibernation image.
4723 * We need to update the domain tracking to reflect that the CPU
4724 * will be accessing all the pages to create and restore from the
4725 * hibernation, and so upon restoration those pages will be in the
4728 * To make sure the hibernation image contains the latest state,
4729 * we update that state just before writing out the image.
4731 * To try and reduce the hibernation image, we manually shrink
4732 * the objects as well.
4735 mutex_lock(&dev_priv->drm.struct_mutex);
4736 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4738 for (p = phases; *p; p++) {
4739 list_for_each_entry(obj, *p, global_link) {
4740 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4741 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4744 mutex_unlock(&dev_priv->drm.struct_mutex);
4749 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4751 struct drm_i915_file_private *file_priv = file->driver_priv;
4752 struct drm_i915_gem_request *request;
4754 /* Clean up our request list when the client is going away, so that
4755 * later retire_requests won't dereference our soon-to-be-gone
4758 spin_lock(&file_priv->mm.lock);
4759 list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4760 request->file_priv = NULL;
4761 spin_unlock(&file_priv->mm.lock);
4763 if (!list_empty(&file_priv->rps.link)) {
4764 spin_lock(&to_i915(dev)->rps.client_lock);
4765 list_del(&file_priv->rps.link);
4766 spin_unlock(&to_i915(dev)->rps.client_lock);
4770 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4772 struct drm_i915_file_private *file_priv;
4777 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4781 file->driver_priv = file_priv;
4782 file_priv->dev_priv = to_i915(dev);
4783 file_priv->file = file;
4784 INIT_LIST_HEAD(&file_priv->rps.link);
4786 spin_lock_init(&file_priv->mm.lock);
4787 INIT_LIST_HEAD(&file_priv->mm.request_list);
4789 file_priv->bsd_engine = -1;
4791 ret = i915_gem_context_open(dev, file);
4799 * i915_gem_track_fb - update frontbuffer tracking
4800 * @old: current GEM buffer for the frontbuffer slots
4801 * @new: new GEM buffer for the frontbuffer slots
4802 * @frontbuffer_bits: bitmask of frontbuffer slots
4804 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4805 * from @old and setting them in @new. Both @old and @new can be NULL.
4807 void i915_gem_track_fb(struct drm_i915_gem_object *old,
4808 struct drm_i915_gem_object *new,
4809 unsigned frontbuffer_bits)
4811 /* Control of individual bits within the mask are guarded by
4812 * the owning plane->mutex, i.e. we can never see concurrent
4813 * manipulation of individual bits. But since the bitfield as a whole
4814 * is updated using RMW, we need to use atomics in order to update
4817 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4818 sizeof(atomic_t) * BITS_PER_BYTE);
4821 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4822 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4826 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4827 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4831 /* Allocate a new GEM object and fill it with the supplied data */
4832 struct drm_i915_gem_object *
4833 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
4834 const void *data, size_t size)
4836 struct drm_i915_gem_object *obj;
4837 struct sg_table *sg;
4841 obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
4845 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4849 ret = i915_gem_object_pin_pages(obj);
4854 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4855 obj->mm.dirty = true; /* Backing store is now out of date */
4856 i915_gem_object_unpin_pages(obj);
4858 if (WARN_ON(bytes != size)) {
4859 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4867 i915_gem_object_put(obj);
4868 return ERR_PTR(ret);
4871 struct scatterlist *
4872 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4874 unsigned int *offset)
4876 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4877 struct scatterlist *sg;
4878 unsigned int idx, count;
4881 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4882 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4884 /* As we iterate forward through the sg, we record each entry in a
4885 * radixtree for quick repeated (backwards) lookups. If we have seen
4886 * this index previously, we will have an entry for it.
4888 * Initial lookup is O(N), but this is amortized to O(1) for
4889 * sequential page access (where each new request is consecutive
4890 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4891 * i.e. O(1) with a large constant!
4893 if (n < READ_ONCE(iter->sg_idx))
4896 mutex_lock(&iter->lock);
4898 /* We prefer to reuse the last sg so that repeated lookup of this
4899 * (or the subsequent) sg are fast - comparing against the last
4900 * sg is faster than going through the radixtree.
4905 count = __sg_page_count(sg);
4907 while (idx + count <= n) {
4908 unsigned long exception, i;
4911 /* If we cannot allocate and insert this entry, or the
4912 * individual pages from this range, cancel updating the
4913 * sg_idx so that on this lookup we are forced to linearly
4914 * scan onwards, but on future lookups we will try the
4915 * insertion again (in which case we need to be careful of
4916 * the error return reporting that we have already inserted
4919 ret = radix_tree_insert(&iter->radix, idx, sg);
4920 if (ret && ret != -EEXIST)
4924 RADIX_TREE_EXCEPTIONAL_ENTRY |
4925 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
4926 for (i = 1; i < count; i++) {
4927 ret = radix_tree_insert(&iter->radix, idx + i,
4929 if (ret && ret != -EEXIST)
4934 sg = ____sg_next(sg);
4935 count = __sg_page_count(sg);
4942 mutex_unlock(&iter->lock);
4944 if (unlikely(n < idx)) /* insertion completed by another thread */
4947 /* In case we failed to insert the entry into the radixtree, we need
4948 * to look beyond the current sg.
4950 while (idx + count <= n) {
4952 sg = ____sg_next(sg);
4953 count = __sg_page_count(sg);
4962 sg = radix_tree_lookup(&iter->radix, n);
4965 /* If this index is in the middle of multi-page sg entry,
4966 * the radixtree will contain an exceptional entry that points
4967 * to the start of that range. We will return the pointer to
4968 * the base page and the offset of this page within the
4972 if (unlikely(radix_tree_exception(sg))) {
4973 unsigned long base =
4974 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
4976 sg = radix_tree_lookup(&iter->radix, base);
4988 i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
4990 struct scatterlist *sg;
4991 unsigned int offset;
4993 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
4995 sg = i915_gem_object_get_sg(obj, n, &offset);
4996 return nth_page(sg_page(sg), offset);
4999 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5001 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
5006 page = i915_gem_object_get_page(obj, n);
5008 set_page_dirty(page);
5014 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
5017 struct scatterlist *sg;
5018 unsigned int offset;
5020 sg = i915_gem_object_get_sg(obj, n, &offset);
5021 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
5024 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
5025 #include "selftests/scatterlist.c"
5026 #include "selftests/mock_gem_device.c"