2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/dma_remapping.h>
30 #include <linux/reservation.h>
31 #include <linux/sync_file.h>
32 #include <linux/uaccess.h>
35 #include <drm/i915_drm.h>
38 #include "i915_gem_clflush.h"
39 #include "i915_trace.h"
40 #include "intel_drv.h"
41 #include "intel_frontbuffer.h"
43 #define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
45 #define __EXEC_OBJECT_HAS_PIN BIT(31)
46 #define __EXEC_OBJECT_HAS_FENCE BIT(30)
47 #define __EXEC_OBJECT_NEEDS_MAP BIT(29)
48 #define __EXEC_OBJECT_NEEDS_BIAS BIT(28)
49 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */
50 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
52 #define __EXEC_HAS_RELOC BIT(31)
53 #define __EXEC_VALIDATED BIT(30)
54 #define UPDATE PIN_OFFSET_FIXED
56 #define BATCH_OFFSET_BIAS (256*1024)
58 #define __I915_EXEC_ILLEGAL_FLAGS \
59 (__I915_EXEC_UNKNOWN_FLAGS | I915_EXEC_CONSTANTS_MASK)
62 * DOC: User command execution
64 * Userspace submits commands to be executed on the GPU as an instruction
65 * stream within a GEM object we call a batchbuffer. This instructions may
66 * refer to other GEM objects containing auxiliary state such as kernels,
67 * samplers, render targets and even secondary batchbuffers. Userspace does
68 * not know where in the GPU memory these objects reside and so before the
69 * batchbuffer is passed to the GPU for execution, those addresses in the
70 * batchbuffer and auxiliary objects are updated. This is known as relocation,
71 * or patching. To try and avoid having to relocate each object on the next
72 * execution, userspace is told the location of those objects in this pass,
73 * but this remains just a hint as the kernel may choose a new location for
74 * any object in the future.
76 * Processing an execbuf ioctl is conceptually split up into a few phases.
78 * 1. Validation - Ensure all the pointers, handles and flags are valid.
79 * 2. Reservation - Assign GPU address space for every object
80 * 3. Relocation - Update any addresses to point to the final locations
81 * 4. Serialisation - Order the request with respect to its dependencies
82 * 5. Construction - Construct a request to execute the batchbuffer
83 * 6. Submission (at some point in the future execution)
85 * Reserving resources for the execbuf is the most complicated phase. We
86 * neither want to have to migrate the object in the address space, nor do
87 * we want to have to update any relocations pointing to this object. Ideally,
88 * we want to leave the object where it is and for all the existing relocations
89 * to match. If the object is given a new address, or if userspace thinks the
90 * object is elsewhere, we have to parse all the relocation entries and update
91 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
92 * all the target addresses in all of its objects match the value in the
93 * relocation entries and that they all match the presumed offsets given by the
94 * list of execbuffer objects. Using this knowledge, we know that if we haven't
95 * moved any buffers, all the relocation entries are valid and we can skip
96 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
97 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
99 * The addresses written in the objects must match the corresponding
100 * reloc.presumed_offset which in turn must match the corresponding
103 * Any render targets written to in the batch must be flagged with
106 * To avoid stalling, execobject.offset should match the current
107 * address of that object within the active context.
109 * The reservation is done is multiple phases. First we try and keep any
110 * object already bound in its current location - so as long as meets the
111 * constraints imposed by the new execbuffer. Any object left unbound after the
112 * first pass is then fitted into any available idle space. If an object does
113 * not fit, all objects are removed from the reservation and the process rerun
114 * after sorting the objects into a priority order (more difficult to fit
115 * objects are tried first). Failing that, the entire VM is cleared and we try
116 * to fit the execbuf once last time before concluding that it simply will not
119 * A small complication to all of this is that we allow userspace not only to
120 * specify an alignment and a size for the object in the address space, but
121 * we also allow userspace to specify the exact offset. This objects are
122 * simpler to place (the location is known a priori) all we have to do is make
123 * sure the space is available.
125 * Once all the objects are in place, patching up the buried pointers to point
126 * to the final locations is a fairly simple job of walking over the relocation
127 * entry arrays, looking up the right address and rewriting the value into
128 * the object. Simple! ... The relocation entries are stored in user memory
129 * and so to access them we have to copy them into a local buffer. That copy
130 * has to avoid taking any pagefaults as they may lead back to a GEM object
131 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
132 * the relocation into multiple passes. First we try to do everything within an
133 * atomic context (avoid the pagefaults) which requires that we never wait. If
134 * we detect that we may wait, or if we need to fault, then we have to fallback
135 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
136 * bells yet?) Dropping the mutex means that we lose all the state we have
137 * built up so far for the execbuf and we must reset any global data. However,
138 * we do leave the objects pinned in their final locations - which is a
139 * potential issue for concurrent execbufs. Once we have left the mutex, we can
140 * allocate and copy all the relocation entries into a large array at our
141 * leisure, reacquire the mutex, reclaim all the objects and other state and
142 * then proceed to update any incorrect addresses with the objects.
144 * As we process the relocation entries, we maintain a record of whether the
145 * object is being written to. Using NORELOC, we expect userspace to provide
146 * this information instead. We also check whether we can skip the relocation
147 * by comparing the expected value inside the relocation entry with the target's
148 * final address. If they differ, we have to map the current object and rewrite
149 * the 4 or 8 byte pointer within.
151 * Serialising an execbuf is quite simple according to the rules of the GEM
152 * ABI. Execution within each context is ordered by the order of submission.
153 * Writes to any GEM object are in order of submission and are exclusive. Reads
154 * from a GEM object are unordered with respect to other reads, but ordered by
155 * writes. A write submitted after a read cannot occur before the read, and
156 * similarly any read submitted after a write cannot occur before the write.
157 * Writes are ordered between engines such that only one write occurs at any
158 * time (completing any reads beforehand) - using semaphores where available
159 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
160 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
161 * reads before starting, and any read (either using set-domain or pread) must
162 * flush all GPU writes before starting. (Note we only employ a barrier before,
163 * we currently rely on userspace not concurrently starting a new execution
164 * whilst reading or writing to an object. This may be an advantage or not
165 * depending on how much you trust userspace not to shoot themselves in the
166 * foot.) Serialisation may just result in the request being inserted into
167 * a DAG awaiting its turn, but most simple is to wait on the CPU until
168 * all dependencies are resolved.
170 * After all of that, is just a matter of closing the request and handing it to
171 * the hardware (well, leaving it in a queue to be executed). However, we also
172 * offer the ability for batchbuffers to be run with elevated privileges so
173 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
174 * Before any batch is given extra privileges we first must check that it
175 * contains no nefarious instructions, we check that each instruction is from
176 * our whitelist and all registers are also from an allowed list. We first
177 * copy the user's batchbuffer to a shadow (so that the user doesn't have
178 * access to it, either by the CPU or GPU as we scan it) and then parse each
179 * instruction. If everything is ok, we set a flag telling the hardware to run
180 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
183 struct i915_execbuffer {
184 struct drm_i915_private *i915; /** i915 backpointer */
185 struct drm_file *file; /** per-file lookup tables and limits */
186 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
187 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
189 struct intel_engine_cs *engine; /** engine to queue the request to */
190 struct i915_gem_context *ctx; /** context for building the request */
191 struct i915_address_space *vm; /** GTT and vma for the request */
193 struct drm_i915_gem_request *request; /** our request to build */
194 struct i915_vma *batch; /** identity of the batch obj/vma */
196 /** actual size of execobj[] as we may extend it for the cmdparser */
197 unsigned int buffer_count;
199 /** list of vma not yet bound during reservation phase */
200 struct list_head unbound;
202 /** list of vma that have execobj.relocation_count */
203 struct list_head relocs;
206 * Track the most recently used object for relocations, as we
207 * frequently have to perform multiple relocations within the same
211 struct drm_mm_node node; /** temporary GTT binding */
212 unsigned long vaddr; /** Current kmap address */
213 unsigned long page; /** Currently mapped page index */
214 bool use_64bit_reloc : 1;
217 bool needs_unfenced : 1;
220 u64 invalid_flags; /** Set of execobj.flags that are invalid */
221 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
223 u32 batch_start_offset; /** Location within object of batch */
224 u32 batch_len; /** Length of batch within object */
225 u32 batch_flags; /** Flags composed for emit_bb_start() */
228 * Indicate either the size of the hastable used to resolve
229 * relocation handles, or if negative that we are using a direct
230 * index into the execobj[].
233 struct hlist_head *buckets; /** ht for relocation handles */
237 * As an alternative to creating a hashtable of handle-to-vma for a batch,
238 * we used the last available reserved field in the execobject[] and stash
239 * a link from the execobj to its vma.
241 #define __exec_to_vma(ee) (ee)->rsvd2
242 #define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee))
245 * Used to convert any address to canonical form.
246 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
247 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
248 * addresses to be in a canonical form:
249 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
250 * canonical form [63:48] == [47]."
252 #define GEN8_HIGH_ADDRESS_BIT 47
253 static inline u64 gen8_canonical_addr(u64 address)
255 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
258 static inline u64 gen8_noncanonical_addr(u64 address)
260 return address & GENMASK_ULL(GEN8_HIGH_ADDRESS_BIT, 0);
263 static int eb_create(struct i915_execbuffer *eb)
265 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
266 unsigned int size = 1 + ilog2(eb->buffer_count);
269 * Without a 1:1 association between relocation handles and
270 * the execobject[] index, we instead create a hashtable.
271 * We size it dynamically based on available memory, starting
272 * first with 1:1 assocative hash and scaling back until
273 * the allocation succeeds.
275 * Later on we use a positive lut_size to indicate we are
276 * using this hashtable, and a negative value to indicate a
280 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
288 if (unlikely(!eb->buckets)) {
289 eb->buckets = kzalloc(sizeof(struct hlist_head),
291 if (unlikely(!eb->buckets))
297 eb->lut_size = -eb->buffer_count;
304 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
305 const struct i915_vma *vma)
307 if (!(entry->flags & __EXEC_OBJECT_HAS_PIN))
310 if (vma->node.size < entry->pad_to_size)
313 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
316 if (entry->flags & EXEC_OBJECT_PINNED &&
317 vma->node.start != entry->offset)
320 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
321 vma->node.start < BATCH_OFFSET_BIAS)
324 if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
325 (vma->node.start + vma->node.size - 1) >> 32)
332 eb_pin_vma(struct i915_execbuffer *eb,
333 struct drm_i915_gem_exec_object2 *entry,
334 struct i915_vma *vma)
338 flags = vma->node.start;
339 flags |= PIN_USER | PIN_NONBLOCK | PIN_OFFSET_FIXED;
340 if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_GTT))
342 if (unlikely(i915_vma_pin(vma, 0, 0, flags)))
345 if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
346 if (unlikely(i915_vma_get_fence(vma))) {
351 if (i915_vma_pin_fence(vma))
352 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
355 entry->flags |= __EXEC_OBJECT_HAS_PIN;
359 __eb_unreserve_vma(struct i915_vma *vma,
360 const struct drm_i915_gem_exec_object2 *entry)
362 GEM_BUG_ON(!(entry->flags & __EXEC_OBJECT_HAS_PIN));
364 if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE))
365 i915_vma_unpin_fence(vma);
367 __i915_vma_unpin(vma);
371 eb_unreserve_vma(struct i915_vma *vma,
372 struct drm_i915_gem_exec_object2 *entry)
374 if (!(entry->flags & __EXEC_OBJECT_HAS_PIN))
377 __eb_unreserve_vma(vma, entry);
378 entry->flags &= ~__EXEC_OBJECT_RESERVED;
382 eb_validate_vma(struct i915_execbuffer *eb,
383 struct drm_i915_gem_exec_object2 *entry,
384 struct i915_vma *vma)
386 if (unlikely(entry->flags & eb->invalid_flags))
389 if (unlikely(entry->alignment && !is_power_of_2(entry->alignment)))
393 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
394 * any non-page-aligned or non-canonical addresses.
396 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
397 entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
400 /* pad_to_size was once a reserved field, so sanitize it */
401 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
402 if (unlikely(offset_in_page(entry->pad_to_size)))
405 entry->pad_to_size = 0;
408 if (unlikely(vma->exec_entry)) {
409 DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n",
410 entry->handle, (int)(entry - eb->exec));
415 * From drm_mm perspective address space is continuous,
416 * so from this point we're always using non-canonical
419 entry->offset = gen8_noncanonical_addr(entry->offset);
425 eb_add_vma(struct i915_execbuffer *eb,
426 struct drm_i915_gem_exec_object2 *entry,
427 struct i915_vma *vma)
431 GEM_BUG_ON(i915_vma_is_closed(vma));
433 if (!(eb->args->flags & __EXEC_VALIDATED)) {
434 err = eb_validate_vma(eb, entry, vma);
439 if (eb->lut_size >= 0) {
440 vma->exec_handle = entry->handle;
441 hlist_add_head(&vma->exec_node,
442 &eb->buckets[hash_32(entry->handle,
446 if (entry->relocation_count)
447 list_add_tail(&vma->reloc_link, &eb->relocs);
449 if (!eb->reloc_cache.has_fence) {
450 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
452 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
453 eb->reloc_cache.needs_unfenced) &&
454 i915_gem_object_is_tiled(vma->obj))
455 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
458 if (!(entry->flags & EXEC_OBJECT_PINNED))
459 entry->flags |= eb->context_flags;
462 * Stash a pointer from the vma to execobj, so we can query its flags,
463 * size, alignment etc as provided by the user. Also we stash a pointer
464 * to the vma inside the execobj so that we can use a direct lookup
465 * to find the right target VMA when doing relocations.
467 vma->exec_entry = entry;
468 __exec_to_vma(entry) = (uintptr_t)i915_vma_get(vma);
472 eb_pin_vma(eb, entry, vma);
473 if (eb_vma_misplaced(entry, vma)) {
474 eb_unreserve_vma(vma, entry);
476 list_add_tail(&vma->exec_link, &eb->unbound);
477 if (drm_mm_node_allocated(&vma->node))
478 err = i915_vma_unbind(vma);
480 if (entry->offset != vma->node.start) {
481 entry->offset = vma->node.start | UPDATE;
482 eb->args->flags |= __EXEC_HAS_RELOC;
488 static inline int use_cpu_reloc(const struct reloc_cache *cache,
489 const struct drm_i915_gem_object *obj)
491 if (!i915_gem_object_has_struct_page(obj))
494 if (DBG_USE_CPU_RELOC)
495 return DBG_USE_CPU_RELOC > 0;
497 return (cache->has_llc ||
499 obj->cache_level != I915_CACHE_NONE);
502 static int eb_reserve_vma(const struct i915_execbuffer *eb,
503 struct i915_vma *vma)
505 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
509 flags = PIN_USER | PIN_NONBLOCK;
510 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
514 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
515 * limit address to the first 4GBs for unflagged objects.
517 if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
518 flags |= PIN_ZONE_4G;
520 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
521 flags |= PIN_MAPPABLE;
523 if (entry->flags & EXEC_OBJECT_PINNED) {
524 flags |= entry->offset | PIN_OFFSET_FIXED;
525 flags &= ~PIN_NONBLOCK; /* force overlapping PINNED checks */
526 } else if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) {
527 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
530 err = i915_vma_pin(vma, entry->pad_to_size, entry->alignment, flags);
534 if (entry->offset != vma->node.start) {
535 entry->offset = vma->node.start | UPDATE;
536 eb->args->flags |= __EXEC_HAS_RELOC;
539 entry->flags |= __EXEC_OBJECT_HAS_PIN;
540 GEM_BUG_ON(eb_vma_misplaced(entry, vma));
542 if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
543 err = i915_vma_get_fence(vma);
549 if (i915_vma_pin_fence(vma))
550 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
556 static int eb_reserve(struct i915_execbuffer *eb)
558 const unsigned int count = eb->buffer_count;
559 struct list_head last;
560 struct i915_vma *vma;
561 unsigned int i, pass;
565 * Attempt to pin all of the buffers into the GTT.
566 * This is done in 3 phases:
568 * 1a. Unbind all objects that do not match the GTT constraints for
569 * the execbuffer (fenceable, mappable, alignment etc).
570 * 1b. Increment pin count for already bound objects.
571 * 2. Bind new objects.
572 * 3. Decrement pin count.
574 * This avoid unnecessary unbinding of later objects in order to make
575 * room for the earlier objects *unless* we need to defragment.
581 list_for_each_entry(vma, &eb->unbound, exec_link) {
582 err = eb_reserve_vma(eb, vma);
589 /* Resort *all* the objects into priority order */
590 INIT_LIST_HEAD(&eb->unbound);
591 INIT_LIST_HEAD(&last);
592 for (i = 0; i < count; i++) {
593 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
595 if (entry->flags & EXEC_OBJECT_PINNED &&
596 entry->flags & __EXEC_OBJECT_HAS_PIN)
599 vma = exec_to_vma(entry);
600 eb_unreserve_vma(vma, entry);
602 if (entry->flags & EXEC_OBJECT_PINNED)
603 list_add(&vma->exec_link, &eb->unbound);
604 else if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
605 list_add_tail(&vma->exec_link, &eb->unbound);
607 list_add_tail(&vma->exec_link, &last);
609 list_splice_tail(&last, &eb->unbound);
616 /* Too fragmented, unbind everything and retry */
617 err = i915_gem_evict_vm(eb->vm);
628 static inline struct hlist_head *
629 ht_head(const struct i915_gem_context_vma_lut *lut, u32 handle)
631 return &lut->ht[hash_32(handle, lut->ht_bits)];
635 ht_needs_resize(const struct i915_gem_context_vma_lut *lut)
637 return (4*lut->ht_count > 3*lut->ht_size ||
638 4*lut->ht_count + 1 < lut->ht_size);
641 static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
643 return eb->buffer_count - 1;
646 static int eb_select_context(struct i915_execbuffer *eb)
648 struct i915_gem_context *ctx;
650 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
651 if (unlikely(IS_ERR(ctx)))
654 if (unlikely(i915_gem_context_is_banned(ctx))) {
655 DRM_DEBUG("Context %u tried to submit while banned\n",
660 eb->ctx = i915_gem_context_get(ctx);
661 eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base;
663 eb->context_flags = 0;
664 if (ctx->flags & CONTEXT_NO_ZEROMAP)
665 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
670 static int eb_lookup_vmas(struct i915_execbuffer *eb)
672 #define INTERMEDIATE BIT(0)
673 const unsigned int count = eb->buffer_count;
674 struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut;
675 struct i915_vma *vma;
681 INIT_LIST_HEAD(&eb->relocs);
682 INIT_LIST_HEAD(&eb->unbound);
684 if (unlikely(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS))
685 flush_work(&lut->resize);
686 GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS);
688 for (i = 0; i < count; i++) {
689 __exec_to_vma(&eb->exec[i]) = 0;
691 hlist_for_each_entry(vma,
692 ht_head(lut, eb->exec[i].handle),
694 if (vma->ctx_handle != eb->exec[i].handle)
697 err = eb_add_vma(eb, &eb->exec[i], vma);
712 spin_lock(&eb->file->table_lock);
714 * Grab a reference to the object and release the lock so we can lookup
715 * or create the VMA without using GFP_ATOMIC
717 idr = &eb->file->object_idr;
718 for (i = slow_pass; i < count; i++) {
719 struct drm_i915_gem_object *obj;
721 if (__exec_to_vma(&eb->exec[i]))
724 obj = to_intel_bo(idr_find(idr, eb->exec[i].handle));
725 if (unlikely(!obj)) {
726 spin_unlock(&eb->file->table_lock);
727 DRM_DEBUG("Invalid object handle %d at index %d\n",
728 eb->exec[i].handle, i);
733 __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj;
735 spin_unlock(&eb->file->table_lock);
737 for (i = slow_pass; i < count; i++) {
738 struct drm_i915_gem_object *obj;
740 if (!(__exec_to_vma(&eb->exec[i]) & INTERMEDIATE))
744 * NOTE: We can leak any vmas created here when something fails
745 * later on. But that's no issue since vma_unbind can deal with
746 * vmas which are not actually bound. And since only
747 * lookup_or_create exists as an interface to get at the vma
748 * from the (obj, vm) we don't run the risk of creating
749 * duplicated vmas for the same vm.
751 obj = u64_to_ptr(typeof(*obj),
752 __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE);
753 vma = i915_vma_instance(obj, eb->vm, NULL);
754 if (unlikely(IS_ERR(vma))) {
755 DRM_DEBUG("Failed to lookup VMA\n");
760 /* First come, first served */
763 vma->ctx_handle = eb->exec[i].handle;
764 hlist_add_head(&vma->ctx_node,
765 ht_head(lut, eb->exec[i].handle));
767 lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS;
768 if (i915_vma_is_ggtt(vma)) {
769 GEM_BUG_ON(obj->vma_hashed);
770 obj->vma_hashed = vma;
774 err = eb_add_vma(eb, &eb->exec[i], vma);
779 if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) {
780 if (ht_needs_resize(lut))
781 queue_work(system_highpri_wq, &lut->resize);
783 lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS;
787 /* take note of the batch buffer before we might reorder the lists */
788 i = eb_batch_index(eb);
789 eb->batch = exec_to_vma(&eb->exec[i]);
792 * SNA is doing fancy tricks with compressing batch buffers, which leads
793 * to negative relocation deltas. Usually that works out ok since the
794 * relocate address is still positive, except when the batch is placed
795 * very low in the GTT. Ensure this doesn't happen.
797 * Note that actual hangs have only been observed on gen7, but for
798 * paranoia do it everywhere.
800 if (!(eb->exec[i].flags & EXEC_OBJECT_PINNED))
801 eb->exec[i].flags |= __EXEC_OBJECT_NEEDS_BIAS;
802 if (eb->reloc_cache.has_fence)
803 eb->exec[i].flags |= EXEC_OBJECT_NEEDS_FENCE;
805 eb->args->flags |= __EXEC_VALIDATED;
806 return eb_reserve(eb);
809 for (i = slow_pass; i < count; i++) {
810 if (__exec_to_vma(&eb->exec[i]) & INTERMEDIATE)
811 __exec_to_vma(&eb->exec[i]) = 0;
813 lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS;
818 static struct i915_vma *
819 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
821 if (eb->lut_size < 0) {
822 if (handle >= -eb->lut_size)
824 return exec_to_vma(&eb->exec[handle]);
826 struct hlist_head *head;
827 struct i915_vma *vma;
829 head = &eb->buckets[hash_32(handle, eb->lut_size)];
830 hlist_for_each_entry(vma, head, exec_node) {
831 if (vma->exec_handle == handle)
838 static void eb_release_vmas(const struct i915_execbuffer *eb)
840 const unsigned int count = eb->buffer_count;
843 for (i = 0; i < count; i++) {
844 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
845 struct i915_vma *vma = exec_to_vma(entry);
850 GEM_BUG_ON(vma->exec_entry != entry);
851 vma->exec_entry = NULL;
853 eb_unreserve_vma(vma, entry);
859 static void eb_reset_vmas(const struct i915_execbuffer *eb)
862 if (eb->lut_size >= 0)
863 memset(eb->buckets, 0,
864 sizeof(struct hlist_head) << eb->lut_size);
867 static void eb_destroy(const struct i915_execbuffer *eb)
869 if (eb->lut_size >= 0)
874 relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
875 const struct i915_vma *target)
877 return gen8_canonical_addr((int)reloc->delta + target->node.start);
880 static void reloc_cache_init(struct reloc_cache *cache,
881 struct drm_i915_private *i915)
885 /* Must be a variable in the struct to allow GCC to unroll. */
886 cache->has_llc = HAS_LLC(i915);
887 cache->has_fence = INTEL_GEN(i915) < 4;
888 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
889 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
890 cache->node.allocated = false;
893 static inline void *unmask_page(unsigned long p)
895 return (void *)(uintptr_t)(p & PAGE_MASK);
898 static inline unsigned int unmask_flags(unsigned long p)
900 return p & ~PAGE_MASK;
903 #define KMAP 0x4 /* after CLFLUSH_FLAGS */
905 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
907 struct drm_i915_private *i915 =
908 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
912 static void reloc_cache_reset(struct reloc_cache *cache)
919 vaddr = unmask_page(cache->vaddr);
920 if (cache->vaddr & KMAP) {
921 if (cache->vaddr & CLFLUSH_AFTER)
924 kunmap_atomic(vaddr);
925 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
928 io_mapping_unmap_atomic((void __iomem *)vaddr);
929 if (cache->node.allocated) {
930 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
932 ggtt->base.clear_range(&ggtt->base,
935 drm_mm_remove_node(&cache->node);
937 i915_vma_unpin((struct i915_vma *)cache->node.mm);
945 static void *reloc_kmap(struct drm_i915_gem_object *obj,
946 struct reloc_cache *cache,
952 kunmap_atomic(unmask_page(cache->vaddr));
954 unsigned int flushes;
957 err = i915_gem_obj_prepare_shmem_write(obj, &flushes);
961 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
962 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
964 cache->vaddr = flushes | KMAP;
965 cache->node.mm = (void *)obj;
970 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
971 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
977 static void *reloc_iomap(struct drm_i915_gem_object *obj,
978 struct reloc_cache *cache,
981 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
982 unsigned long offset;
986 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
988 struct i915_vma *vma;
991 if (use_cpu_reloc(cache, obj))
994 err = i915_gem_object_set_to_gtt_domain(obj, true);
998 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
999 PIN_MAPPABLE | PIN_NONBLOCK);
1001 memset(&cache->node, 0, sizeof(cache->node));
1002 err = drm_mm_insert_node_in_range
1003 (&ggtt->base.mm, &cache->node,
1004 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1005 0, ggtt->mappable_end,
1007 if (err) /* no inactive aperture space, use cpu reloc */
1010 err = i915_vma_put_fence(vma);
1012 i915_vma_unpin(vma);
1013 return ERR_PTR(err);
1016 cache->node.start = vma->node.start;
1017 cache->node.mm = (void *)vma;
1021 offset = cache->node.start;
1022 if (cache->node.allocated) {
1024 ggtt->base.insert_page(&ggtt->base,
1025 i915_gem_object_get_dma_address(obj, page),
1026 offset, I915_CACHE_NONE, 0);
1028 offset += page << PAGE_SHIFT;
1031 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->mappable,
1034 cache->vaddr = (unsigned long)vaddr;
1039 static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1040 struct reloc_cache *cache,
1045 if (cache->page == page) {
1046 vaddr = unmask_page(cache->vaddr);
1049 if ((cache->vaddr & KMAP) == 0)
1050 vaddr = reloc_iomap(obj, cache, page);
1052 vaddr = reloc_kmap(obj, cache, page);
1058 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1060 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1061 if (flushes & CLFLUSH_BEFORE) {
1069 * Writes to the same cacheline are serialised by the CPU
1070 * (including clflush). On the write path, we only require
1071 * that it hits memory in an orderly fashion and place
1072 * mb barriers at the start and end of the relocation phase
1073 * to ensure ordering of clflush wrt to the system.
1075 if (flushes & CLFLUSH_AFTER)
1082 relocate_entry(struct i915_vma *vma,
1083 const struct drm_i915_gem_relocation_entry *reloc,
1084 struct i915_execbuffer *eb,
1085 const struct i915_vma *target)
1087 struct drm_i915_gem_object *obj = vma->obj;
1088 u64 offset = reloc->offset;
1089 u64 target_offset = relocation_target(reloc, target);
1090 bool wide = eb->reloc_cache.use_64bit_reloc;
1094 vaddr = reloc_vaddr(obj, &eb->reloc_cache, offset >> PAGE_SHIFT);
1096 return PTR_ERR(vaddr);
1098 clflush_write32(vaddr + offset_in_page(offset),
1099 lower_32_bits(target_offset),
1100 eb->reloc_cache.vaddr);
1103 offset += sizeof(u32);
1104 target_offset >>= 32;
1109 return target->node.start | UPDATE;
1113 eb_relocate_entry(struct i915_execbuffer *eb,
1114 struct i915_vma *vma,
1115 const struct drm_i915_gem_relocation_entry *reloc)
1117 struct i915_vma *target;
1120 /* we've already hold a reference to all valid objects */
1121 target = eb_get_vma(eb, reloc->target_handle);
1122 if (unlikely(!target))
1125 /* Validate that the target is in a valid r/w GPU domain */
1126 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1127 DRM_DEBUG("reloc with multiple write domains: "
1128 "target %d offset %d "
1129 "read %08x write %08x",
1130 reloc->target_handle,
1131 (int) reloc->offset,
1132 reloc->read_domains,
1133 reloc->write_domain);
1136 if (unlikely((reloc->write_domain | reloc->read_domains)
1137 & ~I915_GEM_GPU_DOMAINS)) {
1138 DRM_DEBUG("reloc with read/write non-GPU domains: "
1139 "target %d offset %d "
1140 "read %08x write %08x",
1141 reloc->target_handle,
1142 (int) reloc->offset,
1143 reloc->read_domains,
1144 reloc->write_domain);
1148 if (reloc->write_domain) {
1149 target->exec_entry->flags |= EXEC_OBJECT_WRITE;
1152 * Sandybridge PPGTT errata: We need a global gtt mapping
1153 * for MI and pipe_control writes because the gpu doesn't
1154 * properly redirect them through the ppgtt for non_secure
1157 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1158 IS_GEN6(eb->i915)) {
1159 err = i915_vma_bind(target, target->obj->cache_level,
1162 "Unexpected failure to bind target VMA!"))
1168 * If the relocation already has the right value in it, no
1169 * more work needs to be done.
1171 if (gen8_canonical_addr(target->node.start) == reloc->presumed_offset)
1174 /* Check that the relocation address is valid... */
1175 if (unlikely(reloc->offset >
1176 vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1177 DRM_DEBUG("Relocation beyond object bounds: "
1178 "target %d offset %d size %d.\n",
1179 reloc->target_handle,
1184 if (unlikely(reloc->offset & 3)) {
1185 DRM_DEBUG("Relocation not 4-byte aligned: "
1186 "target %d offset %d.\n",
1187 reloc->target_handle,
1188 (int)reloc->offset);
1193 * If we write into the object, we need to force the synchronisation
1194 * barrier, either with an asynchronous clflush or if we executed the
1195 * patching using the GPU (though that should be serialised by the
1196 * timeline). To be completely sure, and since we are required to
1197 * do relocations we are already stalling, disable the user's opt
1198 * of our synchronisation.
1200 vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC;
1202 /* and update the user's relocation entry */
1203 return relocate_entry(vma, reloc, eb, target);
1206 static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
1208 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1209 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1210 struct drm_i915_gem_relocation_entry __user *urelocs;
1211 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1212 unsigned int remain;
1214 urelocs = u64_to_user_ptr(entry->relocs_ptr);
1215 remain = entry->relocation_count;
1216 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1220 * We must check that the entire relocation array is safe
1221 * to read. However, if the array is not writable the user loses
1222 * the updated relocation values.
1224 if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(urelocs))))
1228 struct drm_i915_gem_relocation_entry *r = stack;
1229 unsigned int count =
1230 min_t(unsigned int, remain, ARRAY_SIZE(stack));
1231 unsigned int copied;
1234 * This is the fast path and we cannot handle a pagefault
1235 * whilst holding the struct mutex lest the user pass in the
1236 * relocations contained within a mmaped bo. For in such a case
1237 * we, the page fault handler would call i915_gem_fault() and
1238 * we would try to acquire the struct mutex again. Obviously
1239 * this is bad and so lockdep complains vehemently.
1241 pagefault_disable();
1242 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1244 if (unlikely(copied)) {
1251 u64 offset = eb_relocate_entry(eb, vma, r);
1253 if (likely(offset == 0)) {
1254 } else if ((s64)offset < 0) {
1255 remain = (int)offset;
1259 * Note that reporting an error now
1260 * leaves everything in an inconsistent
1261 * state as we have *already* changed
1262 * the relocation value inside the
1263 * object. As we have not changed the
1264 * reloc.presumed_offset or will not
1265 * change the execobject.offset, on the
1266 * call we may not rewrite the value
1267 * inside the object, leaving it
1268 * dangling and causing a GPU hang. Unless
1269 * userspace dynamically rebuilds the
1270 * relocations on each execbuf rather than
1271 * presume a static tree.
1273 * We did previously check if the relocations
1274 * were writable (access_ok), an error now
1275 * would be a strange race with mprotect,
1276 * having already demonstrated that we
1277 * can read from this userspace address.
1279 offset = gen8_canonical_addr(offset & ~UPDATE);
1281 &urelocs[r-stack].presumed_offset);
1283 } while (r++, --count);
1284 urelocs += ARRAY_SIZE(stack);
1287 reloc_cache_reset(&eb->reloc_cache);
1292 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma)
1294 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1295 struct drm_i915_gem_relocation_entry *relocs =
1296 u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1300 for (i = 0; i < entry->relocation_count; i++) {
1301 u64 offset = eb_relocate_entry(eb, vma, &relocs[i]);
1303 if ((s64)offset < 0) {
1310 reloc_cache_reset(&eb->reloc_cache);
1314 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1316 const char __user *addr, *end;
1318 char __maybe_unused c;
1320 size = entry->relocation_count;
1324 if (size > N_RELOC(ULONG_MAX))
1327 addr = u64_to_user_ptr(entry->relocs_ptr);
1328 size *= sizeof(struct drm_i915_gem_relocation_entry);
1329 if (!access_ok(VERIFY_READ, addr, size))
1333 for (; addr < end; addr += PAGE_SIZE) {
1334 int err = __get_user(c, addr);
1338 return __get_user(c, end - 1);
1341 static int eb_copy_relocations(const struct i915_execbuffer *eb)
1343 const unsigned int count = eb->buffer_count;
1347 for (i = 0; i < count; i++) {
1348 const unsigned int nreloc = eb->exec[i].relocation_count;
1349 struct drm_i915_gem_relocation_entry __user *urelocs;
1350 struct drm_i915_gem_relocation_entry *relocs;
1352 unsigned long copied;
1357 err = check_relocations(&eb->exec[i]);
1361 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1362 size = nreloc * sizeof(*relocs);
1364 relocs = kvmalloc_array(size, 1, GFP_TEMPORARY);
1371 /* copy_from_user is limited to < 4GiB */
1375 min_t(u64, BIT_ULL(31), size - copied);
1377 if (__copy_from_user((char *)relocs + copied,
1378 (char *)urelocs + copied,
1386 } while (copied < size);
1389 * As we do not update the known relocation offsets after
1390 * relocating (due to the complexities in lock handling),
1391 * we need to mark them as invalid now so that we force the
1392 * relocation processing next time. Just in case the target
1393 * object is evicted and then rebound into its old
1394 * presumed_offset before the next execbuffer - if that
1395 * happened we would make the mistake of assuming that the
1396 * relocations were valid.
1398 user_access_begin();
1399 for (copied = 0; copied < nreloc; copied++)
1401 &urelocs[copied].presumed_offset,
1406 eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1413 struct drm_i915_gem_relocation_entry *relocs =
1414 u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1415 if (eb->exec[i].relocation_count)
1421 static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1423 const unsigned int count = eb->buffer_count;
1426 if (unlikely(i915.prefault_disable))
1429 for (i = 0; i < count; i++) {
1432 err = check_relocations(&eb->exec[i]);
1440 static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
1442 struct drm_device *dev = &eb->i915->drm;
1443 bool have_copy = false;
1444 struct i915_vma *vma;
1448 if (signal_pending(current)) {
1453 /* We may process another execbuffer during the unlock... */
1455 mutex_unlock(&dev->struct_mutex);
1458 * We take 3 passes through the slowpatch.
1460 * 1 - we try to just prefault all the user relocation entries and
1461 * then attempt to reuse the atomic pagefault disabled fast path again.
1463 * 2 - we copy the user entries to a local buffer here outside of the
1464 * local and allow ourselves to wait upon any rendering before
1467 * 3 - we already have a local copy of the relocation entries, but
1468 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1471 err = eb_prefault_relocations(eb);
1472 } else if (!have_copy) {
1473 err = eb_copy_relocations(eb);
1474 have_copy = err == 0;
1480 mutex_lock(&dev->struct_mutex);
1484 err = i915_mutex_lock_interruptible(dev);
1486 mutex_lock(&dev->struct_mutex);
1490 /* reacquire the objects */
1491 err = eb_lookup_vmas(eb);
1495 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1497 pagefault_disable();
1498 err = eb_relocate_vma(eb, vma);
1503 err = eb_relocate_vma_slow(eb, vma);
1510 * Leave the user relocations as are, this is the painfully slow path,
1511 * and we want to avoid the complication of dropping the lock whilst
1512 * having buffers reserved in the aperture and so causing spurious
1513 * ENOSPC for random operations.
1522 const unsigned int count = eb->buffer_count;
1525 for (i = 0; i < count; i++) {
1526 const struct drm_i915_gem_exec_object2 *entry =
1528 struct drm_i915_gem_relocation_entry *relocs;
1530 if (!entry->relocation_count)
1533 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1538 return err ?: have_copy;
1541 static int eb_relocate(struct i915_execbuffer *eb)
1543 if (eb_lookup_vmas(eb))
1546 /* The objects are in their final locations, apply the relocations. */
1547 if (eb->args->flags & __EXEC_HAS_RELOC) {
1548 struct i915_vma *vma;
1550 list_for_each_entry(vma, &eb->relocs, reloc_link) {
1551 if (eb_relocate_vma(eb, vma))
1559 return eb_relocate_slow(eb);
1562 static void eb_export_fence(struct drm_i915_gem_object *obj,
1563 struct drm_i915_gem_request *req,
1566 struct reservation_object *resv = obj->resv;
1569 * Ignore errors from failing to allocate the new fence, we can't
1570 * handle an error right now. Worst case should be missed
1571 * synchronisation leading to rendering corruption.
1573 reservation_object_lock(resv, NULL);
1574 if (flags & EXEC_OBJECT_WRITE)
1575 reservation_object_add_excl_fence(resv, &req->fence);
1576 else if (reservation_object_reserve_shared(resv) == 0)
1577 reservation_object_add_shared_fence(resv, &req->fence);
1578 reservation_object_unlock(resv);
1581 static int eb_move_to_gpu(struct i915_execbuffer *eb)
1583 const unsigned int count = eb->buffer_count;
1587 for (i = 0; i < count; i++) {
1588 const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
1589 struct i915_vma *vma = exec_to_vma(entry);
1590 struct drm_i915_gem_object *obj = vma->obj;
1592 if (entry->flags & EXEC_OBJECT_CAPTURE) {
1593 struct i915_gem_capture_list *capture;
1595 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1596 if (unlikely(!capture))
1599 capture->next = eb->request->capture_list;
1601 eb->request->capture_list = capture;
1604 if (entry->flags & EXEC_OBJECT_ASYNC)
1607 if (unlikely(obj->cache_dirty && !obj->cache_coherent))
1608 i915_gem_clflush_object(obj, 0);
1610 err = i915_gem_request_await_object
1611 (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE);
1616 i915_vma_move_to_active(vma, eb->request, entry->flags);
1617 __eb_unreserve_vma(vma, entry);
1618 vma->exec_entry = NULL;
1621 for (i = 0; i < count; i++) {
1622 const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
1623 struct i915_vma *vma = exec_to_vma(entry);
1625 eb_export_fence(vma->obj, eb->request, entry->flags);
1630 /* Unconditionally flush any chipset caches (for streaming writes). */
1631 i915_gem_chipset_flush(eb->i915);
1633 /* Unconditionally invalidate GPU caches and TLBs. */
1634 return eb->engine->emit_flush(eb->request, EMIT_INVALIDATE);
1637 static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1639 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1642 /* Kernel clipping was a DRI1 misfeature */
1643 if (exec->num_cliprects || exec->cliprects_ptr)
1646 if (exec->DR4 == 0xffffffff) {
1647 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1650 if (exec->DR1 || exec->DR4)
1653 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1659 void i915_vma_move_to_active(struct i915_vma *vma,
1660 struct drm_i915_gem_request *req,
1663 struct drm_i915_gem_object *obj = vma->obj;
1664 const unsigned int idx = req->engine->id;
1666 lockdep_assert_held(&req->i915->drm.struct_mutex);
1667 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1670 * Add a reference if we're newly entering the active list.
1671 * The order in which we add operations to the retirement queue is
1672 * vital here: mark_active adds to the start of the callback list,
1673 * such that subsequent callbacks are called first. Therefore we
1674 * add the active reference first and queue for it to be dropped
1677 if (!i915_vma_is_active(vma))
1678 obj->active_count++;
1679 i915_vma_set_active(vma, idx);
1680 i915_gem_active_set(&vma->last_read[idx], req);
1681 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1683 obj->base.write_domain = 0;
1684 if (flags & EXEC_OBJECT_WRITE) {
1685 obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
1687 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1688 i915_gem_active_set(&obj->frontbuffer_write, req);
1690 obj->base.read_domains = 0;
1692 obj->base.read_domains |= I915_GEM_GPU_DOMAINS;
1694 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1695 i915_gem_active_set(&vma->last_fence, req);
1698 static int i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1703 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1704 DRM_DEBUG("sol reset is gen7/rcs only\n");
1708 cs = intel_ring_begin(req, 4 * 2 + 2);
1712 *cs++ = MI_LOAD_REGISTER_IMM(4);
1713 for (i = 0; i < 4; i++) {
1714 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1718 intel_ring_advance(req, cs);
1723 static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master)
1725 struct drm_i915_gem_object *shadow_batch_obj;
1726 struct i915_vma *vma;
1729 shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
1730 PAGE_ALIGN(eb->batch_len));
1731 if (IS_ERR(shadow_batch_obj))
1732 return ERR_CAST(shadow_batch_obj);
1734 err = intel_engine_cmd_parser(eb->engine,
1737 eb->batch_start_offset,
1741 if (err == -EACCES) /* unhandled chained batch */
1748 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1753 memset(&eb->exec[eb->buffer_count++],
1754 0, sizeof(*vma->exec_entry));
1755 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1756 __exec_to_vma(vma->exec_entry) = (uintptr_t)i915_vma_get(vma);
1759 i915_gem_object_unpin_pages(shadow_batch_obj);
1764 add_to_client(struct drm_i915_gem_request *req, struct drm_file *file)
1766 req->file_priv = file->driver_priv;
1767 list_add_tail(&req->client_link, &req->file_priv->mm.request_list);
1770 static int eb_submit(struct i915_execbuffer *eb)
1774 err = eb_move_to_gpu(eb);
1778 err = i915_switch_context(eb->request);
1782 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
1783 err = i915_reset_gen7_sol_offsets(eb->request);
1788 err = eb->engine->emit_bb_start(eb->request,
1789 eb->batch->node.start +
1790 eb->batch_start_offset,
1800 * Find one BSD ring to dispatch the corresponding BSD command.
1801 * The engine index is returned.
1804 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1805 struct drm_file *file)
1807 struct drm_i915_file_private *file_priv = file->driver_priv;
1809 /* Check whether the file_priv has already selected one ring. */
1810 if ((int)file_priv->bsd_engine < 0)
1811 file_priv->bsd_engine = atomic_fetch_xor(1,
1812 &dev_priv->mm.bsd_engine_dispatch_index);
1814 return file_priv->bsd_engine;
1817 #define I915_USER_RINGS (4)
1819 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1820 [I915_EXEC_DEFAULT] = RCS,
1821 [I915_EXEC_RENDER] = RCS,
1822 [I915_EXEC_BLT] = BCS,
1823 [I915_EXEC_BSD] = VCS,
1824 [I915_EXEC_VEBOX] = VECS
1827 static struct intel_engine_cs *
1828 eb_select_engine(struct drm_i915_private *dev_priv,
1829 struct drm_file *file,
1830 struct drm_i915_gem_execbuffer2 *args)
1832 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1833 struct intel_engine_cs *engine;
1835 if (user_ring_id > I915_USER_RINGS) {
1836 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1840 if ((user_ring_id != I915_EXEC_BSD) &&
1841 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1842 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1843 "bsd dispatch flags: %d\n", (int)(args->flags));
1847 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1848 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1850 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1851 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1852 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1853 bsd_idx <= I915_EXEC_BSD_RING2) {
1854 bsd_idx >>= I915_EXEC_BSD_SHIFT;
1857 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1862 engine = dev_priv->engine[_VCS(bsd_idx)];
1864 engine = dev_priv->engine[user_ring_map[user_ring_id]];
1868 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1876 i915_gem_do_execbuffer(struct drm_device *dev,
1877 struct drm_file *file,
1878 struct drm_i915_gem_execbuffer2 *args,
1879 struct drm_i915_gem_exec_object2 *exec)
1881 struct i915_execbuffer eb;
1882 struct dma_fence *in_fence = NULL;
1883 struct sync_file *out_fence = NULL;
1884 int out_fence_fd = -1;
1887 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
1888 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1890 eb.i915 = to_i915(dev);
1893 if (!(args->flags & I915_EXEC_NO_RELOC))
1894 args->flags |= __EXEC_HAS_RELOC;
1897 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1898 if (USES_FULL_PPGTT(eb.i915))
1899 eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1900 reloc_cache_init(&eb.reloc_cache, eb.i915);
1902 eb.buffer_count = args->buffer_count;
1903 eb.batch_start_offset = args->batch_start_offset;
1904 eb.batch_len = args->batch_len;
1907 if (args->flags & I915_EXEC_SECURE) {
1908 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1911 eb.batch_flags |= I915_DISPATCH_SECURE;
1913 if (args->flags & I915_EXEC_IS_PINNED)
1914 eb.batch_flags |= I915_DISPATCH_PINNED;
1916 eb.engine = eb_select_engine(eb.i915, file, args);
1920 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1921 if (!HAS_RESOURCE_STREAMER(eb.i915)) {
1922 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1925 if (eb.engine->id != RCS) {
1926 DRM_DEBUG("RS is not available on %s\n",
1931 eb.batch_flags |= I915_DISPATCH_RS;
1934 if (args->flags & I915_EXEC_FENCE_IN) {
1935 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
1940 if (args->flags & I915_EXEC_FENCE_OUT) {
1941 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
1942 if (out_fence_fd < 0) {
1952 * Take a local wakeref for preparing to dispatch the execbuf as
1953 * we expect to access the hardware fairly frequently in the
1954 * process. Upon first dispatch, we acquire another prolonged
1955 * wakeref that we hold until the GPU has been idle for at least
1958 intel_runtime_pm_get(eb.i915);
1959 err = i915_mutex_lock_interruptible(dev);
1963 err = eb_select_context(&eb);
1967 err = eb_relocate(&eb);
1970 * If the user expects the execobject.offset and
1971 * reloc.presumed_offset to be an exact match,
1972 * as for using NO_RELOC, then we cannot update
1973 * the execobject.offset until we have completed
1976 args->flags &= ~__EXEC_HAS_RELOC;
1980 if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) {
1981 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1985 if (eb.batch_start_offset > eb.batch->size ||
1986 eb.batch_len > eb.batch->size - eb.batch_start_offset) {
1987 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1992 if (eb.engine->needs_cmd_parser && eb.batch_len) {
1993 struct i915_vma *vma;
1995 vma = eb_parse(&eb, drm_is_current_master(file));
2003 * Batch parsed and accepted:
2005 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
2006 * bit from MI_BATCH_BUFFER_START commands issued in
2007 * the dispatch_execbuffer implementations. We
2008 * specifically don't want that set on batches the
2009 * command parser has accepted.
2011 eb.batch_flags |= I915_DISPATCH_SECURE;
2012 eb.batch_start_offset = 0;
2017 if (eb.batch_len == 0)
2018 eb.batch_len = eb.batch->size - eb.batch_start_offset;
2021 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2022 * batch" bit. Hence we need to pin secure batches into the global gtt.
2023 * hsw should have this fixed, but bdw mucks it up again. */
2024 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2025 struct i915_vma *vma;
2028 * So on first glance it looks freaky that we pin the batch here
2029 * outside of the reservation loop. But:
2030 * - The batch is already pinned into the relevant ppgtt, so we
2031 * already have the backing storage fully allocated.
2032 * - No other BO uses the global gtt (well contexts, but meh),
2033 * so we don't really have issues with multiple objects not
2034 * fitting due to fragmentation.
2035 * So this is actually safe.
2037 vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0);
2046 /* Allocate a request for this batch buffer nice and early. */
2047 eb.request = i915_gem_request_alloc(eb.engine, eb.ctx);
2048 if (IS_ERR(eb.request)) {
2049 err = PTR_ERR(eb.request);
2050 goto err_batch_unpin;
2054 err = i915_gem_request_await_dma_fence(eb.request, in_fence);
2059 if (out_fence_fd != -1) {
2060 out_fence = sync_file_create(&eb.request->fence);
2068 * Whilst this request exists, batch_obj will be on the
2069 * active_list, and so will hold the active reference. Only when this
2070 * request is retired will the the batch_obj be moved onto the
2071 * inactive_list and lose its active reference. Hence we do not need
2072 * to explicitly hold another reference here.
2074 eb.request->batch = eb.batch;
2076 trace_i915_gem_request_queue(eb.request, eb.batch_flags);
2077 err = eb_submit(&eb);
2079 __i915_add_request(eb.request, err == 0);
2080 add_to_client(eb.request, file);
2084 fd_install(out_fence_fd, out_fence->file);
2085 args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
2086 args->rsvd2 |= (u64)out_fence_fd << 32;
2089 fput(out_fence->file);
2094 if (eb.batch_flags & I915_DISPATCH_SECURE)
2095 i915_vma_unpin(eb.batch);
2098 eb_release_vmas(&eb);
2099 i915_gem_context_put(eb.ctx);
2101 mutex_unlock(&dev->struct_mutex);
2103 intel_runtime_pm_put(eb.i915);
2105 if (out_fence_fd != -1)
2106 put_unused_fd(out_fence_fd);
2108 dma_fence_put(in_fence);
2113 * Legacy execbuffer just creates an exec2 list from the original exec object
2114 * list array and passes it to the real function.
2117 i915_gem_execbuffer(struct drm_device *dev, void *data,
2118 struct drm_file *file)
2120 const size_t sz = sizeof(struct drm_i915_gem_exec_object2);
2121 struct drm_i915_gem_execbuffer *args = data;
2122 struct drm_i915_gem_execbuffer2 exec2;
2123 struct drm_i915_gem_exec_object *exec_list = NULL;
2124 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2128 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2129 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2133 exec2.buffers_ptr = args->buffers_ptr;
2134 exec2.buffer_count = args->buffer_count;
2135 exec2.batch_start_offset = args->batch_start_offset;
2136 exec2.batch_len = args->batch_len;
2137 exec2.DR1 = args->DR1;
2138 exec2.DR4 = args->DR4;
2139 exec2.num_cliprects = args->num_cliprects;
2140 exec2.cliprects_ptr = args->cliprects_ptr;
2141 exec2.flags = I915_EXEC_RENDER;
2142 i915_execbuffer2_set_context_id(exec2, 0);
2144 if (!i915_gem_check_execbuffer(&exec2))
2147 /* Copy in the exec list from userland */
2148 exec_list = kvmalloc_array(args->buffer_count, sizeof(*exec_list),
2149 __GFP_NOWARN | GFP_TEMPORARY);
2150 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2151 __GFP_NOWARN | GFP_TEMPORARY);
2152 if (exec_list == NULL || exec2_list == NULL) {
2153 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2154 args->buffer_count);
2159 err = copy_from_user(exec_list,
2160 u64_to_user_ptr(args->buffers_ptr),
2161 sizeof(*exec_list) * args->buffer_count);
2163 DRM_DEBUG("copy %d exec entries failed %d\n",
2164 args->buffer_count, err);
2170 for (i = 0; i < args->buffer_count; i++) {
2171 exec2_list[i].handle = exec_list[i].handle;
2172 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2173 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2174 exec2_list[i].alignment = exec_list[i].alignment;
2175 exec2_list[i].offset = exec_list[i].offset;
2176 if (INTEL_GEN(to_i915(dev)) < 4)
2177 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2179 exec2_list[i].flags = 0;
2182 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list);
2183 if (exec2.flags & __EXEC_HAS_RELOC) {
2184 struct drm_i915_gem_exec_object __user *user_exec_list =
2185 u64_to_user_ptr(args->buffers_ptr);
2187 /* Copy the new buffer offsets back to the user's exec list. */
2188 for (i = 0; i < args->buffer_count; i++) {
2189 if (!(exec2_list[i].offset & UPDATE))
2192 exec2_list[i].offset =
2193 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2194 exec2_list[i].offset &= PIN_OFFSET_MASK;
2195 if (__copy_to_user(&user_exec_list[i].offset,
2196 &exec2_list[i].offset,
2197 sizeof(user_exec_list[i].offset)))
2208 i915_gem_execbuffer2(struct drm_device *dev, void *data,
2209 struct drm_file *file)
2211 const size_t sz = sizeof(struct drm_i915_gem_exec_object2);
2212 struct drm_i915_gem_execbuffer2 *args = data;
2213 struct drm_i915_gem_exec_object2 *exec2_list;
2216 if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) {
2217 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
2221 if (!i915_gem_check_execbuffer(args))
2224 /* Allocate an extra slot for use by the command parser */
2225 exec2_list = kvmalloc_array(args->buffer_count + 1, sz,
2226 __GFP_NOWARN | GFP_TEMPORARY);
2227 if (exec2_list == NULL) {
2228 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
2229 args->buffer_count);
2232 if (copy_from_user(exec2_list,
2233 u64_to_user_ptr(args->buffers_ptr),
2234 sizeof(*exec2_list) * args->buffer_count)) {
2235 DRM_DEBUG("copy %d exec entries failed\n", args->buffer_count);
2240 err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
2243 * Now that we have begun execution of the batchbuffer, we ignore
2244 * any new error after this point. Also given that we have already
2245 * updated the associated relocations, we try to write out the current
2246 * object locations irrespective of any error.
2248 if (args->flags & __EXEC_HAS_RELOC) {
2249 struct drm_i915_gem_exec_object2 __user *user_exec_list =
2250 u64_to_user_ptr(args->buffers_ptr);
2253 /* Copy the new buffer offsets back to the user's exec list. */
2254 user_access_begin();
2255 for (i = 0; i < args->buffer_count; i++) {
2256 if (!(exec2_list[i].offset & UPDATE))
2259 exec2_list[i].offset =
2260 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2261 unsafe_put_user(exec2_list[i].offset,
2262 &user_exec_list[i].offset,
2269 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;