drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  54 };
  55
  56 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  57         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  58         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  59         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  60         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  61         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  62 };
  63
  64 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  71 };
  72
  73 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  74         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  76         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  77         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are the same */
  83         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  84         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  85         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  86         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  87         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  88         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  89 };
  90
  91 /* IIR can theoretically queue up two events. Be paranoid. */
  92 #define GEN8_IRQ_RESET_NDX(type, which) do { \
  93         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  94         POSTING_READ(GEN8_##type##_IMR(which)); \
  95         I915_WRITE(GEN8_##type##_IER(which), 0); \
  96         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  97         POSTING_READ(GEN8_##type##_IIR(which)); \
  98         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  99         POSTING_READ(GEN8_##type##_IIR(which)); \
 100 } while (0)
 101
 102 #define GEN5_IRQ_RESET(type) do { \
 103         I915_WRITE(type##IMR, 0xffffffff); \
 104         POSTING_READ(type##IMR); \
 105         I915_WRITE(type##IER, 0); \
 106         I915_WRITE(type##IIR, 0xffffffff); \
 107         POSTING_READ(type##IIR); \
 108         I915_WRITE(type##IIR, 0xffffffff); \
 109         POSTING_READ(type##IIR); \
 110 } while (0)
 111
 112 /*
 113  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 114  */
 115 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
 116         u32 val = I915_READ(reg); \
 117         if (val) { \
 118                 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
 119                      (reg), val); \
 120                 I915_WRITE((reg), 0xffffffff); \
 121                 POSTING_READ(reg); \
 122                 I915_WRITE((reg), 0xffffffff); \
 123                 POSTING_READ(reg); \
 124         } \
 125 } while (0)
 126
 127 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 128         GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
 129         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 130         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 131         POSTING_READ(GEN8_##type##_IMR(which)); \
 132 } while (0)
 133
 134 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 135         GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
 136         I915_WRITE(type##IER, (ier_val)); \
 137         I915_WRITE(type##IMR, (imr_val)); \
 138         POSTING_READ(type##IMR); \
 139 } while (0)
 140
 141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 142
 143 /* For display hotplug interrupt */
 144 void
 145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 146 {
 147         assert_spin_locked(&dev_priv->irq_lock);
 148
 149         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 150                 return;
 151
 152         if ((dev_priv->irq_mask & mask) != 0) {
 153                 dev_priv->irq_mask &= ~mask;
 154                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 155                 POSTING_READ(DEIMR);
 156         }
 157 }
 158
 159 void
 160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 161 {
 162         assert_spin_locked(&dev_priv->irq_lock);
 163
 164         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 165                 return;
 166
 167         if ((dev_priv->irq_mask & mask) != mask) {
 168                 dev_priv->irq_mask |= mask;
 169                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 170                 POSTING_READ(DEIMR);
 171         }
 172 }
 173
 174 /**
 175  * ilk_update_gt_irq - update GTIMR
 176  * @dev_priv: driver private
 177  * @interrupt_mask: mask of interrupt bits to update
 178  * @enabled_irq_mask: mask of interrupt bits to enable
 179  */
 180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 181                               uint32_t interrupt_mask,
 182                               uint32_t enabled_irq_mask)
 183 {
 184         assert_spin_locked(&dev_priv->irq_lock);
 185
 186         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 187
 188         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 189                 return;
 190
 191         dev_priv->gt_irq_mask &= ~interrupt_mask;
 192         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 193         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 194         POSTING_READ(GTIMR);
 195 }
 196
 197 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 198 {
 199         ilk_update_gt_irq(dev_priv, mask, mask);
 200 }
 201
 202 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 203 {
 204         ilk_update_gt_irq(dev_priv, mask, 0);
 205 }
 206
 207 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
 208 {
 209         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 210 }
 211
 212 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
 213 {
 214         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 215 }
 216
 217 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
 218 {
 219         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 220 }
 221
 222 /**
 223   * snb_update_pm_irq - update GEN6_PMIMR
 224   * @dev_priv: driver private
 225   * @interrupt_mask: mask of interrupt bits to update
 226   * @enabled_irq_mask: mask of interrupt bits to enable
 227   */
 228 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 229                               uint32_t interrupt_mask,
 230                               uint32_t enabled_irq_mask)
 231 {
 232         uint32_t new_val;
 233
 234         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 235
 236         assert_spin_locked(&dev_priv->irq_lock);
 237
 238         new_val = dev_priv->pm_irq_mask;
 239         new_val &= ~interrupt_mask;
 240         new_val |= (~enabled_irq_mask & interrupt_mask);
 241
 242         if (new_val != dev_priv->pm_irq_mask) {
 243                 dev_priv->pm_irq_mask = new_val;
 244                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 245                 POSTING_READ(gen6_pm_imr(dev_priv));
 246         }
 247 }
 248
 249 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 250 {
 251         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 252                 return;
 253
 254         snb_update_pm_irq(dev_priv, mask, mask);
 255 }
 256
 257 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 258                                   uint32_t mask)
 259 {
 260         snb_update_pm_irq(dev_priv, mask, 0);
 261 }
 262
 263 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 264 {
 265         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 266                 return;
 267
 268         __gen6_disable_pm_irq(dev_priv, mask);
 269 }
 270
 271 void gen6_reset_rps_interrupts(struct drm_device *dev)
 272 {
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         uint32_t reg = gen6_pm_iir(dev_priv);
 275
 276         spin_lock_irq(&dev_priv->irq_lock);
 277         I915_WRITE(reg, dev_priv->pm_rps_events);
 278         I915_WRITE(reg, dev_priv->pm_rps_events);
 279         POSTING_READ(reg);
 280         dev_priv->rps.pm_iir = 0;
 281         spin_unlock_irq(&dev_priv->irq_lock);
 282 }
 283
 284 void gen6_enable_rps_interrupts(struct drm_device *dev)
 285 {
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287
 288         spin_lock_irq(&dev_priv->irq_lock);
 289
 290         WARN_ON(dev_priv->rps.pm_iir);
 291         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 292         dev_priv->rps.interrupts_enabled = true;
 293         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 294                                 dev_priv->pm_rps_events);
 295         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 296
 297         spin_unlock_irq(&dev_priv->irq_lock);
 298 }
 299
 300 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 301 {
 302         /*
 303          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
 304          * if GEN6_PM_UP_EI_EXPIRED is masked.
 305          *
 306          * TODO: verify if this can be reproduced on VLV,CHV.
 307          */
 308         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
 309                 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
 310
 311         if (INTEL_INFO(dev_priv)->gen >= 8)
 312                 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
 313
 314         return mask;
 315 }
 316
 317 void gen6_disable_rps_interrupts(struct drm_device *dev)
 318 {
 319         struct drm_i915_private *dev_priv = dev->dev_private;
 320
 321         spin_lock_irq(&dev_priv->irq_lock);
 322         dev_priv->rps.interrupts_enabled = false;
 323         spin_unlock_irq(&dev_priv->irq_lock);
 324
 325         cancel_work_sync(&dev_priv->rps.work);
 326
 327         spin_lock_irq(&dev_priv->irq_lock);
 328
 329         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 330
 331         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 332         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 333                                 ~dev_priv->pm_rps_events);
 334
 335         spin_unlock_irq(&dev_priv->irq_lock);
 336
 337         synchronize_irq(dev->irq);
 338 }
 339
 340 /**
 341  * ibx_display_interrupt_update - update SDEIMR
 342  * @dev_priv: driver private
 343  * @interrupt_mask: mask of interrupt bits to update
 344  * @enabled_irq_mask: mask of interrupt bits to enable
 345  */
 346 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 347                                   uint32_t interrupt_mask,
 348                                   uint32_t enabled_irq_mask)
 349 {
 350         uint32_t sdeimr = I915_READ(SDEIMR);
 351         sdeimr &= ~interrupt_mask;
 352         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 353
 354         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 355
 356         assert_spin_locked(&dev_priv->irq_lock);
 357
 358         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 359                 return;
 360
 361         I915_WRITE(SDEIMR, sdeimr);
 362         POSTING_READ(SDEIMR);
 363 }
 364
 365 static void
 366 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 367                        u32 enable_mask, u32 status_mask)
 368 {
 369         u32 reg = PIPESTAT(pipe);
 370         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 371
 372         assert_spin_locked(&dev_priv->irq_lock);
 373         WARN_ON(!intel_irqs_enabled(dev_priv));
 374
 375         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 376                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 377                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 378                       pipe_name(pipe), enable_mask, status_mask))
 379                 return;
 380
 381         if ((pipestat & enable_mask) == enable_mask)
 382                 return;
 383
 384         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 385
 386         /* Enable the interrupt, clear any pending status */
 387         pipestat |= enable_mask | status_mask;
 388         I915_WRITE(reg, pipestat);
 389         POSTING_READ(reg);
 390 }
 391
 392 static void
 393 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 394                         u32 enable_mask, u32 status_mask)
 395 {
 396         u32 reg = PIPESTAT(pipe);
 397         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 398
 399         assert_spin_locked(&dev_priv->irq_lock);
 400         WARN_ON(!intel_irqs_enabled(dev_priv));
 401
 402         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 403                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 404                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 405                       pipe_name(pipe), enable_mask, status_mask))
 406                 return;
 407
 408         if ((pipestat & enable_mask) == 0)
 409                 return;
 410
 411         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 412
 413         pipestat &= ~enable_mask;
 414         I915_WRITE(reg, pipestat);
 415         POSTING_READ(reg);
 416 }
 417
 418 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 419 {
 420         u32 enable_mask = status_mask << 16;
 421
 422         /*
 423          * On pipe A we don't support the PSR interrupt yet,
 424          * on pipe B and C the same bit MBZ.
 425          */
 426         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 427                 return 0;
 428         /*
 429          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 430          * A the same bit is for perf counters which we don't use either.
 431          */
 432         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 433                 return 0;
 434
 435         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 436                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 437                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 438         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 439                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 440         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 441                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 442
 443         return enable_mask;
 444 }
 445
 446 void
 447 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 448                      u32 status_mask)
 449 {
 450         u32 enable_mask;
 451
 452         if (IS_VALLEYVIEW(dev_priv->dev))
 453                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 454                                                            status_mask);
 455         else
 456                 enable_mask = status_mask << 16;
 457         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 458 }
 459
 460 void
 461 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 462                       u32 status_mask)
 463 {
 464         u32 enable_mask;
 465
 466         if (IS_VALLEYVIEW(dev_priv->dev))
 467                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 468                                                            status_mask);
 469         else
 470                 enable_mask = status_mask << 16;
 471         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 472 }
 473
 474 /**
 475  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 476  */
 477 static void i915_enable_asle_pipestat(struct drm_device *dev)
 478 {
 479         struct drm_i915_private *dev_priv = dev->dev_private;
 480
 481         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 482                 return;
 483
 484         spin_lock_irq(&dev_priv->irq_lock);
 485
 486         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 487         if (INTEL_INFO(dev)->gen >= 4)
 488                 i915_enable_pipestat(dev_priv, PIPE_A,
 489                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 490
 491         spin_unlock_irq(&dev_priv->irq_lock);
 492 }
 493
 494 /*
 495  * This timing diagram depicts the video signal in and
 496  * around the vertical blanking period.
 497  *
 498  * Assumptions about the fictitious mode used in this example:
 499  *  vblank_start >= 3
 500  *  vsync_start = vblank_start + 1
 501  *  vsync_end = vblank_start + 2
 502  *  vtotal = vblank_start + 3
 503  *
 504  *           start of vblank:
 505  *           latch double buffered registers
 506  *           increment frame counter (ctg+)
 507  *           generate start of vblank interrupt (gen4+)
 508  *           |
 509  *           |          frame start:
 510  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 511  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 512  *           |          |
 513  *           |          |  start of vsync:
 514  *           |          |  generate vsync interrupt
 515  *           |          |  |
 516  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 517  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 518  * ----va---> <-----------------vb--------------------> <--------va-------------
 519  *       |          |       <----vs----->                     |
 520  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 521  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 522  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 523  *       |          |                                         |
 524  *       last visible pixel                                   first visible pixel
 525  *                  |                                         increment frame counter (gen3/4)
 526  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 527  *
 528  * x  = horizontal active
 529  * _  = horizontal blanking
 530  * hs = horizontal sync
 531  * va = vertical active
 532  * vb = vertical blanking
 533  * vs = vertical sync
 534  * vbs = vblank_start (number)
 535  *
 536  * Summary:
 537  * - most events happen at the start of horizontal sync
 538  * - frame start happens at the start of horizontal blank, 1-4 lines
 539  *   (depending on PIPECONF settings) after the start of vblank
 540  * - gen3/4 pixel and frame counter are synchronized with the start
 541  *   of horizontal active on the first line of vertical active
 542  */
 543
 544 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 545 {
 546         /* Gen2 doesn't have a hardware frame counter */
 547         return 0;
 548 }
 549
 550 /* Called from drm generic code, passed a 'crtc', which
 551  * we use as a pipe index
 552  */
 553 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 554 {
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         unsigned long high_frame;
 557         unsigned long low_frame;
 558         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 559         struct intel_crtc *intel_crtc =
 560                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 561         const struct drm_display_mode *mode =
 562                 &intel_crtc->config->base.adjusted_mode;
 563
 564         htotal = mode->crtc_htotal;
 565         hsync_start = mode->crtc_hsync_start;
 566         vbl_start = mode->crtc_vblank_start;
 567         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 568                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 569
 570         /* Convert to pixel count */
 571         vbl_start *= htotal;
 572
 573         /* Start of vblank event occurs at start of hsync */
 574         vbl_start -= htotal - hsync_start;
 575
 576         high_frame = PIPEFRAME(pipe);
 577         low_frame = PIPEFRAMEPIXEL(pipe);
 578
 579         /*
 580          * High & low register fields aren't synchronized, so make sure
 581          * we get a low value that's stable across two reads of the high
 582          * register.
 583          */
 584         do {
 585                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 586                 low   = I915_READ(low_frame);
 587                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 588         } while (high1 != high2);
 589
 590         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 591         pixel = low & PIPE_PIXEL_MASK;
 592         low >>= PIPE_FRAME_LOW_SHIFT;
 593
 594         /*
 595          * The frame counter increments at beginning of active.
 596          * Cook up a vblank counter by also checking the pixel
 597          * counter against vblank start.
 598          */
 599         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 600 }
 601
 602 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 603 {
 604         struct drm_i915_private *dev_priv = dev->dev_private;
 605         int reg = PIPE_FRMCOUNT_GM45(pipe);
 606
 607         return I915_READ(reg);
 608 }
 609
 610 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 611 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 612
 613 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 614 {
 615         struct drm_device *dev = crtc->base.dev;
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617         const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
 618         enum pipe pipe = crtc->pipe;
 619         int position, vtotal;
 620
 621         vtotal = mode->crtc_vtotal;
 622         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 623                 vtotal /= 2;
 624
 625         if (IS_GEN2(dev))
 626                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 627         else
 628                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 629
 630         /*
 631          * See update_scanline_offset() for the details on the
 632          * scanline_offset adjustment.
 633          */
 634         return (position + crtc->scanline_offset) % vtotal;
 635 }
 636
 637 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 638                                     unsigned int flags, int *vpos, int *hpos,
 639                                     ktime_t *stime, ktime_t *etime)
 640 {
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 644         const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
 645         int position;
 646         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 647         bool in_vbl = true;
 648         int ret = 0;
 649         unsigned long irqflags;
 650
 651         if (!intel_crtc->active) {
 652                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 653                                  "pipe %c\n", pipe_name(pipe));
 654                 return 0;
 655         }
 656
 657         htotal = mode->crtc_htotal;
 658         hsync_start = mode->crtc_hsync_start;
 659         vtotal = mode->crtc_vtotal;
 660         vbl_start = mode->crtc_vblank_start;
 661         vbl_end = mode->crtc_vblank_end;
 662
 663         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 664                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 665                 vbl_end /= 2;
 666                 vtotal /= 2;
 667         }
 668
 669         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 670
 671         /*
 672          * Lock uncore.lock, as we will do multiple timing critical raw
 673          * register reads, potentially with preemption disabled, so the
 674          * following code must not block on uncore.lock.
 675          */
 676         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 677
 678         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 679
 680         /* Get optional system timestamp before query. */
 681         if (stime)
 682                 *stime = ktime_get();
 683
 684         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 685                 /* No obvious pixelcount register. Only query vertical
 686                  * scanout position from Display scan line register.
 687                  */
 688                 position = __intel_get_crtc_scanline(intel_crtc);
 689         } else {
 690                 /* Have access to pixelcount since start of frame.
 691                  * We can split this into vertical and horizontal
 692                  * scanout position.
 693                  */
 694                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 695
 696                 /* convert to pixel counts */
 697                 vbl_start *= htotal;
 698                 vbl_end *= htotal;
 699                 vtotal *= htotal;
 700
 701                 /*
 702                  * In interlaced modes, the pixel counter counts all pixels,
 703                  * so one field will have htotal more pixels. In order to avoid
 704                  * the reported position from jumping backwards when the pixel
 705                  * counter is beyond the length of the shorter field, just
 706                  * clamp the position the length of the shorter field. This
 707                  * matches how the scanline counter based position works since
 708                  * the scanline counter doesn't count the two half lines.
 709                  */
 710                 if (position >= vtotal)
 711                         position = vtotal - 1;
 712
 713                 /*
 714                  * Start of vblank interrupt is triggered at start of hsync,
 715                  * just prior to the first active line of vblank. However we
 716                  * consider lines to start at the leading edge of horizontal
 717                  * active. So, should we get here before we've crossed into
 718                  * the horizontal active of the first line in vblank, we would
 719                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 720                  * always add htotal-hsync_start to the current pixel position.
 721                  */
 722                 position = (position + htotal - hsync_start) % vtotal;
 723         }
 724
 725         /* Get optional system timestamp after query. */
 726         if (etime)
 727                 *etime = ktime_get();
 728
 729         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 730
 731         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 732
 733         in_vbl = position >= vbl_start && position < vbl_end;
 734
 735         /*
 736          * While in vblank, position will be negative
 737          * counting up towards 0 at vbl_end. And outside
 738          * vblank, position will be positive counting
 739          * up since vbl_end.
 740          */
 741         if (position >= vbl_start)
 742                 position -= vbl_end;
 743         else
 744                 position += vtotal - vbl_end;
 745
 746         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 747                 *vpos = position;
 748                 *hpos = 0;
 749         } else {
 750                 *vpos = position / htotal;
 751                 *hpos = position - (*vpos * htotal);
 752         }
 753
 754         /* In vblank? */
 755         if (in_vbl)
 756                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 757
 758         return ret;
 759 }
 760
 761 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 762 {
 763         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 764         unsigned long irqflags;
 765         int position;
 766
 767         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 768         position = __intel_get_crtc_scanline(crtc);
 769         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 770
 771         return position;
 772 }
 773
 774 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 775                               int *max_error,
 776                               struct timeval *vblank_time,
 777                               unsigned flags)
 778 {
 779         struct drm_crtc *crtc;
 780
 781         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 782                 DRM_ERROR("Invalid crtc %d\n", pipe);
 783                 return -EINVAL;
 784         }
 785
 786         /* Get drm_crtc to timestamp: */
 787         crtc = intel_get_crtc_for_pipe(dev, pipe);
 788         if (crtc == NULL) {
 789                 DRM_ERROR("Invalid crtc %d\n", pipe);
 790                 return -EINVAL;
 791         }
 792
 793         if (!crtc->state->enable) {
 794                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 795                 return -EBUSY;
 796         }
 797
 798         /* Helper routine in DRM core does all the work: */
 799         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 800                                                      vblank_time, flags,
 801                                                      crtc,
 802                                                      &to_intel_crtc(crtc)->config->base.adjusted_mode);
 803 }
 804
 805 static bool intel_hpd_irq_event(struct drm_device *dev,
 806                                 struct drm_connector *connector)
 807 {
 808         enum drm_connector_status old_status;
 809
 810         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 811         old_status = connector->status;
 812
 813         connector->status = connector->funcs->detect(connector, false);
 814         if (old_status == connector->status)
 815                 return false;
 816
 817         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 818                       connector->base.id,
 819                       connector->name,
 820                       drm_get_connector_status_name(old_status),
 821                       drm_get_connector_status_name(connector->status));
 822
 823         return true;
 824 }
 825
 826 static void i915_digport_work_func(struct work_struct *work)
 827 {
 828         struct drm_i915_private *dev_priv =
 829                 container_of(work, struct drm_i915_private, dig_port_work);
 830         u32 long_port_mask, short_port_mask;
 831         struct intel_digital_port *intel_dig_port;
 832         int i;
 833         u32 old_bits = 0;
 834
 835         spin_lock_irq(&dev_priv->irq_lock);
 836         long_port_mask = dev_priv->long_hpd_port_mask;
 837         dev_priv->long_hpd_port_mask = 0;
 838         short_port_mask = dev_priv->short_hpd_port_mask;
 839         dev_priv->short_hpd_port_mask = 0;
 840         spin_unlock_irq(&dev_priv->irq_lock);
 841
 842         for (i = 0; i < I915_MAX_PORTS; i++) {
 843                 bool valid = false;
 844                 bool long_hpd = false;
 845                 intel_dig_port = dev_priv->hpd_irq_port[i];
 846                 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
 847                         continue;
 848
 849                 if (long_port_mask & (1 << i))  {
 850                         valid = true;
 851                         long_hpd = true;
 852                 } else if (short_port_mask & (1 << i))
 853                         valid = true;
 854
 855                 if (valid) {
 856                         enum irqreturn ret;
 857
 858                         ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
 859                         if (ret == IRQ_NONE) {
 860                                 /* fall back to old school hpd */
 861                                 old_bits |= (1 << intel_dig_port->base.hpd_pin);
 862                         }
 863                 }
 864         }
 865
 866         if (old_bits) {
 867                 spin_lock_irq(&dev_priv->irq_lock);
 868                 dev_priv->hpd_event_bits |= old_bits;
 869                 spin_unlock_irq(&dev_priv->irq_lock);
 870                 schedule_work(&dev_priv->hotplug_work);
 871         }
 872 }
 873
 874 /*
 875  * Handle hotplug events outside the interrupt handler proper.
 876  */
 877 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 878
 879 static void i915_hotplug_work_func(struct work_struct *work)
 880 {
 881         struct drm_i915_private *dev_priv =
 882                 container_of(work, struct drm_i915_private, hotplug_work);
 883         struct drm_device *dev = dev_priv->dev;
 884         struct drm_mode_config *mode_config = &dev->mode_config;
 885         struct intel_connector *intel_connector;
 886         struct intel_encoder *intel_encoder;
 887         struct drm_connector *connector;
 888         bool hpd_disabled = false;
 889         bool changed = false;
 890         u32 hpd_event_bits;
 891
 892         mutex_lock(&mode_config->mutex);
 893         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 894
 895         spin_lock_irq(&dev_priv->irq_lock);
 896
 897         hpd_event_bits = dev_priv->hpd_event_bits;
 898         dev_priv->hpd_event_bits = 0;
 899         list_for_each_entry(connector, &mode_config->connector_list, head) {
 900                 intel_connector = to_intel_connector(connector);
 901                 if (!intel_connector->encoder)
 902                         continue;
 903                 intel_encoder = intel_connector->encoder;
 904                 if (intel_encoder->hpd_pin > HPD_NONE &&
 905                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 906                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 907                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 908                                  "switching from hotplug detection to polling\n",
 909                                 connector->name);
 910                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 911                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 912                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 913                         hpd_disabled = true;
 914                 }
 915                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 916                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 917                                       connector->name, intel_encoder->hpd_pin);
 918                 }
 919         }
 920          /* if there were no outputs to poll, poll was disabled,
 921           * therefore make sure it's enabled when disabling HPD on
 922           * some connectors */
 923         if (hpd_disabled) {
 924                 drm_kms_helper_poll_enable(dev);
 925                 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
 926                                  msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 927         }
 928
 929         spin_unlock_irq(&dev_priv->irq_lock);
 930
 931         list_for_each_entry(connector, &mode_config->connector_list, head) {
 932                 intel_connector = to_intel_connector(connector);
 933                 if (!intel_connector->encoder)
 934                         continue;
 935                 intel_encoder = intel_connector->encoder;
 936                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 937                         if (intel_encoder->hot_plug)
 938                                 intel_encoder->hot_plug(intel_encoder);
 939                         if (intel_hpd_irq_event(dev, connector))
 940                                 changed = true;
 941                 }
 942         }
 943         mutex_unlock(&mode_config->mutex);
 944
 945         if (changed)
 946                 drm_kms_helper_hotplug_event(dev);
 947 }
 948
 949 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 busy_up, busy_down, max_avg, min_avg;
 953         u8 new_delay;
 954
 955         spin_lock(&mchdev_lock);
 956
 957         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 958
 959         new_delay = dev_priv->ips.cur_delay;
 960
 961         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 962         busy_up = I915_READ(RCPREVBSYTUPAVG);
 963         busy_down = I915_READ(RCPREVBSYTDNAVG);
 964         max_avg = I915_READ(RCBMAXAVG);
 965         min_avg = I915_READ(RCBMINAVG);
 966
 967         /* Handle RCS change request from hw */
 968         if (busy_up > max_avg) {
 969                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 970                         new_delay = dev_priv->ips.cur_delay - 1;
 971                 if (new_delay < dev_priv->ips.max_delay)
 972                         new_delay = dev_priv->ips.max_delay;
 973         } else if (busy_down < min_avg) {
 974                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 975                         new_delay = dev_priv->ips.cur_delay + 1;
 976                 if (new_delay > dev_priv->ips.min_delay)
 977                         new_delay = dev_priv->ips.min_delay;
 978         }
 979
 980         if (ironlake_set_drps(dev, new_delay))
 981                 dev_priv->ips.cur_delay = new_delay;
 982
 983         spin_unlock(&mchdev_lock);
 984
 985         return;
 986 }
 987
 988 static void notify_ring(struct intel_engine_cs *ring)
 989 {
 990         if (!intel_ring_initialized(ring))
 991                 return;
 992
 993         trace_i915_gem_request_notify(ring);
 994
 995         wake_up_all(&ring->irq_queue);
 996 }
 997
 998 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 999                         struct intel_rps_ei *ei)
1000 {
1001         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1002         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1003         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1004 }
1005
1006 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1007                          const struct intel_rps_ei *old,
1008                          const struct intel_rps_ei *now,
1009                          int threshold)
1010 {
1011         u64 time, c0;
1012
1013         if (old->cz_clock == 0)
1014                 return false;
1015
1016         time = now->cz_clock - old->cz_clock;
1017         time *= threshold * dev_priv->mem_freq;
1018
1019         /* Workload can be split between render + media, e.g. SwapBuffers
1020          * being blitted in X after being rendered in mesa. To account for
1021          * this we need to combine both engines into our activity counter.
1022          */
1023         c0 = now->render_c0 - old->render_c0;
1024         c0 += now->media_c0 - old->media_c0;
1025         c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
1026
1027         return c0 >= time;
1028 }
1029
1030 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1031 {
1032         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1033         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1034 }
1035
1036 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1037 {
1038         struct intel_rps_ei now;
1039         u32 events = 0;
1040
1041         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1042                 return 0;
1043
1044         vlv_c0_read(dev_priv, &now);
1045         if (now.cz_clock == 0)
1046                 return 0;
1047
1048         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1049                 if (!vlv_c0_above(dev_priv,
1050                                   &dev_priv->rps.down_ei, &now,
1051                                   dev_priv->rps.down_threshold))
1052                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1053                 dev_priv->rps.down_ei = now;
1054         }
1055
1056         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1057                 if (vlv_c0_above(dev_priv,
1058                                  &dev_priv->rps.up_ei, &now,
1059                                  dev_priv->rps.up_threshold))
1060                         events |= GEN6_PM_RP_UP_THRESHOLD;
1061                 dev_priv->rps.up_ei = now;
1062         }
1063
1064         return events;
1065 }
1066
1067 static void gen6_pm_rps_work(struct work_struct *work)
1068 {
1069         struct drm_i915_private *dev_priv =
1070                 container_of(work, struct drm_i915_private, rps.work);
1071         u32 pm_iir;
1072         int new_delay, adj;
1073
1074         spin_lock_irq(&dev_priv->irq_lock);
1075         /* Speed up work cancelation during disabling rps interrupts. */
1076         if (!dev_priv->rps.interrupts_enabled) {
1077                 spin_unlock_irq(&dev_priv->irq_lock);
1078                 return;
1079         }
1080         pm_iir = dev_priv->rps.pm_iir;
1081         dev_priv->rps.pm_iir = 0;
1082         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1083         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1084         spin_unlock_irq(&dev_priv->irq_lock);
1085
1086         /* Make sure we didn't queue anything we're not going to process. */
1087         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1088
1089         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1090                 return;
1091
1092         mutex_lock(&dev_priv->rps.hw_lock);
1093
1094         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1095
1096         adj = dev_priv->rps.last_adj;
1097         new_delay = dev_priv->rps.cur_freq;
1098         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1099                 if (adj > 0)
1100                         adj *= 2;
1101                 else /* CHV needs even encode values */
1102                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1103                 /*
1104                  * For better performance, jump directly
1105                  * to RPe if we're below it.
1106                  */
1107                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1108                         new_delay = dev_priv->rps.efficient_freq;
1109                         adj = 0;
1110                 }
1111         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1112                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1113                         new_delay = dev_priv->rps.efficient_freq;
1114                 else
1115                         new_delay = dev_priv->rps.min_freq_softlimit;
1116                 adj = 0;
1117         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1118                 if (adj < 0)
1119                         adj *= 2;
1120                 else /* CHV needs even encode values */
1121                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1122         } else { /* unknown event */
1123                 adj = 0;
1124         }
1125
1126         dev_priv->rps.last_adj = adj;
1127
1128         /* sysfs frequency interfaces may have snuck in while servicing the
1129          * interrupt
1130          */
1131         new_delay += adj;
1132         new_delay = clamp_t(int, new_delay,
1133                             dev_priv->rps.min_freq_softlimit,
1134                             dev_priv->rps.max_freq_softlimit);
1135
1136         intel_set_rps(dev_priv->dev, new_delay);
1137
1138         mutex_unlock(&dev_priv->rps.hw_lock);
1139 }
1140
1141
1142 /**
1143  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1144  * occurred.
1145  * @work: workqueue struct
1146  *
1147  * Doesn't actually do anything except notify userspace. As a consequence of
1148  * this event, userspace should try to remap the bad rows since statistically
1149  * it is likely the same row is more likely to go bad again.
1150  */
1151 static void ivybridge_parity_work(struct work_struct *work)
1152 {
1153         struct drm_i915_private *dev_priv =
1154                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1155         u32 error_status, row, bank, subbank;
1156         char *parity_event[6];
1157         uint32_t misccpctl;
1158         uint8_t slice = 0;
1159
1160         /* We must turn off DOP level clock gating to access the L3 registers.
1161          * In order to prevent a get/put style interface, acquire struct mutex
1162          * any time we access those registers.
1163          */
1164         mutex_lock(&dev_priv->dev->struct_mutex);
1165
1166         /* If we've screwed up tracking, just let the interrupt fire again */
1167         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1168                 goto out;
1169
1170         misccpctl = I915_READ(GEN7_MISCCPCTL);
1171         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1172         POSTING_READ(GEN7_MISCCPCTL);
1173
1174         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1175                 u32 reg;
1176
1177                 slice--;
1178                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1179                         break;
1180
1181                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1182
1183                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1184
1185                 error_status = I915_READ(reg);
1186                 row = GEN7_PARITY_ERROR_ROW(error_status);
1187                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1188                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1189
1190                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1191                 POSTING_READ(reg);
1192
1193                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1194                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1195                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1196                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1197                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1198                 parity_event[5] = NULL;
1199
1200                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1201                                    KOBJ_CHANGE, parity_event);
1202
1203                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1204                           slice, row, bank, subbank);
1205
1206                 kfree(parity_event[4]);
1207                 kfree(parity_event[3]);
1208                 kfree(parity_event[2]);
1209                 kfree(parity_event[1]);
1210         }
1211
1212         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1213
1214 out:
1215         WARN_ON(dev_priv->l3_parity.which_slice);
1216         spin_lock_irq(&dev_priv->irq_lock);
1217         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1218         spin_unlock_irq(&dev_priv->irq_lock);
1219
1220         mutex_unlock(&dev_priv->dev->struct_mutex);
1221 }
1222
1223 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1224 {
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226
1227         if (!HAS_L3_DPF(dev))
1228                 return;
1229
1230         spin_lock(&dev_priv->irq_lock);
1231         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1232         spin_unlock(&dev_priv->irq_lock);
1233
1234         iir &= GT_PARITY_ERROR(dev);
1235         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1236                 dev_priv->l3_parity.which_slice |= 1 << 1;
1237
1238         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1239                 dev_priv->l3_parity.which_slice |= 1 << 0;
1240
1241         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1242 }
1243
1244 static void ilk_gt_irq_handler(struct drm_device *dev,
1245                                struct drm_i915_private *dev_priv,
1246                                u32 gt_iir)
1247 {
1248         if (gt_iir &
1249             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1250                 notify_ring(&dev_priv->ring[RCS]);
1251         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1252                 notify_ring(&dev_priv->ring[VCS]);
1253 }
1254
1255 static void snb_gt_irq_handler(struct drm_device *dev,
1256                                struct drm_i915_private *dev_priv,
1257                                u32 gt_iir)
1258 {
1259
1260         if (gt_iir &
1261             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1262                 notify_ring(&dev_priv->ring[RCS]);
1263         if (gt_iir & GT_BSD_USER_INTERRUPT)
1264                 notify_ring(&dev_priv->ring[VCS]);
1265         if (gt_iir & GT_BLT_USER_INTERRUPT)
1266                 notify_ring(&dev_priv->ring[BCS]);
1267
1268         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1269                       GT_BSD_CS_ERROR_INTERRUPT |
1270                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1271                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1272
1273         if (gt_iir & GT_PARITY_ERROR(dev))
1274                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1275 }
1276
1277 static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1278                                        u32 master_ctl)
1279 {
1280         irqreturn_t ret = IRQ_NONE;
1281
1282         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1283                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
1284                 if (tmp) {
1285                         I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
1286                         ret = IRQ_HANDLED;
1287
1288                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1289                                 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1290                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1291                                 notify_ring(&dev_priv->ring[RCS]);
1292
1293                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1294                                 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1295                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1296                                 notify_ring(&dev_priv->ring[BCS]);
1297                 } else
1298                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1299         }
1300
1301         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1302                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
1303                 if (tmp) {
1304                         I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
1305                         ret = IRQ_HANDLED;
1306
1307                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1308                                 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1309                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1310                                 notify_ring(&dev_priv->ring[VCS]);
1311
1312                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1313                                 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1314                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1315                                 notify_ring(&dev_priv->ring[VCS2]);
1316                 } else
1317                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1318         }
1319
1320         if (master_ctl & GEN8_GT_VECS_IRQ) {
1321                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1322                 if (tmp) {
1323                         I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1324                         ret = IRQ_HANDLED;
1325
1326                         if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1327                                 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1328                         if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1329                                 notify_ring(&dev_priv->ring[VECS]);
1330                 } else
1331                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1332         }
1333
1334         if (master_ctl & GEN8_GT_PM_IRQ) {
1335                 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
1336                 if (tmp & dev_priv->pm_rps_events) {
1337                         I915_WRITE_FW(GEN8_GT_IIR(2),
1338                                       tmp & dev_priv->pm_rps_events);
1339                         ret = IRQ_HANDLED;
1340                         gen6_rps_irq_handler(dev_priv, tmp);
1341                 } else
1342                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1343         }
1344
1345         return ret;
1346 }
1347
1348 #define HPD_STORM_DETECT_PERIOD 1000
1349 #define HPD_STORM_THRESHOLD 5
1350
1351 static int pch_port_to_hotplug_shift(enum port port)
1352 {
1353         switch (port) {
1354         case PORT_A:
1355         case PORT_E:
1356         default:
1357                 return -1;
1358         case PORT_B:
1359                 return 0;
1360         case PORT_C:
1361                 return 8;
1362         case PORT_D:
1363                 return 16;
1364         }
1365 }
1366
1367 static int i915_port_to_hotplug_shift(enum port port)
1368 {
1369         switch (port) {
1370         case PORT_A:
1371         case PORT_E:
1372         default:
1373                 return -1;
1374         case PORT_B:
1375                 return 17;
1376         case PORT_C:
1377                 return 19;
1378         case PORT_D:
1379                 return 21;
1380         }
1381 }
1382
1383 static inline enum port get_port_from_pin(enum hpd_pin pin)
1384 {
1385         switch (pin) {
1386         case HPD_PORT_B:
1387                 return PORT_B;
1388         case HPD_PORT_C:
1389                 return PORT_C;
1390         case HPD_PORT_D:
1391                 return PORT_D;
1392         default:
1393                 return PORT_A; /* no hpd */
1394         }
1395 }
1396
1397 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1398                                          u32 hotplug_trigger,
1399                                          u32 dig_hotplug_reg,
1400                                          const u32 hpd[HPD_NUM_PINS])
1401 {
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         int i;
1404         enum port port;
1405         bool storm_detected = false;
1406         bool queue_dig = false, queue_hp = false;
1407         u32 dig_shift;
1408         u32 dig_port_mask = 0;
1409
1410         if (!hotplug_trigger)
1411                 return;
1412
1413         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1414                          hotplug_trigger, dig_hotplug_reg);
1415
1416         spin_lock(&dev_priv->irq_lock);
1417         for (i = 1; i < HPD_NUM_PINS; i++) {
1418                 if (!(hpd[i] & hotplug_trigger))
1419                         continue;
1420
1421                 port = get_port_from_pin(i);
1422                 if (port && dev_priv->hpd_irq_port[port]) {
1423                         bool long_hpd;
1424
1425                         if (HAS_PCH_SPLIT(dev)) {
1426                                 dig_shift = pch_port_to_hotplug_shift(port);
1427                                 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1428                         } else {
1429                                 dig_shift = i915_port_to_hotplug_shift(port);
1430                                 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1431                         }
1432
1433                         DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1434                                          port_name(port),
1435                                          long_hpd ? "long" : "short");
1436                         /* for long HPD pulses we want to have the digital queue happen,
1437                            but we still want HPD storm detection to function. */
1438                         if (long_hpd) {
1439                                 dev_priv->long_hpd_port_mask |= (1 << port);
1440                                 dig_port_mask |= hpd[i];
1441                         } else {
1442                                 /* for short HPD just trigger the digital queue */
1443                                 dev_priv->short_hpd_port_mask |= (1 << port);
1444                                 hotplug_trigger &= ~hpd[i];
1445                         }
1446                         queue_dig = true;
1447                 }
1448         }
1449
1450         for (i = 1; i < HPD_NUM_PINS; i++) {
1451                 if (hpd[i] & hotplug_trigger &&
1452                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1453                         /*
1454                          * On GMCH platforms the interrupt mask bits only
1455                          * prevent irq generation, not the setting of the
1456                          * hotplug bits itself. So only WARN about unexpected
1457                          * interrupts on saner platforms.
1458                          */
1459                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1460                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1461                                   hotplug_trigger, i, hpd[i]);
1462
1463                         continue;
1464                 }
1465
1466                 if (!(hpd[i] & hotplug_trigger) ||
1467                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1468                         continue;
1469
1470                 if (!(dig_port_mask & hpd[i])) {
1471                         dev_priv->hpd_event_bits |= (1 << i);
1472                         queue_hp = true;
1473                 }
1474
1475                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1476                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1477                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1478                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1479                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1480                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1481                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1482                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1483                         dev_priv->hpd_event_bits &= ~(1 << i);
1484                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1485                         storm_detected = true;
1486                 } else {
1487                         dev_priv->hpd_stats[i].hpd_cnt++;
1488                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1489                                       dev_priv->hpd_stats[i].hpd_cnt);
1490                 }
1491         }
1492
1493         if (storm_detected)
1494                 dev_priv->display.hpd_irq_setup(dev);
1495         spin_unlock(&dev_priv->irq_lock);
1496
1497         /*
1498          * Our hotplug handler can grab modeset locks (by calling down into the
1499          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1500          * queue for otherwise the flush_work in the pageflip code will
1501          * deadlock.
1502          */
1503         if (queue_dig)
1504                 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1505         if (queue_hp)
1506                 schedule_work(&dev_priv->hotplug_work);
1507 }
1508
1509 static void gmbus_irq_handler(struct drm_device *dev)
1510 {
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512
1513         wake_up_all(&dev_priv->gmbus_wait_queue);
1514 }
1515
1516 static void dp_aux_irq_handler(struct drm_device *dev)
1517 {
1518         struct drm_i915_private *dev_priv = dev->dev_private;
1519
1520         wake_up_all(&dev_priv->gmbus_wait_queue);
1521 }
1522
1523 #if defined(CONFIG_DEBUG_FS)
1524 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1525                                          uint32_t crc0, uint32_t crc1,
1526                                          uint32_t crc2, uint32_t crc3,
1527                                          uint32_t crc4)
1528 {
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1531         struct intel_pipe_crc_entry *entry;
1532         int head, tail;
1533
1534         spin_lock(&pipe_crc->lock);
1535
1536         if (!pipe_crc->entries) {
1537                 spin_unlock(&pipe_crc->lock);
1538                 DRM_DEBUG_KMS("spurious interrupt\n");
1539                 return;
1540         }
1541
1542         head = pipe_crc->head;
1543         tail = pipe_crc->tail;
1544
1545         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1546                 spin_unlock(&pipe_crc->lock);
1547                 DRM_ERROR("CRC buffer overflowing\n");
1548                 return;
1549         }
1550
1551         entry = &pipe_crc->entries[head];
1552
1553         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1554         entry->crc[0] = crc0;
1555         entry->crc[1] = crc1;
1556         entry->crc[2] = crc2;
1557         entry->crc[3] = crc3;
1558         entry->crc[4] = crc4;
1559
1560         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1561         pipe_crc->head = head;
1562
1563         spin_unlock(&pipe_crc->lock);
1564
1565         wake_up_interruptible(&pipe_crc->wq);
1566 }
1567 #else
1568 static inline void
1569 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1570                              uint32_t crc0, uint32_t crc1,
1571                              uint32_t crc2, uint32_t crc3,
1572                              uint32_t crc4) {}
1573 #endif
1574
1575
1576 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1577 {
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579
1580         display_pipe_crc_irq_handler(dev, pipe,
1581                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1582                                      0, 0, 0, 0);
1583 }
1584
1585 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589         display_pipe_crc_irq_handler(dev, pipe,
1590                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1591                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1592                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1593                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1594                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1595 }
1596
1597 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1598 {
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         uint32_t res1, res2;
1601
1602         if (INTEL_INFO(dev)->gen >= 3)
1603                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1604         else
1605                 res1 = 0;
1606
1607         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1608                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1609         else
1610                 res2 = 0;
1611
1612         display_pipe_crc_irq_handler(dev, pipe,
1613                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1614                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1615                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1616                                      res1, res2);
1617 }
1618
1619 /* The RPS events need forcewake, so we add them to a work queue and mask their
1620  * IMR bits until the work is done. Other interrupts can be processed without
1621  * the work queue. */
1622 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1623 {
1624         if (pm_iir & dev_priv->pm_rps_events) {
1625                 spin_lock(&dev_priv->irq_lock);
1626                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1627                 if (dev_priv->rps.interrupts_enabled) {
1628                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1629                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1630                 }
1631                 spin_unlock(&dev_priv->irq_lock);
1632         }
1633
1634         if (INTEL_INFO(dev_priv)->gen >= 8)
1635                 return;
1636
1637         if (HAS_VEBOX(dev_priv->dev)) {
1638                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1639                         notify_ring(&dev_priv->ring[VECS]);
1640
1641                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1642                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1643         }
1644 }
1645
1646 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1647 {
1648         if (!drm_handle_vblank(dev, pipe))
1649                 return false;
1650
1651         return true;
1652 }
1653
1654 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1655 {
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         u32 pipe_stats[I915_MAX_PIPES] = { };
1658         int pipe;
1659
1660         spin_lock(&dev_priv->irq_lock);
1661         for_each_pipe(dev_priv, pipe) {
1662                 int reg;
1663                 u32 mask, iir_bit = 0;
1664
1665                 /*
1666                  * PIPESTAT bits get signalled even when the interrupt is
1667                  * disabled with the mask bits, and some of the status bits do
1668                  * not generate interrupts at all (like the underrun bit). Hence
1669                  * we need to be careful that we only handle what we want to
1670                  * handle.
1671                  */
1672
1673                 /* fifo underruns are filterered in the underrun handler. */
1674                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1675
1676                 switch (pipe) {
1677                 case PIPE_A:
1678                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1679                         break;
1680                 case PIPE_B:
1681                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1682                         break;
1683                 case PIPE_C:
1684                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1685                         break;
1686                 }
1687                 if (iir & iir_bit)
1688                         mask |= dev_priv->pipestat_irq_mask[pipe];
1689
1690                 if (!mask)
1691                         continue;
1692
1693                 reg = PIPESTAT(pipe);
1694                 mask |= PIPESTAT_INT_ENABLE_MASK;
1695                 pipe_stats[pipe] = I915_READ(reg) & mask;
1696
1697                 /*
1698                  * Clear the PIPE*STAT regs before the IIR
1699                  */
1700                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1701                                         PIPESTAT_INT_STATUS_MASK))
1702                         I915_WRITE(reg, pipe_stats[pipe]);
1703         }
1704         spin_unlock(&dev_priv->irq_lock);
1705
1706         for_each_pipe(dev_priv, pipe) {
1707                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1708                     intel_pipe_handle_vblank(dev, pipe))
1709                         intel_check_page_flip(dev, pipe);
1710
1711                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1712                         intel_prepare_page_flip(dev, pipe);
1713                         intel_finish_page_flip(dev, pipe);
1714                 }
1715
1716                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1717                         i9xx_pipe_crc_irq_handler(dev, pipe);
1718
1719                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1720                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1721         }
1722
1723         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1724                 gmbus_irq_handler(dev);
1725 }
1726
1727 static void i9xx_hpd_irq_handler(struct drm_device *dev)
1728 {
1729         struct drm_i915_private *dev_priv = dev->dev_private;
1730         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1731
1732         if (hotplug_status) {
1733                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1734                 /*
1735                  * Make sure hotplug status is cleared before we clear IIR, or else we
1736                  * may miss hotplug events.
1737                  */
1738                 POSTING_READ(PORT_HOTPLUG_STAT);
1739
1740                 if (IS_G4X(dev)) {
1741                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1742
1743                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1744                 } else {
1745                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1746
1747                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
1748                 }
1749
1750                 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1751                     hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1752                         dp_aux_irq_handler(dev);
1753         }
1754 }
1755
1756 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1757 {
1758         struct drm_device *dev = arg;
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         u32 iir, gt_iir, pm_iir;
1761         irqreturn_t ret = IRQ_NONE;
1762
1763         if (!intel_irqs_enabled(dev_priv))
1764                 return IRQ_NONE;
1765
1766         while (true) {
1767                 /* Find, clear, then process each source of interrupt */
1768
1769                 gt_iir = I915_READ(GTIIR);
1770                 if (gt_iir)
1771                         I915_WRITE(GTIIR, gt_iir);
1772
1773                 pm_iir = I915_READ(GEN6_PMIIR);
1774                 if (pm_iir)
1775                         I915_WRITE(GEN6_PMIIR, pm_iir);
1776
1777                 iir = I915_READ(VLV_IIR);
1778                 if (iir) {
1779                         /* Consume port before clearing IIR or we'll miss events */
1780                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1781                                 i9xx_hpd_irq_handler(dev);
1782                         I915_WRITE(VLV_IIR, iir);
1783                 }
1784
1785                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1786                         goto out;
1787
1788                 ret = IRQ_HANDLED;
1789
1790                 if (gt_iir)
1791                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1792                 if (pm_iir)
1793                         gen6_rps_irq_handler(dev_priv, pm_iir);
1794                 /* Call regardless, as some status bits might not be
1795                  * signalled in iir */
1796                 valleyview_pipestat_irq_handler(dev, iir);
1797         }
1798
1799 out:
1800         return ret;
1801 }
1802
1803 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1804 {
1805         struct drm_device *dev = arg;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         u32 master_ctl, iir;
1808         irqreturn_t ret = IRQ_NONE;
1809
1810         if (!intel_irqs_enabled(dev_priv))
1811                 return IRQ_NONE;
1812
1813         for (;;) {
1814                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1815                 iir = I915_READ(VLV_IIR);
1816
1817                 if (master_ctl == 0 && iir == 0)
1818                         break;
1819
1820                 ret = IRQ_HANDLED;
1821
1822                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1823
1824                 /* Find, clear, then process each source of interrupt */
1825
1826                 if (iir) {
1827                         /* Consume port before clearing IIR or we'll miss events */
1828                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
1829                                 i9xx_hpd_irq_handler(dev);
1830                         I915_WRITE(VLV_IIR, iir);
1831                 }
1832
1833                 gen8_gt_irq_handler(dev_priv, master_ctl);
1834
1835                 /* Call regardless, as some status bits might not be
1836                  * signalled in iir */
1837                 valleyview_pipestat_irq_handler(dev, iir);
1838
1839                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1840                 POSTING_READ(GEN8_MASTER_IRQ);
1841         }
1842
1843         return ret;
1844 }
1845
1846 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1847 {
1848         struct drm_i915_private *dev_priv = dev->dev_private;
1849         int pipe;
1850         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1851         u32 dig_hotplug_reg;
1852
1853         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1854         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1855
1856         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
1857
1858         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1859                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1860                                SDE_AUDIO_POWER_SHIFT);
1861                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1862                                  port_name(port));
1863         }
1864
1865         if (pch_iir & SDE_AUX_MASK)
1866                 dp_aux_irq_handler(dev);
1867
1868         if (pch_iir & SDE_GMBUS)
1869                 gmbus_irq_handler(dev);
1870
1871         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1872                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1873
1874         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1875                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1876
1877         if (pch_iir & SDE_POISON)
1878                 DRM_ERROR("PCH poison interrupt\n");
1879
1880         if (pch_iir & SDE_FDI_MASK)
1881                 for_each_pipe(dev_priv, pipe)
1882                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1883                                          pipe_name(pipe),
1884                                          I915_READ(FDI_RX_IIR(pipe)));
1885
1886         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1887                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1888
1889         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1890                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1891
1892         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1893                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1894
1895         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1896                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1897 }
1898
1899 static void ivb_err_int_handler(struct drm_device *dev)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         u32 err_int = I915_READ(GEN7_ERR_INT);
1903         enum pipe pipe;
1904
1905         if (err_int & ERR_INT_POISON)
1906                 DRM_ERROR("Poison interrupt\n");
1907
1908         for_each_pipe(dev_priv, pipe) {
1909                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1910                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1911
1912                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1913                         if (IS_IVYBRIDGE(dev))
1914                                 ivb_pipe_crc_irq_handler(dev, pipe);
1915                         else
1916                                 hsw_pipe_crc_irq_handler(dev, pipe);
1917                 }
1918         }
1919
1920         I915_WRITE(GEN7_ERR_INT, err_int);
1921 }
1922
1923 static void cpt_serr_int_handler(struct drm_device *dev)
1924 {
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         u32 serr_int = I915_READ(SERR_INT);
1927
1928         if (serr_int & SERR_INT_POISON)
1929                 DRM_ERROR("PCH poison interrupt\n");
1930
1931         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1932                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1933
1934         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1935                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1936
1937         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1938                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
1939
1940         I915_WRITE(SERR_INT, serr_int);
1941 }
1942
1943 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         int pipe;
1947         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1948         u32 dig_hotplug_reg;
1949
1950         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1951         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1952
1953         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
1954
1955         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1956                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1957                                SDE_AUDIO_POWER_SHIFT_CPT);
1958                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1959                                  port_name(port));
1960         }
1961
1962         if (pch_iir & SDE_AUX_MASK_CPT)
1963                 dp_aux_irq_handler(dev);
1964
1965         if (pch_iir & SDE_GMBUS_CPT)
1966                 gmbus_irq_handler(dev);
1967
1968         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1969                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1970
1971         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1972                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1973
1974         if (pch_iir & SDE_FDI_MASK_CPT)
1975                 for_each_pipe(dev_priv, pipe)
1976                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1977                                          pipe_name(pipe),
1978                                          I915_READ(FDI_RX_IIR(pipe)));
1979
1980         if (pch_iir & SDE_ERROR_CPT)
1981                 cpt_serr_int_handler(dev);
1982 }
1983
1984 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         enum pipe pipe;
1988
1989         if (de_iir & DE_AUX_CHANNEL_A)
1990                 dp_aux_irq_handler(dev);
1991
1992         if (de_iir & DE_GSE)
1993                 intel_opregion_asle_intr(dev);
1994
1995         if (de_iir & DE_POISON)
1996                 DRM_ERROR("Poison interrupt\n");
1997
1998         for_each_pipe(dev_priv, pipe) {
1999                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2000                     intel_pipe_handle_vblank(dev, pipe))
2001                         intel_check_page_flip(dev, pipe);
2002
2003                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2004                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2005
2006                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2007                         i9xx_pipe_crc_irq_handler(dev, pipe);
2008
2009                 /* plane/pipes map 1:1 on ilk+ */
2010                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2011                         intel_prepare_page_flip(dev, pipe);
2012                         intel_finish_page_flip_plane(dev, pipe);
2013                 }
2014         }
2015
2016         /* check event from PCH */
2017         if (de_iir & DE_PCH_EVENT) {
2018                 u32 pch_iir = I915_READ(SDEIIR);
2019
2020                 if (HAS_PCH_CPT(dev))
2021                         cpt_irq_handler(dev, pch_iir);
2022                 else
2023                         ibx_irq_handler(dev, pch_iir);
2024
2025                 /* should clear PCH hotplug event before clear CPU irq */
2026                 I915_WRITE(SDEIIR, pch_iir);
2027         }
2028
2029         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2030                 ironlake_rps_change_irq_handler(dev);
2031 }
2032
2033 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2034 {
2035         struct drm_i915_private *dev_priv = dev->dev_private;
2036         enum pipe pipe;
2037
2038         if (de_iir & DE_ERR_INT_IVB)
2039                 ivb_err_int_handler(dev);
2040
2041         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2042                 dp_aux_irq_handler(dev);
2043
2044         if (de_iir & DE_GSE_IVB)
2045                 intel_opregion_asle_intr(dev);
2046
2047         for_each_pipe(dev_priv, pipe) {
2048                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2049                     intel_pipe_handle_vblank(dev, pipe))
2050                         intel_check_page_flip(dev, pipe);
2051
2052                 /* plane/pipes map 1:1 on ilk+ */
2053                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2054                         intel_prepare_page_flip(dev, pipe);
2055                         intel_finish_page_flip_plane(dev, pipe);
2056                 }
2057         }
2058
2059         /* check event from PCH */
2060         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2061                 u32 pch_iir = I915_READ(SDEIIR);
2062
2063                 cpt_irq_handler(dev, pch_iir);
2064
2065                 /* clear PCH hotplug event before clear CPU irq */
2066                 I915_WRITE(SDEIIR, pch_iir);
2067         }
2068 }
2069
2070 /*
2071  * To handle irqs with the minimum potential races with fresh interrupts, we:
2072  * 1 - Disable Master Interrupt Control.
2073  * 2 - Find the source(s) of the interrupt.
2074  * 3 - Clear the Interrupt Identity bits (IIR).
2075  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2076  * 5 - Re-enable Master Interrupt Control.
2077  */
2078 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2079 {
2080         struct drm_device *dev = arg;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2083         irqreturn_t ret = IRQ_NONE;
2084
2085         if (!intel_irqs_enabled(dev_priv))
2086                 return IRQ_NONE;
2087
2088         /* We get interrupts on unclaimed registers, so check for this before we
2089          * do any I915_{READ,WRITE}. */
2090         intel_uncore_check_errors(dev);
2091
2092         /* disable master interrupt before clearing iir  */
2093         de_ier = I915_READ(DEIER);
2094         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2095         POSTING_READ(DEIER);
2096
2097         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2098          * interrupts will will be stored on its back queue, and then we'll be
2099          * able to process them after we restore SDEIER (as soon as we restore
2100          * it, we'll get an interrupt if SDEIIR still has something to process
2101          * due to its back queue). */
2102         if (!HAS_PCH_NOP(dev)) {
2103                 sde_ier = I915_READ(SDEIER);
2104                 I915_WRITE(SDEIER, 0);
2105                 POSTING_READ(SDEIER);
2106         }
2107
2108         /* Find, clear, then process each source of interrupt */
2109
2110         gt_iir = I915_READ(GTIIR);
2111         if (gt_iir) {
2112                 I915_WRITE(GTIIR, gt_iir);
2113                 ret = IRQ_HANDLED;
2114                 if (INTEL_INFO(dev)->gen >= 6)
2115                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2116                 else
2117                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2118         }
2119
2120         de_iir = I915_READ(DEIIR);
2121         if (de_iir) {
2122                 I915_WRITE(DEIIR, de_iir);
2123                 ret = IRQ_HANDLED;
2124                 if (INTEL_INFO(dev)->gen >= 7)
2125                         ivb_display_irq_handler(dev, de_iir);
2126                 else
2127                         ilk_display_irq_handler(dev, de_iir);
2128         }
2129
2130         if (INTEL_INFO(dev)->gen >= 6) {
2131                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2132                 if (pm_iir) {
2133                         I915_WRITE(GEN6_PMIIR, pm_iir);
2134                         ret = IRQ_HANDLED;
2135                         gen6_rps_irq_handler(dev_priv, pm_iir);
2136                 }
2137         }
2138
2139         I915_WRITE(DEIER, de_ier);
2140         POSTING_READ(DEIER);
2141         if (!HAS_PCH_NOP(dev)) {
2142                 I915_WRITE(SDEIER, sde_ier);
2143                 POSTING_READ(SDEIER);
2144         }
2145
2146         return ret;
2147 }
2148
2149 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2150 {
2151         struct drm_device *dev = arg;
2152         struct drm_i915_private *dev_priv = dev->dev_private;
2153         u32 master_ctl;
2154         irqreturn_t ret = IRQ_NONE;
2155         uint32_t tmp = 0;
2156         enum pipe pipe;
2157         u32 aux_mask = GEN8_AUX_CHANNEL_A;
2158
2159         if (!intel_irqs_enabled(dev_priv))
2160                 return IRQ_NONE;
2161
2162         if (IS_GEN9(dev))
2163                 aux_mask |=  GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2164                         GEN9_AUX_CHANNEL_D;
2165
2166         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2167         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2168         if (!master_ctl)
2169                 return IRQ_NONE;
2170
2171         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2172
2173         /* Find, clear, then process each source of interrupt */
2174
2175         ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2176
2177         if (master_ctl & GEN8_DE_MISC_IRQ) {
2178                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2179                 if (tmp) {
2180                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2181                         ret = IRQ_HANDLED;
2182                         if (tmp & GEN8_DE_MISC_GSE)
2183                                 intel_opregion_asle_intr(dev);
2184                         else
2185                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2186                 }
2187                 else
2188                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2189         }
2190
2191         if (master_ctl & GEN8_DE_PORT_IRQ) {
2192                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2193                 if (tmp) {
2194                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2195                         ret = IRQ_HANDLED;
2196
2197                         if (tmp & aux_mask)
2198                                 dp_aux_irq_handler(dev);
2199                         else
2200                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2201                 }
2202                 else
2203                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2204         }
2205
2206         for_each_pipe(dev_priv, pipe) {
2207                 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
2208
2209                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2210                         continue;
2211
2212                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2213                 if (pipe_iir) {
2214                         ret = IRQ_HANDLED;
2215                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2216
2217                         if (pipe_iir & GEN8_PIPE_VBLANK &&
2218                             intel_pipe_handle_vblank(dev, pipe))
2219                                 intel_check_page_flip(dev, pipe);
2220
2221                         if (IS_GEN9(dev))
2222                                 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2223                         else
2224                                 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2225
2226                         if (flip_done) {
2227                                 intel_prepare_page_flip(dev, pipe);
2228                                 intel_finish_page_flip_plane(dev, pipe);
2229                         }
2230
2231                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2232                                 hsw_pipe_crc_irq_handler(dev, pipe);
2233
2234                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2235                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2236                                                                     pipe);
2237
2238
2239                         if (IS_GEN9(dev))
2240                                 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2241                         else
2242                                 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2243
2244                         if (fault_errors)
2245                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2246                                           pipe_name(pipe),
2247                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2248                 } else
2249                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2250         }
2251
2252         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2253                 /*
2254                  * FIXME(BDW): Assume for now that the new interrupt handling
2255                  * scheme also closed the SDE interrupt handling race we've seen
2256                  * on older pch-split platforms. But this needs testing.
2257                  */
2258                 u32 pch_iir = I915_READ(SDEIIR);
2259                 if (pch_iir) {
2260                         I915_WRITE(SDEIIR, pch_iir);
2261                         ret = IRQ_HANDLED;
2262                         cpt_irq_handler(dev, pch_iir);
2263                 } else
2264                         DRM_ERROR("The master control interrupt lied (SDE)!\n");
2265
2266         }
2267
2268         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2269         POSTING_READ_FW(GEN8_MASTER_IRQ);
2270
2271         return ret;
2272 }
2273
2274 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2275                                bool reset_completed)
2276 {
2277         struct intel_engine_cs *ring;
2278         int i;
2279
2280         /*
2281          * Notify all waiters for GPU completion events that reset state has
2282          * been changed, and that they need to restart their wait after
2283          * checking for potential errors (and bail out to drop locks if there is
2284          * a gpu reset pending so that i915_error_work_func can acquire them).
2285          */
2286
2287         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2288         for_each_ring(ring, dev_priv, i)
2289                 wake_up_all(&ring->irq_queue);
2290
2291         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2292         wake_up_all(&dev_priv->pending_flip_queue);
2293
2294         /*
2295          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2296          * reset state is cleared.
2297          */
2298         if (reset_completed)
2299                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2300 }
2301
2302 /**
2303  * i915_reset_and_wakeup - do process context error handling work
2304  *
2305  * Fire an error uevent so userspace can see that a hang or error
2306  * was detected.
2307  */
2308 static void i915_reset_and_wakeup(struct drm_device *dev)
2309 {
2310         struct drm_i915_private *dev_priv = to_i915(dev);
2311         struct i915_gpu_error *error = &dev_priv->gpu_error;
2312         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2313         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2314         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2315         int ret;
2316
2317         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2318
2319         /*
2320          * Note that there's only one work item which does gpu resets, so we
2321          * need not worry about concurrent gpu resets potentially incrementing
2322          * error->reset_counter twice. We only need to take care of another
2323          * racing irq/hangcheck declaring the gpu dead for a second time. A
2324          * quick check for that is good enough: schedule_work ensures the
2325          * correct ordering between hang detection and this work item, and since
2326          * the reset in-progress bit is only ever set by code outside of this
2327          * work we don't need to worry about any other races.
2328          */
2329         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2330                 DRM_DEBUG_DRIVER("resetting chip\n");
2331                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2332                                    reset_event);
2333
2334                 /*
2335                  * In most cases it's guaranteed that we get here with an RPM
2336                  * reference held, for example because there is a pending GPU
2337                  * request that won't finish until the reset is done. This
2338                  * isn't the case at least when we get here by doing a
2339                  * simulated reset via debugs, so get an RPM reference.
2340                  */
2341                 intel_runtime_pm_get(dev_priv);
2342
2343                 intel_prepare_reset(dev);
2344
2345                 /*
2346                  * All state reset _must_ be completed before we update the
2347                  * reset counter, for otherwise waiters might miss the reset
2348                  * pending state and not properly drop locks, resulting in
2349                  * deadlocks with the reset work.
2350                  */
2351                 ret = i915_reset(dev);
2352
2353                 intel_finish_reset(dev);
2354
2355                 intel_runtime_pm_put(dev_priv);
2356
2357                 if (ret == 0) {
2358                         /*
2359                          * After all the gem state is reset, increment the reset
2360                          * counter and wake up everyone waiting for the reset to
2361                          * complete.
2362                          *
2363                          * Since unlock operations are a one-sided barrier only,
2364                          * we need to insert a barrier here to order any seqno
2365                          * updates before
2366                          * the counter increment.
2367                          */
2368                         smp_mb__before_atomic();
2369                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2370
2371                         kobject_uevent_env(&dev->primary->kdev->kobj,
2372                                            KOBJ_CHANGE, reset_done_event);
2373                 } else {
2374                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2375                 }
2376
2377                 /*
2378                  * Note: The wake_up also serves as a memory barrier so that
2379                  * waiters see the update value of the reset counter atomic_t.
2380                  */
2381                 i915_error_wake_up(dev_priv, true);
2382         }
2383 }
2384
2385 static void i915_report_and_clear_eir(struct drm_device *dev)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         uint32_t instdone[I915_NUM_INSTDONE_REG];
2389         u32 eir = I915_READ(EIR);
2390         int pipe, i;
2391
2392         if (!eir)
2393                 return;
2394
2395         pr_err("render error detected, EIR: 0x%08x\n", eir);
2396
2397         i915_get_extra_instdone(dev, instdone);
2398
2399         if (IS_G4X(dev)) {
2400                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2401                         u32 ipeir = I915_READ(IPEIR_I965);
2402
2403                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2404                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2405                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2406                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2407                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2408                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2409                         I915_WRITE(IPEIR_I965, ipeir);
2410                         POSTING_READ(IPEIR_I965);
2411                 }
2412                 if (eir & GM45_ERROR_PAGE_TABLE) {
2413                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2414                         pr_err("page table error\n");
2415                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2416                         I915_WRITE(PGTBL_ER, pgtbl_err);
2417                         POSTING_READ(PGTBL_ER);
2418                 }
2419         }
2420
2421         if (!IS_GEN2(dev)) {
2422                 if (eir & I915_ERROR_PAGE_TABLE) {
2423                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2424                         pr_err("page table error\n");
2425                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2426                         I915_WRITE(PGTBL_ER, pgtbl_err);
2427                         POSTING_READ(PGTBL_ER);
2428                 }
2429         }
2430
2431         if (eir & I915_ERROR_MEMORY_REFRESH) {
2432                 pr_err("memory refresh error:\n");
2433                 for_each_pipe(dev_priv, pipe)
2434                         pr_err("pipe %c stat: 0x%08x\n",
2435                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2436                 /* pipestat has already been acked */
2437         }
2438         if (eir & I915_ERROR_INSTRUCTION) {
2439                 pr_err("instruction error\n");
2440                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2441                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2442                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2443                 if (INTEL_INFO(dev)->gen < 4) {
2444                         u32 ipeir = I915_READ(IPEIR);
2445
2446                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2447                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2448                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2449                         I915_WRITE(IPEIR, ipeir);
2450                         POSTING_READ(IPEIR);
2451                 } else {
2452                         u32 ipeir = I915_READ(IPEIR_I965);
2453
2454                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2455                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2456                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2457                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2458                         I915_WRITE(IPEIR_I965, ipeir);
2459                         POSTING_READ(IPEIR_I965);
2460                 }
2461         }
2462
2463         I915_WRITE(EIR, eir);
2464         POSTING_READ(EIR);
2465         eir = I915_READ(EIR);
2466         if (eir) {
2467                 /*
2468                  * some errors might have become stuck,
2469                  * mask them.
2470                  */
2471                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2472                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2473                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2474         }
2475 }
2476
2477 /**
2478  * i915_handle_error - handle a gpu error
2479  * @dev: drm device
2480  *
2481  * Do some basic checking of regsiter state at error time and
2482  * dump it to the syslog.  Also call i915_capture_error_state() to make
2483  * sure we get a record and make it available in debugfs.  Fire a uevent
2484  * so userspace knows something bad happened (should trigger collection
2485  * of a ring dump etc.).
2486  */
2487 void i915_handle_error(struct drm_device *dev, bool wedged,
2488                        const char *fmt, ...)
2489 {
2490         struct drm_i915_private *dev_priv = dev->dev_private;
2491         va_list args;
2492         char error_msg[80];
2493
2494         va_start(args, fmt);
2495         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2496         va_end(args);
2497
2498         i915_capture_error_state(dev, wedged, error_msg);
2499         i915_report_and_clear_eir(dev);
2500
2501         if (wedged) {
2502                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2503                                 &dev_priv->gpu_error.reset_counter);
2504
2505                 /*
2506                  * Wakeup waiting processes so that the reset function
2507                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2508                  * various locks. By bumping the reset counter first, the woken
2509                  * processes will see a reset in progress and back off,
2510                  * releasing their locks and then wait for the reset completion.
2511                  * We must do this for _all_ gpu waiters that might hold locks
2512                  * that the reset work needs to acquire.
2513                  *
2514                  * Note: The wake_up serves as the required memory barrier to
2515                  * ensure that the waiters see the updated value of the reset
2516                  * counter atomic_t.
2517                  */
2518                 i915_error_wake_up(dev_priv, false);
2519         }
2520
2521         i915_reset_and_wakeup(dev);
2522 }
2523
2524 /* Called from drm generic code, passed 'crtc' which
2525  * we use as a pipe index
2526  */
2527 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2528 {
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         unsigned long irqflags;
2531
2532         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2533         if (INTEL_INFO(dev)->gen >= 4)
2534                 i915_enable_pipestat(dev_priv, pipe,
2535                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2536         else
2537                 i915_enable_pipestat(dev_priv, pipe,
2538                                      PIPE_VBLANK_INTERRUPT_STATUS);
2539         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2540
2541         return 0;
2542 }
2543
2544 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2545 {
2546         struct drm_i915_private *dev_priv = dev->dev_private;
2547         unsigned long irqflags;
2548         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2549                                                      DE_PIPE_VBLANK(pipe);
2550
2551         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2552         ironlake_enable_display_irq(dev_priv, bit);
2553         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2554
2555         return 0;
2556 }
2557
2558 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2559 {
2560         struct drm_i915_private *dev_priv = dev->dev_private;
2561         unsigned long irqflags;
2562
2563         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2564         i915_enable_pipestat(dev_priv, pipe,
2565                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2566         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2567
2568         return 0;
2569 }
2570
2571 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2572 {
2573         struct drm_i915_private *dev_priv = dev->dev_private;
2574         unsigned long irqflags;
2575
2576         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2577         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2578         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2579         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2580         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2581         return 0;
2582 }
2583
2584 /* Called from drm generic code, passed 'crtc' which
2585  * we use as a pipe index
2586  */
2587 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2588 {
2589         struct drm_i915_private *dev_priv = dev->dev_private;
2590         unsigned long irqflags;
2591
2592         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2593         i915_disable_pipestat(dev_priv, pipe,
2594                               PIPE_VBLANK_INTERRUPT_STATUS |
2595                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2596         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2597 }
2598
2599 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2600 {
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602         unsigned long irqflags;
2603         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2604                                                      DE_PIPE_VBLANK(pipe);
2605
2606         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2607         ironlake_disable_display_irq(dev_priv, bit);
2608         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2609 }
2610
2611 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2612 {
2613         struct drm_i915_private *dev_priv = dev->dev_private;
2614         unsigned long irqflags;
2615
2616         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2617         i915_disable_pipestat(dev_priv, pipe,
2618                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2619         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2620 }
2621
2622 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2623 {
2624         struct drm_i915_private *dev_priv = dev->dev_private;
2625         unsigned long irqflags;
2626
2627         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2628         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2629         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2630         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2631         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2632 }
2633
2634 static struct drm_i915_gem_request *
2635 ring_last_request(struct intel_engine_cs *ring)
2636 {
2637         return list_entry(ring->request_list.prev,
2638                           struct drm_i915_gem_request, list);
2639 }
2640
2641 static bool
2642 ring_idle(struct intel_engine_cs *ring)
2643 {
2644         return (list_empty(&ring->request_list) ||
2645                 i915_gem_request_completed(ring_last_request(ring), false));
2646 }
2647
2648 static bool
2649 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2650 {
2651         if (INTEL_INFO(dev)->gen >= 8) {
2652                 return (ipehr >> 23) == 0x1c;
2653         } else {
2654                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2655                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2656                                  MI_SEMAPHORE_REGISTER);
2657         }
2658 }
2659
2660 static struct intel_engine_cs *
2661 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
2662 {
2663         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2664         struct intel_engine_cs *signaller;
2665         int i;
2666
2667         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2668                 for_each_ring(signaller, dev_priv, i) {
2669                         if (ring == signaller)
2670                                 continue;
2671
2672                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
2673                                 return signaller;
2674                 }
2675         } else {
2676                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2677
2678                 for_each_ring(signaller, dev_priv, i) {
2679                         if(ring == signaller)
2680                                 continue;
2681
2682                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
2683                                 return signaller;
2684                 }
2685         }
2686
2687         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2688                   ring->id, ipehr, offset);
2689
2690         return NULL;
2691 }
2692
2693 static struct intel_engine_cs *
2694 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
2695 {
2696         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2697         u32 cmd, ipehr, head;
2698         u64 offset = 0;
2699         int i, backwards;
2700
2701         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2702         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
2703                 return NULL;
2704
2705         /*
2706          * HEAD is likely pointing to the dword after the actual command,
2707          * so scan backwards until we find the MBOX. But limit it to just 3
2708          * or 4 dwords depending on the semaphore wait command size.
2709          * Note that we don't care about ACTHD here since that might
2710          * point at at batch, and semaphores are always emitted into the
2711          * ringbuffer itself.
2712          */
2713         head = I915_READ_HEAD(ring) & HEAD_ADDR;
2714         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
2715
2716         for (i = backwards; i; --i) {
2717                 /*
2718                  * Be paranoid and presume the hw has gone off into the wild -
2719                  * our ring is smaller than what the hardware (and hence
2720                  * HEAD_ADDR) allows. Also handles wrap-around.
2721                  */
2722                 head &= ring->buffer->size - 1;
2723
2724                 /* This here seems to blow up */
2725                 cmd = ioread32(ring->buffer->virtual_start + head);
2726                 if (cmd == ipehr)
2727                         break;
2728
2729                 head -= 4;
2730         }
2731
2732         if (!i)
2733                 return NULL;
2734
2735         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
2736         if (INTEL_INFO(ring->dev)->gen >= 8) {
2737                 offset = ioread32(ring->buffer->virtual_start + head + 12);
2738                 offset <<= 32;
2739                 offset = ioread32(ring->buffer->virtual_start + head + 8);
2740         }
2741         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
2742 }
2743
2744 static int semaphore_passed(struct intel_engine_cs *ring)
2745 {
2746         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2747         struct intel_engine_cs *signaller;
2748         u32 seqno;
2749
2750         ring->hangcheck.deadlock++;
2751
2752         signaller = semaphore_waits_for(ring, &seqno);
2753         if (signaller == NULL)
2754                 return -1;
2755
2756         /* Prevent pathological recursion due to driver bugs */
2757         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
2758                 return -1;
2759
2760         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2761                 return 1;
2762
2763         /* cursory check for an unkickable deadlock */
2764         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2765             semaphore_passed(signaller) < 0)
2766                 return -1;
2767
2768         return 0;
2769 }
2770
2771 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2772 {
2773         struct intel_engine_cs *ring;
2774         int i;
2775
2776         for_each_ring(ring, dev_priv, i)
2777                 ring->hangcheck.deadlock = 0;
2778 }
2779
2780 static enum intel_ring_hangcheck_action
2781 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2782 {
2783         struct drm_device *dev = ring->dev;
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         u32 tmp;
2786
2787         if (acthd != ring->hangcheck.acthd) {
2788                 if (acthd > ring->hangcheck.max_acthd) {
2789                         ring->hangcheck.max_acthd = acthd;
2790                         return HANGCHECK_ACTIVE;
2791                 }
2792
2793                 return HANGCHECK_ACTIVE_LOOP;
2794         }
2795
2796         if (IS_GEN2(dev))
2797                 return HANGCHECK_HUNG;
2798
2799         /* Is the chip hanging on a WAIT_FOR_EVENT?
2800          * If so we can simply poke the RB_WAIT bit
2801          * and break the hang. This should work on
2802          * all but the second generation chipsets.
2803          */
2804         tmp = I915_READ_CTL(ring);
2805         if (tmp & RING_WAIT) {
2806                 i915_handle_error(dev, false,
2807                                   "Kicking stuck wait on %s",
2808                                   ring->name);
2809                 I915_WRITE_CTL(ring, tmp);
2810                 return HANGCHECK_KICK;
2811         }
2812
2813         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2814                 switch (semaphore_passed(ring)) {
2815                 default:
2816                         return HANGCHECK_HUNG;
2817                 case 1:
2818                         i915_handle_error(dev, false,
2819                                           "Kicking stuck semaphore on %s",
2820                                           ring->name);
2821                         I915_WRITE_CTL(ring, tmp);
2822                         return HANGCHECK_KICK;
2823                 case 0:
2824                         return HANGCHECK_WAIT;
2825                 }
2826         }
2827
2828         return HANGCHECK_HUNG;
2829 }
2830
2831 /*
2832  * This is called when the chip hasn't reported back with completed
2833  * batchbuffers in a long time. We keep track per ring seqno progress and
2834  * if there are no progress, hangcheck score for that ring is increased.
2835  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2836  * we kick the ring. If we see no progress on three subsequent calls
2837  * we assume chip is wedged and try to fix it by resetting the chip.
2838  */
2839 static void i915_hangcheck_elapsed(struct work_struct *work)
2840 {
2841         struct drm_i915_private *dev_priv =
2842                 container_of(work, typeof(*dev_priv),
2843                              gpu_error.hangcheck_work.work);
2844         struct drm_device *dev = dev_priv->dev;
2845         struct intel_engine_cs *ring;
2846         int i;
2847         int busy_count = 0, rings_hung = 0;
2848         bool stuck[I915_NUM_RINGS] = { 0 };
2849 #define BUSY 1
2850 #define KICK 5
2851 #define HUNG 20
2852
2853         if (!i915.enable_hangcheck)
2854                 return;
2855
2856         for_each_ring(ring, dev_priv, i) {
2857                 u64 acthd;
2858                 u32 seqno;
2859                 bool busy = true;
2860
2861                 semaphore_clear_deadlocks(dev_priv);
2862
2863                 seqno = ring->get_seqno(ring, false);
2864                 acthd = intel_ring_get_active_head(ring);
2865
2866                 if (ring->hangcheck.seqno == seqno) {
2867                         if (ring_idle(ring)) {
2868                                 ring->hangcheck.action = HANGCHECK_IDLE;
2869
2870                                 if (waitqueue_active(&ring->irq_queue)) {
2871                                         /* Issue a wake-up to catch stuck h/w. */
2872                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2873                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2874                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2875                                                                   ring->name);
2876                                                 else
2877                                                         DRM_INFO("Fake missed irq on %s\n",
2878                                                                  ring->name);
2879                                                 wake_up_all(&ring->irq_queue);
2880                                         }
2881                                         /* Safeguard against driver failure */
2882                                         ring->hangcheck.score += BUSY;
2883                                 } else
2884                                         busy = false;
2885                         } else {
2886                                 /* We always increment the hangcheck score
2887                                  * if the ring is busy and still processing
2888                                  * the same request, so that no single request
2889                                  * can run indefinitely (such as a chain of
2890                                  * batches). The only time we do not increment
2891                                  * the hangcheck score on this ring, if this
2892                                  * ring is in a legitimate wait for another
2893                                  * ring. In that case the waiting ring is a
2894                                  * victim and we want to be sure we catch the
2895                                  * right culprit. Then every time we do kick
2896                                  * the ring, add a small increment to the
2897                                  * score so that we can catch a batch that is
2898                                  * being repeatedly kicked and so responsible
2899                                  * for stalling the machine.
2900                                  */
2901                                 ring->hangcheck.action = ring_stuck(ring,
2902                                                                     acthd);
2903
2904                                 switch (ring->hangcheck.action) {
2905                                 case HANGCHECK_IDLE:
2906                                 case HANGCHECK_WAIT:
2907                                 case HANGCHECK_ACTIVE:
2908                                         break;
2909                                 case HANGCHECK_ACTIVE_LOOP:
2910                                         ring->hangcheck.score += BUSY;
2911                                         break;
2912                                 case HANGCHECK_KICK:
2913                                         ring->hangcheck.score += KICK;
2914                                         break;
2915                                 case HANGCHECK_HUNG:
2916                                         ring->hangcheck.score += HUNG;
2917                                         stuck[i] = true;
2918                                         break;
2919                                 }
2920                         }
2921                 } else {
2922                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2923
2924                         /* Gradually reduce the count so that we catch DoS
2925                          * attempts across multiple batches.
2926                          */
2927                         if (ring->hangcheck.score > 0)
2928                                 ring->hangcheck.score--;
2929
2930                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
2931                 }
2932
2933                 ring->hangcheck.seqno = seqno;
2934                 ring->hangcheck.acthd = acthd;
2935                 busy_count += busy;
2936         }
2937
2938         for_each_ring(ring, dev_priv, i) {
2939                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2940                         DRM_INFO("%s on %s\n",
2941                                  stuck[i] ? "stuck" : "no progress",
2942                                  ring->name);
2943                         rings_hung++;
2944                 }
2945         }
2946
2947         if (rings_hung)
2948                 return i915_handle_error(dev, true, "Ring hung");
2949
2950         if (busy_count)
2951                 /* Reset timer case chip hangs without another request
2952                  * being added */
2953                 i915_queue_hangcheck(dev);
2954 }
2955
2956 void i915_queue_hangcheck(struct drm_device *dev)
2957 {
2958         struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
2959
2960         if (!i915.enable_hangcheck)
2961                 return;
2962
2963         /* Don't continually defer the hangcheck so that it is always run at
2964          * least once after work has been scheduled on any ring. Otherwise,
2965          * we will ignore a hung ring if a second ring is kept busy.
2966          */
2967
2968         queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
2969                            round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
2970 }
2971
2972 static void ibx_irq_reset(struct drm_device *dev)
2973 {
2974         struct drm_i915_private *dev_priv = dev->dev_private;
2975
2976         if (HAS_PCH_NOP(dev))
2977                 return;
2978
2979         GEN5_IRQ_RESET(SDE);
2980
2981         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2982                 I915_WRITE(SERR_INT, 0xffffffff);
2983 }
2984
2985 /*
2986  * SDEIER is also touched by the interrupt handler to work around missed PCH
2987  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2988  * instead we unconditionally enable all PCH interrupt sources here, but then
2989  * only unmask them as needed with SDEIMR.
2990  *
2991  * This function needs to be called before interrupts are enabled.
2992  */
2993 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2994 {
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996
2997         if (HAS_PCH_NOP(dev))
2998                 return;
2999
3000         WARN_ON(I915_READ(SDEIER) != 0);
3001         I915_WRITE(SDEIER, 0xffffffff);
3002         POSTING_READ(SDEIER);
3003 }
3004
3005 static void gen5_gt_irq_reset(struct drm_device *dev)
3006 {
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008
3009         GEN5_IRQ_RESET(GT);
3010         if (INTEL_INFO(dev)->gen >= 6)
3011                 GEN5_IRQ_RESET(GEN6_PM);
3012 }
3013
3014 /* drm_dma.h hooks
3015 */
3016 static void ironlake_irq_reset(struct drm_device *dev)
3017 {
3018         struct drm_i915_private *dev_priv = dev->dev_private;
3019
3020         I915_WRITE(HWSTAM, 0xffffffff);
3021
3022         GEN5_IRQ_RESET(DE);
3023         if (IS_GEN7(dev))
3024                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3025
3026         gen5_gt_irq_reset(dev);
3027
3028         ibx_irq_reset(dev);
3029 }
3030
3031 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3032 {
3033         enum pipe pipe;
3034
3035         I915_WRITE(PORT_HOTPLUG_EN, 0);
3036         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3037
3038         for_each_pipe(dev_priv, pipe)
3039                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3040
3041         GEN5_IRQ_RESET(VLV_);
3042 }
3043
3044 static void valleyview_irq_preinstall(struct drm_device *dev)
3045 {
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047
3048         /* VLV magic */
3049         I915_WRITE(VLV_IMR, 0);
3050         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3051         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3052         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3053
3054         gen5_gt_irq_reset(dev);
3055
3056         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3057
3058         vlv_display_irq_reset(dev_priv);
3059 }
3060
3061 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3062 {
3063         GEN8_IRQ_RESET_NDX(GT, 0);
3064         GEN8_IRQ_RESET_NDX(GT, 1);
3065         GEN8_IRQ_RESET_NDX(GT, 2);
3066         GEN8_IRQ_RESET_NDX(GT, 3);
3067 }
3068
3069 static void gen8_irq_reset(struct drm_device *dev)
3070 {
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         int pipe;
3073
3074         I915_WRITE(GEN8_MASTER_IRQ, 0);
3075         POSTING_READ(GEN8_MASTER_IRQ);
3076
3077         gen8_gt_irq_reset(dev_priv);
3078
3079         for_each_pipe(dev_priv, pipe)
3080                 if (intel_display_power_is_enabled(dev_priv,
3081                                                    POWER_DOMAIN_PIPE(pipe)))
3082                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3083
3084         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3085         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3086         GEN5_IRQ_RESET(GEN8_PCU_);
3087
3088         ibx_irq_reset(dev);
3089 }
3090
3091 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3092                                      unsigned int pipe_mask)
3093 {
3094         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3095
3096         spin_lock_irq(&dev_priv->irq_lock);
3097         if (pipe_mask & 1 << PIPE_A)
3098                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3099                                   dev_priv->de_irq_mask[PIPE_A],
3100                                   ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
3101         if (pipe_mask & 1 << PIPE_B)
3102                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3103                                   dev_priv->de_irq_mask[PIPE_B],
3104                                   ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3105         if (pipe_mask & 1 << PIPE_C)
3106                 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3107                                   dev_priv->de_irq_mask[PIPE_C],
3108                                   ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
3109         spin_unlock_irq(&dev_priv->irq_lock);
3110 }
3111
3112 static void cherryview_irq_preinstall(struct drm_device *dev)
3113 {
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115
3116         I915_WRITE(GEN8_MASTER_IRQ, 0);
3117         POSTING_READ(GEN8_MASTER_IRQ);
3118
3119         gen8_gt_irq_reset(dev_priv);
3120
3121         GEN5_IRQ_RESET(GEN8_PCU_);
3122
3123         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3124
3125         vlv_display_irq_reset(dev_priv);
3126 }
3127
3128 static void ibx_hpd_irq_setup(struct drm_device *dev)
3129 {
3130         struct drm_i915_private *dev_priv = dev->dev_private;
3131         struct intel_encoder *intel_encoder;
3132         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3133
3134         if (HAS_PCH_IBX(dev)) {
3135                 hotplug_irqs = SDE_HOTPLUG_MASK;
3136                 for_each_intel_encoder(dev, intel_encoder)
3137                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3138                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3139         } else {
3140                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3141                 for_each_intel_encoder(dev, intel_encoder)
3142                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3143                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3144         }
3145
3146         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3147
3148         /*
3149          * Enable digital hotplug on the PCH, and configure the DP short pulse
3150          * duration to 2ms (which is the minimum in the Display Port spec)
3151          *
3152          * This register is the same on all known PCH chips.
3153          */
3154         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3155         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3156         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3157         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3158         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3159         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3160 }
3161
3162 static void ibx_irq_postinstall(struct drm_device *dev)
3163 {
3164         struct drm_i915_private *dev_priv = dev->dev_private;
3165         u32 mask;
3166
3167         if (HAS_PCH_NOP(dev))
3168                 return;
3169
3170         if (HAS_PCH_IBX(dev))
3171                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3172         else
3173                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3174
3175         GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3176         I915_WRITE(SDEIMR, ~mask);
3177 }
3178
3179 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3180 {
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         u32 pm_irqs, gt_irqs;
3183
3184         pm_irqs = gt_irqs = 0;
3185
3186         dev_priv->gt_irq_mask = ~0;
3187         if (HAS_L3_DPF(dev)) {
3188                 /* L3 parity interrupt is always unmasked. */
3189                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3190                 gt_irqs |= GT_PARITY_ERROR(dev);
3191         }
3192
3193         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3194         if (IS_GEN5(dev)) {
3195                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3196                            ILK_BSD_USER_INTERRUPT;
3197         } else {
3198                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3199         }
3200
3201         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3202
3203         if (INTEL_INFO(dev)->gen >= 6) {
3204                 /*
3205                  * RPS interrupts will get enabled/disabled on demand when RPS
3206                  * itself is enabled/disabled.
3207                  */
3208                 if (HAS_VEBOX(dev))
3209                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3210
3211                 dev_priv->pm_irq_mask = 0xffffffff;
3212                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3213         }
3214 }
3215
3216 static int ironlake_irq_postinstall(struct drm_device *dev)
3217 {
3218         struct drm_i915_private *dev_priv = dev->dev_private;
3219         u32 display_mask, extra_mask;
3220
3221         if (INTEL_INFO(dev)->gen >= 7) {
3222                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3223                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3224                                 DE_PLANEB_FLIP_DONE_IVB |
3225                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3226                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3227                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3228         } else {
3229                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3230                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3231                                 DE_AUX_CHANNEL_A |
3232                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3233                                 DE_POISON);
3234                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3235                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3236         }
3237
3238         dev_priv->irq_mask = ~display_mask;
3239
3240         I915_WRITE(HWSTAM, 0xeffe);
3241
3242         ibx_irq_pre_postinstall(dev);
3243
3244         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3245
3246         gen5_gt_irq_postinstall(dev);
3247
3248         ibx_irq_postinstall(dev);
3249
3250         if (IS_IRONLAKE_M(dev)) {
3251                 /* Enable PCU event interrupts
3252                  *
3253                  * spinlocking not required here for correctness since interrupt
3254                  * setup is guaranteed to run in single-threaded context. But we
3255                  * need it to make the assert_spin_locked happy. */
3256                 spin_lock_irq(&dev_priv->irq_lock);
3257                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3258                 spin_unlock_irq(&dev_priv->irq_lock);
3259         }
3260
3261         return 0;
3262 }
3263
3264 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3265 {
3266         u32 pipestat_mask;
3267         u32 iir_mask;
3268         enum pipe pipe;
3269
3270         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3271                         PIPE_FIFO_UNDERRUN_STATUS;
3272
3273         for_each_pipe(dev_priv, pipe)
3274                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3275         POSTING_READ(PIPESTAT(PIPE_A));
3276
3277         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3278                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3279
3280         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3281         for_each_pipe(dev_priv, pipe)
3282                       i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3283
3284         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3285                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3286                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3287         if (IS_CHERRYVIEW(dev_priv))
3288                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3289         dev_priv->irq_mask &= ~iir_mask;
3290
3291         I915_WRITE(VLV_IIR, iir_mask);
3292         I915_WRITE(VLV_IIR, iir_mask);
3293         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3294         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3295         POSTING_READ(VLV_IMR);
3296 }
3297
3298 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3299 {
3300         u32 pipestat_mask;
3301         u32 iir_mask;
3302         enum pipe pipe;
3303
3304         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3305                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3306                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3307         if (IS_CHERRYVIEW(dev_priv))
3308                 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3309
3310         dev_priv->irq_mask |= iir_mask;
3311         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3312         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3313         I915_WRITE(VLV_IIR, iir_mask);
3314         I915_WRITE(VLV_IIR, iir_mask);
3315         POSTING_READ(VLV_IIR);
3316
3317         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3318                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3319
3320         i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3321         for_each_pipe(dev_priv, pipe)
3322                 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
3323
3324         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3325                         PIPE_FIFO_UNDERRUN_STATUS;
3326
3327         for_each_pipe(dev_priv, pipe)
3328                 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
3329         POSTING_READ(PIPESTAT(PIPE_A));
3330 }
3331
3332 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3333 {
3334         assert_spin_locked(&dev_priv->irq_lock);
3335
3336         if (dev_priv->display_irqs_enabled)
3337                 return;
3338
3339         dev_priv->display_irqs_enabled = true;
3340
3341         if (intel_irqs_enabled(dev_priv))
3342                 valleyview_display_irqs_install(dev_priv);
3343 }
3344
3345 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3346 {
3347         assert_spin_locked(&dev_priv->irq_lock);
3348
3349         if (!dev_priv->display_irqs_enabled)
3350                 return;
3351
3352         dev_priv->display_irqs_enabled = false;
3353
3354         if (intel_irqs_enabled(dev_priv))
3355                 valleyview_display_irqs_uninstall(dev_priv);
3356 }
3357
3358 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3359 {
3360         dev_priv->irq_mask = ~0;
3361
3362         I915_WRITE(PORT_HOTPLUG_EN, 0);
3363         POSTING_READ(PORT_HOTPLUG_EN);
3364
3365         I915_WRITE(VLV_IIR, 0xffffffff);
3366         I915_WRITE(VLV_IIR, 0xffffffff);
3367         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3368         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3369         POSTING_READ(VLV_IMR);
3370
3371         /* Interrupt setup is already guaranteed to be single-threaded, this is
3372          * just to make the assert_spin_locked check happy. */
3373         spin_lock_irq(&dev_priv->irq_lock);
3374         if (dev_priv->display_irqs_enabled)
3375                 valleyview_display_irqs_install(dev_priv);
3376         spin_unlock_irq(&dev_priv->irq_lock);
3377 }
3378
3379 static int valleyview_irq_postinstall(struct drm_device *dev)
3380 {
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382
3383         vlv_display_irq_postinstall(dev_priv);
3384
3385         gen5_gt_irq_postinstall(dev);
3386
3387         /* ack & enable invalid PTE error interrupts */
3388 #if 0 /* FIXME: add support to irq handler for checking these bits */
3389         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3390         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3391 #endif
3392
3393         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3394
3395         return 0;
3396 }
3397
3398 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3399 {
3400         /* These are interrupts we'll toggle with the ring mask register */
3401         uint32_t gt_interrupts[] = {
3402                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3403                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3404                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3405                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3406                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3407                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3408                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3409                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3410                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3411                 0,
3412                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3413                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3414                 };
3415
3416         dev_priv->pm_irq_mask = 0xffffffff;
3417         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3418         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3419         /*
3420          * RPS interrupts will get enabled/disabled on demand when RPS itself
3421          * is enabled/disabled.
3422          */
3423         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3424         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3425 }
3426
3427 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3428 {
3429         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3430         uint32_t de_pipe_enables;
3431         int pipe;
3432         u32 aux_en = GEN8_AUX_CHANNEL_A;
3433
3434         if (IS_GEN9(dev_priv)) {
3435                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3436                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3437                 aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3438                         GEN9_AUX_CHANNEL_D;
3439         } else
3440                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3441                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3442
3443         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3444                                            GEN8_PIPE_FIFO_UNDERRUN;
3445
3446         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3447         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3448         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3449
3450         for_each_pipe(dev_priv, pipe)
3451                 if (intel_display_power_is_enabled(dev_priv,
3452                                 POWER_DOMAIN_PIPE(pipe)))
3453                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3454                                           dev_priv->de_irq_mask[pipe],
3455                                           de_pipe_enables);
3456
3457         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
3458 }
3459
3460 static int gen8_irq_postinstall(struct drm_device *dev)
3461 {
3462         struct drm_i915_private *dev_priv = dev->dev_private;
3463
3464         ibx_irq_pre_postinstall(dev);
3465
3466         gen8_gt_irq_postinstall(dev_priv);
3467         gen8_de_irq_postinstall(dev_priv);
3468
3469         ibx_irq_postinstall(dev);
3470
3471         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3472         POSTING_READ(GEN8_MASTER_IRQ);
3473
3474         return 0;
3475 }
3476
3477 static int cherryview_irq_postinstall(struct drm_device *dev)
3478 {
3479         struct drm_i915_private *dev_priv = dev->dev_private;
3480
3481         vlv_display_irq_postinstall(dev_priv);
3482
3483         gen8_gt_irq_postinstall(dev_priv);
3484
3485         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3486         POSTING_READ(GEN8_MASTER_IRQ);
3487
3488         return 0;
3489 }
3490
3491 static void gen8_irq_uninstall(struct drm_device *dev)
3492 {
3493         struct drm_i915_private *dev_priv = dev->dev_private;
3494
3495         if (!dev_priv)
3496                 return;
3497
3498         gen8_irq_reset(dev);
3499 }
3500
3501 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3502 {
3503         /* Interrupt setup is already guaranteed to be single-threaded, this is
3504          * just to make the assert_spin_locked check happy. */
3505         spin_lock_irq(&dev_priv->irq_lock);
3506         if (dev_priv->display_irqs_enabled)
3507                 valleyview_display_irqs_uninstall(dev_priv);
3508         spin_unlock_irq(&dev_priv->irq_lock);
3509
3510         vlv_display_irq_reset(dev_priv);
3511
3512         dev_priv->irq_mask = ~0;
3513 }
3514
3515 static void valleyview_irq_uninstall(struct drm_device *dev)
3516 {
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519         if (!dev_priv)
3520                 return;
3521
3522         I915_WRITE(VLV_MASTER_IER, 0);
3523
3524         gen5_gt_irq_reset(dev);
3525
3526         I915_WRITE(HWSTAM, 0xffffffff);
3527
3528         vlv_display_irq_uninstall(dev_priv);
3529 }
3530
3531 static void cherryview_irq_uninstall(struct drm_device *dev)
3532 {
3533         struct drm_i915_private *dev_priv = dev->dev_private;
3534
3535         if (!dev_priv)
3536                 return;
3537
3538         I915_WRITE(GEN8_MASTER_IRQ, 0);
3539         POSTING_READ(GEN8_MASTER_IRQ);
3540
3541         gen8_gt_irq_reset(dev_priv);
3542
3543         GEN5_IRQ_RESET(GEN8_PCU_);
3544
3545         vlv_display_irq_uninstall(dev_priv);
3546 }
3547
3548 static void ironlake_irq_uninstall(struct drm_device *dev)
3549 {
3550         struct drm_i915_private *dev_priv = dev->dev_private;
3551
3552         if (!dev_priv)
3553                 return;
3554
3555         ironlake_irq_reset(dev);
3556 }
3557
3558 static void i8xx_irq_preinstall(struct drm_device * dev)
3559 {
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         int pipe;
3562
3563         for_each_pipe(dev_priv, pipe)
3564                 I915_WRITE(PIPESTAT(pipe), 0);
3565         I915_WRITE16(IMR, 0xffff);
3566         I915_WRITE16(IER, 0x0);
3567         POSTING_READ16(IER);
3568 }
3569
3570 static int i8xx_irq_postinstall(struct drm_device *dev)
3571 {
3572         struct drm_i915_private *dev_priv = dev->dev_private;
3573
3574         I915_WRITE16(EMR,
3575                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3576
3577         /* Unmask the interrupts that we always want on. */
3578         dev_priv->irq_mask =
3579                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3580                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3581                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3582                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3583                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3584         I915_WRITE16(IMR, dev_priv->irq_mask);
3585
3586         I915_WRITE16(IER,
3587                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3588                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3589                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3590                      I915_USER_INTERRUPT);
3591         POSTING_READ16(IER);
3592
3593         /* Interrupt setup is already guaranteed to be single-threaded, this is
3594          * just to make the assert_spin_locked check happy. */
3595         spin_lock_irq(&dev_priv->irq_lock);
3596         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3597         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3598         spin_unlock_irq(&dev_priv->irq_lock);
3599
3600         return 0;
3601 }
3602
3603 /*
3604  * Returns true when a page flip has completed.
3605  */
3606 static bool i8xx_handle_vblank(struct drm_device *dev,
3607                                int plane, int pipe, u32 iir)
3608 {
3609         struct drm_i915_private *dev_priv = dev->dev_private;
3610         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3611
3612         if (!intel_pipe_handle_vblank(dev, pipe))
3613                 return false;
3614
3615         if ((iir & flip_pending) == 0)
3616                 goto check_page_flip;
3617
3618         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3619          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3620          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3621          * the flip is completed (no longer pending). Since this doesn't raise
3622          * an interrupt per se, we watch for the change at vblank.
3623          */
3624         if (I915_READ16(ISR) & flip_pending)
3625                 goto check_page_flip;
3626
3627         intel_prepare_page_flip(dev, plane);
3628         intel_finish_page_flip(dev, pipe);
3629         return true;
3630
3631 check_page_flip:
3632         intel_check_page_flip(dev, pipe);
3633         return false;
3634 }
3635
3636 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3637 {
3638         struct drm_device *dev = arg;
3639         struct drm_i915_private *dev_priv = dev->dev_private;
3640         u16 iir, new_iir;
3641         u32 pipe_stats[2];
3642         int pipe;
3643         u16 flip_mask =
3644                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3645                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3646
3647         if (!intel_irqs_enabled(dev_priv))
3648                 return IRQ_NONE;
3649
3650         iir = I915_READ16(IIR);
3651         if (iir == 0)
3652                 return IRQ_NONE;
3653
3654         while (iir & ~flip_mask) {
3655                 /* Can't rely on pipestat interrupt bit in iir as it might
3656                  * have been cleared after the pipestat interrupt was received.
3657                  * It doesn't set the bit in iir again, but it still produces
3658                  * interrupts (for non-MSI).
3659                  */
3660                 spin_lock(&dev_priv->irq_lock);
3661                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3662                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3663
3664                 for_each_pipe(dev_priv, pipe) {
3665                         int reg = PIPESTAT(pipe);
3666                         pipe_stats[pipe] = I915_READ(reg);
3667
3668                         /*
3669                          * Clear the PIPE*STAT regs before the IIR
3670                          */
3671                         if (pipe_stats[pipe] & 0x8000ffff)
3672                                 I915_WRITE(reg, pipe_stats[pipe]);
3673                 }
3674                 spin_unlock(&dev_priv->irq_lock);
3675
3676                 I915_WRITE16(IIR, iir & ~flip_mask);
3677                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3678
3679                 if (iir & I915_USER_INTERRUPT)
3680                         notify_ring(&dev_priv->ring[RCS]);
3681
3682                 for_each_pipe(dev_priv, pipe) {
3683                         int plane = pipe;
3684                         if (HAS_FBC(dev))
3685                                 plane = !plane;
3686
3687                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3688                             i8xx_handle_vblank(dev, plane, pipe, iir))
3689                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3690
3691                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3692                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3693
3694                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3695                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3696                                                                     pipe);
3697                 }
3698
3699                 iir = new_iir;
3700         }
3701
3702         return IRQ_HANDLED;
3703 }
3704
3705 static void i8xx_irq_uninstall(struct drm_device * dev)
3706 {
3707         struct drm_i915_private *dev_priv = dev->dev_private;
3708         int pipe;
3709
3710         for_each_pipe(dev_priv, pipe) {
3711                 /* Clear enable bits; then clear status bits */
3712                 I915_WRITE(PIPESTAT(pipe), 0);
3713                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3714         }
3715         I915_WRITE16(IMR, 0xffff);
3716         I915_WRITE16(IER, 0x0);
3717         I915_WRITE16(IIR, I915_READ16(IIR));
3718 }
3719
3720 static void i915_irq_preinstall(struct drm_device * dev)
3721 {
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         int pipe;
3724
3725         if (I915_HAS_HOTPLUG(dev)) {
3726                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3727                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3728         }
3729
3730         I915_WRITE16(HWSTAM, 0xeffe);
3731         for_each_pipe(dev_priv, pipe)
3732                 I915_WRITE(PIPESTAT(pipe), 0);
3733         I915_WRITE(IMR, 0xffffffff);
3734         I915_WRITE(IER, 0x0);
3735         POSTING_READ(IER);
3736 }
3737
3738 static int i915_irq_postinstall(struct drm_device *dev)
3739 {
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         u32 enable_mask;
3742
3743         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3744
3745         /* Unmask the interrupts that we always want on. */
3746         dev_priv->irq_mask =
3747                 ~(I915_ASLE_INTERRUPT |
3748                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3749                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3750                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3751                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3752                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3753
3754         enable_mask =
3755                 I915_ASLE_INTERRUPT |
3756                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3757                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3758                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3759                 I915_USER_INTERRUPT;
3760
3761         if (I915_HAS_HOTPLUG(dev)) {
3762                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3763                 POSTING_READ(PORT_HOTPLUG_EN);
3764
3765                 /* Enable in IER... */
3766                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3767                 /* and unmask in IMR */
3768                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3769         }
3770
3771         I915_WRITE(IMR, dev_priv->irq_mask);
3772         I915_WRITE(IER, enable_mask);
3773         POSTING_READ(IER);
3774
3775         i915_enable_asle_pipestat(dev);
3776
3777         /* Interrupt setup is already guaranteed to be single-threaded, this is
3778          * just to make the assert_spin_locked check happy. */
3779         spin_lock_irq(&dev_priv->irq_lock);
3780         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3781         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3782         spin_unlock_irq(&dev_priv->irq_lock);
3783
3784         return 0;
3785 }
3786
3787 /*
3788  * Returns true when a page flip has completed.
3789  */
3790 static bool i915_handle_vblank(struct drm_device *dev,
3791                                int plane, int pipe, u32 iir)
3792 {
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3795
3796         if (!intel_pipe_handle_vblank(dev, pipe))
3797                 return false;
3798
3799         if ((iir & flip_pending) == 0)
3800                 goto check_page_flip;
3801
3802         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3803          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3804          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3805          * the flip is completed (no longer pending). Since this doesn't raise
3806          * an interrupt per se, we watch for the change at vblank.
3807          */
3808         if (I915_READ(ISR) & flip_pending)
3809                 goto check_page_flip;
3810
3811         intel_prepare_page_flip(dev, plane);
3812         intel_finish_page_flip(dev, pipe);
3813         return true;
3814
3815 check_page_flip:
3816         intel_check_page_flip(dev, pipe);
3817         return false;
3818 }
3819
3820 static irqreturn_t i915_irq_handler(int irq, void *arg)
3821 {
3822         struct drm_device *dev = arg;
3823         struct drm_i915_private *dev_priv = dev->dev_private;
3824         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3825         u32 flip_mask =
3826                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3827                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3828         int pipe, ret = IRQ_NONE;
3829
3830         if (!intel_irqs_enabled(dev_priv))
3831                 return IRQ_NONE;
3832
3833         iir = I915_READ(IIR);
3834         do {
3835                 bool irq_received = (iir & ~flip_mask) != 0;
3836                 bool blc_event = false;
3837
3838                 /* Can't rely on pipestat interrupt bit in iir as it might
3839                  * have been cleared after the pipestat interrupt was received.
3840                  * It doesn't set the bit in iir again, but it still produces
3841                  * interrupts (for non-MSI).
3842                  */
3843                 spin_lock(&dev_priv->irq_lock);
3844                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3845                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3846
3847                 for_each_pipe(dev_priv, pipe) {
3848                         int reg = PIPESTAT(pipe);
3849                         pipe_stats[pipe] = I915_READ(reg);
3850
3851                         /* Clear the PIPE*STAT regs before the IIR */
3852                         if (pipe_stats[pipe] & 0x8000ffff) {
3853                                 I915_WRITE(reg, pipe_stats[pipe]);
3854                                 irq_received = true;
3855                         }
3856                 }
3857                 spin_unlock(&dev_priv->irq_lock);
3858
3859                 if (!irq_received)
3860                         break;
3861
3862                 /* Consume port.  Then clear IIR or we'll miss events */
3863                 if (I915_HAS_HOTPLUG(dev) &&
3864                     iir & I915_DISPLAY_PORT_INTERRUPT)
3865                         i9xx_hpd_irq_handler(dev);
3866
3867                 I915_WRITE(IIR, iir & ~flip_mask);
3868                 new_iir = I915_READ(IIR); /* Flush posted writes */
3869
3870                 if (iir & I915_USER_INTERRUPT)
3871                         notify_ring(&dev_priv->ring[RCS]);
3872
3873                 for_each_pipe(dev_priv, pipe) {
3874                         int plane = pipe;
3875                         if (HAS_FBC(dev))
3876                                 plane = !plane;
3877
3878                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3879                             i915_handle_vblank(dev, plane, pipe, iir))
3880                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3881
3882                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3883                                 blc_event = true;
3884
3885                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3886                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3887
3888                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3889                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3890                                                                     pipe);
3891                 }
3892
3893                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3894                         intel_opregion_asle_intr(dev);
3895
3896                 /* With MSI, interrupts are only generated when iir
3897                  * transitions from zero to nonzero.  If another bit got
3898                  * set while we were handling the existing iir bits, then
3899                  * we would never get another interrupt.
3900                  *
3901                  * This is fine on non-MSI as well, as if we hit this path
3902                  * we avoid exiting the interrupt handler only to generate
3903                  * another one.
3904                  *
3905                  * Note that for MSI this could cause a stray interrupt report
3906                  * if an interrupt landed in the time between writing IIR and
3907                  * the posting read.  This should be rare enough to never
3908                  * trigger the 99% of 100,000 interrupts test for disabling
3909                  * stray interrupts.
3910                  */
3911                 ret = IRQ_HANDLED;
3912                 iir = new_iir;
3913         } while (iir & ~flip_mask);
3914
3915         return ret;
3916 }
3917
3918 static void i915_irq_uninstall(struct drm_device * dev)
3919 {
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921         int pipe;
3922
3923         if (I915_HAS_HOTPLUG(dev)) {
3924                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3925                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3926         }
3927
3928         I915_WRITE16(HWSTAM, 0xffff);
3929         for_each_pipe(dev_priv, pipe) {
3930                 /* Clear enable bits; then clear status bits */
3931                 I915_WRITE(PIPESTAT(pipe), 0);
3932                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3933         }
3934         I915_WRITE(IMR, 0xffffffff);
3935         I915_WRITE(IER, 0x0);
3936
3937         I915_WRITE(IIR, I915_READ(IIR));
3938 }
3939
3940 static void i965_irq_preinstall(struct drm_device * dev)
3941 {
3942         struct drm_i915_private *dev_priv = dev->dev_private;
3943         int pipe;
3944
3945         I915_WRITE(PORT_HOTPLUG_EN, 0);
3946         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3947
3948         I915_WRITE(HWSTAM, 0xeffe);
3949         for_each_pipe(dev_priv, pipe)
3950                 I915_WRITE(PIPESTAT(pipe), 0);
3951         I915_WRITE(IMR, 0xffffffff);
3952         I915_WRITE(IER, 0x0);
3953         POSTING_READ(IER);
3954 }
3955
3956 static int i965_irq_postinstall(struct drm_device *dev)
3957 {
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         u32 enable_mask;
3960         u32 error_mask;
3961
3962         /* Unmask the interrupts that we always want on. */
3963         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3964                                I915_DISPLAY_PORT_INTERRUPT |
3965                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3966                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3967                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3968                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3969                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3970
3971         enable_mask = ~dev_priv->irq_mask;
3972         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3973                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3974         enable_mask |= I915_USER_INTERRUPT;
3975
3976         if (IS_G4X(dev))
3977                 enable_mask |= I915_BSD_USER_INTERRUPT;
3978
3979         /* Interrupt setup is already guaranteed to be single-threaded, this is
3980          * just to make the assert_spin_locked check happy. */
3981         spin_lock_irq(&dev_priv->irq_lock);
3982         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3983         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3984         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3985         spin_unlock_irq(&dev_priv->irq_lock);
3986
3987         /*
3988          * Enable some error detection, note the instruction error mask
3989          * bit is reserved, so we leave it masked.
3990          */
3991         if (IS_G4X(dev)) {
3992                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3993                                GM45_ERROR_MEM_PRIV |
3994                                GM45_ERROR_CP_PRIV |
3995                                I915_ERROR_MEMORY_REFRESH);
3996         } else {
3997                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3998                                I915_ERROR_MEMORY_REFRESH);
3999         }
4000         I915_WRITE(EMR, error_mask);
4001
4002         I915_WRITE(IMR, dev_priv->irq_mask);
4003         I915_WRITE(IER, enable_mask);
4004         POSTING_READ(IER);
4005
4006         I915_WRITE(PORT_HOTPLUG_EN, 0);
4007         POSTING_READ(PORT_HOTPLUG_EN);
4008
4009         i915_enable_asle_pipestat(dev);
4010
4011         return 0;
4012 }
4013
4014 static void i915_hpd_irq_setup(struct drm_device *dev)
4015 {
4016         struct drm_i915_private *dev_priv = dev->dev_private;
4017         struct intel_encoder *intel_encoder;
4018         u32 hotplug_en;
4019
4020         assert_spin_locked(&dev_priv->irq_lock);
4021
4022         hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4023         hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4024         /* Note HDMI and DP share hotplug bits */
4025         /* enable bits are the same for all generations */
4026         for_each_intel_encoder(dev, intel_encoder)
4027                 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4028                         hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4029         /* Programming the CRT detection parameters tends
4030            to generate a spurious hotplug event about three
4031            seconds later.  So just do it once.
4032         */
4033         if (IS_G4X(dev))
4034                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4035         hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4036         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4037
4038         /* Ignore TV since it's buggy */
4039         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4040 }
4041
4042 static irqreturn_t i965_irq_handler(int irq, void *arg)
4043 {
4044         struct drm_device *dev = arg;
4045         struct drm_i915_private *dev_priv = dev->dev_private;
4046         u32 iir, new_iir;
4047         u32 pipe_stats[I915_MAX_PIPES];
4048         int ret = IRQ_NONE, pipe;
4049         u32 flip_mask =
4050                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4051                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4052
4053         if (!intel_irqs_enabled(dev_priv))
4054                 return IRQ_NONE;
4055
4056         iir = I915_READ(IIR);
4057
4058         for (;;) {
4059                 bool irq_received = (iir & ~flip_mask) != 0;
4060                 bool blc_event = false;
4061
4062                 /* Can't rely on pipestat interrupt bit in iir as it might
4063                  * have been cleared after the pipestat interrupt was received.
4064                  * It doesn't set the bit in iir again, but it still produces
4065                  * interrupts (for non-MSI).
4066                  */
4067                 spin_lock(&dev_priv->irq_lock);
4068                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4069                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4070
4071                 for_each_pipe(dev_priv, pipe) {
4072                         int reg = PIPESTAT(pipe);
4073                         pipe_stats[pipe] = I915_READ(reg);
4074
4075                         /*
4076                          * Clear the PIPE*STAT regs before the IIR
4077                          */
4078                         if (pipe_stats[pipe] & 0x8000ffff) {
4079                                 I915_WRITE(reg, pipe_stats[pipe]);
4080                                 irq_received = true;
4081                         }
4082                 }
4083                 spin_unlock(&dev_priv->irq_lock);
4084
4085                 if (!irq_received)
4086                         break;
4087
4088                 ret = IRQ_HANDLED;
4089
4090                 /* Consume port.  Then clear IIR or we'll miss events */
4091                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4092                         i9xx_hpd_irq_handler(dev);
4093
4094                 I915_WRITE(IIR, iir & ~flip_mask);
4095                 new_iir = I915_READ(IIR); /* Flush posted writes */
4096
4097                 if (iir & I915_USER_INTERRUPT)
4098                         notify_ring(&dev_priv->ring[RCS]);
4099                 if (iir & I915_BSD_USER_INTERRUPT)
4100                         notify_ring(&dev_priv->ring[VCS]);
4101
4102                 for_each_pipe(dev_priv, pipe) {
4103                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4104                             i915_handle_vblank(dev, pipe, pipe, iir))
4105                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4106
4107                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4108                                 blc_event = true;
4109
4110                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4111                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4112
4113                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4114                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4115                 }
4116
4117                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4118                         intel_opregion_asle_intr(dev);
4119
4120                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4121                         gmbus_irq_handler(dev);
4122
4123                 /* With MSI, interrupts are only generated when iir
4124                  * transitions from zero to nonzero.  If another bit got
4125                  * set while we were handling the existing iir bits, then
4126                  * we would never get another interrupt.
4127                  *
4128                  * This is fine on non-MSI as well, as if we hit this path
4129                  * we avoid exiting the interrupt handler only to generate
4130                  * another one.
4131                  *
4132                  * Note that for MSI this could cause a stray interrupt report
4133                  * if an interrupt landed in the time between writing IIR and
4134                  * the posting read.  This should be rare enough to never
4135                  * trigger the 99% of 100,000 interrupts test for disabling
4136                  * stray interrupts.
4137                  */
4138                 iir = new_iir;
4139         }
4140
4141         return ret;
4142 }
4143
4144 static void i965_irq_uninstall(struct drm_device * dev)
4145 {
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         int pipe;
4148
4149         if (!dev_priv)
4150                 return;
4151
4152         I915_WRITE(PORT_HOTPLUG_EN, 0);
4153         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4154
4155         I915_WRITE(HWSTAM, 0xffffffff);
4156         for_each_pipe(dev_priv, pipe)
4157                 I915_WRITE(PIPESTAT(pipe), 0);
4158         I915_WRITE(IMR, 0xffffffff);
4159         I915_WRITE(IER, 0x0);
4160
4161         for_each_pipe(dev_priv, pipe)
4162                 I915_WRITE(PIPESTAT(pipe),
4163                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4164         I915_WRITE(IIR, I915_READ(IIR));
4165 }
4166
4167 static void intel_hpd_irq_reenable_work(struct work_struct *work)
4168 {
4169         struct drm_i915_private *dev_priv =
4170                 container_of(work, typeof(*dev_priv),
4171                              hotplug_reenable_work.work);
4172         struct drm_device *dev = dev_priv->dev;
4173         struct drm_mode_config *mode_config = &dev->mode_config;
4174         int i;
4175
4176         intel_runtime_pm_get(dev_priv);
4177
4178         spin_lock_irq(&dev_priv->irq_lock);
4179         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4180                 struct drm_connector *connector;
4181
4182                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4183                         continue;
4184
4185                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4186
4187                 list_for_each_entry(connector, &mode_config->connector_list, head) {
4188                         struct intel_connector *intel_connector = to_intel_connector(connector);
4189
4190                         if (intel_connector->encoder->hpd_pin == i) {
4191                                 if (connector->polled != intel_connector->polled)
4192                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4193                                                          connector->name);
4194                                 connector->polled = intel_connector->polled;
4195                                 if (!connector->polled)
4196                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4197                         }
4198                 }
4199         }
4200         if (dev_priv->display.hpd_irq_setup)
4201                 dev_priv->display.hpd_irq_setup(dev);
4202         spin_unlock_irq(&dev_priv->irq_lock);
4203
4204         intel_runtime_pm_put(dev_priv);
4205 }
4206
4207 /**
4208  * intel_irq_init - initializes irq support
4209  * @dev_priv: i915 device instance
4210  *
4211  * This function initializes all the irq support including work items, timers
4212  * and all the vtables. It does not setup the interrupt itself though.
4213  */
4214 void intel_irq_init(struct drm_i915_private *dev_priv)
4215 {
4216         struct drm_device *dev = dev_priv->dev;
4217
4218         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4219         INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4220         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4221         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4222
4223         /* Let's track the enabled rps events */
4224         if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4225                 /* WaGsvRC0ResidencyMethod:vlv */
4226                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4227         else
4228                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4229
4230         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4231                           i915_hangcheck_elapsed);
4232         INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4233                           intel_hpd_irq_reenable_work);
4234
4235         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4236
4237         if (IS_GEN2(dev_priv)) {
4238                 dev->max_vblank_count = 0;
4239                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4240         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4241                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4242                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4243         } else {
4244                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4245                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4246         }
4247
4248         /*
4249          * Opt out of the vblank disable timer on everything except gen2.
4250          * Gen2 doesn't have a hardware frame counter and so depends on
4251          * vblank interrupts to produce sane vblank seuquence numbers.
4252          */
4253         if (!IS_GEN2(dev_priv))
4254                 dev->vblank_disable_immediate = true;
4255
4256         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4257         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4258
4259         if (IS_CHERRYVIEW(dev_priv)) {
4260                 dev->driver->irq_handler = cherryview_irq_handler;
4261                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4262                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4263                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4264                 dev->driver->enable_vblank = valleyview_enable_vblank;
4265                 dev->driver->disable_vblank = valleyview_disable_vblank;
4266                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4267         } else if (IS_VALLEYVIEW(dev_priv)) {
4268                 dev->driver->irq_handler = valleyview_irq_handler;
4269                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4270                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4271                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4272                 dev->driver->enable_vblank = valleyview_enable_vblank;
4273                 dev->driver->disable_vblank = valleyview_disable_vblank;
4274                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4275         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4276                 dev->driver->irq_handler = gen8_irq_handler;
4277                 dev->driver->irq_preinstall = gen8_irq_reset;
4278                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4279                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4280                 dev->driver->enable_vblank = gen8_enable_vblank;
4281                 dev->driver->disable_vblank = gen8_disable_vblank;
4282                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4283         } else if (HAS_PCH_SPLIT(dev)) {
4284                 dev->driver->irq_handler = ironlake_irq_handler;
4285                 dev->driver->irq_preinstall = ironlake_irq_reset;
4286                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4287                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4288                 dev->driver->enable_vblank = ironlake_enable_vblank;
4289                 dev->driver->disable_vblank = ironlake_disable_vblank;
4290                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4291         } else {
4292                 if (INTEL_INFO(dev_priv)->gen == 2) {
4293                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4294                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4295                         dev->driver->irq_handler = i8xx_irq_handler;
4296                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4297                 } else if (INTEL_INFO(dev_priv)->gen == 3) {
4298                         dev->driver->irq_preinstall = i915_irq_preinstall;
4299                         dev->driver->irq_postinstall = i915_irq_postinstall;
4300                         dev->driver->irq_uninstall = i915_irq_uninstall;
4301                         dev->driver->irq_handler = i915_irq_handler;
4302                 } else {
4303                         dev->driver->irq_preinstall = i965_irq_preinstall;
4304                         dev->driver->irq_postinstall = i965_irq_postinstall;
4305                         dev->driver->irq_uninstall = i965_irq_uninstall;
4306                         dev->driver->irq_handler = i965_irq_handler;
4307                 }
4308                 if (I915_HAS_HOTPLUG(dev_priv))
4309                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4310                 dev->driver->enable_vblank = i915_enable_vblank;
4311                 dev->driver->disable_vblank = i915_disable_vblank;
4312         }
4313 }
4314
4315 /**
4316  * intel_hpd_init - initializes and enables hpd support
4317  * @dev_priv: i915 device instance
4318  *
4319  * This function enables the hotplug support. It requires that interrupts have
4320  * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4321  * poll request can run concurrently to other code, so locking rules must be
4322  * obeyed.
4323  *
4324  * This is a separate step from interrupt enabling to simplify the locking rules
4325  * in the driver load and resume code.
4326  */
4327 void intel_hpd_init(struct drm_i915_private *dev_priv)
4328 {
4329         struct drm_device *dev = dev_priv->dev;
4330         struct drm_mode_config *mode_config = &dev->mode_config;
4331         struct drm_connector *connector;
4332         int i;
4333
4334         for (i = 1; i < HPD_NUM_PINS; i++) {
4335                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4336                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4337         }
4338         list_for_each_entry(connector, &mode_config->connector_list, head) {
4339                 struct intel_connector *intel_connector = to_intel_connector(connector);
4340                 connector->polled = intel_connector->polled;
4341                 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4342                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4343                 if (intel_connector->mst_port)
4344                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4345         }
4346
4347         /* Interrupt setup is already guaranteed to be single-threaded, this is
4348          * just to make the assert_spin_locked checks happy. */
4349         spin_lock_irq(&dev_priv->irq_lock);
4350         if (dev_priv->display.hpd_irq_setup)
4351                 dev_priv->display.hpd_irq_setup(dev);
4352         spin_unlock_irq(&dev_priv->irq_lock);
4353 }
4354
4355 /**
4356  * intel_irq_install - enables the hardware interrupt
4357  * @dev_priv: i915 device instance
4358  *
4359  * This function enables the hardware interrupt handling, but leaves the hotplug
4360  * handling still disabled. It is called after intel_irq_init().
4361  *
4362  * In the driver load and resume code we need working interrupts in a few places
4363  * but don't want to deal with the hassle of concurrent probe and hotplug
4364  * workers. Hence the split into this two-stage approach.
4365  */
4366 int intel_irq_install(struct drm_i915_private *dev_priv)
4367 {
4368         /*
4369          * We enable some interrupt sources in our postinstall hooks, so mark
4370          * interrupts as enabled _before_ actually enabling them to avoid
4371          * special cases in our ordering checks.
4372          */
4373         dev_priv->pm.irqs_enabled = true;
4374
4375         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4376 }
4377
4378 /**
4379  * intel_irq_uninstall - finilizes all irq handling
4380  * @dev_priv: i915 device instance
4381  *
4382  * This stops interrupt and hotplug handling and unregisters and frees all
4383  * resources acquired in the init functions.
4384  */
4385 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4386 {
4387         drm_irq_uninstall(dev_priv->dev);
4388         intel_hpd_cancel_work(dev_priv);
4389         dev_priv->pm.irqs_enabled = false;
4390 }
4391
4392 /**
4393  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4394  * @dev_priv: i915 device instance
4395  *
4396  * This function is used to disable interrupts at runtime, both in the runtime
4397  * pm and the system suspend/resume code.
4398  */
4399 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4400 {
4401         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4402         dev_priv->pm.irqs_enabled = false;
4403         synchronize_irq(dev_priv->dev->irq);
4404 }
4405
4406 /**
4407  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4408  * @dev_priv: i915 device instance
4409  *
4410  * This function is used to enable interrupts at runtime, both in the runtime
4411  * pm and the system suspend/resume code.
4412  */
4413 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4414 {
4415         dev_priv->pm.irqs_enabled = true;
4416         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4417         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4418 }