drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 /* For display hotplug interrupt */
  68 static void
  69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  70 {
  71         if ((dev_priv->irq_mask & mask) != 0) {
  72                 dev_priv->irq_mask &= ~mask;
  73                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  74                 POSTING_READ(DEIMR);
  75         }
  76 }
  77
  78 static inline void
  79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  80 {
  81         if ((dev_priv->irq_mask & mask) != mask) {
  82                 dev_priv->irq_mask |= mask;
  83                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  84                 POSTING_READ(DEIMR);
  85         }
  86 }
  87
  88 static inline u32
  89 i915_pipestat(int pipe)
  90 {
  91         if (pipe == 0)
  92                 return PIPEASTAT;
  93         if (pipe == 1)
  94                 return PIPEBSTAT;
  95         BUG();
  96 }
  97
  98 void
  99 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 100 {
 101         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 102                 u32 reg = i915_pipestat(pipe);
 103
 104                 dev_priv->pipestat[pipe] |= mask;
 105                 /* Enable the interrupt, clear any pending status */
 106                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 107                 POSTING_READ(reg);
 108         }
 109 }
 110
 111 void
 112 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 113 {
 114         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 115                 u32 reg = i915_pipestat(pipe);
 116
 117                 dev_priv->pipestat[pipe] &= ~mask;
 118                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 119                 POSTING_READ(reg);
 120         }
 121 }
 122
 123 /**
 124  * intel_enable_asle - enable ASLE interrupt for OpRegion
 125  */
 126 void intel_enable_asle(struct drm_device *dev)
 127 {
 128         drm_i915_private_t *dev_priv = dev->dev_private;
 129         unsigned long irqflags;
 130
 131         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 132
 133         if (HAS_PCH_SPLIT(dev))
 134                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 135         else {
 136                 i915_enable_pipestat(dev_priv, 1,
 137                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 138                 if (INTEL_INFO(dev)->gen >= 4)
 139                         i915_enable_pipestat(dev_priv, 0,
 140                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 141         }
 142
 143         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 144 }
 145
 146 /**
 147  * i915_pipe_enabled - check if a pipe is enabled
 148  * @dev: DRM device
 149  * @pipe: pipe to check
 150  *
 151  * Reading certain registers when the pipe is disabled can hang the chip.
 152  * Use this routine to make sure the PLL is running and the pipe is active
 153  * before reading such registers if unsure.
 154  */
 155 static int
 156 i915_pipe_enabled(struct drm_device *dev, int pipe)
 157 {
 158         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 159         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 160 }
 161
 162 /* Called from drm generic code, passed a 'crtc', which
 163  * we use as a pipe index
 164  */
 165 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 166 {
 167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 168         unsigned long high_frame;
 169         unsigned long low_frame;
 170         u32 high1, high2, low;
 171
 172         if (!i915_pipe_enabled(dev, pipe)) {
 173                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 174                                 "pipe %d\n", pipe);
 175                 return 0;
 176         }
 177
 178         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 179         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 180
 181         /*
 182          * High & low register fields aren't synchronized, so make sure
 183          * we get a low value that's stable across two reads of the high
 184          * register.
 185          */
 186         do {
 187                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 188                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 189                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 190         } while (high1 != high2);
 191
 192         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 193         low >>= PIPE_FRAME_LOW_SHIFT;
 194         return (high1 << 8) | low;
 195 }
 196
 197 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 198 {
 199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 200         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 201
 202         if (!i915_pipe_enabled(dev, pipe)) {
 203                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 204                                         "pipe %d\n", pipe);
 205                 return 0;
 206         }
 207
 208         return I915_READ(reg);
 209 }
 210
 211 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 212                              int *vpos, int *hpos)
 213 {
 214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 215         u32 vbl = 0, position = 0;
 216         int vbl_start, vbl_end, htotal, vtotal;
 217         bool in_vbl = true;
 218         int ret = 0;
 219
 220         if (!i915_pipe_enabled(dev, pipe)) {
 221                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 222                                         "pipe %d\n", pipe);
 223                 return 0;
 224         }
 225
 226         /* Get vtotal. */
 227         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 228
 229         if (INTEL_INFO(dev)->gen >= 4) {
 230                 /* No obvious pixelcount register. Only query vertical
 231                  * scanout position from Display scan line register.
 232                  */
 233                 position = I915_READ(PIPEDSL(pipe));
 234
 235                 /* Decode into vertical scanout position. Don't have
 236                  * horizontal scanout position.
 237                  */
 238                 *vpos = position & 0x1fff;
 239                 *hpos = 0;
 240         } else {
 241                 /* Have access to pixelcount since start of frame.
 242                  * We can split this into vertical and horizontal
 243                  * scanout position.
 244                  */
 245                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 246
 247                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 248                 *vpos = position / htotal;
 249                 *hpos = position - (*vpos * htotal);
 250         }
 251
 252         /* Query vblank area. */
 253         vbl = I915_READ(VBLANK(pipe));
 254
 255         /* Test position against vblank region. */
 256         vbl_start = vbl & 0x1fff;
 257         vbl_end = (vbl >> 16) & 0x1fff;
 258
 259         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 260                 in_vbl = false;
 261
 262         /* Inside "upper part" of vblank area? Apply corrective offset: */
 263         if (in_vbl && (*vpos >= vbl_start))
 264                 *vpos = *vpos - vtotal;
 265
 266         /* Readouts valid? */
 267         if (vbl > 0)
 268                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 269
 270         /* In vblank? */
 271         if (in_vbl)
 272                 ret |= DRM_SCANOUTPOS_INVBL;
 273
 274         return ret;
 275 }
 276
 277 int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 278                               int *max_error,
 279                               struct timeval *vblank_time,
 280                               unsigned flags)
 281 {
 282         struct drm_i915_private *dev_priv = dev->dev_private;
 283         struct drm_crtc *crtc;
 284
 285         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 286                 DRM_ERROR("Invalid crtc %d\n", pipe);
 287                 return -EINVAL;
 288         }
 289
 290         /* Get drm_crtc to timestamp: */
 291         crtc = intel_get_crtc_for_pipe(dev, pipe);
 292         if (crtc == NULL) {
 293                 DRM_ERROR("Invalid crtc %d\n", pipe);
 294                 return -EINVAL;
 295         }
 296
 297         if (!crtc->enabled) {
 298                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 299                 return -EBUSY;
 300         }
 301
 302         /* Helper routine in DRM core does all the work: */
 303         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 304                                                      vblank_time, flags,
 305                                                      crtc);
 306 }
 307
 308 /*
 309  * Handle hotplug events outside the interrupt handler proper.
 310  */
 311 static void i915_hotplug_work_func(struct work_struct *work)
 312 {
 313         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 314                                                     hotplug_work);
 315         struct drm_device *dev = dev_priv->dev;
 316         struct drm_mode_config *mode_config = &dev->mode_config;
 317         struct intel_encoder *encoder;
 318
 319         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 320                 if (encoder->hot_plug)
 321                         encoder->hot_plug(encoder);
 322
 323         /* Just fire off a uevent and let userspace tell us what to do */
 324         drm_helper_hpd_irq_event(dev);
 325 }
 326
 327 static void i915_handle_rps_change(struct drm_device *dev)
 328 {
 329         drm_i915_private_t *dev_priv = dev->dev_private;
 330         u32 busy_up, busy_down, max_avg, min_avg;
 331         u8 new_delay = dev_priv->cur_delay;
 332
 333         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 334         busy_up = I915_READ(RCPREVBSYTUPAVG);
 335         busy_down = I915_READ(RCPREVBSYTDNAVG);
 336         max_avg = I915_READ(RCBMAXAVG);
 337         min_avg = I915_READ(RCBMINAVG);
 338
 339         /* Handle RCS change request from hw */
 340         if (busy_up > max_avg) {
 341                 if (dev_priv->cur_delay != dev_priv->max_delay)
 342                         new_delay = dev_priv->cur_delay - 1;
 343                 if (new_delay < dev_priv->max_delay)
 344                         new_delay = dev_priv->max_delay;
 345         } else if (busy_down < min_avg) {
 346                 if (dev_priv->cur_delay != dev_priv->min_delay)
 347                         new_delay = dev_priv->cur_delay + 1;
 348                 if (new_delay > dev_priv->min_delay)
 349                         new_delay = dev_priv->min_delay;
 350         }
 351
 352         if (ironlake_set_drps(dev, new_delay))
 353                 dev_priv->cur_delay = new_delay;
 354
 355         return;
 356 }
 357
 358 static void notify_ring(struct drm_device *dev,
 359                         struct intel_ring_buffer *ring)
 360 {
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         u32 seqno;
 363
 364         if (ring->obj == NULL)
 365                 return;
 366
 367         seqno = ring->get_seqno(ring);
 368         trace_i915_gem_request_complete(ring, seqno);
 369
 370         ring->irq_seqno = seqno;
 371         wake_up_all(&ring->irq_queue);
 372
 373         dev_priv->hangcheck_count = 0;
 374         mod_timer(&dev_priv->hangcheck_timer,
 375                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 376 }
 377
 378 static void gen6_pm_irq_handler(struct drm_device *dev)
 379 {
 380         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 381         u8 new_delay = dev_priv->cur_delay;
 382         u32 pm_iir;
 383
 384         pm_iir = I915_READ(GEN6_PMIIR);
 385         if (!pm_iir)
 386                 return;
 387
 388         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 389                 if (dev_priv->cur_delay != dev_priv->max_delay)
 390                         new_delay = dev_priv->cur_delay + 1;
 391                 if (new_delay > dev_priv->max_delay)
 392                         new_delay = dev_priv->max_delay;
 393         } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 394                 if (dev_priv->cur_delay != dev_priv->min_delay)
 395                         new_delay = dev_priv->cur_delay - 1;
 396                 if (new_delay < dev_priv->min_delay) {
 397                         new_delay = dev_priv->min_delay;
 398                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 399                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 400                                    ((new_delay << 16) & 0x3f0000));
 401                 } else {
 402                         /* Make sure we continue to get down interrupts
 403                          * until we hit the minimum frequency */
 404                         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 405                                    I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 406                 }
 407
 408         }
 409
 410         gen6_set_rps(dev, new_delay);
 411         dev_priv->cur_delay = new_delay;
 412
 413         I915_WRITE(GEN6_PMIIR, pm_iir);
 414 }
 415
 416 static void pch_irq_handler(struct drm_device *dev)
 417 {
 418         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 419         u32 pch_iir;
 420
 421         pch_iir = I915_READ(SDEIIR);
 422
 423         if (pch_iir & SDE_AUDIO_POWER_MASK)
 424                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 425                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 426                                  SDE_AUDIO_POWER_SHIFT);
 427
 428         if (pch_iir & SDE_GMBUS)
 429                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 430
 431         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 432                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 433
 434         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 435                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 436
 437         if (pch_iir & SDE_POISON)
 438                 DRM_ERROR("PCH poison interrupt\n");
 439
 440         if (pch_iir & SDE_FDI_MASK) {
 441                 u32 fdia, fdib;
 442
 443                 fdia = I915_READ(FDI_RXA_IIR);
 444                 fdib = I915_READ(FDI_RXB_IIR);
 445                 DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
 446         }
 447
 448         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 449                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 450
 451         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 452                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 453
 454         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 455                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 456         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 457                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 458 }
 459
 460 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 461 {
 462         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 463         int ret = IRQ_NONE;
 464         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 465         u32 hotplug_mask;
 466         struct drm_i915_master_private *master_priv;
 467         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 468
 469         if (IS_GEN6(dev))
 470                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 471
 472         /* disable master interrupt before clearing iir  */
 473         de_ier = I915_READ(DEIER);
 474         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 475         POSTING_READ(DEIER);
 476
 477         de_iir = I915_READ(DEIIR);
 478         gt_iir = I915_READ(GTIIR);
 479         pch_iir = I915_READ(SDEIIR);
 480         pm_iir = I915_READ(GEN6_PMIIR);
 481
 482         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 483             (!IS_GEN6(dev) || pm_iir == 0))
 484                 goto done;
 485
 486         if (HAS_PCH_CPT(dev))
 487                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 488         else
 489                 hotplug_mask = SDE_HOTPLUG_MASK;
 490
 491         ret = IRQ_HANDLED;
 492
 493         if (dev->primary->master) {
 494                 master_priv = dev->primary->master->driver_priv;
 495                 if (master_priv->sarea_priv)
 496                         master_priv->sarea_priv->last_dispatch =
 497                                 READ_BREADCRUMB(dev_priv);
 498         }
 499
 500         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 501                 notify_ring(dev, &dev_priv->ring[RCS]);
 502         if (gt_iir & bsd_usr_interrupt)
 503                 notify_ring(dev, &dev_priv->ring[VCS]);
 504         if (gt_iir & GT_BLT_USER_INTERRUPT)
 505                 notify_ring(dev, &dev_priv->ring[BCS]);
 506
 507         if (de_iir & DE_GSE)
 508                 intel_opregion_gse_intr(dev);
 509
 510         if (de_iir & DE_PLANEA_FLIP_DONE) {
 511                 intel_prepare_page_flip(dev, 0);
 512                 intel_finish_page_flip_plane(dev, 0);
 513         }
 514
 515         if (de_iir & DE_PLANEB_FLIP_DONE) {
 516                 intel_prepare_page_flip(dev, 1);
 517                 intel_finish_page_flip_plane(dev, 1);
 518         }
 519
 520         if (de_iir & DE_PIPEA_VBLANK)
 521                 drm_handle_vblank(dev, 0);
 522
 523         if (de_iir & DE_PIPEB_VBLANK)
 524                 drm_handle_vblank(dev, 1);
 525
 526         /* check event from PCH */
 527         if (de_iir & DE_PCH_EVENT) {
 528                 if (pch_iir & hotplug_mask)
 529                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 530                 pch_irq_handler(dev);
 531         }
 532
 533         if (de_iir & DE_PCU_EVENT) {
 534                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 535                 i915_handle_rps_change(dev);
 536         }
 537
 538         if (IS_GEN6(dev))
 539                 gen6_pm_irq_handler(dev);
 540
 541         /* should clear PCH hotplug event before clear CPU irq */
 542         I915_WRITE(SDEIIR, pch_iir);
 543         I915_WRITE(GTIIR, gt_iir);
 544         I915_WRITE(DEIIR, de_iir);
 545
 546 done:
 547         I915_WRITE(DEIER, de_ier);
 548         POSTING_READ(DEIER);
 549
 550         return ret;
 551 }
 552
 553 /**
 554  * i915_error_work_func - do process context error handling work
 555  * @work: work struct
 556  *
 557  * Fire an error uevent so userspace can see that a hang or error
 558  * was detected.
 559  */
 560 static void i915_error_work_func(struct work_struct *work)
 561 {
 562         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 563                                                     error_work);
 564         struct drm_device *dev = dev_priv->dev;
 565         char *error_event[] = { "ERROR=1", NULL };
 566         char *reset_event[] = { "RESET=1", NULL };
 567         char *reset_done_event[] = { "ERROR=0", NULL };
 568
 569         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 570
 571         if (atomic_read(&dev_priv->mm.wedged)) {
 572                 DRM_DEBUG_DRIVER("resetting chip\n");
 573                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 574                 if (!i915_reset(dev, GRDOM_RENDER)) {
 575                         atomic_set(&dev_priv->mm.wedged, 0);
 576                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 577                 }
 578                 complete_all(&dev_priv->error_completion);
 579         }
 580 }
 581
 582 #ifdef CONFIG_DEBUG_FS
 583 static struct drm_i915_error_object *
 584 i915_error_object_create(struct drm_i915_private *dev_priv,
 585                          struct drm_i915_gem_object *src)
 586 {
 587         struct drm_i915_error_object *dst;
 588         int page, page_count;
 589         u32 reloc_offset;
 590
 591         if (src == NULL || src->pages == NULL)
 592                 return NULL;
 593
 594         page_count = src->base.size / PAGE_SIZE;
 595
 596         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 597         if (dst == NULL)
 598                 return NULL;
 599
 600         reloc_offset = src->gtt_offset;
 601         for (page = 0; page < page_count; page++) {
 602                 unsigned long flags;
 603                 void __iomem *s;
 604                 void *d;
 605
 606                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 607                 if (d == NULL)
 608                         goto unwind;
 609
 610                 local_irq_save(flags);
 611                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 612                                              reloc_offset);
 613                 memcpy_fromio(d, s, PAGE_SIZE);
 614                 io_mapping_unmap_atomic(s);
 615                 local_irq_restore(flags);
 616
 617                 dst->pages[page] = d;
 618
 619                 reloc_offset += PAGE_SIZE;
 620         }
 621         dst->page_count = page_count;
 622         dst->gtt_offset = src->gtt_offset;
 623
 624         return dst;
 625
 626 unwind:
 627         while (page--)
 628                 kfree(dst->pages[page]);
 629         kfree(dst);
 630         return NULL;
 631 }
 632
 633 static void
 634 i915_error_object_free(struct drm_i915_error_object *obj)
 635 {
 636         int page;
 637
 638         if (obj == NULL)
 639                 return;
 640
 641         for (page = 0; page < obj->page_count; page++)
 642                 kfree(obj->pages[page]);
 643
 644         kfree(obj);
 645 }
 646
 647 static void
 648 i915_error_state_free(struct drm_device *dev,
 649                       struct drm_i915_error_state *error)
 650 {
 651         int i;
 652
 653         for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 654                 i915_error_object_free(error->batchbuffer[i]);
 655
 656         for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 657                 i915_error_object_free(error->ringbuffer[i]);
 658
 659         kfree(error->active_bo);
 660         kfree(error->overlay);
 661         kfree(error);
 662 }
 663
 664 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 665                            int count,
 666                            struct list_head *head)
 667 {
 668         struct drm_i915_gem_object *obj;
 669         int i = 0;
 670
 671         list_for_each_entry(obj, head, mm_list) {
 672                 err->size = obj->base.size;
 673                 err->name = obj->base.name;
 674                 err->seqno = obj->last_rendering_seqno;
 675                 err->gtt_offset = obj->gtt_offset;
 676                 err->read_domains = obj->base.read_domains;
 677                 err->write_domain = obj->base.write_domain;
 678                 err->fence_reg = obj->fence_reg;
 679                 err->pinned = 0;
 680                 if (obj->pin_count > 0)
 681                         err->pinned = 1;
 682                 if (obj->user_pin_count > 0)
 683                         err->pinned = -1;
 684                 err->tiling = obj->tiling_mode;
 685                 err->dirty = obj->dirty;
 686                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 687                 err->ring = obj->ring ? obj->ring->id : 0;
 688                 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
 689
 690                 if (++i == count)
 691                         break;
 692
 693                 err++;
 694         }
 695
 696         return i;
 697 }
 698
 699 static void i915_gem_record_fences(struct drm_device *dev,
 700                                    struct drm_i915_error_state *error)
 701 {
 702         struct drm_i915_private *dev_priv = dev->dev_private;
 703         int i;
 704
 705         /* Fences */
 706         switch (INTEL_INFO(dev)->gen) {
 707         case 6:
 708                 for (i = 0; i < 16; i++)
 709                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 710                 break;
 711         case 5:
 712         case 4:
 713                 for (i = 0; i < 16; i++)
 714                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 715                 break;
 716         case 3:
 717                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 718                         for (i = 0; i < 8; i++)
 719                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 720         case 2:
 721                 for (i = 0; i < 8; i++)
 722                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 723                 break;
 724
 725         }
 726 }
 727
 728 static struct drm_i915_error_object *
 729 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 730                              struct intel_ring_buffer *ring)
 731 {
 732         struct drm_i915_gem_object *obj;
 733         u32 seqno;
 734
 735         if (!ring->get_seqno)
 736                 return NULL;
 737
 738         seqno = ring->get_seqno(ring);
 739         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 740                 if (obj->ring != ring)
 741                         continue;
 742
 743                 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 744                         continue;
 745
 746                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 747                         continue;
 748
 749                 /* We need to copy these to an anonymous buffer as the simplest
 750                  * method to avoid being overwritten by userspace.
 751                  */
 752                 return i915_error_object_create(dev_priv, obj);
 753         }
 754
 755         return NULL;
 756 }
 757
 758 /**
 759  * i915_capture_error_state - capture an error record for later analysis
 760  * @dev: drm device
 761  *
 762  * Should be called when an error is detected (either a hang or an error
 763  * interrupt) to capture error state from the time of the error.  Fills
 764  * out a structure which becomes available in debugfs for user level tools
 765  * to pick up.
 766  */
 767 static void i915_capture_error_state(struct drm_device *dev)
 768 {
 769         struct drm_i915_private *dev_priv = dev->dev_private;
 770         struct drm_i915_gem_object *obj;
 771         struct drm_i915_error_state *error;
 772         unsigned long flags;
 773         int i;
 774
 775         spin_lock_irqsave(&dev_priv->error_lock, flags);
 776         error = dev_priv->first_error;
 777         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 778         if (error)
 779                 return;
 780
 781         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 782         if (!error) {
 783                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 784                 return;
 785         }
 786
 787         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 788                  dev->primary->index);
 789
 790         error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
 791         error->eir = I915_READ(EIR);
 792         error->pgtbl_er = I915_READ(PGTBL_ER);
 793         error->pipeastat = I915_READ(PIPEASTAT);
 794         error->pipebstat = I915_READ(PIPEBSTAT);
 795         error->instpm = I915_READ(INSTPM);
 796         error->error = 0;
 797         if (INTEL_INFO(dev)->gen >= 6) {
 798                 error->error = I915_READ(ERROR_GEN6);
 799
 800                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 801                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 802                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 803                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 804                 error->bcs_seqno = 0;
 805                 if (dev_priv->ring[BCS].get_seqno)
 806                         error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
 807
 808                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 809                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 810                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 811                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 812                 error->vcs_seqno = 0;
 813                 if (dev_priv->ring[VCS].get_seqno)
 814                         error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
 815         }
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 error->ipeir = I915_READ(IPEIR_I965);
 818                 error->ipehr = I915_READ(IPEHR_I965);
 819                 error->instdone = I915_READ(INSTDONE_I965);
 820                 error->instps = I915_READ(INSTPS);
 821                 error->instdone1 = I915_READ(INSTDONE1);
 822                 error->acthd = I915_READ(ACTHD_I965);
 823                 error->bbaddr = I915_READ64(BB_ADDR);
 824         } else {
 825                 error->ipeir = I915_READ(IPEIR);
 826                 error->ipehr = I915_READ(IPEHR);
 827                 error->instdone = I915_READ(INSTDONE);
 828                 error->acthd = I915_READ(ACTHD);
 829                 error->bbaddr = 0;
 830         }
 831         i915_gem_record_fences(dev, error);
 832
 833         /* Record the active batch and ring buffers */
 834         for (i = 0; i < I915_NUM_RINGS; i++) {
 835                 error->batchbuffer[i] =
 836                         i915_error_first_batchbuffer(dev_priv,
 837                                                      &dev_priv->ring[i]);
 838
 839                 error->ringbuffer[i] =
 840                         i915_error_object_create(dev_priv,
 841                                                  dev_priv->ring[i].obj);
 842         }
 843
 844         /* Record buffers on the active and pinned lists. */
 845         error->active_bo = NULL;
 846         error->pinned_bo = NULL;
 847
 848         i = 0;
 849         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 850                 i++;
 851         error->active_bo_count = i;
 852         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 853                 i++;
 854         error->pinned_bo_count = i - error->active_bo_count;
 855
 856         error->active_bo = NULL;
 857         error->pinned_bo = NULL;
 858         if (i) {
 859                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 860                                            GFP_ATOMIC);
 861                 if (error->active_bo)
 862                         error->pinned_bo =
 863                                 error->active_bo + error->active_bo_count;
 864         }
 865
 866         if (error->active_bo)
 867                 error->active_bo_count =
 868                         capture_bo_list(error->active_bo,
 869                                         error->active_bo_count,
 870                                         &dev_priv->mm.active_list);
 871
 872         if (error->pinned_bo)
 873                 error->pinned_bo_count =
 874                         capture_bo_list(error->pinned_bo,
 875                                         error->pinned_bo_count,
 876                                         &dev_priv->mm.pinned_list);
 877
 878         do_gettimeofday(&error->time);
 879
 880         error->overlay = intel_overlay_capture_error_state(dev);
 881         error->display = intel_display_capture_error_state(dev);
 882
 883         spin_lock_irqsave(&dev_priv->error_lock, flags);
 884         if (dev_priv->first_error == NULL) {
 885                 dev_priv->first_error = error;
 886                 error = NULL;
 887         }
 888         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 889
 890         if (error)
 891                 i915_error_state_free(dev, error);
 892 }
 893
 894 void i915_destroy_error_state(struct drm_device *dev)
 895 {
 896         struct drm_i915_private *dev_priv = dev->dev_private;
 897         struct drm_i915_error_state *error;
 898
 899         spin_lock(&dev_priv->error_lock);
 900         error = dev_priv->first_error;
 901         dev_priv->first_error = NULL;
 902         spin_unlock(&dev_priv->error_lock);
 903
 904         if (error)
 905                 i915_error_state_free(dev, error);
 906 }
 907 #else
 908 #define i915_capture_error_state(x)
 909 #endif
 910
 911 static void i915_report_and_clear_eir(struct drm_device *dev)
 912 {
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914         u32 eir = I915_READ(EIR);
 915
 916         if (!eir)
 917                 return;
 918
 919         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 920                eir);
 921
 922         if (IS_G4X(dev)) {
 923                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 924                         u32 ipeir = I915_READ(IPEIR_I965);
 925
 926                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 927                                I915_READ(IPEIR_I965));
 928                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 929                                I915_READ(IPEHR_I965));
 930                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 931                                I915_READ(INSTDONE_I965));
 932                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 933                                I915_READ(INSTPS));
 934                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 935                                I915_READ(INSTDONE1));
 936                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 937                                I915_READ(ACTHD_I965));
 938                         I915_WRITE(IPEIR_I965, ipeir);
 939                         POSTING_READ(IPEIR_I965);
 940                 }
 941                 if (eir & GM45_ERROR_PAGE_TABLE) {
 942                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 943                         printk(KERN_ERR "page table error\n");
 944                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 945                                pgtbl_err);
 946                         I915_WRITE(PGTBL_ER, pgtbl_err);
 947                         POSTING_READ(PGTBL_ER);
 948                 }
 949         }
 950
 951         if (!IS_GEN2(dev)) {
 952                 if (eir & I915_ERROR_PAGE_TABLE) {
 953                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 954                         printk(KERN_ERR "page table error\n");
 955                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 956                                pgtbl_err);
 957                         I915_WRITE(PGTBL_ER, pgtbl_err);
 958                         POSTING_READ(PGTBL_ER);
 959                 }
 960         }
 961
 962         if (eir & I915_ERROR_MEMORY_REFRESH) {
 963                 u32 pipea_stats = I915_READ(PIPEASTAT);
 964                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 965
 966                 printk(KERN_ERR "memory refresh error\n");
 967                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 968                        pipea_stats);
 969                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 970                        pipeb_stats);
 971                 /* pipestat has already been acked */
 972         }
 973         if (eir & I915_ERROR_INSTRUCTION) {
 974                 printk(KERN_ERR "instruction error\n");
 975                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 976                        I915_READ(INSTPM));
 977                 if (INTEL_INFO(dev)->gen < 4) {
 978                         u32 ipeir = I915_READ(IPEIR);
 979
 980                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 981                                I915_READ(IPEIR));
 982                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 983                                I915_READ(IPEHR));
 984                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 985                                I915_READ(INSTDONE));
 986                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 987                                I915_READ(ACTHD));
 988                         I915_WRITE(IPEIR, ipeir);
 989                         POSTING_READ(IPEIR);
 990                 } else {
 991                         u32 ipeir = I915_READ(IPEIR_I965);
 992
 993                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 994                                I915_READ(IPEIR_I965));
 995                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 996                                I915_READ(IPEHR_I965));
 997                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 998                                I915_READ(INSTDONE_I965));
 999                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
1000                                I915_READ(INSTPS));
1001                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1002                                I915_READ(INSTDONE1));
1003                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
1004                                I915_READ(ACTHD_I965));
1005                         I915_WRITE(IPEIR_I965, ipeir);
1006                         POSTING_READ(IPEIR_I965);
1007                 }
1008         }
1009
1010         I915_WRITE(EIR, eir);
1011         POSTING_READ(EIR);
1012         eir = I915_READ(EIR);
1013         if (eir) {
1014                 /*
1015                  * some errors might have become stuck,
1016                  * mask them.
1017                  */
1018                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1019                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1020                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1021         }
1022 }
1023
1024 /**
1025  * i915_handle_error - handle an error interrupt
1026  * @dev: drm device
1027  *
1028  * Do some basic checking of regsiter state at error interrupt time and
1029  * dump it to the syslog.  Also call i915_capture_error_state() to make
1030  * sure we get a record and make it available in debugfs.  Fire a uevent
1031  * so userspace knows something bad happened (should trigger collection
1032  * of a ring dump etc.).
1033  */
1034 void i915_handle_error(struct drm_device *dev, bool wedged)
1035 {
1036         struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038         i915_capture_error_state(dev);
1039         i915_report_and_clear_eir(dev);
1040
1041         if (wedged) {
1042                 INIT_COMPLETION(dev_priv->error_completion);
1043                 atomic_set(&dev_priv->mm.wedged, 1);
1044
1045                 /*
1046                  * Wakeup waiting processes so they don't hang
1047                  */
1048                 wake_up_all(&dev_priv->ring[RCS].irq_queue);
1049                 if (HAS_BSD(dev))
1050                         wake_up_all(&dev_priv->ring[VCS].irq_queue);
1051                 if (HAS_BLT(dev))
1052                         wake_up_all(&dev_priv->ring[BCS].irq_queue);
1053         }
1054
1055         queue_work(dev_priv->wq, &dev_priv->error_work);
1056 }
1057
1058 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1059 {
1060         drm_i915_private_t *dev_priv = dev->dev_private;
1061         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1063         struct drm_i915_gem_object *obj;
1064         struct intel_unpin_work *work;
1065         unsigned long flags;
1066         bool stall_detected;
1067
1068         /* Ignore early vblank irqs */
1069         if (intel_crtc == NULL)
1070                 return;
1071
1072         spin_lock_irqsave(&dev->event_lock, flags);
1073         work = intel_crtc->unpin_work;
1074
1075         if (work == NULL || work->pending || !work->enable_stall_check) {
1076                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1077                 spin_unlock_irqrestore(&dev->event_lock, flags);
1078                 return;
1079         }
1080
1081         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1082         obj = work->pending_flip_obj;
1083         if (INTEL_INFO(dev)->gen >= 4) {
1084                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
1085                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1086         } else {
1087                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
1088                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1089                                                         crtc->y * crtc->fb->pitch +
1090                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1091         }
1092
1093         spin_unlock_irqrestore(&dev->event_lock, flags);
1094
1095         if (stall_detected) {
1096                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1097                 intel_prepare_page_flip(dev, intel_crtc->plane);
1098         }
1099 }
1100
1101 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1102 {
1103         struct drm_device *dev = (struct drm_device *) arg;
1104         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1105         struct drm_i915_master_private *master_priv;
1106         u32 iir, new_iir;
1107         u32 pipea_stats, pipeb_stats;
1108         u32 vblank_status;
1109         int vblank = 0;
1110         unsigned long irqflags;
1111         int irq_received;
1112         int ret = IRQ_NONE;
1113
1114         atomic_inc(&dev_priv->irq_received);
1115
1116         if (HAS_PCH_SPLIT(dev))
1117                 return ironlake_irq_handler(dev);
1118
1119         iir = I915_READ(IIR);
1120
1121         if (INTEL_INFO(dev)->gen >= 4)
1122                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1123         else
1124                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1125
1126         for (;;) {
1127                 irq_received = iir != 0;
1128
1129                 /* Can't rely on pipestat interrupt bit in iir as it might
1130                  * have been cleared after the pipestat interrupt was received.
1131                  * It doesn't set the bit in iir again, but it still produces
1132                  * interrupts (for non-MSI).
1133                  */
1134                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1135                 pipea_stats = I915_READ(PIPEASTAT);
1136                 pipeb_stats = I915_READ(PIPEBSTAT);
1137
1138                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1139                         i915_handle_error(dev, false);
1140
1141                 /*
1142                  * Clear the PIPE(A|B)STAT regs before the IIR
1143                  */
1144                 if (pipea_stats & 0x8000ffff) {
1145                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1146                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1147                         I915_WRITE(PIPEASTAT, pipea_stats);
1148                         irq_received = 1;
1149                 }
1150
1151                 if (pipeb_stats & 0x8000ffff) {
1152                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1153                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1154                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1155                         irq_received = 1;
1156                 }
1157                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1158
1159                 if (!irq_received)
1160                         break;
1161
1162                 ret = IRQ_HANDLED;
1163
1164                 /* Consume port.  Then clear IIR or we'll miss events */
1165                 if ((I915_HAS_HOTPLUG(dev)) &&
1166                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1167                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1168
1169                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1170                                   hotplug_status);
1171                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1172                                 queue_work(dev_priv->wq,
1173                                            &dev_priv->hotplug_work);
1174
1175                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1176                         I915_READ(PORT_HOTPLUG_STAT);
1177                 }
1178
1179                 I915_WRITE(IIR, iir);
1180                 new_iir = I915_READ(IIR); /* Flush posted writes */
1181
1182                 if (dev->primary->master) {
1183                         master_priv = dev->primary->master->driver_priv;
1184                         if (master_priv->sarea_priv)
1185                                 master_priv->sarea_priv->last_dispatch =
1186                                         READ_BREADCRUMB(dev_priv);
1187                 }
1188
1189                 if (iir & I915_USER_INTERRUPT)
1190                         notify_ring(dev, &dev_priv->ring[RCS]);
1191                 if (iir & I915_BSD_USER_INTERRUPT)
1192                         notify_ring(dev, &dev_priv->ring[VCS]);
1193
1194                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1195                         intel_prepare_page_flip(dev, 0);
1196                         if (dev_priv->flip_pending_is_done)
1197                                 intel_finish_page_flip_plane(dev, 0);
1198                 }
1199
1200                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1201                         intel_prepare_page_flip(dev, 1);
1202                         if (dev_priv->flip_pending_is_done)
1203                                 intel_finish_page_flip_plane(dev, 1);
1204                 }
1205
1206                 if (pipea_stats & vblank_status &&
1207                     drm_handle_vblank(dev, 0)) {
1208                         vblank++;
1209                         if (!dev_priv->flip_pending_is_done) {
1210                                 i915_pageflip_stall_check(dev, 0);
1211                                 intel_finish_page_flip(dev, 0);
1212                         }
1213                 }
1214
1215                 if (pipeb_stats & vblank_status &&
1216                     drm_handle_vblank(dev, 1)) {
1217                         vblank++;
1218                         if (!dev_priv->flip_pending_is_done) {
1219                                 i915_pageflip_stall_check(dev, 1);
1220                                 intel_finish_page_flip(dev, 1);
1221                         }
1222                 }
1223
1224                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1225                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1226                     (iir & I915_ASLE_INTERRUPT))
1227                         intel_opregion_asle_intr(dev);
1228
1229                 /* With MSI, interrupts are only generated when iir
1230                  * transitions from zero to nonzero.  If another bit got
1231                  * set while we were handling the existing iir bits, then
1232                  * we would never get another interrupt.
1233                  *
1234                  * This is fine on non-MSI as well, as if we hit this path
1235                  * we avoid exiting the interrupt handler only to generate
1236                  * another one.
1237                  *
1238                  * Note that for MSI this could cause a stray interrupt report
1239                  * if an interrupt landed in the time between writing IIR and
1240                  * the posting read.  This should be rare enough to never
1241                  * trigger the 99% of 100,000 interrupts test for disabling
1242                  * stray interrupts.
1243                  */
1244                 iir = new_iir;
1245         }
1246
1247         return ret;
1248 }
1249
1250 static int i915_emit_irq(struct drm_device * dev)
1251 {
1252         drm_i915_private_t *dev_priv = dev->dev_private;
1253         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1254
1255         i915_kernel_lost_context(dev);
1256
1257         DRM_DEBUG_DRIVER("\n");
1258
1259         dev_priv->counter++;
1260         if (dev_priv->counter > 0x7FFFFFFFUL)
1261                 dev_priv->counter = 1;
1262         if (master_priv->sarea_priv)
1263                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1264
1265         if (BEGIN_LP_RING(4) == 0) {
1266                 OUT_RING(MI_STORE_DWORD_INDEX);
1267                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1268                 OUT_RING(dev_priv->counter);
1269                 OUT_RING(MI_USER_INTERRUPT);
1270                 ADVANCE_LP_RING();
1271         }
1272
1273         return dev_priv->counter;
1274 }
1275
1276 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1277 {
1278         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1279         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1280         int ret = 0;
1281         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1282
1283         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1284                   READ_BREADCRUMB(dev_priv));
1285
1286         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1287                 if (master_priv->sarea_priv)
1288                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1289                 return 0;
1290         }
1291
1292         if (master_priv->sarea_priv)
1293                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1294
1295         if (ring->irq_get(ring)) {
1296                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1297                             READ_BREADCRUMB(dev_priv) >= irq_nr);
1298                 ring->irq_put(ring);
1299         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1300                 ret = -EBUSY;
1301
1302         if (ret == -EBUSY) {
1303                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1304                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1305         }
1306
1307         return ret;
1308 }
1309
1310 /* Needs the lock as it touches the ring.
1311  */
1312 int i915_irq_emit(struct drm_device *dev, void *data,
1313                          struct drm_file *file_priv)
1314 {
1315         drm_i915_private_t *dev_priv = dev->dev_private;
1316         drm_i915_irq_emit_t *emit = data;
1317         int result;
1318
1319         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1320                 DRM_ERROR("called with no initialization\n");
1321                 return -EINVAL;
1322         }
1323
1324         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1325
1326         mutex_lock(&dev->struct_mutex);
1327         result = i915_emit_irq(dev);
1328         mutex_unlock(&dev->struct_mutex);
1329
1330         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1331                 DRM_ERROR("copy_to_user\n");
1332                 return -EFAULT;
1333         }
1334
1335         return 0;
1336 }
1337
1338 /* Doesn't need the hardware lock.
1339  */
1340 int i915_irq_wait(struct drm_device *dev, void *data,
1341                          struct drm_file *file_priv)
1342 {
1343         drm_i915_private_t *dev_priv = dev->dev_private;
1344         drm_i915_irq_wait_t *irqwait = data;
1345
1346         if (!dev_priv) {
1347                 DRM_ERROR("called with no initialization\n");
1348                 return -EINVAL;
1349         }
1350
1351         return i915_wait_irq(dev, irqwait->irq_seq);
1352 }
1353
1354 static void i915_vblank_work_func(struct work_struct *work)
1355 {
1356         drm_i915_private_t *dev_priv =
1357                 container_of(work, drm_i915_private_t, vblank_work);
1358
1359         if (atomic_read(&dev_priv->vblank_enabled)) {
1360                 if (!dev_priv->vblank_pm_qos.pm_qos_class)
1361                         pm_qos_add_request(&dev_priv->vblank_pm_qos,
1362                                            PM_QOS_CPU_DMA_LATENCY,
1363                                            15); //>=20 won't work
1364         } else {
1365                 if (dev_priv->vblank_pm_qos.pm_qos_class)
1366                         pm_qos_remove_request(&dev_priv->vblank_pm_qos);
1367         }
1368 }
1369
1370 /* Called from drm generic code, passed 'crtc' which
1371  * we use as a pipe index
1372  */
1373 int i915_enable_vblank(struct drm_device *dev, int pipe)
1374 {
1375         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1376         unsigned long irqflags;
1377
1378         if (!i915_pipe_enabled(dev, pipe))
1379                 return -EINVAL;
1380
1381         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1382         if (HAS_PCH_SPLIT(dev))
1383                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1384                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1385         else if (INTEL_INFO(dev)->gen >= 4)
1386                 i915_enable_pipestat(dev_priv, pipe,
1387                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1388         else
1389                 i915_enable_pipestat(dev_priv, pipe,
1390                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1391         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1392
1393         /* gen3 platforms have an issue with vsync interrupts not reaching
1394          * cpu during deep c-state sleep (>C1), so we need to install a
1395          * PM QoS handle to prevent C-state starvation of the GPU.
1396          */
1397         if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) {
1398                 atomic_inc(&dev_priv->vblank_enabled);
1399                 queue_work(dev_priv->wq, &dev_priv->vblank_work);
1400         }
1401
1402         return 0;
1403 }
1404
1405 /* Called from drm generic code, passed 'crtc' which
1406  * we use as a pipe index
1407  */
1408 void i915_disable_vblank(struct drm_device *dev, int pipe)
1409 {
1410         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1411         unsigned long irqflags;
1412
1413         if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) {
1414                 atomic_dec(&dev_priv->vblank_enabled);
1415                 queue_work(dev_priv->wq, &dev_priv->vblank_work);
1416         }
1417
1418         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1419         if (HAS_PCH_SPLIT(dev))
1420                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1421                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1422         else
1423                 i915_disable_pipestat(dev_priv, pipe,
1424                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1425                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1426         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1427 }
1428
1429 /* Set the vblank monitor pipe
1430  */
1431 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1432                          struct drm_file *file_priv)
1433 {
1434         drm_i915_private_t *dev_priv = dev->dev_private;
1435
1436         if (!dev_priv) {
1437                 DRM_ERROR("called with no initialization\n");
1438                 return -EINVAL;
1439         }
1440
1441         return 0;
1442 }
1443
1444 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1445                          struct drm_file *file_priv)
1446 {
1447         drm_i915_private_t *dev_priv = dev->dev_private;
1448         drm_i915_vblank_pipe_t *pipe = data;
1449
1450         if (!dev_priv) {
1451                 DRM_ERROR("called with no initialization\n");
1452                 return -EINVAL;
1453         }
1454
1455         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1456
1457         return 0;
1458 }
1459
1460 /**
1461  * Schedule buffer swap at given vertical blank.
1462  */
1463 int i915_vblank_swap(struct drm_device *dev, void *data,
1464                      struct drm_file *file_priv)
1465 {
1466         /* The delayed swap mechanism was fundamentally racy, and has been
1467          * removed.  The model was that the client requested a delayed flip/swap
1468          * from the kernel, then waited for vblank before continuing to perform
1469          * rendering.  The problem was that the kernel might wake the client
1470          * up before it dispatched the vblank swap (since the lock has to be
1471          * held while touching the ringbuffer), in which case the client would
1472          * clear and start the next frame before the swap occurred, and
1473          * flicker would occur in addition to likely missing the vblank.
1474          *
1475          * In the absence of this ioctl, userland falls back to a correct path
1476          * of waiting for a vblank, then dispatching the swap on its own.
1477          * Context switching to userland and back is plenty fast enough for
1478          * meeting the requirements of vblank swapping.
1479          */
1480         return -EINVAL;
1481 }
1482
1483 static u32
1484 ring_last_seqno(struct intel_ring_buffer *ring)
1485 {
1486         return list_entry(ring->request_list.prev,
1487                           struct drm_i915_gem_request, list)->seqno;
1488 }
1489
1490 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1491 {
1492         if (list_empty(&ring->request_list) ||
1493             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1494                 /* Issue a wake-up to catch stuck h/w. */
1495                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1496                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1497                                   ring->name,
1498                                   ring->waiting_seqno,
1499                                   ring->get_seqno(ring));
1500                         wake_up_all(&ring->irq_queue);
1501                         *err = true;
1502                 }
1503                 return true;
1504         }
1505         return false;
1506 }
1507
1508 static bool kick_ring(struct intel_ring_buffer *ring)
1509 {
1510         struct drm_device *dev = ring->dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         u32 tmp = I915_READ_CTL(ring);
1513         if (tmp & RING_WAIT) {
1514                 DRM_ERROR("Kicking stuck wait on %s\n",
1515                           ring->name);
1516                 I915_WRITE_CTL(ring, tmp);
1517                 return true;
1518         }
1519         if (IS_GEN6(dev) &&
1520             (tmp & RING_WAIT_SEMAPHORE)) {
1521                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1522                           ring->name);
1523                 I915_WRITE_CTL(ring, tmp);
1524                 return true;
1525         }
1526         return false;
1527 }
1528
1529 /**
1530  * This is called when the chip hasn't reported back with completed
1531  * batchbuffers in a long time. The first time this is called we simply record
1532  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1533  * again, we assume the chip is wedged and try to fix it.
1534  */
1535 void i915_hangcheck_elapsed(unsigned long data)
1536 {
1537         struct drm_device *dev = (struct drm_device *)data;
1538         drm_i915_private_t *dev_priv = dev->dev_private;
1539         uint32_t acthd, instdone, instdone1;
1540         bool err = false;
1541
1542         /* If all work is done then ACTHD clearly hasn't advanced. */
1543         if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1544             i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1545             i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1546                 dev_priv->hangcheck_count = 0;
1547                 if (err)
1548                         goto repeat;
1549                 return;
1550         }
1551
1552         if (INTEL_INFO(dev)->gen < 4) {
1553                 acthd = I915_READ(ACTHD);
1554                 instdone = I915_READ(INSTDONE);
1555                 instdone1 = 0;
1556         } else {
1557                 acthd = I915_READ(ACTHD_I965);
1558                 instdone = I915_READ(INSTDONE_I965);
1559                 instdone1 = I915_READ(INSTDONE1);
1560         }
1561
1562         if (dev_priv->last_acthd == acthd &&
1563             dev_priv->last_instdone == instdone &&
1564             dev_priv->last_instdone1 == instdone1) {
1565                 if (dev_priv->hangcheck_count++ > 1) {
1566                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1567
1568                         if (!IS_GEN2(dev)) {
1569                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1570                                  * If so we can simply poke the RB_WAIT bit
1571                                  * and break the hang. This should work on
1572                                  * all but the second generation chipsets.
1573                                  */
1574
1575                                 if (kick_ring(&dev_priv->ring[RCS]))
1576                                         goto repeat;
1577
1578                                 if (HAS_BSD(dev) &&
1579                                     kick_ring(&dev_priv->ring[VCS]))
1580                                         goto repeat;
1581
1582                                 if (HAS_BLT(dev) &&
1583                                     kick_ring(&dev_priv->ring[BCS]))
1584                                         goto repeat;
1585                         }
1586
1587                         i915_handle_error(dev, true);
1588                         return;
1589                 }
1590         } else {
1591                 dev_priv->hangcheck_count = 0;
1592
1593                 dev_priv->last_acthd = acthd;
1594                 dev_priv->last_instdone = instdone;
1595                 dev_priv->last_instdone1 = instdone1;
1596         }
1597
1598 repeat:
1599         /* Reset timer case chip hangs without another request being added */
1600         mod_timer(&dev_priv->hangcheck_timer,
1601                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1602 }
1603
1604 /* drm_dma.h hooks
1605 */
1606 static void ironlake_irq_preinstall(struct drm_device *dev)
1607 {
1608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1609
1610         I915_WRITE(HWSTAM, 0xeffe);
1611
1612         /* XXX hotplug from PCH */
1613
1614         I915_WRITE(DEIMR, 0xffffffff);
1615         I915_WRITE(DEIER, 0x0);
1616         POSTING_READ(DEIER);
1617
1618         /* and GT */
1619         I915_WRITE(GTIMR, 0xffffffff);
1620         I915_WRITE(GTIER, 0x0);
1621         POSTING_READ(GTIER);
1622
1623         /* south display irq */
1624         I915_WRITE(SDEIMR, 0xffffffff);
1625         I915_WRITE(SDEIER, 0x0);
1626         POSTING_READ(SDEIER);
1627 }
1628
1629 static int ironlake_irq_postinstall(struct drm_device *dev)
1630 {
1631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1632         /* enable kind of interrupts always enabled */
1633         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1634                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1635         u32 render_irqs;
1636         u32 hotplug_mask;
1637
1638         dev_priv->irq_mask = ~display_mask;
1639
1640         /* should always can generate irq */
1641         I915_WRITE(DEIIR, I915_READ(DEIIR));
1642         I915_WRITE(DEIMR, dev_priv->irq_mask);
1643         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1644         POSTING_READ(DEIER);
1645
1646         dev_priv->gt_irq_mask = ~0;
1647
1648         I915_WRITE(GTIIR, I915_READ(GTIIR));
1649         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1650
1651         if (IS_GEN6(dev))
1652                 render_irqs =
1653                         GT_USER_INTERRUPT |
1654                         GT_GEN6_BSD_USER_INTERRUPT |
1655                         GT_BLT_USER_INTERRUPT;
1656         else
1657                 render_irqs =
1658                         GT_USER_INTERRUPT |
1659                         GT_PIPE_NOTIFY |
1660                         GT_BSD_USER_INTERRUPT;
1661         I915_WRITE(GTIER, render_irqs);
1662         POSTING_READ(GTIER);
1663
1664         if (HAS_PCH_CPT(dev)) {
1665                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1666                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1667         } else {
1668                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1669                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1670                 hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
1671                 I915_WRITE(FDI_RXA_IMR, 0);
1672                 I915_WRITE(FDI_RXB_IMR, 0);
1673         }
1674
1675         dev_priv->pch_irq_mask = ~hotplug_mask;
1676
1677         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1678         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1679         I915_WRITE(SDEIER, hotplug_mask);
1680         POSTING_READ(SDEIER);
1681
1682         if (IS_IRONLAKE_M(dev)) {
1683                 /* Clear & enable PCU event interrupts */
1684                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1685                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1686                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1687         }
1688
1689         return 0;
1690 }
1691
1692 void i915_driver_irq_preinstall(struct drm_device * dev)
1693 {
1694         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1695
1696         atomic_set(&dev_priv->irq_received, 0);
1697         atomic_set(&dev_priv->vblank_enabled, 0);
1698
1699         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1700         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1701         INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_func);
1702
1703         if (HAS_PCH_SPLIT(dev)) {
1704                 ironlake_irq_preinstall(dev);
1705                 return;
1706         }
1707
1708         if (I915_HAS_HOTPLUG(dev)) {
1709                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1710                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1711         }
1712
1713         I915_WRITE(HWSTAM, 0xeffe);
1714         I915_WRITE(PIPEASTAT, 0);
1715         I915_WRITE(PIPEBSTAT, 0);
1716         I915_WRITE(IMR, 0xffffffff);
1717         I915_WRITE(IER, 0x0);
1718         POSTING_READ(IER);
1719 }
1720
1721 /*
1722  * Must be called after intel_modeset_init or hotplug interrupts won't be
1723  * enabled correctly.
1724  */
1725 int i915_driver_irq_postinstall(struct drm_device *dev)
1726 {
1727         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1728         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1729         u32 error_mask;
1730
1731         DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1732         if (HAS_BSD(dev))
1733                 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1734         if (HAS_BLT(dev))
1735                 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1736
1737         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1738
1739         if (HAS_PCH_SPLIT(dev))
1740                 return ironlake_irq_postinstall(dev);
1741
1742         /* Unmask the interrupts that we always want on. */
1743         dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1744
1745         dev_priv->pipestat[0] = 0;
1746         dev_priv->pipestat[1] = 0;
1747
1748         if (I915_HAS_HOTPLUG(dev)) {
1749                 /* Enable in IER... */
1750                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1751                 /* and unmask in IMR */
1752                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1753         }
1754
1755         /*
1756          * Enable some error detection, note the instruction error mask
1757          * bit is reserved, so we leave it masked.
1758          */
1759         if (IS_G4X(dev)) {
1760                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1761                                GM45_ERROR_MEM_PRIV |
1762                                GM45_ERROR_CP_PRIV |
1763                                I915_ERROR_MEMORY_REFRESH);
1764         } else {
1765                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1766                                I915_ERROR_MEMORY_REFRESH);
1767         }
1768         I915_WRITE(EMR, error_mask);
1769
1770         I915_WRITE(IMR, dev_priv->irq_mask);
1771         I915_WRITE(IER, enable_mask);
1772         POSTING_READ(IER);
1773
1774         if (I915_HAS_HOTPLUG(dev)) {
1775                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1776
1777                 /* Note HDMI and DP share bits */
1778                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1779                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1780                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1781                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1782                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1783                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1784                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1785                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1786                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1787                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1788                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1789                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1790
1791                         /* Programming the CRT detection parameters tends
1792                            to generate a spurious hotplug event about three
1793                            seconds later.  So just do it once.
1794                         */
1795                         if (IS_G4X(dev))
1796                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1797                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1798                 }
1799
1800                 /* Ignore TV since it's buggy */
1801
1802                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1803         }
1804
1805         intel_opregion_enable_asle(dev);
1806
1807         return 0;
1808 }
1809
1810 static void ironlake_irq_uninstall(struct drm_device *dev)
1811 {
1812         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1813         I915_WRITE(HWSTAM, 0xffffffff);
1814
1815         I915_WRITE(DEIMR, 0xffffffff);
1816         I915_WRITE(DEIER, 0x0);
1817         I915_WRITE(DEIIR, I915_READ(DEIIR));
1818
1819         I915_WRITE(GTIMR, 0xffffffff);
1820         I915_WRITE(GTIER, 0x0);
1821         I915_WRITE(GTIIR, I915_READ(GTIIR));
1822 }
1823
1824 void i915_driver_irq_uninstall(struct drm_device * dev)
1825 {
1826         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1827
1828         if (!dev_priv)
1829                 return;
1830
1831         dev_priv->vblank_pipe = 0;
1832
1833         if (HAS_PCH_SPLIT(dev)) {
1834                 ironlake_irq_uninstall(dev);
1835                 return;
1836         }
1837
1838         if (I915_HAS_HOTPLUG(dev)) {
1839                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1840                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1841         }
1842
1843         I915_WRITE(HWSTAM, 0xffffffff);
1844         I915_WRITE(PIPEASTAT, 0);
1845         I915_WRITE(PIPEBSTAT, 0);
1846         I915_WRITE(IMR, 0xffffffff);
1847         I915_WRITE(IER, 0x0);
1848
1849         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1850         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1851         I915_WRITE(IIR, I915_READ(IIR));
1852 }