drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include "intel_drv.h"
  29 #include "i915_drv.h"
  30
  31 static const struct {
  32         int clock;
  33         u32 config;
  34 } hdmi_audio_clock[] = {
  35         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  36         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  37         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  38         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  39         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  40         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  41         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  42         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  43         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  44         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  45 };
  46
  47 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
  48 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
  49 {
  50         int i;
  51
  52         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
  53                 if (mode->clock == hdmi_audio_clock[i].clock)
  54                         break;
  55         }
  56
  57         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
  58                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
  59                 i = 1;
  60         }
  61
  62         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
  63                       hdmi_audio_clock[i].clock,
  64                       hdmi_audio_clock[i].config);
  65
  66         return hdmi_audio_clock[i].config;
  67 }
  68
  69 static bool intel_eld_uptodate(struct drm_connector *connector,
  70                                int reg_eldv, uint32_t bits_eldv,
  71                                int reg_elda, uint32_t bits_elda,
  72                                int reg_edid)
  73 {
  74         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  75         uint8_t *eld = connector->eld;
  76         uint32_t tmp;
  77         int i;
  78
  79         tmp = I915_READ(reg_eldv);
  80         tmp &= bits_eldv;
  81
  82         if (!eld[0])
  83                 return !tmp;
  84
  85         if (!tmp)
  86                 return false;
  87
  88         tmp = I915_READ(reg_elda);
  89         tmp &= ~bits_elda;
  90         I915_WRITE(reg_elda, tmp);
  91
  92         for (i = 0; i < eld[2]; i++)
  93                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  94                         return false;
  95
  96         return true;
  97 }
  98
  99 static void g4x_write_eld(struct drm_connector *connector,
 100                           struct intel_encoder *encoder,
 101                           struct drm_display_mode *mode)
 102 {
 103         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 104         uint8_t *eld = connector->eld;
 105         uint32_t eldv;
 106         uint32_t tmp;
 107         int len, i;
 108
 109         tmp = I915_READ(G4X_AUD_VID_DID);
 110         if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
 111                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 112         else
 113                 eldv = G4X_ELDV_DEVCTG;
 114
 115         if (intel_eld_uptodate(connector,
 116                                G4X_AUD_CNTL_ST, eldv,
 117                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
 118                                G4X_HDMIW_HDMIEDID))
 119                 return;
 120
 121         tmp = I915_READ(G4X_AUD_CNTL_ST);
 122         tmp &= ~(eldv | G4X_ELD_ADDR);
 123         len = (tmp >> 9) & 0x1f;                /* ELD buffer size */
 124         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 125
 126         if (!eld[0])
 127                 return;
 128
 129         len = min_t(int, eld[2], len);
 130         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 131         for (i = 0; i < len; i++)
 132                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 133
 134         tmp = I915_READ(G4X_AUD_CNTL_ST);
 135         tmp |= eldv;
 136         I915_WRITE(G4X_AUD_CNTL_ST, tmp);
 137 }
 138
 139 static void haswell_write_eld(struct drm_connector *connector,
 140                               struct intel_encoder *encoder,
 141                               struct drm_display_mode *mode)
 142 {
 143         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 144         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 145         uint8_t *eld = connector->eld;
 146         uint32_t eldv;
 147         uint32_t tmp;
 148         int len, i;
 149         enum pipe pipe = intel_crtc->pipe;
 150         enum port port;
 151         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
 152         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
 153         int aud_config = HSW_AUD_CFG(pipe);
 154         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
 155
 156         /* Audio output enable */
 157         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
 158         tmp = I915_READ(aud_cntrl_st2);
 159         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
 160         I915_WRITE(aud_cntrl_st2, tmp);
 161         POSTING_READ(aud_cntrl_st2);
 162
 163         /* Set ELD valid state */
 164         tmp = I915_READ(aud_cntrl_st2);
 165         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
 166         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
 167         I915_WRITE(aud_cntrl_st2, tmp);
 168         tmp = I915_READ(aud_cntrl_st2);
 169         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
 170
 171         /* Enable HDMI mode */
 172         tmp = I915_READ(aud_config);
 173         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
 174         /* clear N_programing_enable and N_value_index */
 175         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
 176         I915_WRITE(aud_config, tmp);
 177
 178         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 179
 180         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
 181
 182         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 183                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 184         else
 185                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 186
 187         if (intel_eld_uptodate(connector,
 188                                aud_cntrl_st2, eldv,
 189                                aud_cntl_st, IBX_ELD_ADDRESS,
 190                                hdmiw_hdmiedid))
 191                 return;
 192
 193         tmp = I915_READ(aud_cntrl_st2);
 194         tmp &= ~eldv;
 195         I915_WRITE(aud_cntrl_st2, tmp);
 196
 197         if (!eld[0])
 198                 return;
 199
 200         tmp = I915_READ(aud_cntl_st);
 201         tmp &= ~IBX_ELD_ADDRESS;
 202         I915_WRITE(aud_cntl_st, tmp);
 203         port = (tmp >> 29) & DIP_PORT_SEL_MASK;         /* DIP_Port_Select, 0x1 = PortB */
 204         DRM_DEBUG_DRIVER("port num:%d\n", port);
 205
 206         len = min_t(int, eld[2], 21);   /* 84 bytes of hw ELD buffer */
 207         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 208         for (i = 0; i < len; i++)
 209                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 210
 211         tmp = I915_READ(aud_cntrl_st2);
 212         tmp |= eldv;
 213         I915_WRITE(aud_cntrl_st2, tmp);
 214 }
 215
 216 static void ironlake_write_eld(struct drm_connector *connector,
 217                                struct intel_encoder *encoder,
 218                                struct drm_display_mode *mode)
 219 {
 220         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 221         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 222         uint8_t *eld = connector->eld;
 223         uint32_t eldv;
 224         uint32_t tmp;
 225         int len, i;
 226         int hdmiw_hdmiedid;
 227         int aud_config;
 228         int aud_cntl_st;
 229         int aud_cntrl_st2;
 230         enum pipe pipe = intel_crtc->pipe;
 231         enum port port;
 232
 233         if (HAS_PCH_IBX(connector->dev)) {
 234                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 235                 aud_config = IBX_AUD_CFG(pipe);
 236                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 237                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 238         } else if (IS_VALLEYVIEW(connector->dev)) {
 239                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 240                 aud_config = VLV_AUD_CFG(pipe);
 241                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 242                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 243         } else {
 244                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 245                 aud_config = CPT_AUD_CFG(pipe);
 246                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 247                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 248         }
 249
 250         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 251
 252         if (IS_VALLEYVIEW(connector->dev))  {
 253                 struct intel_digital_port *intel_dig_port;
 254
 255                 intel_dig_port = enc_to_dig_port(&encoder->base);
 256                 port = intel_dig_port->port;
 257         } else {
 258                 tmp = I915_READ(aud_cntl_st);
 259                 port = (tmp >> 29) & DIP_PORT_SEL_MASK;
 260                 /* DIP_Port_Select, 0x1 = PortB */
 261         }
 262
 263         if (!port) {
 264                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 265                 /* operate blindly on all ports */
 266                 eldv = IBX_ELD_VALIDB;
 267                 eldv |= IBX_ELD_VALIDB << 4;
 268                 eldv |= IBX_ELD_VALIDB << 8;
 269         } else {
 270                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(port));
 271                 eldv = IBX_ELD_VALIDB << ((port - 1) * 4);
 272         }
 273
 274         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
 275                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 276         else
 277                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 278
 279         if (intel_eld_uptodate(connector,
 280                                aud_cntrl_st2, eldv,
 281                                aud_cntl_st, IBX_ELD_ADDRESS,
 282                                hdmiw_hdmiedid))
 283                 return;
 284
 285         tmp = I915_READ(aud_cntrl_st2);
 286         tmp &= ~eldv;
 287         I915_WRITE(aud_cntrl_st2, tmp);
 288
 289         if (!eld[0])
 290                 return;
 291
 292         tmp = I915_READ(aud_cntl_st);
 293         tmp &= ~IBX_ELD_ADDRESS;
 294         I915_WRITE(aud_cntl_st, tmp);
 295
 296         len = min_t(int, eld[2], 21);   /* 84 bytes of hw ELD buffer */
 297         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 298         for (i = 0; i < len; i++)
 299                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 300
 301         tmp = I915_READ(aud_cntrl_st2);
 302         tmp |= eldv;
 303         I915_WRITE(aud_cntrl_st2, tmp);
 304 }
 305
 306 void intel_write_eld(struct intel_encoder *intel_encoder)
 307 {
 308         struct drm_encoder *encoder = &intel_encoder->base;
 309         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 310         struct drm_display_mode *mode = &crtc->config.adjusted_mode;
 311         struct drm_connector *connector;
 312         struct drm_device *dev = encoder->dev;
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         connector = drm_select_eld(encoder, mode);
 316         if (!connector)
 317                 return;
 318
 319         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 320                          connector->base.id,
 321                          connector->name,
 322                          connector->encoder->base.id,
 323                          connector->encoder->name);
 324
 325         /* ELD Conn_Type */
 326         connector->eld[5] &= ~(3 << 2);
 327         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 328                 connector->eld[5] |= (1 << 2);
 329
 330         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
 331
 332         if (dev_priv->display.write_eld)
 333                 dev_priv->display.write_eld(connector, intel_encoder, mode);
 334 }
 335
 336 /**
 337  * intel_init_audio - Set up chip specific audio functions
 338  * @dev: drm device
 339  */
 340 void intel_init_audio(struct drm_device *dev)
 341 {
 342         struct drm_i915_private *dev_priv = dev->dev_private;
 343
 344         if (IS_G4X(dev))
 345                 dev_priv->display.write_eld = g4x_write_eld;
 346         else if (IS_VALLEYVIEW(dev))
 347                 dev_priv->display.write_eld = ironlake_write_eld;
 348         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 349                 dev_priv->display.write_eld = haswell_write_eld;
 350         else if (HAS_PCH_SPLIT(dev))
 351                 dev_priv->display.write_eld = ironlake_write_eld;
 352 }