drivers/gpu/drm/i915/intel_audio.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/kernel.h>
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_edid.h>
  28 #include "intel_drv.h"
  29 #include "i915_drv.h"
  30
  31 static const struct {
  32         int clock;
  33         u32 config;
  34 } hdmi_audio_clock[] = {
  35         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  36         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  37         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  38         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  39         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  40         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  41         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  42         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  43         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
  44         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
  45 };
  46
  47 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
  48 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
  49 {
  50         int i;
  51
  52         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
  53                 if (mode->clock == hdmi_audio_clock[i].clock)
  54                         break;
  55         }
  56
  57         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
  58                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
  59                 i = 1;
  60         }
  61
  62         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
  63                       hdmi_audio_clock[i].clock,
  64                       hdmi_audio_clock[i].config);
  65
  66         return hdmi_audio_clock[i].config;
  67 }
  68
  69 static bool intel_eld_uptodate(struct drm_connector *connector,
  70                                int reg_eldv, uint32_t bits_eldv,
  71                                int reg_elda, uint32_t bits_elda,
  72                                int reg_edid)
  73 {
  74         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  75         uint8_t *eld = connector->eld;
  76         uint32_t i;
  77
  78         i = I915_READ(reg_eldv);
  79         i &= bits_eldv;
  80
  81         if (!eld[0])
  82                 return !i;
  83
  84         if (!i)
  85                 return false;
  86
  87         i = I915_READ(reg_elda);
  88         i &= ~bits_elda;
  89         I915_WRITE(reg_elda, i);
  90
  91         for (i = 0; i < eld[2]; i++)
  92                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  93                         return false;
  94
  95         return true;
  96 }
  97
  98 static void g4x_write_eld(struct drm_connector *connector,
  99                           struct drm_crtc *crtc,
 100                           struct drm_display_mode *mode)
 101 {
 102         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 103         uint8_t *eld = connector->eld;
 104         uint32_t eldv;
 105         uint32_t len;
 106         uint32_t i;
 107
 108         i = I915_READ(G4X_AUD_VID_DID);
 109
 110         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
 111                 eldv = G4X_ELDV_DEVCL_DEVBLC;
 112         else
 113                 eldv = G4X_ELDV_DEVCTG;
 114
 115         if (intel_eld_uptodate(connector,
 116                                G4X_AUD_CNTL_ST, eldv,
 117                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
 118                                G4X_HDMIW_HDMIEDID))
 119                 return;
 120
 121         i = I915_READ(G4X_AUD_CNTL_ST);
 122         i &= ~(eldv | G4X_ELD_ADDR);
 123         len = (i >> 9) & 0x1f;          /* ELD buffer size */
 124         I915_WRITE(G4X_AUD_CNTL_ST, i);
 125
 126         if (!eld[0])
 127                 return;
 128
 129         len = min_t(uint8_t, eld[2], len);
 130         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 131         for (i = 0; i < len; i++)
 132                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
 133
 134         i = I915_READ(G4X_AUD_CNTL_ST);
 135         i |= eldv;
 136         I915_WRITE(G4X_AUD_CNTL_ST, i);
 137 }
 138
 139 static void haswell_write_eld(struct drm_connector *connector,
 140                               struct drm_crtc *crtc,
 141                               struct drm_display_mode *mode)
 142 {
 143         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 145         uint8_t *eld = connector->eld;
 146         uint32_t eldv;
 147         uint32_t i;
 148         int len;
 149         int pipe = to_intel_crtc(crtc)->pipe;
 150         int tmp;
 151
 152         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
 153         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
 154         int aud_config = HSW_AUD_CFG(pipe);
 155         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
 156
 157         /* Audio output enable */
 158         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
 159         tmp = I915_READ(aud_cntrl_st2);
 160         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
 161         I915_WRITE(aud_cntrl_st2, tmp);
 162         POSTING_READ(aud_cntrl_st2);
 163
 164         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
 165
 166         /* Set ELD valid state */
 167         tmp = I915_READ(aud_cntrl_st2);
 168         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
 169         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
 170         I915_WRITE(aud_cntrl_st2, tmp);
 171         tmp = I915_READ(aud_cntrl_st2);
 172         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
 173
 174         /* Enable HDMI mode */
 175         tmp = I915_READ(aud_config);
 176         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
 177         /* clear N_programing_enable and N_value_index */
 178         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
 179         I915_WRITE(aud_config, tmp);
 180
 181         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 182
 183         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
 184
 185         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 186                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
 187                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
 188                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 189         } else {
 190                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 191         }
 192
 193         if (intel_eld_uptodate(connector,
 194                                aud_cntrl_st2, eldv,
 195                                aud_cntl_st, IBX_ELD_ADDRESS,
 196                                hdmiw_hdmiedid))
 197                 return;
 198
 199         i = I915_READ(aud_cntrl_st2);
 200         i &= ~eldv;
 201         I915_WRITE(aud_cntrl_st2, i);
 202
 203         if (!eld[0])
 204                 return;
 205
 206         i = I915_READ(aud_cntl_st);
 207         i &= ~IBX_ELD_ADDRESS;
 208         I915_WRITE(aud_cntl_st, i);
 209         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
 210         DRM_DEBUG_DRIVER("port num:%d\n", i);
 211
 212         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
 213         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 214         for (i = 0; i < len; i++)
 215                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 216
 217         i = I915_READ(aud_cntrl_st2);
 218         i |= eldv;
 219         I915_WRITE(aud_cntrl_st2, i);
 220
 221 }
 222
 223 static void ironlake_write_eld(struct drm_connector *connector,
 224                                struct drm_crtc *crtc,
 225                                struct drm_display_mode *mode)
 226 {
 227         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 229         uint8_t *eld = connector->eld;
 230         uint32_t eldv;
 231         uint32_t i;
 232         int len;
 233         int hdmiw_hdmiedid;
 234         int aud_config;
 235         int aud_cntl_st;
 236         int aud_cntrl_st2;
 237         int pipe = to_intel_crtc(crtc)->pipe;
 238
 239         if (HAS_PCH_IBX(connector->dev)) {
 240                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 241                 aud_config = IBX_AUD_CFG(pipe);
 242                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 243                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 244         } else if (IS_VALLEYVIEW(connector->dev)) {
 245                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 246                 aud_config = VLV_AUD_CFG(pipe);
 247                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 248                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 249         } else {
 250                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 251                 aud_config = CPT_AUD_CFG(pipe);
 252                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 253                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 254         }
 255
 256         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 257
 258         if (IS_VALLEYVIEW(connector->dev))  {
 259                 struct intel_encoder *intel_encoder;
 260                 struct intel_digital_port *intel_dig_port;
 261
 262                 intel_encoder = intel_attached_encoder(connector);
 263                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
 264                 i = intel_dig_port->port;
 265         } else {
 266                 i = I915_READ(aud_cntl_st);
 267                 i = (i >> 29) & DIP_PORT_SEL_MASK;
 268                 /* DIP_Port_Select, 0x1 = PortB */
 269         }
 270
 271         if (!i) {
 272                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 273                 /* operate blindly on all ports */
 274                 eldv = IBX_ELD_VALIDB;
 275                 eldv |= IBX_ELD_VALIDB << 4;
 276                 eldv |= IBX_ELD_VALIDB << 8;
 277         } else {
 278                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
 279                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
 280         }
 281
 282         if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 283                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
 284                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
 285                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
 286         } else {
 287                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
 288         }
 289
 290         if (intel_eld_uptodate(connector,
 291                                aud_cntrl_st2, eldv,
 292                                aud_cntl_st, IBX_ELD_ADDRESS,
 293                                hdmiw_hdmiedid))
 294                 return;
 295
 296         i = I915_READ(aud_cntrl_st2);
 297         i &= ~eldv;
 298         I915_WRITE(aud_cntrl_st2, i);
 299
 300         if (!eld[0])
 301                 return;
 302
 303         i = I915_READ(aud_cntl_st);
 304         i &= ~IBX_ELD_ADDRESS;
 305         I915_WRITE(aud_cntl_st, i);
 306
 307         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
 308         DRM_DEBUG_DRIVER("ELD size %d\n", len);
 309         for (i = 0; i < len; i++)
 310                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
 311
 312         i = I915_READ(aud_cntrl_st2);
 313         i |= eldv;
 314         I915_WRITE(aud_cntrl_st2, i);
 315 }
 316
 317 void intel_write_eld(struct drm_encoder *encoder,
 318                      struct drm_display_mode *mode)
 319 {
 320         struct drm_crtc *crtc = encoder->crtc;
 321         struct drm_connector *connector;
 322         struct drm_device *dev = encoder->dev;
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324
 325         connector = drm_select_eld(encoder, mode);
 326         if (!connector)
 327                 return;
 328
 329         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
 330                          connector->base.id,
 331                          connector->name,
 332                          connector->encoder->base.id,
 333                          connector->encoder->name);
 334
 335         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
 336
 337         if (dev_priv->display.write_eld)
 338                 dev_priv->display.write_eld(connector, crtc, mode);
 339 }
 340
 341 /**
 342  * intel_init_audio - Set up chip specific audio functions
 343  * @dev: drm device
 344  */
 345 void intel_init_audio(struct drm_device *dev)
 346 {
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348
 349         if (IS_G4X(dev))
 350                 dev_priv->display.write_eld = g4x_write_eld;
 351         else if (IS_VALLEYVIEW(dev))
 352                 dev_priv->display.write_eld = ironlake_write_eld;
 353         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 354                 dev_priv->display.write_eld = haswell_write_eld;
 355         else if (HAS_PCH_SPLIT(dev))
 356                 dev_priv->display.write_eld = ironlake_write_eld;
 357 }