drivers/gpu/drm/i915/intel_color.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_drv.h"
  26
  27 #define CTM_COEFF_SIGN  (1ULL << 63)
  28
  29 #define CTM_COEFF_1_0   (1ULL << 32)
  30 #define CTM_COEFF_2_0   (CTM_COEFF_1_0 << 1)
  31 #define CTM_COEFF_4_0   (CTM_COEFF_2_0 << 1)
  32 #define CTM_COEFF_8_0   (CTM_COEFF_4_0 << 1)
  33 #define CTM_COEFF_0_5   (CTM_COEFF_1_0 >> 1)
  34 #define CTM_COEFF_0_25  (CTM_COEFF_0_5 >> 1)
  35 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
  36
  37 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
  38
  39 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
  40 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
  41
  42 #define LEGACY_LUT_LENGTH               256
  43
  44 /* Post offset values for RGB->YCBCR conversion */
  45 #define POSTOFF_RGB_TO_YUV_HI 0x800
  46 #define POSTOFF_RGB_TO_YUV_ME 0x100
  47 #define POSTOFF_RGB_TO_YUV_LO 0x800
  48
  49 /*
  50  * These values are direct register values specified in the Bspec,
  51  * for RGB->YUV conversion matrix (colorspace BT709)
  52  */
  53 #define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8
  54 #define CSC_RGB_TO_YUV_BU 0x37e80000
  55 #define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0
  56 #define CSC_RGB_TO_YUV_BY 0xb5280000
  57 #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
  58 #define CSC_RGB_TO_YUV_BV 0x1e080000
  59
  60 /*
  61  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  62  * format). This macro takes the coefficient we want transformed and the
  63  * number of fractional bits.
  64  *
  65  * We only have a 9 bits precision window which slides depending on the value
  66  * of the CTM coefficient and we write the value from bit 3. We also round the
  67  * value.
  68  */
  69 #define ILK_CSC_COEFF_FP(coeff, fbits)  \
  70         (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
  71
  72 #define ILK_CSC_COEFF_LIMITED_RANGE     \
  73         ILK_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
  74 #define ILK_CSC_COEFF_1_0               \
  75         ((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
  76
  77 static bool lut_is_legacy(struct drm_property_blob *lut)
  78 {
  79         return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
  80 }
  81
  82 static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *crtc_state)
  83 {
  84         return !crtc_state->base.degamma_lut &&
  85                 !crtc_state->base.ctm &&
  86                 crtc_state->base.gamma_lut &&
  87                 lut_is_legacy(crtc_state->base.gamma_lut);
  88 }
  89
  90 /*
  91  * When using limited range, multiply the matrix given by userspace by
  92  * the matrix that we would use for the limited range.
  93  */
  94 static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
  95 {
  96         int i;
  97
  98         for (i = 0; i < 9; i++) {
  99                 u64 user_coeff = input[i];
 100                 u32 limited_coeff = CTM_COEFF_LIMITED_RANGE;
 101                 u32 abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff), 0,
 102                                           CTM_COEFF_4_0 - 1) >> 2;
 103
 104                 /*
 105                  * By scaling every co-efficient with limited range (16-235)
 106                  * vs full range (0-255) the final o/p will be scaled down to
 107                  * fit in the limited range supported by the panel.
 108                  */
 109                 result[i] = mul_u32_u32(limited_coeff, abs_coeff) >> 30;
 110                 result[i] |= user_coeff & CTM_COEFF_SIGN;
 111         }
 112
 113         return result;
 114 }
 115
 116 static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 117 {
 118         int pipe = crtc->pipe;
 119         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 120
 121         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 122         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 123         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 124
 125         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
 126         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
 127
 128         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
 129         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
 130
 131         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
 132         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
 133
 134         I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
 135         I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
 136         I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
 137         I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 138 }
 139
 140 static void ilk_load_csc_matrix(struct intel_crtc_state *crtc_state)
 141 {
 142         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 143         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 144         int i, pipe = crtc->pipe;
 145         u16 coeffs[9] = { 0, };
 146         bool limited_color_range = false;
 147
 148         /*
 149          * FIXME if there's a gamma LUT after the CSC, we should
 150          * do the range compression using the gamma LUT instead.
 151          */
 152         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
 153                 limited_color_range = crtc_state->limited_color_range;
 154
 155         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 156             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
 157                 ilk_load_ycbcr_conversion_matrix(crtc);
 158                 return;
 159         } else if (crtc_state->base.ctm) {
 160                 struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 161                 const u64 *input;
 162                 u64 temp[9];
 163
 164                 if (limited_color_range)
 165                         input = ctm_mult_by_limited(temp, ctm->matrix);
 166                 else
 167                         input = ctm->matrix;
 168
 169                 /*
 170                  * Convert fixed point S31.32 input to format supported by the
 171                  * hardware.
 172                  */
 173                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 174                         u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
 175
 176                         /*
 177                          * Clamp input value to min/max supported by
 178                          * hardware.
 179                          */
 180                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
 181
 182                         /* sign bit */
 183                         if (CTM_COEFF_NEGATIVE(input[i]))
 184                                 coeffs[i] |= 1 << 15;
 185
 186                         if (abs_coeff < CTM_COEFF_0_125)
 187                                 coeffs[i] |= (3 << 12) |
 188                                         ILK_CSC_COEFF_FP(abs_coeff, 12);
 189                         else if (abs_coeff < CTM_COEFF_0_25)
 190                                 coeffs[i] |= (2 << 12) |
 191                                         ILK_CSC_COEFF_FP(abs_coeff, 11);
 192                         else if (abs_coeff < CTM_COEFF_0_5)
 193                                 coeffs[i] |= (1 << 12) |
 194                                         ILK_CSC_COEFF_FP(abs_coeff, 10);
 195                         else if (abs_coeff < CTM_COEFF_1_0)
 196                                 coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
 197                         else if (abs_coeff < CTM_COEFF_2_0)
 198                                 coeffs[i] |= (7 << 12) |
 199                                         ILK_CSC_COEFF_FP(abs_coeff, 8);
 200                         else
 201                                 coeffs[i] |= (6 << 12) |
 202                                         ILK_CSC_COEFF_FP(abs_coeff, 7);
 203                 }
 204         } else {
 205                 /*
 206                  * Load an identity matrix if no coefficients are provided.
 207                  *
 208                  * TODO: Check what kind of values actually come out of the
 209                  * pipe with these coeff/postoff values and adjust to get the
 210                  * best accuracy. Perhaps we even need to take the bpc value
 211                  * into consideration.
 212                  */
 213                 for (i = 0; i < 3; i++) {
 214                         if (limited_color_range)
 215                                 coeffs[i * 3 + i] =
 216                                         ILK_CSC_COEFF_LIMITED_RANGE;
 217                         else
 218                                 coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
 219                 }
 220         }
 221
 222         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
 223         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
 224
 225         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
 226         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
 227
 228         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
 229         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
 230
 231         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 232         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 233         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 234
 235         if (INTEL_GEN(dev_priv) > 6) {
 236                 u16 postoff = 0;
 237
 238                 if (limited_color_range)
 239                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
 240
 241                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
 242                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
 243                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
 244
 245                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 246         } else {
 247                 u32 mode = CSC_MODE_YUV_TO_RGB;
 248
 249                 if (limited_color_range)
 250                         mode |= CSC_BLACK_SCREEN_OFFSET;
 251
 252                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
 253         }
 254 }
 255
 256 /*
 257  * Set up the pipe CSC unit on CherryView.
 258  */
 259 static void cherryview_load_csc_matrix(struct intel_crtc_state *crtc_state)
 260 {
 261         struct drm_device *dev = crtc_state->base.crtc->dev;
 262         struct drm_i915_private *dev_priv = to_i915(dev);
 263         int pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 264         u32 mode;
 265
 266         if (crtc_state->base.ctm) {
 267                 struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
 268                 u16 coeffs[9] = { 0, };
 269                 int i;
 270
 271                 for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
 272                         u64 abs_coeff =
 273                                 ((1ULL << 63) - 1) & ctm->matrix[i];
 274
 275                         /* Round coefficient. */
 276                         abs_coeff += 1 << (32 - 13);
 277                         /* Clamp to hardware limits. */
 278                         abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 279
 280                         /* Write coefficients in S3.12 format. */
 281                         if (ctm->matrix[i] & (1ULL << 63))
 282                                 coeffs[i] = 1 << 15;
 283                         coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
 284                         coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 285                 }
 286
 287                 I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
 288                            coeffs[1] << 16 | coeffs[0]);
 289                 I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
 290                            coeffs[3] << 16 | coeffs[2]);
 291                 I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
 292                            coeffs[5] << 16 | coeffs[4]);
 293                 I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
 294                            coeffs[7] << 16 | coeffs[6]);
 295                 I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 296         }
 297
 298         mode = (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
 299         if (!crtc_state_is_legacy_gamma(crtc_state)) {
 300                 mode |= (crtc_state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
 301                         (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
 302         }
 303         I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 304 }
 305
 306 void intel_color_set_csc(struct intel_crtc_state *crtc_state)
 307 {
 308         struct drm_device *dev = crtc_state->base.crtc->dev;
 309         struct drm_i915_private *dev_priv = to_i915(dev);
 310
 311         if (dev_priv->display.load_csc_matrix)
 312                 dev_priv->display.load_csc_matrix(crtc_state);
 313 }
 314
 315 /* Loads the legacy palette/gamma unit for the CRTC. */
 316 static void i9xx_load_luts_internal(struct intel_crtc_state *crtc_state,
 317                                     struct drm_property_blob *blob)
 318 {
 319         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 320         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 321         enum pipe pipe = crtc->pipe;
 322         int i;
 323
 324         if (HAS_GMCH_DISPLAY(dev_priv)) {
 325                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 326                         assert_dsi_pll_enabled(dev_priv);
 327                 else
 328                         assert_pll_enabled(dev_priv, pipe);
 329         }
 330
 331         if (blob) {
 332                 struct drm_color_lut *lut = blob->data;
 333                 for (i = 0; i < 256; i++) {
 334                         u32 word =
 335                                 (drm_color_lut_extract(lut[i].red, 8) << 16) |
 336                                 (drm_color_lut_extract(lut[i].green, 8) << 8) |
 337                                 drm_color_lut_extract(lut[i].blue, 8);
 338
 339                         if (HAS_GMCH_DISPLAY(dev_priv))
 340                                 I915_WRITE(PALETTE(pipe, i), word);
 341                         else
 342                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 343                 }
 344         } else {
 345                 for (i = 0; i < 256; i++) {
 346                         u32 word = (i << 16) | (i << 8) | i;
 347
 348                         if (HAS_GMCH_DISPLAY(dev_priv))
 349                                 I915_WRITE(PALETTE(pipe, i), word);
 350                         else
 351                                 I915_WRITE(LGC_PALETTE(pipe, i), word);
 352                 }
 353         }
 354 }
 355
 356 static void i9xx_load_luts(struct intel_crtc_state *crtc_state)
 357 {
 358         i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 359 }
 360
 361 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
 362 static void haswell_load_luts(struct intel_crtc_state *crtc_state)
 363 {
 364         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 365         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 366         bool reenable_ips = false;
 367
 368         /*
 369          * Workaround : Do not read or write the pipe palette/gamma data while
 370          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 371          */
 372         if (IS_HASWELL(dev_priv) && crtc_state->ips_enabled &&
 373             (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
 374                 hsw_disable_ips(crtc_state);
 375                 reenable_ips = true;
 376         }
 377
 378         crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 379         I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
 380
 381         i9xx_load_luts(crtc_state);
 382
 383         if (reenable_ips)
 384                 hsw_enable_ips(crtc_state);
 385 }
 386
 387 static void bdw_load_degamma_lut(struct intel_crtc_state *crtc_state)
 388 {
 389         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 390         enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 391         u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 392
 393         I915_WRITE(PREC_PAL_INDEX(pipe),
 394                    PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
 395
 396         if (crtc_state->base.degamma_lut) {
 397                 struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;
 398
 399                 for (i = 0; i < lut_size; i++) {
 400                         u32 word =
 401                         drm_color_lut_extract(lut[i].red, 10) << 20 |
 402                         drm_color_lut_extract(lut[i].green, 10) << 10 |
 403                         drm_color_lut_extract(lut[i].blue, 10);
 404
 405                         I915_WRITE(PREC_PAL_DATA(pipe), word);
 406                 }
 407         } else {
 408                 for (i = 0; i < lut_size; i++) {
 409                         u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
 410
 411                         I915_WRITE(PREC_PAL_DATA(pipe),
 412                                    (v << 20) | (v << 10) | v);
 413                 }
 414         }
 415 }
 416
 417 static void bdw_load_gamma_lut(struct intel_crtc_state *crtc_state, u32 offset)
 418 {
 419         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 420         enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 421         u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 422
 423         WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
 424
 425         I915_WRITE(PREC_PAL_INDEX(pipe),
 426                    (offset ? PAL_PREC_SPLIT_MODE : 0) |
 427                    PAL_PREC_AUTO_INCREMENT |
 428                    offset);
 429
 430         if (crtc_state->base.gamma_lut) {
 431                 struct drm_color_lut *lut = crtc_state->base.gamma_lut->data;
 432
 433                 for (i = 0; i < lut_size; i++) {
 434                         u32 word =
 435                         (drm_color_lut_extract(lut[i].red, 10) << 20) |
 436                         (drm_color_lut_extract(lut[i].green, 10) << 10) |
 437                         drm_color_lut_extract(lut[i].blue, 10);
 438
 439                         I915_WRITE(PREC_PAL_DATA(pipe), word);
 440                 }
 441
 442                 /* Program the max register to clamp values > 1.0. */
 443                 i = lut_size - 1;
 444                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
 445                            drm_color_lut_extract(lut[i].red, 16));
 446                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
 447                            drm_color_lut_extract(lut[i].green, 16));
 448                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
 449                            drm_color_lut_extract(lut[i].blue, 16));
 450         } else {
 451                 for (i = 0; i < lut_size; i++) {
 452                         u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
 453
 454                         I915_WRITE(PREC_PAL_DATA(pipe),
 455                                    (v << 20) | (v << 10) | v);
 456                 }
 457
 458                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
 459                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
 460                 I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
 461         }
 462 }
 463
 464 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
 465 static void broadwell_load_luts(struct intel_crtc_state *crtc_state)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 468         enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 469
 470         if (crtc_state_is_legacy_gamma(crtc_state)) {
 471                 haswell_load_luts(crtc_state);
 472                 return;
 473         }
 474
 475         bdw_load_degamma_lut(crtc_state);
 476         bdw_load_gamma_lut(crtc_state,
 477                            INTEL_INFO(dev_priv)->color.degamma_lut_size);
 478
 479         crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
 480         I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
 481         POSTING_READ(GAMMA_MODE(pipe));
 482
 483         /*
 484          * Reset the index, otherwise it prevents the legacy palette to be
 485          * written properly.
 486          */
 487         I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 488 }
 489
 490 static void glk_load_degamma_lut(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 493         enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 494         const u32 lut_size = 33;
 495         u32 i;
 496
 497         /*
 498          * When setting the auto-increment bit, the hardware seems to
 499          * ignore the index bits, so we need to reset it to index 0
 500          * separately.
 501          */
 502         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
 503         I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
 504
 505         /*
 506          *  FIXME: The pipe degamma table in geminilake doesn't support
 507          *  different values per channel, so this just loads a linear table.
 508          */
 509         for (i = 0; i < lut_size; i++) {
 510                 u32 v = (i * (1 << 16)) / (lut_size - 1);
 511
 512                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
 513         }
 514
 515         /* Clamp values > 1.0. */
 516         while (i++ < 35)
 517                 I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
 518 }
 519
 520 static void glk_load_luts(struct intel_crtc_state *crtc_state)
 521 {
 522         struct drm_device *dev = crtc_state->base.crtc->dev;
 523         struct drm_i915_private *dev_priv = to_i915(dev);
 524         enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
 525
 526         glk_load_degamma_lut(crtc_state);
 527
 528         if (crtc_state_is_legacy_gamma(crtc_state)) {
 529                 haswell_load_luts(crtc_state);
 530                 return;
 531         }
 532
 533         bdw_load_gamma_lut(crtc_state, 0);
 534
 535         crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
 536         I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
 537         POSTING_READ(GAMMA_MODE(pipe));
 538 }
 539
 540 /* Loads the palette/gamma unit for the CRTC on CherryView. */
 541 static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
 542 {
 543         struct drm_crtc *crtc = crtc_state->base.crtc;
 544         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 545         enum pipe pipe = to_intel_crtc(crtc)->pipe;
 546         struct drm_color_lut *lut;
 547         u32 i, lut_size;
 548         u32 word0, word1;
 549
 550         if (crtc_state_is_legacy_gamma(crtc_state)) {
 551                 /* Turn off degamma/gamma on CGM block. */
 552                 I915_WRITE(CGM_PIPE_MODE(pipe),
 553                            (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
 554                 i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);
 555                 return;
 556         }
 557
 558         if (crtc_state->base.degamma_lut) {
 559                 lut = crtc_state->base.degamma_lut->data;
 560                 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 561                 for (i = 0; i < lut_size; i++) {
 562                         /* Write LUT in U0.14 format. */
 563                         word0 =
 564                         (drm_color_lut_extract(lut[i].green, 14) << 16) |
 565                         drm_color_lut_extract(lut[i].blue, 14);
 566                         word1 = drm_color_lut_extract(lut[i].red, 14);
 567
 568                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
 569                         I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
 570                 }
 571         }
 572
 573         if (crtc_state->base.gamma_lut) {
 574                 lut = crtc_state->base.gamma_lut->data;
 575                 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 576                 for (i = 0; i < lut_size; i++) {
 577                         /* Write LUT in U0.10 format. */
 578                         word0 =
 579                         (drm_color_lut_extract(lut[i].green, 10) << 16) |
 580                         drm_color_lut_extract(lut[i].blue, 10);
 581                         word1 = drm_color_lut_extract(lut[i].red, 10);
 582
 583                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
 584                         I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
 585                 }
 586         }
 587
 588         I915_WRITE(CGM_PIPE_MODE(pipe),
 589                    (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
 590                    (crtc_state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
 591                    (crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
 592
 593         /*
 594          * Also program a linear LUT in the legacy block (behind the
 595          * CGM block).
 596          */
 597         i9xx_load_luts_internal(crtc_state, NULL);
 598 }
 599
 600 void intel_color_load_luts(struct intel_crtc_state *crtc_state)
 601 {
 602         struct drm_device *dev = crtc_state->base.crtc->dev;
 603         struct drm_i915_private *dev_priv = to_i915(dev);
 604
 605         dev_priv->display.load_luts(crtc_state);
 606 }
 607
 608 static int check_lut_size(const struct drm_property_blob *lut, int expected)
 609 {
 610         int len;
 611
 612         if (!lut)
 613                 return 0;
 614
 615         len = drm_color_lut_size(lut);
 616         if (len != expected) {
 617                 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
 618                               len, expected);
 619                 return -EINVAL;
 620         }
 621
 622         return 0;
 623 }
 624
 625 int intel_color_check(struct intel_crtc_state *crtc_state)
 626 {
 627         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 628         int gamma_length, degamma_length;
 629         u32 gamma_tests, degamma_tests;
 630
 631         degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 632         gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 633         degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
 634         gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
 635
 636         /* Always allow legacy gamma LUT with no further checking. */
 637         if (crtc_state_is_legacy_gamma(crtc_state))
 638                 return 0;
 639
 640         if (check_lut_size(crtc_state->base.degamma_lut, degamma_length) ||
 641             check_lut_size(crtc_state->base.gamma_lut, gamma_length))
 642                 return -EINVAL;
 643
 644         if (drm_color_lut_check(crtc_state->base.degamma_lut, degamma_tests) ||
 645             drm_color_lut_check(crtc_state->base.gamma_lut, gamma_tests))
 646                 return -EINVAL;
 647
 648
 649         return 0;
 650 }
 651
 652 void intel_color_init(struct intel_crtc *crtc)
 653 {
 654         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 655
 656         drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 657
 658         if (IS_CHERRYVIEW(dev_priv)) {
 659                 dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
 660                 dev_priv->display.load_luts = cherryview_load_luts;
 661         } else if (IS_HASWELL(dev_priv)) {
 662                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 663                 dev_priv->display.load_luts = haswell_load_luts;
 664         } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
 665                    IS_BROXTON(dev_priv)) {
 666                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 667                 dev_priv->display.load_luts = broadwell_load_luts;
 668         } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 669                 dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
 670                 dev_priv->display.load_luts = glk_load_luts;
 671         } else {
 672                 dev_priv->display.load_luts = i9xx_load_luts;
 673         }
 674
 675         /* Enable color management support when we have degamma & gamma LUTs. */
 676         if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
 677             INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 678                 drm_crtc_enable_color_mgmt(&crtc->base,
 679                                            INTEL_INFO(dev_priv)->color.degamma_lut_size,
 680                                            true,
 681                                            INTEL_INFO(dev_priv)->color.gamma_lut_size);
 682 }