2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
131 /* Skylake H and S */
132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x80009010, 0x000000C0, 0x1 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x80007011, 0x000000C0, 0x1 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x80005012, 0x000000C0, 0x1 },
145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x0000201B, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x80007011, 0x000000CD, 0x0 },
149 { 0x80009010, 0x000000C0, 0x1 },
150 { 0x0000201B, 0x0000009D, 0x0 },
151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x80005012, 0x000000C0, 0x1 },
158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x80007011, 0x000000CD, 0x0 },
162 { 0x80009010, 0x000000C0, 0x3 },
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x80005012, 0x000000C0, 0x3 },
172 * eDP 1.4 low vswing translation parameters
174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
189 * eDP 1.4 low vswing translation parameters
191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
206 * eDP 1.4 low vswing translation parameters
208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
221 /* Skylake U, H and S */
222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x80006012, 0x000000CD, 0x1 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x80007011, 0x000000CB, 0x3 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x80006013, 0x000000C0, 0x3 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
251 struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
256 bool default_index; /* true if the entry represents default value */
259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
287 /* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
304 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
311 struct drm_encoder *encoder = &intel_encoder->base;
313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
325 case INTEL_OUTPUT_ANALOG:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
337 struct intel_digital_port *dig_port;
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
345 static const struct ddi_buf_trans *
346 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
350 return skl_y_ddi_translations_dp;
351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
353 return skl_u_ddi_translations_dp;
355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
356 return skl_ddi_translations_dp;
360 static const struct ddi_buf_trans *
361 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
363 if (dev_priv->vbt.edp.low_vswing) {
364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
366 return skl_y_ddi_translations_edp;
367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
369 return skl_u_ddi_translations_edp;
371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
372 return skl_ddi_translations_edp;
376 return skl_get_buf_trans_dp(dev_priv, n_entries);
379 static const struct ddi_buf_trans *
380 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
384 return skl_y_ddi_translations_hdmi;
386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
387 return skl_ddi_translations_hdmi;
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
398 void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
415 if (IS_BROXTON(dev_priv)) {
416 if (encoder->type != INTEL_OUTPUT_HDMI)
419 /* Vswing programming for HDMI */
420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
426 ddi_translations_fdi = NULL;
427 ddi_translations_dp =
428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
429 ddi_translations_edp =
430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
431 ddi_translations_hdmi =
432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
433 hdmi_default_entry = 8;
434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
443 } else if (IS_BROADWELL(dev_priv)) {
444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
446 ddi_translations_edp = bdw_ddi_translations_edp;
447 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
448 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
449 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
450 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
451 hdmi_default_entry = 7;
452 } else if (IS_HASWELL(dev_priv)) {
453 ddi_translations_fdi = hsw_ddi_translations_fdi;
454 ddi_translations_dp = hsw_ddi_translations_dp;
455 ddi_translations_edp = hsw_ddi_translations_dp;
456 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
458 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
459 hdmi_default_entry = 6;
461 WARN(1, "ddi translation table missing\n");
462 ddi_translations_edp = bdw_ddi_translations_dp;
463 ddi_translations_fdi = bdw_ddi_translations_fdi;
464 ddi_translations_dp = bdw_ddi_translations_dp;
465 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
466 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
467 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
468 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
469 hdmi_default_entry = 7;
472 switch (encoder->type) {
473 case INTEL_OUTPUT_EDP:
474 ddi_translations = ddi_translations_edp;
475 size = n_edp_entries;
477 case INTEL_OUTPUT_DISPLAYPORT:
478 case INTEL_OUTPUT_HDMI:
479 ddi_translations = ddi_translations_dp;
482 case INTEL_OUTPUT_ANALOG:
483 ddi_translations = ddi_translations_fdi;
490 for (i = 0; i < size; i++) {
491 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
492 ddi_translations[i].trans1 | iboost_bit);
493 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
494 ddi_translations[i].trans2);
497 if (encoder->type != INTEL_OUTPUT_HDMI)
500 /* Choose a good default if VBT is badly populated */
501 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
502 hdmi_level >= n_hdmi_entries)
503 hdmi_level = hdmi_default_entry;
505 /* Entry 9 is for HDMI: */
506 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
507 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
508 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
509 ddi_translations_hdmi[hdmi_level].trans2);
512 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
515 i915_reg_t reg = DDI_BUF_CTL(port);
518 for (i = 0; i < 16; i++) {
520 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
523 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
526 /* Starting with Haswell, different DDI ports can work in FDI mode for
527 * connection to the PCH-located connectors. For this, it is necessary to train
528 * both the DDI port and PCH receiver for the desired DDI buffer settings.
530 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
531 * please note that when FDI mode is active on DDI E, it shares 2 lines with
532 * DDI A (which is used for eDP)
535 void hsw_fdi_link_train(struct drm_crtc *crtc)
537 struct drm_device *dev = crtc->dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
540 struct intel_encoder *encoder;
541 u32 temp, i, rx_ctl_val;
543 for_each_encoder_on_crtc(dev, crtc, encoder) {
544 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
545 intel_prepare_ddi_buffer(encoder);
548 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
549 * mode set "sequence for CRT port" document:
550 * - TP1 to TP2 time with the default value
553 * WaFDIAutoLinkSetTimingOverrride:hsw
555 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
556 FDI_RX_PWRDN_LANE0_VAL(2) |
557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
559 /* Enable the PCH Receiver FDI PLL */
560 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
562 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
563 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
564 POSTING_READ(FDI_RX_CTL(PIPE_A));
567 /* Switch from Rawclk to PCDclk */
568 rx_ctl_val |= FDI_PCDCLK;
569 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
571 /* Configure Port Clock Select */
572 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
573 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
575 /* Start the training iterating through available voltages and emphasis,
576 * testing each value twice. */
577 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
578 /* Configure DP_TP_CTL with auto-training */
579 I915_WRITE(DP_TP_CTL(PORT_E),
580 DP_TP_CTL_FDI_AUTOTRAIN |
581 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
582 DP_TP_CTL_LINK_TRAIN_PAT1 |
585 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
586 * DDI E does not support port reversal, the functionality is
587 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
588 * port reversal bit */
589 I915_WRITE(DDI_BUF_CTL(PORT_E),
591 ((intel_crtc->config->fdi_lanes - 1) << 1) |
592 DDI_BUF_TRANS_SELECT(i / 2));
593 POSTING_READ(DDI_BUF_CTL(PORT_E));
597 /* Program PCH FDI Receiver TU */
598 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
600 /* Enable PCH FDI Receiver with auto-training */
601 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603 POSTING_READ(FDI_RX_CTL(PIPE_A));
605 /* Wait for FDI receiver lane calibration */
608 /* Unset FDI_RX_MISC pwrdn lanes */
609 temp = I915_READ(FDI_RX_MISC(PIPE_A));
610 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
611 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
612 POSTING_READ(FDI_RX_MISC(PIPE_A));
614 /* Wait for FDI auto training time */
617 temp = I915_READ(DP_TP_STATUS(PORT_E));
618 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
619 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
624 * Leave things enabled even if we failed to train FDI.
625 * Results in less fireworks from the state checker.
627 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
628 DRM_ERROR("FDI link training failed!\n");
632 temp = I915_READ(DDI_BUF_CTL(PORT_E));
633 temp &= ~DDI_BUF_CTL_ENABLE;
634 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
635 POSTING_READ(DDI_BUF_CTL(PORT_E));
637 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
638 temp = I915_READ(DP_TP_CTL(PORT_E));
639 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
640 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
641 I915_WRITE(DP_TP_CTL(PORT_E), temp);
642 POSTING_READ(DP_TP_CTL(PORT_E));
644 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
646 rx_ctl_val &= ~FDI_RX_ENABLE;
647 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
648 POSTING_READ(FDI_RX_CTL(PIPE_A));
650 /* Reset FDI_RX_MISC pwrdn lanes */
651 temp = I915_READ(FDI_RX_MISC(PIPE_A));
652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
653 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
654 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
655 POSTING_READ(FDI_RX_MISC(PIPE_A));
658 /* Enable normal pixel sending for FDI */
659 I915_WRITE(DP_TP_CTL(PORT_E),
660 DP_TP_CTL_FDI_AUTOTRAIN |
661 DP_TP_CTL_LINK_TRAIN_NORMAL |
662 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
666 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
668 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
669 struct intel_digital_port *intel_dig_port =
670 enc_to_dig_port(&encoder->base);
672 intel_dp->DP = intel_dig_port->saved_port_bits |
673 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
674 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
677 static struct intel_encoder *
678 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
680 struct drm_device *dev = crtc->dev;
681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
682 struct intel_encoder *intel_encoder, *ret = NULL;
683 int num_encoders = 0;
685 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
690 if (num_encoders != 1)
691 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
692 pipe_name(intel_crtc->pipe));
698 struct intel_encoder *
699 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
702 struct intel_encoder *ret = NULL;
703 struct drm_atomic_state *state;
704 struct drm_connector *connector;
705 struct drm_connector_state *connector_state;
706 int num_encoders = 0;
709 state = crtc_state->base.state;
711 for_each_connector_in_state(state, connector, connector_state, i) {
712 if (connector_state->crtc != crtc_state->base.crtc)
715 ret = to_intel_encoder(connector_state->best_encoder);
719 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
720 pipe_name(crtc->pipe));
728 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
731 int refclk = LC_FREQ;
735 wrpll = I915_READ(reg);
736 switch (wrpll & WRPLL_PLL_REF_MASK) {
738 case WRPLL_PLL_NON_SSC:
740 * We could calculate spread here, but our checking
741 * code only cares about 5% accuracy, and spread is a max of
746 case WRPLL_PLL_LCPLL:
750 WARN(1, "bad wrpll refclk\n");
754 r = wrpll & WRPLL_DIVIDER_REF_MASK;
755 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
756 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
758 /* Convert to KHz, p & r have a fixed point portion */
759 return (refclk * n * 100) / (p * r);
762 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
765 i915_reg_t cfgcr1_reg, cfgcr2_reg;
766 uint32_t cfgcr1_val, cfgcr2_val;
767 uint32_t p0, p1, p2, dco_freq;
769 cfgcr1_reg = DPLL_CFGCR1(dpll);
770 cfgcr2_reg = DPLL_CFGCR2(dpll);
772 cfgcr1_val = I915_READ(cfgcr1_reg);
773 cfgcr2_val = I915_READ(cfgcr2_reg);
775 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
776 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
778 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
779 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
785 case DPLL_CFGCR2_PDIV_1:
788 case DPLL_CFGCR2_PDIV_2:
791 case DPLL_CFGCR2_PDIV_3:
794 case DPLL_CFGCR2_PDIV_7:
800 case DPLL_CFGCR2_KDIV_5:
803 case DPLL_CFGCR2_KDIV_2:
806 case DPLL_CFGCR2_KDIV_3:
809 case DPLL_CFGCR2_KDIV_1:
814 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
816 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
819 return dco_freq / (p0 * p1 * p2 * 5);
822 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
826 if (pipe_config->has_pch_encoder)
827 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
828 &pipe_config->fdi_m_n);
829 else if (pipe_config->has_dp_encoder)
830 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
831 &pipe_config->dp_m_n);
832 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
833 dotclock = pipe_config->port_clock * 2 / 3;
835 dotclock = pipe_config->port_clock;
837 if (pipe_config->pixel_multiplier)
838 dotclock /= pipe_config->pixel_multiplier;
840 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
843 static void skl_ddi_clock_get(struct intel_encoder *encoder,
844 struct intel_crtc_state *pipe_config)
846 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
848 uint32_t dpll_ctl1, dpll;
850 dpll = pipe_config->ddi_pll_sel;
852 dpll_ctl1 = I915_READ(DPLL_CTRL1);
854 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
855 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
857 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
858 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
860 switch (link_clock) {
861 case DPLL_CTRL1_LINK_RATE_810:
864 case DPLL_CTRL1_LINK_RATE_1080:
867 case DPLL_CTRL1_LINK_RATE_1350:
870 case DPLL_CTRL1_LINK_RATE_1620:
873 case DPLL_CTRL1_LINK_RATE_2160:
876 case DPLL_CTRL1_LINK_RATE_2700:
880 WARN(1, "Unsupported link rate\n");
886 pipe_config->port_clock = link_clock;
888 ddi_dotclock_get(pipe_config);
891 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
892 struct intel_crtc_state *pipe_config)
894 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
898 val = pipe_config->ddi_pll_sel;
899 switch (val & PORT_CLK_SEL_MASK) {
900 case PORT_CLK_SEL_LCPLL_810:
903 case PORT_CLK_SEL_LCPLL_1350:
906 case PORT_CLK_SEL_LCPLL_2700:
909 case PORT_CLK_SEL_WRPLL1:
910 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
912 case PORT_CLK_SEL_WRPLL2:
913 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
915 case PORT_CLK_SEL_SPLL:
916 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
917 if (pll == SPLL_PLL_FREQ_810MHz)
919 else if (pll == SPLL_PLL_FREQ_1350MHz)
921 else if (pll == SPLL_PLL_FREQ_2700MHz)
924 WARN(1, "bad spll freq\n");
929 WARN(1, "bad port clock sel\n");
933 pipe_config->port_clock = link_clock * 2;
935 ddi_dotclock_get(pipe_config);
938 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
939 enum intel_dpll_id dpll)
941 struct intel_shared_dpll *pll;
942 struct intel_dpll_hw_state *state;
945 /* For DDI ports we always use a shared PLL. */
946 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
949 pll = &dev_priv->shared_dplls[dpll];
950 state = &pll->config.hw_state;
953 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
954 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
955 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
956 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
957 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
958 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
960 return chv_calc_dpll_params(100000, &clock);
963 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
964 struct intel_crtc_state *pipe_config)
966 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
967 enum port port = intel_ddi_get_encoder_port(encoder);
968 uint32_t dpll = port;
970 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
972 ddi_dotclock_get(pipe_config);
975 void intel_ddi_clock_get(struct intel_encoder *encoder,
976 struct intel_crtc_state *pipe_config)
978 struct drm_device *dev = encoder->base.dev;
980 if (INTEL_INFO(dev)->gen <= 8)
981 hsw_ddi_clock_get(encoder, pipe_config);
982 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
983 skl_ddi_clock_get(encoder, pipe_config);
984 else if (IS_BROXTON(dev))
985 bxt_ddi_clock_get(encoder, pipe_config);
989 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
990 struct intel_crtc_state *crtc_state,
991 struct intel_encoder *intel_encoder)
993 struct intel_shared_dpll *pll;
995 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
998 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
999 pipe_name(intel_crtc->pipe));
1005 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1006 struct intel_crtc_state *crtc_state,
1007 struct intel_encoder *intel_encoder)
1009 struct intel_shared_dpll *pll;
1011 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1013 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1014 pipe_name(intel_crtc->pipe));
1022 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1023 struct intel_crtc_state *crtc_state,
1024 struct intel_encoder *intel_encoder)
1026 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1030 * Tries to find a *shared* PLL for the CRTC and store it in
1031 * intel_crtc->ddi_pll_sel.
1033 * For private DPLLs, compute_config() should do the selection for us. This
1034 * function should be folded into compute_config() eventually.
1036 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1037 struct intel_crtc_state *crtc_state)
1039 struct drm_device *dev = intel_crtc->base.dev;
1040 struct intel_encoder *intel_encoder =
1041 intel_ddi_get_crtc_new_encoder(crtc_state);
1043 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1044 return skl_ddi_pll_select(intel_crtc, crtc_state,
1046 else if (IS_BROXTON(dev))
1047 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1050 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1054 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1056 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1058 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1060 int type = intel_encoder->type;
1063 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1064 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1066 temp = TRANS_MSA_SYNC_CLK;
1067 switch (intel_crtc->config->pipe_bpp) {
1069 temp |= TRANS_MSA_6_BPC;
1072 temp |= TRANS_MSA_8_BPC;
1075 temp |= TRANS_MSA_10_BPC;
1078 temp |= TRANS_MSA_12_BPC;
1083 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1087 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1090 struct drm_device *dev = crtc->dev;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
1092 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1094 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1096 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1098 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1099 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1102 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1105 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1106 struct drm_encoder *encoder = &intel_encoder->base;
1107 struct drm_device *dev = crtc->dev;
1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109 enum pipe pipe = intel_crtc->pipe;
1110 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1111 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1112 int type = intel_encoder->type;
1115 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1116 temp = TRANS_DDI_FUNC_ENABLE;
1117 temp |= TRANS_DDI_SELECT_PORT(port);
1119 switch (intel_crtc->config->pipe_bpp) {
1121 temp |= TRANS_DDI_BPC_6;
1124 temp |= TRANS_DDI_BPC_8;
1127 temp |= TRANS_DDI_BPC_10;
1130 temp |= TRANS_DDI_BPC_12;
1136 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1137 temp |= TRANS_DDI_PVSYNC;
1138 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1139 temp |= TRANS_DDI_PHSYNC;
1141 if (cpu_transcoder == TRANSCODER_EDP) {
1144 /* On Haswell, can only use the always-on power well for
1145 * eDP when not using the panel fitter, and when not
1146 * using motion blur mitigation (which we don't
1148 if (IS_HASWELL(dev) &&
1149 (intel_crtc->config->pch_pfit.enabled ||
1150 intel_crtc->config->pch_pfit.force_thru))
1151 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1153 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1156 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1159 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1167 if (type == INTEL_OUTPUT_HDMI) {
1168 if (intel_crtc->config->has_hdmi_sink)
1169 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1171 temp |= TRANS_DDI_MODE_SELECT_DVI;
1173 } else if (type == INTEL_OUTPUT_ANALOG) {
1174 temp |= TRANS_DDI_MODE_SELECT_FDI;
1175 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1177 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1178 type == INTEL_OUTPUT_EDP) {
1179 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1181 if (intel_dp->is_mst) {
1182 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1184 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1186 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1187 } else if (type == INTEL_OUTPUT_DP_MST) {
1188 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1190 if (intel_dp->is_mst) {
1191 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1193 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1195 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1197 WARN(1, "Invalid encoder type %d for pipe %c\n",
1198 intel_encoder->type, pipe_name(pipe));
1201 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1204 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1205 enum transcoder cpu_transcoder)
1207 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1208 uint32_t val = I915_READ(reg);
1210 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1211 val |= TRANS_DDI_PORT_NONE;
1212 I915_WRITE(reg, val);
1215 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1217 struct drm_device *dev = intel_connector->base.dev;
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 struct intel_encoder *intel_encoder = intel_connector->encoder;
1220 int type = intel_connector->base.connector_type;
1221 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1223 enum transcoder cpu_transcoder;
1224 enum intel_display_power_domain power_domain;
1228 power_domain = intel_display_port_power_domain(intel_encoder);
1229 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1232 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1238 cpu_transcoder = TRANSCODER_EDP;
1240 cpu_transcoder = (enum transcoder) pipe;
1242 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1244 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1245 case TRANS_DDI_MODE_SELECT_HDMI:
1246 case TRANS_DDI_MODE_SELECT_DVI:
1247 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1250 case TRANS_DDI_MODE_SELECT_DP_SST:
1251 ret = type == DRM_MODE_CONNECTOR_eDP ||
1252 type == DRM_MODE_CONNECTOR_DisplayPort;
1255 case TRANS_DDI_MODE_SELECT_DP_MST:
1256 /* if the transcoder is in MST state then
1257 * connector isn't connected */
1261 case TRANS_DDI_MODE_SELECT_FDI:
1262 ret = type == DRM_MODE_CONNECTOR_VGA;
1271 intel_display_power_put(dev_priv, power_domain);
1276 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1279 struct drm_device *dev = encoder->base.dev;
1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 enum port port = intel_ddi_get_encoder_port(encoder);
1282 enum intel_display_power_domain power_domain;
1287 power_domain = intel_display_port_power_domain(encoder);
1288 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1293 tmp = I915_READ(DDI_BUF_CTL(port));
1295 if (!(tmp & DDI_BUF_CTL_ENABLE))
1298 if (port == PORT_A) {
1299 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1301 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1302 case TRANS_DDI_EDP_INPUT_A_ON:
1303 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1306 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1309 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1319 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1320 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1322 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1323 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1324 TRANS_DDI_MODE_SELECT_DP_MST)
1334 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1337 intel_display_power_put(dev_priv, power_domain);
1342 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1344 struct drm_crtc *crtc = &intel_crtc->base;
1345 struct drm_device *dev = crtc->dev;
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1348 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1349 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1351 if (cpu_transcoder != TRANSCODER_EDP)
1352 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1353 TRANS_CLK_SEL_PORT(port));
1356 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1358 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1359 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1361 if (cpu_transcoder != TRANSCODER_EDP)
1362 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1363 TRANS_CLK_SEL_DISABLED);
1366 static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1367 u32 level, enum port port, int type)
1369 const struct ddi_buf_trans *ddi_translations;
1371 uint8_t dp_iboost, hdmi_iboost;
1375 /* VBT may override standard boost values */
1376 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1377 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1379 if (type == INTEL_OUTPUT_DISPLAYPORT) {
1383 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
1384 iboost = ddi_translations[level].i_boost;
1386 } else if (type == INTEL_OUTPUT_EDP) {
1390 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1392 if (WARN_ON(port != PORT_A &&
1393 port != PORT_E && n_entries > 9))
1396 iboost = ddi_translations[level].i_boost;
1398 } else if (type == INTEL_OUTPUT_HDMI) {
1400 iboost = hdmi_iboost;
1402 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1403 iboost = ddi_translations[level].i_boost;
1409 /* Make sure that the requested I_boost is valid */
1410 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1411 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1415 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
1416 reg &= ~BALANCE_LEG_MASK(port);
1417 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
1420 reg |= iboost << BALANCE_LEG_SHIFT(port);
1422 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
1424 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
1427 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1428 u32 level, enum port port, int type)
1430 const struct bxt_ddi_buf_trans *ddi_translations;
1434 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1435 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1436 ddi_translations = bxt_ddi_translations_edp;
1437 } else if (type == INTEL_OUTPUT_DISPLAYPORT
1438 || type == INTEL_OUTPUT_EDP) {
1439 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1440 ddi_translations = bxt_ddi_translations_dp;
1441 } else if (type == INTEL_OUTPUT_HDMI) {
1442 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1443 ddi_translations = bxt_ddi_translations_hdmi;
1445 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1450 /* Check if default value has to be used */
1451 if (level >= n_entries ||
1452 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1453 for (i = 0; i < n_entries; i++) {
1454 if (ddi_translations[i].default_index) {
1462 * While we write to the group register to program all lanes at once we
1463 * can read only lane registers and we pick lanes 0/1 for that.
1465 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1466 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1467 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1469 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1470 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1471 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1472 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1473 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1475 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1476 val &= ~SCALE_DCOMP_METHOD;
1477 if (ddi_translations[level].enable)
1478 val |= SCALE_DCOMP_METHOD;
1480 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1481 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1483 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1485 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1486 val &= ~DE_EMPHASIS;
1487 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1488 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1490 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1491 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1492 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1495 static uint32_t translate_signal_level(int signal_levels)
1499 switch (signal_levels) {
1501 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1503 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1509 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1512 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1516 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1519 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1533 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1541 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1543 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1544 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1545 struct intel_encoder *encoder = &dport->base;
1546 uint8_t train_set = intel_dp->train_set[0];
1547 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1548 DP_TRAIN_PRE_EMPHASIS_MASK);
1549 enum port port = dport->port;
1552 level = translate_signal_level(signal_levels);
1554 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1555 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
1556 else if (IS_BROXTON(dev_priv))
1557 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1559 return DDI_BUF_TRANS_SELECT(level);
1562 void intel_ddi_clk_select(struct intel_encoder *encoder,
1563 const struct intel_crtc_state *pipe_config)
1565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1566 enum port port = intel_ddi_get_encoder_port(encoder);
1568 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1569 uint32_t dpll = pipe_config->ddi_pll_sel;
1572 /* DDI -> PLL mapping */
1573 val = I915_READ(DPLL_CTRL2);
1575 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1576 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1577 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1578 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1580 I915_WRITE(DPLL_CTRL2, val);
1582 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1583 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1584 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
1588 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1590 struct drm_encoder *encoder = &intel_encoder->base;
1591 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1592 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1593 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1594 int type = intel_encoder->type;
1596 intel_prepare_ddi_buffer(intel_encoder);
1598 if (type == INTEL_OUTPUT_EDP) {
1599 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1600 intel_edp_panel_on(intel_dp);
1603 intel_ddi_clk_select(intel_encoder, crtc->config);
1605 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1606 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1608 intel_dp_set_link_params(intel_dp, crtc->config);
1610 intel_ddi_init_dp_buf_reg(intel_encoder);
1612 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1613 intel_dp_start_link_train(intel_dp);
1614 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
1615 intel_dp_stop_link_train(intel_dp);
1616 } else if (type == INTEL_OUTPUT_HDMI) {
1617 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1619 intel_hdmi->set_infoframes(encoder,
1620 crtc->config->has_hdmi_sink,
1621 &crtc->config->base.adjusted_mode);
1625 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1627 struct drm_encoder *encoder = &intel_encoder->base;
1628 struct drm_device *dev = encoder->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1631 int type = intel_encoder->type;
1635 val = I915_READ(DDI_BUF_CTL(port));
1636 if (val & DDI_BUF_CTL_ENABLE) {
1637 val &= ~DDI_BUF_CTL_ENABLE;
1638 I915_WRITE(DDI_BUF_CTL(port), val);
1642 val = I915_READ(DP_TP_CTL(port));
1643 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1644 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1645 I915_WRITE(DP_TP_CTL(port), val);
1648 intel_wait_ddi_buf_idle(dev_priv, port);
1650 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1651 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1652 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1653 intel_edp_panel_vdd_on(intel_dp);
1654 intel_edp_panel_off(intel_dp);
1657 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1658 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1659 DPLL_CTRL2_DDI_CLK_OFF(port)));
1660 else if (INTEL_INFO(dev)->gen < 9)
1661 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1664 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1666 struct drm_encoder *encoder = &intel_encoder->base;
1667 struct drm_crtc *crtc = encoder->crtc;
1668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1669 struct drm_device *dev = encoder->dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1672 int type = intel_encoder->type;
1674 if (type == INTEL_OUTPUT_HDMI) {
1675 struct intel_digital_port *intel_dig_port =
1676 enc_to_dig_port(encoder);
1678 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1679 * are ignored so nothing special needs to be done besides
1680 * enabling the port.
1682 I915_WRITE(DDI_BUF_CTL(port),
1683 intel_dig_port->saved_port_bits |
1684 DDI_BUF_CTL_ENABLE);
1685 } else if (type == INTEL_OUTPUT_EDP) {
1686 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1688 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1689 intel_dp_stop_link_train(intel_dp);
1691 intel_edp_backlight_on(intel_dp);
1692 intel_psr_enable(intel_dp);
1693 intel_edp_drrs_enable(intel_dp);
1696 if (intel_crtc->config->has_audio) {
1697 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1698 intel_audio_codec_enable(intel_encoder);
1702 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1704 struct drm_encoder *encoder = &intel_encoder->base;
1705 struct drm_crtc *crtc = encoder->crtc;
1706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1707 int type = intel_encoder->type;
1708 struct drm_device *dev = encoder->dev;
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1711 if (intel_crtc->config->has_audio) {
1712 intel_audio_codec_disable(intel_encoder);
1713 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1716 if (type == INTEL_OUTPUT_EDP) {
1717 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1719 intel_edp_drrs_disable(intel_dp);
1720 intel_psr_disable(intel_dp);
1721 intel_edp_backlight_off(intel_dp);
1725 static void broxton_phy_init(struct drm_i915_private *dev_priv,
1731 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1732 val |= GT_DISPLAY_POWER_ON(phy);
1733 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1735 /* Considering 10ms timeout until BSpec is updated */
1736 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
1737 DRM_ERROR("timeout during PHY%d power on\n", phy);
1739 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
1740 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
1743 for (lane = 0; lane < 4; lane++) {
1744 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
1746 * Note that on CHV this flag is called UPAR, but has
1747 * the same function.
1749 val &= ~LATENCY_OPTIM;
1751 val |= LATENCY_OPTIM;
1753 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
1757 /* Program PLL Rcomp code offset */
1758 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1759 val &= ~IREF0RC_OFFSET_MASK;
1760 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1761 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1763 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1764 val &= ~IREF1RC_OFFSET_MASK;
1765 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1766 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1768 /* Program power gating */
1769 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1770 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1772 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1774 if (phy == DPIO_PHY0) {
1775 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1776 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1777 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1780 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1781 val &= ~OCL2_LDOFUSE_PWR_DIS;
1783 * On PHY1 disable power on the second channel, since no port is
1784 * connected there. On PHY0 both channels have a port, so leave it
1786 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1787 * power down the second channel on PHY0 as well.
1789 if (phy == DPIO_PHY1)
1790 val |= OCL2_LDOFUSE_PWR_DIS;
1791 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1793 if (phy == DPIO_PHY0) {
1796 * PHY0 isn't connected to an RCOMP resistor so copy over
1797 * the corresponding calibrated value from PHY1, and disable
1798 * the automatic calibration on PHY0.
1800 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
1802 DRM_ERROR("timeout waiting for PHY1 GRC\n");
1804 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
1805 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1806 grc_code = val << GRC_CODE_FAST_SHIFT |
1807 val << GRC_CODE_SLOW_SHIFT |
1809 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1811 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1812 val |= GRC_DIS | GRC_RDY_OVRD;
1813 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1816 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1817 val |= COMMON_RESET_DIS;
1818 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1821 void broxton_ddi_phy_init(struct drm_device *dev)
1823 /* Enable PHY1 first since it provides Rcomp for PHY0 */
1824 broxton_phy_init(dev->dev_private, DPIO_PHY1);
1825 broxton_phy_init(dev->dev_private, DPIO_PHY0);
1828 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
1833 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1834 val &= ~COMMON_RESET_DIS;
1835 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1838 void broxton_ddi_phy_uninit(struct drm_device *dev)
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1842 broxton_phy_uninit(dev_priv, DPIO_PHY1);
1843 broxton_phy_uninit(dev_priv, DPIO_PHY0);
1845 /* FIXME: do this in broxton_phy_uninit per phy */
1846 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
1849 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
1851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1852 struct drm_i915_private *dev_priv =
1853 to_i915(intel_dig_port->base.base.dev);
1854 enum port port = intel_dig_port->port;
1858 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1859 val = I915_READ(DDI_BUF_CTL(port));
1860 if (val & DDI_BUF_CTL_ENABLE) {
1861 val &= ~DDI_BUF_CTL_ENABLE;
1862 I915_WRITE(DDI_BUF_CTL(port), val);
1866 val = I915_READ(DP_TP_CTL(port));
1867 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1868 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1869 I915_WRITE(DP_TP_CTL(port), val);
1870 POSTING_READ(DP_TP_CTL(port));
1873 intel_wait_ddi_buf_idle(dev_priv, port);
1876 val = DP_TP_CTL_ENABLE |
1877 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1878 if (intel_dp->is_mst)
1879 val |= DP_TP_CTL_MODE_MST;
1881 val |= DP_TP_CTL_MODE_SST;
1882 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1883 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1885 I915_WRITE(DP_TP_CTL(port), val);
1886 POSTING_READ(DP_TP_CTL(port));
1888 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1889 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1890 POSTING_READ(DDI_BUF_CTL(port));
1895 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1897 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1898 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1901 intel_ddi_post_disable(intel_encoder);
1903 val = I915_READ(FDI_RX_CTL(PIPE_A));
1904 val &= ~FDI_RX_ENABLE;
1905 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1907 val = I915_READ(FDI_RX_MISC(PIPE_A));
1908 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1909 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1910 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1912 val = I915_READ(FDI_RX_CTL(PIPE_A));
1914 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1916 val = I915_READ(FDI_RX_CTL(PIPE_A));
1917 val &= ~FDI_RX_PLL_ENABLE;
1918 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1921 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1922 struct intel_crtc *intel_crtc)
1926 if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1927 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1929 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1931 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
1938 void intel_ddi_get_config(struct intel_encoder *encoder,
1939 struct intel_crtc_state *pipe_config)
1941 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1942 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1943 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1944 struct intel_hdmi *intel_hdmi;
1945 u32 temp, flags = 0;
1947 /* XXX: DSI transcoder paranoia */
1948 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
1951 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1952 if (temp & TRANS_DDI_PHSYNC)
1953 flags |= DRM_MODE_FLAG_PHSYNC;
1955 flags |= DRM_MODE_FLAG_NHSYNC;
1956 if (temp & TRANS_DDI_PVSYNC)
1957 flags |= DRM_MODE_FLAG_PVSYNC;
1959 flags |= DRM_MODE_FLAG_NVSYNC;
1961 pipe_config->base.adjusted_mode.flags |= flags;
1963 switch (temp & TRANS_DDI_BPC_MASK) {
1964 case TRANS_DDI_BPC_6:
1965 pipe_config->pipe_bpp = 18;
1967 case TRANS_DDI_BPC_8:
1968 pipe_config->pipe_bpp = 24;
1970 case TRANS_DDI_BPC_10:
1971 pipe_config->pipe_bpp = 30;
1973 case TRANS_DDI_BPC_12:
1974 pipe_config->pipe_bpp = 36;
1980 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1981 case TRANS_DDI_MODE_SELECT_HDMI:
1982 pipe_config->has_hdmi_sink = true;
1983 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1985 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
1986 pipe_config->has_infoframe = true;
1988 case TRANS_DDI_MODE_SELECT_DVI:
1989 case TRANS_DDI_MODE_SELECT_FDI:
1991 case TRANS_DDI_MODE_SELECT_DP_SST:
1992 case TRANS_DDI_MODE_SELECT_DP_MST:
1993 pipe_config->has_dp_encoder = true;
1994 pipe_config->lane_count =
1995 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
1996 intel_dp_get_m_n(intel_crtc, pipe_config);
2002 pipe_config->has_audio =
2003 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2005 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2006 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2008 * This is a big fat ugly hack.
2010 * Some machines in UEFI boot mode provide us a VBT that has 18
2011 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2012 * unknown we fail to light up. Yet the same BIOS boots up with
2013 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2014 * max, not what it tells us to use.
2016 * Note: This will still be broken if the eDP panel is not lit
2017 * up by the BIOS, and thus we can't get the mode at module
2020 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2021 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2022 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2025 intel_ddi_clock_get(encoder, pipe_config);
2028 static void intel_ddi_destroy(struct drm_encoder *encoder)
2030 /* HDMI has nothing special to destroy, so we can go with this. */
2031 intel_dp_encoder_destroy(encoder);
2034 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2035 struct intel_crtc_state *pipe_config)
2037 int type = encoder->type;
2038 int port = intel_ddi_get_encoder_port(encoder);
2040 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2043 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2045 if (type == INTEL_OUTPUT_HDMI)
2046 return intel_hdmi_compute_config(encoder, pipe_config);
2048 return intel_dp_compute_config(encoder, pipe_config);
2051 static const struct drm_encoder_funcs intel_ddi_funcs = {
2052 .destroy = intel_ddi_destroy,
2055 static struct intel_connector *
2056 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2058 struct intel_connector *connector;
2059 enum port port = intel_dig_port->port;
2061 connector = intel_connector_alloc();
2065 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2066 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2074 static struct intel_connector *
2075 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2077 struct intel_connector *connector;
2078 enum port port = intel_dig_port->port;
2080 connector = intel_connector_alloc();
2084 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2085 intel_hdmi_init_connector(intel_dig_port, connector);
2090 void intel_ddi_init(struct drm_device *dev, enum port port)
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 struct intel_digital_port *intel_dig_port;
2094 struct intel_encoder *intel_encoder;
2095 struct drm_encoder *encoder;
2096 bool init_hdmi, init_dp;
2099 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2125 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2126 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2127 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2128 if (!init_dp && !init_hdmi) {
2129 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2134 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2135 if (!intel_dig_port)
2138 intel_encoder = &intel_dig_port->base;
2139 encoder = &intel_encoder->base;
2141 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2142 DRM_MODE_ENCODER_TMDS, NULL);
2144 intel_encoder->compute_config = intel_ddi_compute_config;
2145 intel_encoder->enable = intel_enable_ddi;
2146 intel_encoder->pre_enable = intel_ddi_pre_enable;
2147 intel_encoder->disable = intel_disable_ddi;
2148 intel_encoder->post_disable = intel_ddi_post_disable;
2149 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2150 intel_encoder->get_config = intel_ddi_get_config;
2152 intel_dig_port->port = port;
2153 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2154 (DDI_BUF_PORT_REVERSAL |
2158 * Bspec says that DDI_A_4_LANES is the only supported configuration
2159 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2160 * wasn't lit up at boot. Force this bit on in our internal
2161 * configuration so that we use the proper lane count for our
2164 if (IS_BROXTON(dev) && port == PORT_A) {
2165 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2166 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2167 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2172 intel_dig_port->max_lanes = max_lanes;
2174 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2175 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2176 intel_encoder->cloneable = 0;
2179 if (!intel_ddi_init_dp_connector(intel_dig_port))
2182 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2184 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2185 * interrupts to check the external panel connection.
2187 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
2188 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2190 dev_priv->hotplug.irq_port[port] = intel_dig_port;
2193 /* In theory we don't need the encoder->type check, but leave it just in
2194 * case we have some really bad VBTs... */
2195 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2196 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2203 drm_encoder_cleanup(encoder);
2204 kfree(intel_dig_port);