drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45         0x00FFFFFF, 0x00040006          /* HDMI parameters */
  46 };
  47
  48 static const u32 hsw_ddi_translations_fdi[] = {
  49         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  50         0x00D75FFF, 0x000F000A,
  51         0x00C30FFF, 0x00060006,
  52         0x00AAAFFF, 0x001E0000,
  53         0x00FFFFFF, 0x000F000A,
  54         0x00D75FFF, 0x00160004,
  55         0x00C30FFF, 0x001E0000,
  56         0x00FFFFFF, 0x00060006,
  57         0x00D75FFF, 0x001E0000,
  58         0x00FFFFFF, 0x00040006          /* HDMI parameters */
  59 };
  60
  61 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
  62 {
  63         struct drm_encoder *encoder = &intel_encoder->base;
  64         int type = intel_encoder->type;
  65
  66         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
  67             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
  68                 struct intel_digital_port *intel_dig_port =
  69                         enc_to_dig_port(encoder);
  70                 return intel_dig_port->port;
  71
  72         } else if (type == INTEL_OUTPUT_ANALOG) {
  73                 return PORT_E;
  74
  75         } else {
  76                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
  77                 BUG();
  78         }
  79 }
  80
  81 /* On Haswell, DDI port buffers must be programmed with correct values
  82  * in advance. The buffer values are different for FDI and DP modes,
  83  * but the HDMI/DVI fields are shared among those. So we program the DDI
  84  * in either FDI or DP modes only, as HDMI connections will work with both
  85  * of those
  86  */
  87 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
  88                                       bool use_fdi_mode)
  89 {
  90         struct drm_i915_private *dev_priv = dev->dev_private;
  91         u32 reg;
  92         int i;
  93         const u32 *ddi_translations = ((use_fdi_mode) ?
  94                 hsw_ddi_translations_fdi :
  95                 hsw_ddi_translations_dp);
  96
  97         DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
  98                         port_name(port),
  99                         use_fdi_mode ? "FDI" : "DP");
 100
 101         WARN((use_fdi_mode && (port != PORT_E)),
 102                 "Programming port %c in FDI mode, this probably will not work.\n",
 103                 port_name(port));
 104
 105         for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 106                 I915_WRITE(reg, ddi_translations[i]);
 107                 reg += 4;
 108         }
 109 }
 110
 111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 112  * mode and port E for FDI.
 113  */
 114 void intel_prepare_ddi(struct drm_device *dev)
 115 {
 116         int port;
 117
 118         if (!HAS_DDI(dev))
 119                 return;
 120
 121         for (port = PORT_A; port < PORT_E; port++)
 122                 intel_prepare_ddi_buffers(dev, port, false);
 123
 124         /* DDI E is the suggested one to work in FDI mode, so program is as such
 125          * by default. It will have to be re-programmed in case a digital DP
 126          * output will be detected on it
 127          */
 128         intel_prepare_ddi_buffers(dev, PORT_E, true);
 129 }
 130
 131 static const long hsw_ddi_buf_ctl_values[] = {
 132         DDI_BUF_EMP_400MV_0DB_HSW,
 133         DDI_BUF_EMP_400MV_3_5DB_HSW,
 134         DDI_BUF_EMP_400MV_6DB_HSW,
 135         DDI_BUF_EMP_400MV_9_5DB_HSW,
 136         DDI_BUF_EMP_600MV_0DB_HSW,
 137         DDI_BUF_EMP_600MV_3_5DB_HSW,
 138         DDI_BUF_EMP_600MV_6DB_HSW,
 139         DDI_BUF_EMP_800MV_0DB_HSW,
 140         DDI_BUF_EMP_800MV_3_5DB_HSW
 141 };
 142
 143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 144                                     enum port port)
 145 {
 146         uint32_t reg = DDI_BUF_CTL(port);
 147         int i;
 148
 149         for (i = 0; i < 8; i++) {
 150                 udelay(1);
 151                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 152                         return;
 153         }
 154         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 155 }
 156
 157 /* Starting with Haswell, different DDI ports can work in FDI mode for
 158  * connection to the PCH-located connectors. For this, it is necessary to train
 159  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 160  *
 161  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 162  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 163  * DDI A (which is used for eDP)
 164  */
 165
 166 void hsw_fdi_link_train(struct drm_crtc *crtc)
 167 {
 168         struct drm_device *dev = crtc->dev;
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 171         u32 temp, i, rx_ctl_val;
 172
 173         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 174          * mode set "sequence for CRT port" document:
 175          * - TP1 to TP2 time with the default value
 176          * - FDI delay to 90h
 177          */
 178         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 179                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 180                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 181
 182         /* Enable the PCH Receiver FDI PLL */
 183         rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
 184                      ((intel_crtc->fdi_lanes - 1) << 19);
 185         if (dev_priv->fdi_rx_polarity_reversed)
 186                 rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT;
 187         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 188         POSTING_READ(_FDI_RXA_CTL);
 189         udelay(220);
 190
 191         /* Switch from Rawclk to PCDclk */
 192         rx_ctl_val |= FDI_PCDCLK;
 193         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 194
 195         /* Configure Port Clock Select */
 196         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
 197
 198         /* Start the training iterating through available voltages and emphasis,
 199          * testing each value twice. */
 200         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 201                 /* Configure DP_TP_CTL with auto-training */
 202                 I915_WRITE(DP_TP_CTL(PORT_E),
 203                                         DP_TP_CTL_FDI_AUTOTRAIN |
 204                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 205                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 206                                         DP_TP_CTL_ENABLE);
 207
 208                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
 209                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 210                            DDI_BUF_CTL_ENABLE |
 211                            ((intel_crtc->fdi_lanes - 1) << 1) |
 212                            hsw_ddi_buf_ctl_values[i / 2]);
 213                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 214
 215                 udelay(600);
 216
 217                 /* Program PCH FDI Receiver TU */
 218                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 219
 220                 /* Enable PCH FDI Receiver with auto-training */
 221                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 222                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 223                 POSTING_READ(_FDI_RXA_CTL);
 224
 225                 /* Wait for FDI receiver lane calibration */
 226                 udelay(30);
 227
 228                 /* Unset FDI_RX_MISC pwrdn lanes */
 229                 temp = I915_READ(_FDI_RXA_MISC);
 230                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 231                 I915_WRITE(_FDI_RXA_MISC, temp);
 232                 POSTING_READ(_FDI_RXA_MISC);
 233
 234                 /* Wait for FDI auto training time */
 235                 udelay(5);
 236
 237                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 238                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 239                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 240
 241                         /* Enable normal pixel sending for FDI */
 242                         I915_WRITE(DP_TP_CTL(PORT_E),
 243                                    DP_TP_CTL_FDI_AUTOTRAIN |
 244                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 245                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 246                                    DP_TP_CTL_ENABLE);
 247
 248                         return;
 249                 }
 250
 251                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 252                 temp &= ~DDI_BUF_CTL_ENABLE;
 253                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 254                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 255
 256                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 257                 temp = I915_READ(DP_TP_CTL(PORT_E));
 258                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 259                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 260                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 261                 POSTING_READ(DP_TP_CTL(PORT_E));
 262
 263                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 264
 265                 rx_ctl_val &= ~FDI_RX_ENABLE;
 266                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 267                 POSTING_READ(_FDI_RXA_CTL);
 268
 269                 /* Reset FDI_RX_MISC pwrdn lanes */
 270                 temp = I915_READ(_FDI_RXA_MISC);
 271                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 272                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 273                 I915_WRITE(_FDI_RXA_MISC, temp);
 274                 POSTING_READ(_FDI_RXA_MISC);
 275         }
 276
 277         DRM_ERROR("FDI link training failed!\n");
 278 }
 279
 280 /* WRPLL clock dividers */
 281 struct wrpll_tmds_clock {
 282         u32 clock;
 283         u16 p;          /* Post divider */
 284         u16 n2;         /* Feedback divider */
 285         u16 r2;         /* Reference divider */
 286 };
 287
 288 /* Table of matching values for WRPLL clocks programming for each frequency.
 289  * The code assumes this table is sorted. */
 290 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
 291         {19750, 38,     25,     18},
 292         {20000, 48,     32,     18},
 293         {21000, 36,     21,     15},
 294         {21912, 42,     29,     17},
 295         {22000, 36,     22,     15},
 296         {23000, 36,     23,     15},
 297         {23500, 40,     40,     23},
 298         {23750, 26,     16,     14},
 299         {24000, 36,     24,     15},
 300         {25000, 36,     25,     15},
 301         {25175, 26,     40,     33},
 302         {25200, 30,     21,     15},
 303         {26000, 36,     26,     15},
 304         {27000, 30,     21,     14},
 305         {27027, 18,     100,    111},
 306         {27500, 30,     29,     19},
 307         {28000, 34,     30,     17},
 308         {28320, 26,     30,     22},
 309         {28322, 32,     42,     25},
 310         {28750, 24,     23,     18},
 311         {29000, 30,     29,     18},
 312         {29750, 32,     30,     17},
 313         {30000, 30,     25,     15},
 314         {30750, 30,     41,     24},
 315         {31000, 30,     31,     18},
 316         {31500, 30,     28,     16},
 317         {32000, 30,     32,     18},
 318         {32500, 28,     32,     19},
 319         {33000, 24,     22,     15},
 320         {34000, 28,     30,     17},
 321         {35000, 26,     32,     19},
 322         {35500, 24,     30,     19},
 323         {36000, 26,     26,     15},
 324         {36750, 26,     46,     26},
 325         {37000, 24,     23,     14},
 326         {37762, 22,     40,     26},
 327         {37800, 20,     21,     15},
 328         {38000, 24,     27,     16},
 329         {38250, 24,     34,     20},
 330         {39000, 24,     26,     15},
 331         {40000, 24,     32,     18},
 332         {40500, 20,     21,     14},
 333         {40541, 22,     147,    89},
 334         {40750, 18,     19,     14},
 335         {41000, 16,     17,     14},
 336         {41500, 22,     44,     26},
 337         {41540, 22,     44,     26},
 338         {42000, 18,     21,     15},
 339         {42500, 22,     45,     26},
 340         {43000, 20,     43,     27},
 341         {43163, 20,     24,     15},
 342         {44000, 18,     22,     15},
 343         {44900, 20,     108,    65},
 344         {45000, 20,     25,     15},
 345         {45250, 20,     52,     31},
 346         {46000, 18,     23,     15},
 347         {46750, 20,     45,     26},
 348         {47000, 20,     40,     23},
 349         {48000, 18,     24,     15},
 350         {49000, 18,     49,     30},
 351         {49500, 16,     22,     15},
 352         {50000, 18,     25,     15},
 353         {50500, 18,     32,     19},
 354         {51000, 18,     34,     20},
 355         {52000, 18,     26,     15},
 356         {52406, 14,     34,     25},
 357         {53000, 16,     22,     14},
 358         {54000, 16,     24,     15},
 359         {54054, 16,     173,    108},
 360         {54500, 14,     24,     17},
 361         {55000, 12,     22,     18},
 362         {56000, 14,     45,     31},
 363         {56250, 16,     25,     15},
 364         {56750, 14,     25,     17},
 365         {57000, 16,     27,     16},
 366         {58000, 16,     43,     25},
 367         {58250, 16,     38,     22},
 368         {58750, 16,     40,     23},
 369         {59000, 14,     26,     17},
 370         {59341, 14,     40,     26},
 371         {59400, 16,     44,     25},
 372         {60000, 16,     32,     18},
 373         {60500, 12,     39,     29},
 374         {61000, 14,     49,     31},
 375         {62000, 14,     37,     23},
 376         {62250, 14,     42,     26},
 377         {63000, 12,     21,     15},
 378         {63500, 14,     28,     17},
 379         {64000, 12,     27,     19},
 380         {65000, 14,     32,     19},
 381         {65250, 12,     29,     20},
 382         {65500, 12,     32,     22},
 383         {66000, 12,     22,     15},
 384         {66667, 14,     38,     22},
 385         {66750, 10,     21,     17},
 386         {67000, 14,     33,     19},
 387         {67750, 14,     58,     33},
 388         {68000, 14,     30,     17},
 389         {68179, 14,     46,     26},
 390         {68250, 14,     46,     26},
 391         {69000, 12,     23,     15},
 392         {70000, 12,     28,     18},
 393         {71000, 12,     30,     19},
 394         {72000, 12,     24,     15},
 395         {73000, 10,     23,     17},
 396         {74000, 12,     23,     14},
 397         {74176, 8,      100,    91},
 398         {74250, 10,     22,     16},
 399         {74481, 12,     43,     26},
 400         {74500, 10,     29,     21},
 401         {75000, 12,     25,     15},
 402         {75250, 10,     39,     28},
 403         {76000, 12,     27,     16},
 404         {77000, 12,     53,     31},
 405         {78000, 12,     26,     15},
 406         {78750, 12,     28,     16},
 407         {79000, 10,     38,     26},
 408         {79500, 10,     28,     19},
 409         {80000, 12,     32,     18},
 410         {81000, 10,     21,     14},
 411         {81081, 6,      100,    111},
 412         {81624, 8,      29,     24},
 413         {82000, 8,      17,     14},
 414         {83000, 10,     40,     26},
 415         {83950, 10,     28,     18},
 416         {84000, 10,     28,     18},
 417         {84750, 6,      16,     17},
 418         {85000, 6,      17,     18},
 419         {85250, 10,     30,     19},
 420         {85750, 10,     27,     17},
 421         {86000, 10,     43,     27},
 422         {87000, 10,     29,     18},
 423         {88000, 10,     44,     27},
 424         {88500, 10,     41,     25},
 425         {89000, 10,     28,     17},
 426         {89012, 6,      90,     91},
 427         {89100, 10,     33,     20},
 428         {90000, 10,     25,     15},
 429         {91000, 10,     32,     19},
 430         {92000, 10,     46,     27},
 431         {93000, 10,     31,     18},
 432         {94000, 10,     40,     23},
 433         {94500, 10,     28,     16},
 434         {95000, 10,     44,     25},
 435         {95654, 10,     39,     22},
 436         {95750, 10,     39,     22},
 437         {96000, 10,     32,     18},
 438         {97000, 8,      23,     16},
 439         {97750, 8,      42,     29},
 440         {98000, 8,      45,     31},
 441         {99000, 8,      22,     15},
 442         {99750, 8,      34,     23},
 443         {100000,        6,      20,     18},
 444         {100500,        6,      19,     17},
 445         {101000,        6,      37,     33},
 446         {101250,        8,      21,     14},
 447         {102000,        6,      17,     15},
 448         {102250,        6,      25,     22},
 449         {103000,        8,      29,     19},
 450         {104000,        8,      37,     24},
 451         {105000,        8,      28,     18},
 452         {106000,        8,      22,     14},
 453         {107000,        8,      46,     29},
 454         {107214,        8,      27,     17},
 455         {108000,        8,      24,     15},
 456         {108108,        8,      173,    108},
 457         {109000,        6,      23,     19},
 458         {110000,        6,      22,     18},
 459         {110013,        6,      22,     18},
 460         {110250,        8,      49,     30},
 461         {110500,        8,      36,     22},
 462         {111000,        8,      23,     14},
 463         {111264,        8,      150,    91},
 464         {111375,        8,      33,     20},
 465         {112000,        8,      63,     38},
 466         {112500,        8,      25,     15},
 467         {113100,        8,      57,     34},
 468         {113309,        8,      42,     25},
 469         {114000,        8,      27,     16},
 470         {115000,        6,      23,     18},
 471         {116000,        8,      43,     25},
 472         {117000,        8,      26,     15},
 473         {117500,        8,      40,     23},
 474         {118000,        6,      38,     29},
 475         {119000,        8,      30,     17},
 476         {119500,        8,      46,     26},
 477         {119651,        8,      39,     22},
 478         {120000,        8,      32,     18},
 479         {121000,        6,      39,     29},
 480         {121250,        6,      31,     23},
 481         {121750,        6,      23,     17},
 482         {122000,        6,      42,     31},
 483         {122614,        6,      30,     22},
 484         {123000,        6,      41,     30},
 485         {123379,        6,      37,     27},
 486         {124000,        6,      51,     37},
 487         {125000,        6,      25,     18},
 488         {125250,        4,      13,     14},
 489         {125750,        4,      27,     29},
 490         {126000,        6,      21,     15},
 491         {127000,        6,      24,     17},
 492         {127250,        6,      41,     29},
 493         {128000,        6,      27,     19},
 494         {129000,        6,      43,     30},
 495         {129859,        4,      25,     26},
 496         {130000,        6,      26,     18},
 497         {130250,        6,      42,     29},
 498         {131000,        6,      32,     22},
 499         {131500,        6,      38,     26},
 500         {131850,        6,      41,     28},
 501         {132000,        6,      22,     15},
 502         {132750,        6,      28,     19},
 503         {133000,        6,      34,     23},
 504         {133330,        6,      37,     25},
 505         {134000,        6,      61,     41},
 506         {135000,        6,      21,     14},
 507         {135250,        6,      167,    111},
 508         {136000,        6,      62,     41},
 509         {137000,        6,      35,     23},
 510         {138000,        6,      23,     15},
 511         {138500,        6,      40,     26},
 512         {138750,        6,      37,     24},
 513         {139000,        6,      34,     22},
 514         {139050,        6,      34,     22},
 515         {139054,        6,      34,     22},
 516         {140000,        6,      28,     18},
 517         {141000,        6,      36,     23},
 518         {141500,        6,      22,     14},
 519         {142000,        6,      30,     19},
 520         {143000,        6,      27,     17},
 521         {143472,        4,      17,     16},
 522         {144000,        6,      24,     15},
 523         {145000,        6,      29,     18},
 524         {146000,        6,      47,     29},
 525         {146250,        6,      26,     16},
 526         {147000,        6,      49,     30},
 527         {147891,        6,      23,     14},
 528         {148000,        6,      23,     14},
 529         {148250,        6,      28,     17},
 530         {148352,        4,      100,    91},
 531         {148500,        6,      33,     20},
 532         {149000,        6,      48,     29},
 533         {150000,        6,      25,     15},
 534         {151000,        4,      19,     17},
 535         {152000,        6,      27,     16},
 536         {152280,        6,      44,     26},
 537         {153000,        6,      34,     20},
 538         {154000,        6,      53,     31},
 539         {155000,        6,      31,     18},
 540         {155250,        6,      50,     29},
 541         {155750,        6,      45,     26},
 542         {156000,        6,      26,     15},
 543         {157000,        6,      61,     35},
 544         {157500,        6,      28,     16},
 545         {158000,        6,      65,     37},
 546         {158250,        6,      44,     25},
 547         {159000,        6,      53,     30},
 548         {159500,        6,      39,     22},
 549         {160000,        6,      32,     18},
 550         {161000,        4,      31,     26},
 551         {162000,        4,      18,     15},
 552         {162162,        4,      131,    109},
 553         {162500,        4,      53,     44},
 554         {163000,        4,      29,     24},
 555         {164000,        4,      17,     14},
 556         {165000,        4,      22,     18},
 557         {166000,        4,      32,     26},
 558         {167000,        4,      26,     21},
 559         {168000,        4,      46,     37},
 560         {169000,        4,      104,    83},
 561         {169128,        4,      64,     51},
 562         {169500,        4,      39,     31},
 563         {170000,        4,      34,     27},
 564         {171000,        4,      19,     15},
 565         {172000,        4,      51,     40},
 566         {172750,        4,      32,     25},
 567         {172800,        4,      32,     25},
 568         {173000,        4,      41,     32},
 569         {174000,        4,      49,     38},
 570         {174787,        4,      22,     17},
 571         {175000,        4,      35,     27},
 572         {176000,        4,      30,     23},
 573         {177000,        4,      38,     29},
 574         {178000,        4,      29,     22},
 575         {178500,        4,      37,     28},
 576         {179000,        4,      53,     40},
 577         {179500,        4,      73,     55},
 578         {180000,        4,      20,     15},
 579         {181000,        4,      55,     41},
 580         {182000,        4,      31,     23},
 581         {183000,        4,      42,     31},
 582         {184000,        4,      30,     22},
 583         {184750,        4,      26,     19},
 584         {185000,        4,      37,     27},
 585         {186000,        4,      51,     37},
 586         {187000,        4,      36,     26},
 587         {188000,        4,      32,     23},
 588         {189000,        4,      21,     15},
 589         {190000,        4,      38,     27},
 590         {190960,        4,      41,     29},
 591         {191000,        4,      41,     29},
 592         {192000,        4,      27,     19},
 593         {192250,        4,      37,     26},
 594         {193000,        4,      20,     14},
 595         {193250,        4,      53,     37},
 596         {194000,        4,      23,     16},
 597         {194208,        4,      23,     16},
 598         {195000,        4,      26,     18},
 599         {196000,        4,      45,     31},
 600         {197000,        4,      35,     24},
 601         {197750,        4,      41,     28},
 602         {198000,        4,      22,     15},
 603         {198500,        4,      25,     17},
 604         {199000,        4,      28,     19},
 605         {200000,        4,      37,     25},
 606         {201000,        4,      61,     41},
 607         {202000,        4,      112,    75},
 608         {202500,        4,      21,     14},
 609         {203000,        4,      146,    97},
 610         {204000,        4,      62,     41},
 611         {204750,        4,      44,     29},
 612         {205000,        4,      38,     25},
 613         {206000,        4,      29,     19},
 614         {207000,        4,      23,     15},
 615         {207500,        4,      40,     26},
 616         {208000,        4,      37,     24},
 617         {208900,        4,      48,     31},
 618         {209000,        4,      48,     31},
 619         {209250,        4,      31,     20},
 620         {210000,        4,      28,     18},
 621         {211000,        4,      25,     16},
 622         {212000,        4,      22,     14},
 623         {213000,        4,      30,     19},
 624         {213750,        4,      38,     24},
 625         {214000,        4,      46,     29},
 626         {214750,        4,      35,     22},
 627         {215000,        4,      43,     27},
 628         {216000,        4,      24,     15},
 629         {217000,        4,      37,     23},
 630         {218000,        4,      42,     26},
 631         {218250,        4,      42,     26},
 632         {218750,        4,      34,     21},
 633         {219000,        4,      47,     29},
 634         {220000,        4,      44,     27},
 635         {220640,        4,      49,     30},
 636         {220750,        4,      36,     22},
 637         {221000,        4,      36,     22},
 638         {222000,        4,      23,     14},
 639         {222525,        4,      28,     17},
 640         {222750,        4,      33,     20},
 641         {227000,        4,      37,     22},
 642         {230250,        4,      29,     17},
 643         {233500,        4,      38,     22},
 644         {235000,        4,      40,     23},
 645         {238000,        4,      30,     17},
 646         {241500,        2,      17,     19},
 647         {245250,        2,      20,     22},
 648         {247750,        2,      22,     24},
 649         {253250,        2,      15,     16},
 650         {256250,        2,      18,     19},
 651         {262500,        2,      31,     32},
 652         {267250,        2,      66,     67},
 653         {268500,        2,      94,     95},
 654         {270000,        2,      14,     14},
 655         {272500,        2,      77,     76},
 656         {273750,        2,      57,     56},
 657         {280750,        2,      24,     23},
 658         {281250,        2,      23,     22},
 659         {286000,        2,      17,     16},
 660         {291750,        2,      26,     24},
 661         {296703,        2,      56,     51},
 662         {297000,        2,      22,     20},
 663         {298000,        2,      21,     19},
 664 };
 665
 666 static void intel_ddi_mode_set(struct drm_encoder *encoder,
 667                                struct drm_display_mode *mode,
 668                                struct drm_display_mode *adjusted_mode)
 669 {
 670         struct drm_crtc *crtc = encoder->crtc;
 671         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 672         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
 673         int port = intel_ddi_get_encoder_port(intel_encoder);
 674         int pipe = intel_crtc->pipe;
 675         int type = intel_encoder->type;
 676
 677         DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
 678                       port_name(port), pipe_name(pipe));
 679
 680         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 681                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 682
 683                 intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
 684                 switch (intel_dp->lane_count) {
 685                 case 1:
 686                         intel_dp->DP |= DDI_PORT_WIDTH_X1;
 687                         break;
 688                 case 2:
 689                         intel_dp->DP |= DDI_PORT_WIDTH_X2;
 690                         break;
 691                 case 4:
 692                         intel_dp->DP |= DDI_PORT_WIDTH_X4;
 693                         break;
 694                 default:
 695                         intel_dp->DP |= DDI_PORT_WIDTH_X4;
 696                         WARN(1, "Unexpected DP lane count %d\n",
 697                              intel_dp->lane_count);
 698                         break;
 699                 }
 700
 701                 if (intel_dp->has_audio) {
 702                         DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
 703                                          pipe_name(intel_crtc->pipe));
 704
 705                         /* write eld */
 706                         DRM_DEBUG_DRIVER("DP audio: write eld information\n");
 707                         intel_write_eld(encoder, adjusted_mode);
 708                 }
 709
 710                 intel_dp_init_link_config(intel_dp);
 711
 712         } else if (type == INTEL_OUTPUT_HDMI) {
 713                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 714
 715                 if (intel_hdmi->has_audio) {
 716                         /* Proper support for digital audio needs a new logic
 717                          * and a new set of registers, so we leave it for future
 718                          * patch bombing.
 719                          */
 720                         DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
 721                                          pipe_name(intel_crtc->pipe));
 722
 723                         /* write eld */
 724                         DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
 725                         intel_write_eld(encoder, adjusted_mode);
 726                 }
 727
 728                 intel_hdmi->set_infoframes(encoder, adjusted_mode);
 729         }
 730 }
 731
 732 static struct intel_encoder *
 733 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 734 {
 735         struct drm_device *dev = crtc->dev;
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737         struct intel_encoder *intel_encoder, *ret = NULL;
 738         int num_encoders = 0;
 739
 740         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 741                 ret = intel_encoder;
 742                 num_encoders++;
 743         }
 744
 745         if (num_encoders != 1)
 746                 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
 747                      intel_crtc->pipe);
 748
 749         BUG_ON(ret == NULL);
 750         return ret;
 751 }
 752
 753 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 754 {
 755         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 756         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 758         uint32_t val;
 759
 760         switch (intel_crtc->ddi_pll_sel) {
 761         case PORT_CLK_SEL_SPLL:
 762                 plls->spll_refcount--;
 763                 if (plls->spll_refcount == 0) {
 764                         DRM_DEBUG_KMS("Disabling SPLL\n");
 765                         val = I915_READ(SPLL_CTL);
 766                         WARN_ON(!(val & SPLL_PLL_ENABLE));
 767                         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 768                         POSTING_READ(SPLL_CTL);
 769                 }
 770                 break;
 771         case PORT_CLK_SEL_WRPLL1:
 772                 plls->wrpll1_refcount--;
 773                 if (plls->wrpll1_refcount == 0) {
 774                         DRM_DEBUG_KMS("Disabling WRPLL 1\n");
 775                         val = I915_READ(WRPLL_CTL1);
 776                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 777                         I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 778                         POSTING_READ(WRPLL_CTL1);
 779                 }
 780                 break;
 781         case PORT_CLK_SEL_WRPLL2:
 782                 plls->wrpll2_refcount--;
 783                 if (plls->wrpll2_refcount == 0) {
 784                         DRM_DEBUG_KMS("Disabling WRPLL 2\n");
 785                         val = I915_READ(WRPLL_CTL2);
 786                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 787                         I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 788                         POSTING_READ(WRPLL_CTL2);
 789                 }
 790                 break;
 791         }
 792
 793         WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
 794         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 795         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 796
 797         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
 798 }
 799
 800 static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
 801 {
 802         u32 i;
 803
 804         for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
 805                 if (clock <= wrpll_tmds_clock_table[i].clock)
 806                         break;
 807
 808         if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
 809                 i--;
 810
 811         *p = wrpll_tmds_clock_table[i].p;
 812         *n2 = wrpll_tmds_clock_table[i].n2;
 813         *r2 = wrpll_tmds_clock_table[i].r2;
 814
 815         if (wrpll_tmds_clock_table[i].clock != clock)
 816                 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
 817                          wrpll_tmds_clock_table[i].clock, clock);
 818
 819         DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
 820                       clock, *p, *n2, *r2);
 821 }
 822
 823 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
 824 {
 825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 826         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 827         struct drm_encoder *encoder = &intel_encoder->base;
 828         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 829         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 830         int type = intel_encoder->type;
 831         enum pipe pipe = intel_crtc->pipe;
 832         uint32_t reg, val;
 833
 834         /* TODO: reuse PLLs when possible (compare values) */
 835
 836         intel_ddi_put_crtc_pll(crtc);
 837
 838         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 839                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 840
 841                 switch (intel_dp->link_bw) {
 842                 case DP_LINK_BW_1_62:
 843                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 844                         break;
 845                 case DP_LINK_BW_2_7:
 846                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 847                         break;
 848                 case DP_LINK_BW_5_4:
 849                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 850                         break;
 851                 default:
 852                         DRM_ERROR("Link bandwidth %d unsupported\n",
 853                                   intel_dp->link_bw);
 854                         return false;
 855                 }
 856
 857                 /* We don't need to turn any PLL on because we'll use LCPLL. */
 858                 return true;
 859
 860         } else if (type == INTEL_OUTPUT_HDMI) {
 861                 int p, n2, r2;
 862
 863                 if (plls->wrpll1_refcount == 0) {
 864                         DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
 865                                       pipe_name(pipe));
 866                         plls->wrpll1_refcount++;
 867                         reg = WRPLL_CTL1;
 868                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 869                 } else if (plls->wrpll2_refcount == 0) {
 870                         DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
 871                                       pipe_name(pipe));
 872                         plls->wrpll2_refcount++;
 873                         reg = WRPLL_CTL2;
 874                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 875                 } else {
 876                         DRM_ERROR("No WRPLLs available!\n");
 877                         return false;
 878                 }
 879
 880                 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
 881                      "WRPLL already enabled\n");
 882
 883                 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
 884
 885                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
 886                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 887                       WRPLL_DIVIDER_POST(p);
 888
 889         } else if (type == INTEL_OUTPUT_ANALOG) {
 890                 if (plls->spll_refcount == 0) {
 891                         DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 892                                       pipe_name(pipe));
 893                         plls->spll_refcount++;
 894                         reg = SPLL_CTL;
 895                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 896                 }
 897
 898                 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
 899                      "SPLL already enabled\n");
 900
 901                 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 902
 903         } else {
 904                 WARN(1, "Invalid DDI encoder type %d\n", type);
 905                 return false;
 906         }
 907
 908         I915_WRITE(reg, val);
 909         udelay(20);
 910
 911         return true;
 912 }
 913
 914 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 915 {
 916         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 918         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 919         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 920         int type = intel_encoder->type;
 921         uint32_t temp;
 922
 923         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 924
 925                 temp = TRANS_MSA_SYNC_CLK;
 926                 switch (intel_crtc->bpp) {
 927                 case 18:
 928                         temp |= TRANS_MSA_6_BPC;
 929                         break;
 930                 case 24:
 931                         temp |= TRANS_MSA_8_BPC;
 932                         break;
 933                 case 30:
 934                         temp |= TRANS_MSA_10_BPC;
 935                         break;
 936                 case 36:
 937                         temp |= TRANS_MSA_12_BPC;
 938                         break;
 939                 default:
 940                         temp |= TRANS_MSA_8_BPC;
 941                         WARN(1, "%d bpp unsupported by DDI function\n",
 942                              intel_crtc->bpp);
 943                 }
 944                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 945         }
 946 }
 947
 948 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 949 {
 950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 951         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 952         struct drm_encoder *encoder = &intel_encoder->base;
 953         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 954         enum pipe pipe = intel_crtc->pipe;
 955         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 956         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 957         int type = intel_encoder->type;
 958         uint32_t temp;
 959
 960         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 961         temp = TRANS_DDI_FUNC_ENABLE;
 962         temp |= TRANS_DDI_SELECT_PORT(port);
 963
 964         switch (intel_crtc->bpp) {
 965         case 18:
 966                 temp |= TRANS_DDI_BPC_6;
 967                 break;
 968         case 24:
 969                 temp |= TRANS_DDI_BPC_8;
 970                 break;
 971         case 30:
 972                 temp |= TRANS_DDI_BPC_10;
 973                 break;
 974         case 36:
 975                 temp |= TRANS_DDI_BPC_12;
 976                 break;
 977         default:
 978                 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
 979                      intel_crtc->bpp);
 980         }
 981
 982         if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
 983                 temp |= TRANS_DDI_PVSYNC;
 984         if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
 985                 temp |= TRANS_DDI_PHSYNC;
 986
 987         if (cpu_transcoder == TRANSCODER_EDP) {
 988                 switch (pipe) {
 989                 case PIPE_A:
 990                         temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 991                         break;
 992                 case PIPE_B:
 993                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 994                         break;
 995                 case PIPE_C:
 996                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 997                         break;
 998                 default:
 999                         BUG();
1000                         break;
1001                 }
1002         }
1003
1004         if (type == INTEL_OUTPUT_HDMI) {
1005                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1006
1007                 if (intel_hdmi->has_hdmi_sink)
1008                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1009                 else
1010                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1011
1012         } else if (type == INTEL_OUTPUT_ANALOG) {
1013                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1014                 temp |= (intel_crtc->fdi_lanes - 1) << 1;
1015
1016         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1017                    type == INTEL_OUTPUT_EDP) {
1018                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1019
1020                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1021
1022                 switch (intel_dp->lane_count) {
1023                 case 1:
1024                         temp |= TRANS_DDI_PORT_WIDTH_X1;
1025                         break;
1026                 case 2:
1027                         temp |= TRANS_DDI_PORT_WIDTH_X2;
1028                         break;
1029                 case 4:
1030                         temp |= TRANS_DDI_PORT_WIDTH_X4;
1031                         break;
1032                 default:
1033                         temp |= TRANS_DDI_PORT_WIDTH_X4;
1034                         WARN(1, "Unsupported lane count %d\n",
1035                              intel_dp->lane_count);
1036                 }
1037
1038         } else {
1039                 WARN(1, "Invalid encoder type %d for pipe %d\n",
1040                      intel_encoder->type, pipe);
1041         }
1042
1043         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1044 }
1045
1046 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1047                                        enum transcoder cpu_transcoder)
1048 {
1049         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1050         uint32_t val = I915_READ(reg);
1051
1052         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1053         val |= TRANS_DDI_PORT_NONE;
1054         I915_WRITE(reg, val);
1055 }
1056
1057 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1058 {
1059         struct drm_device *dev = intel_connector->base.dev;
1060         struct drm_i915_private *dev_priv = dev->dev_private;
1061         struct intel_encoder *intel_encoder = intel_connector->encoder;
1062         int type = intel_connector->base.connector_type;
1063         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1064         enum pipe pipe = 0;
1065         enum transcoder cpu_transcoder;
1066         uint32_t tmp;
1067
1068         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1069                 return false;
1070
1071         if (port == PORT_A)
1072                 cpu_transcoder = TRANSCODER_EDP;
1073         else
1074                 cpu_transcoder = (enum transcoder) pipe;
1075
1076         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1077
1078         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1079         case TRANS_DDI_MODE_SELECT_HDMI:
1080         case TRANS_DDI_MODE_SELECT_DVI:
1081                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1082
1083         case TRANS_DDI_MODE_SELECT_DP_SST:
1084                 if (type == DRM_MODE_CONNECTOR_eDP)
1085                         return true;
1086         case TRANS_DDI_MODE_SELECT_DP_MST:
1087                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1088
1089         case TRANS_DDI_MODE_SELECT_FDI:
1090                 return (type == DRM_MODE_CONNECTOR_VGA);
1091
1092         default:
1093                 return false;
1094         }
1095 }
1096
1097 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1098                             enum pipe *pipe)
1099 {
1100         struct drm_device *dev = encoder->base.dev;
1101         struct drm_i915_private *dev_priv = dev->dev_private;
1102         enum port port = intel_ddi_get_encoder_port(encoder);
1103         u32 tmp;
1104         int i;
1105
1106         tmp = I915_READ(DDI_BUF_CTL(port));
1107
1108         if (!(tmp & DDI_BUF_CTL_ENABLE))
1109                 return false;
1110
1111         if (port == PORT_A) {
1112                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1113
1114                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1115                 case TRANS_DDI_EDP_INPUT_A_ON:
1116                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1117                         *pipe = PIPE_A;
1118                         break;
1119                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1120                         *pipe = PIPE_B;
1121                         break;
1122                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1123                         *pipe = PIPE_C;
1124                         break;
1125                 }
1126
1127                 return true;
1128         } else {
1129                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1130                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1131
1132                         if ((tmp & TRANS_DDI_PORT_MASK)
1133                             == TRANS_DDI_SELECT_PORT(port)) {
1134                                 *pipe = i;
1135                                 return true;
1136                         }
1137                 }
1138         }
1139
1140         DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
1141
1142         return true;
1143 }
1144
1145 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1146                                        enum pipe pipe)
1147 {
1148         uint32_t temp, ret;
1149         enum port port;
1150         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1151                                                                       pipe);
1152         int i;
1153
1154         if (cpu_transcoder == TRANSCODER_EDP) {
1155                 port = PORT_A;
1156         } else {
1157                 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1158                 temp &= TRANS_DDI_PORT_MASK;
1159
1160                 for (i = PORT_B; i <= PORT_E; i++)
1161                         if (temp == TRANS_DDI_SELECT_PORT(i))
1162                                 port = i;
1163         }
1164
1165         ret = I915_READ(PORT_CLK_SEL(port));
1166
1167         DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1168                       pipe_name(pipe), port_name(port), ret);
1169
1170         return ret;
1171 }
1172
1173 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176         enum pipe pipe;
1177         struct intel_crtc *intel_crtc;
1178
1179         for_each_pipe(pipe) {
1180                 intel_crtc =
1181                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1182
1183                 if (!intel_crtc->active)
1184                         continue;
1185
1186                 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1187                                                                  pipe);
1188
1189                 switch (intel_crtc->ddi_pll_sel) {
1190                 case PORT_CLK_SEL_SPLL:
1191                         dev_priv->ddi_plls.spll_refcount++;
1192                         break;
1193                 case PORT_CLK_SEL_WRPLL1:
1194                         dev_priv->ddi_plls.wrpll1_refcount++;
1195                         break;
1196                 case PORT_CLK_SEL_WRPLL2:
1197                         dev_priv->ddi_plls.wrpll2_refcount++;
1198                         break;
1199                 }
1200         }
1201 }
1202
1203 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1204 {
1205         struct drm_crtc *crtc = &intel_crtc->base;
1206         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1207         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1208         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1209         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1210
1211         if (cpu_transcoder != TRANSCODER_EDP)
1212                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1213                            TRANS_CLK_SEL_PORT(port));
1214 }
1215
1216 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1217 {
1218         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1219         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1220
1221         if (cpu_transcoder != TRANSCODER_EDP)
1222                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1223                            TRANS_CLK_SEL_DISABLED);
1224 }
1225
1226 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1227 {
1228         struct drm_encoder *encoder = &intel_encoder->base;
1229         struct drm_crtc *crtc = encoder->crtc;
1230         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1232         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1233         int type = intel_encoder->type;
1234
1235         if (type == INTEL_OUTPUT_EDP) {
1236                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1237                 ironlake_edp_panel_vdd_on(intel_dp);
1238                 ironlake_edp_panel_on(intel_dp);
1239                 ironlake_edp_panel_vdd_off(intel_dp, true);
1240         }
1241
1242         WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1243         I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1244
1245         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1246                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1247
1248                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1249                 intel_dp_start_link_train(intel_dp);
1250                 intel_dp_complete_link_train(intel_dp);
1251         }
1252 }
1253
1254 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1255 {
1256         struct drm_encoder *encoder = &intel_encoder->base;
1257         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1258         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1259         int type = intel_encoder->type;
1260         uint32_t val;
1261         bool wait = false;
1262
1263         val = I915_READ(DDI_BUF_CTL(port));
1264         if (val & DDI_BUF_CTL_ENABLE) {
1265                 val &= ~DDI_BUF_CTL_ENABLE;
1266                 I915_WRITE(DDI_BUF_CTL(port), val);
1267                 wait = true;
1268         }
1269
1270         val = I915_READ(DP_TP_CTL(port));
1271         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1272         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1273         I915_WRITE(DP_TP_CTL(port), val);
1274
1275         if (wait)
1276                 intel_wait_ddi_buf_idle(dev_priv, port);
1277
1278         if (type == INTEL_OUTPUT_EDP) {
1279                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1280                 ironlake_edp_panel_vdd_on(intel_dp);
1281                 ironlake_edp_panel_off(intel_dp);
1282         }
1283
1284         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1285 }
1286
1287 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1288 {
1289         struct drm_encoder *encoder = &intel_encoder->base;
1290         struct drm_device *dev = encoder->dev;
1291         struct drm_i915_private *dev_priv = dev->dev_private;
1292         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1293         int type = intel_encoder->type;
1294
1295         if (type == INTEL_OUTPUT_HDMI) {
1296                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1297                  * are ignored so nothing special needs to be done besides
1298                  * enabling the port.
1299                  */
1300                 I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
1301         } else if (type == INTEL_OUTPUT_EDP) {
1302                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1303
1304                 ironlake_edp_backlight_on(intel_dp);
1305         }
1306 }
1307
1308 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1309 {
1310         struct drm_encoder *encoder = &intel_encoder->base;
1311         int type = intel_encoder->type;
1312
1313         if (type == INTEL_OUTPUT_EDP) {
1314                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1315
1316                 ironlake_edp_backlight_off(intel_dp);
1317         }
1318 }
1319
1320 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1321 {
1322         if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1323                 return 450;
1324         else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1325                  LCPLL_CLK_FREQ_450)
1326                 return 450;
1327         else if (IS_ULT(dev_priv->dev))
1328                 return 338;
1329         else
1330                 return 540;
1331 }
1332
1333 void intel_ddi_pll_init(struct drm_device *dev)
1334 {
1335         struct drm_i915_private *dev_priv = dev->dev_private;
1336         uint32_t val = I915_READ(LCPLL_CTL);
1337
1338         /* The LCPLL register should be turned on by the BIOS. For now let's
1339          * just check its state and print errors in case something is wrong.
1340          * Don't even try to turn it on.
1341          */
1342
1343         DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1344                       intel_ddi_get_cdclk_freq(dev_priv));
1345
1346         if (val & LCPLL_CD_SOURCE_FCLK)
1347                 DRM_ERROR("CDCLK source is not LCPLL\n");
1348
1349         if (val & LCPLL_PLL_DISABLE)
1350                 DRM_ERROR("LCPLL is disabled\n");
1351 }
1352
1353 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1354 {
1355         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1356         struct intel_dp *intel_dp = &intel_dig_port->dp;
1357         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1358         enum port port = intel_dig_port->port;
1359         bool wait;
1360         uint32_t val;
1361
1362         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1363                 val = I915_READ(DDI_BUF_CTL(port));
1364                 if (val & DDI_BUF_CTL_ENABLE) {
1365                         val &= ~DDI_BUF_CTL_ENABLE;
1366                         I915_WRITE(DDI_BUF_CTL(port), val);
1367                         wait = true;
1368                 }
1369
1370                 val = I915_READ(DP_TP_CTL(port));
1371                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1372                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1373                 I915_WRITE(DP_TP_CTL(port), val);
1374                 POSTING_READ(DP_TP_CTL(port));
1375
1376                 if (wait)
1377                         intel_wait_ddi_buf_idle(dev_priv, port);
1378         }
1379
1380         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1381               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1382         if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1383                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1384         I915_WRITE(DP_TP_CTL(port), val);
1385         POSTING_READ(DP_TP_CTL(port));
1386
1387         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1388         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1389         POSTING_READ(DDI_BUF_CTL(port));
1390
1391         udelay(600);
1392 }
1393
1394 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1395 {
1396         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1397         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1398         uint32_t val;
1399
1400         intel_ddi_post_disable(intel_encoder);
1401
1402         val = I915_READ(_FDI_RXA_CTL);
1403         val &= ~FDI_RX_ENABLE;
1404         I915_WRITE(_FDI_RXA_CTL, val);
1405
1406         val = I915_READ(_FDI_RXA_MISC);
1407         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1408         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1409         I915_WRITE(_FDI_RXA_MISC, val);
1410
1411         val = I915_READ(_FDI_RXA_CTL);
1412         val &= ~FDI_PCDCLK;
1413         I915_WRITE(_FDI_RXA_CTL, val);
1414
1415         val = I915_READ(_FDI_RXA_CTL);
1416         val &= ~FDI_RX_PLL_ENABLE;
1417         I915_WRITE(_FDI_RXA_CTL, val);
1418 }
1419
1420 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1421 {
1422         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1423         int type = intel_encoder->type;
1424
1425         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1426                 intel_dp_check_link_status(intel_dp);
1427 }
1428
1429 static void intel_ddi_destroy(struct drm_encoder *encoder)
1430 {
1431         /* HDMI has nothing special to destroy, so we can go with this. */
1432         intel_dp_encoder_destroy(encoder);
1433 }
1434
1435 static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1436                                  const struct drm_display_mode *mode,
1437                                  struct drm_display_mode *adjusted_mode)
1438 {
1439         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1440         int type = intel_encoder->type;
1441
1442         WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1443
1444         if (type == INTEL_OUTPUT_HDMI)
1445                 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1446         else
1447                 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1448 }
1449
1450 static const struct drm_encoder_funcs intel_ddi_funcs = {
1451         .destroy = intel_ddi_destroy,
1452 };
1453
1454 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1455         .mode_fixup = intel_ddi_mode_fixup,
1456         .mode_set = intel_ddi_mode_set,
1457         .disable = intel_encoder_noop,
1458 };
1459
1460 void intel_ddi_init(struct drm_device *dev, enum port port)
1461 {
1462         struct intel_digital_port *intel_dig_port;
1463         struct intel_encoder *intel_encoder;
1464         struct drm_encoder *encoder;
1465         struct intel_connector *hdmi_connector = NULL;
1466         struct intel_connector *dp_connector = NULL;
1467
1468         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1469         if (!intel_dig_port)
1470                 return;
1471
1472         dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1473         if (!dp_connector) {
1474                 kfree(intel_dig_port);
1475                 return;
1476         }
1477
1478         if (port != PORT_A) {
1479                 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1480                                          GFP_KERNEL);
1481                 if (!hdmi_connector) {
1482                         kfree(dp_connector);
1483                         kfree(intel_dig_port);
1484                         return;
1485                 }
1486         }
1487
1488         intel_encoder = &intel_dig_port->base;
1489         encoder = &intel_encoder->base;
1490
1491         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1492                          DRM_MODE_ENCODER_TMDS);
1493         drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1494
1495         intel_encoder->enable = intel_enable_ddi;
1496         intel_encoder->pre_enable = intel_ddi_pre_enable;
1497         intel_encoder->disable = intel_disable_ddi;
1498         intel_encoder->post_disable = intel_ddi_post_disable;
1499         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1500
1501         intel_dig_port->port = port;
1502         if (hdmi_connector)
1503                 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1504         else
1505                 intel_dig_port->hdmi.sdvox_reg = 0;
1506         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1507
1508         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1509         intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
1510         intel_encoder->cloneable = false;
1511         intel_encoder->hot_plug = intel_ddi_hot_plug;
1512
1513         if (hdmi_connector)
1514                 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1515         intel_dp_init_connector(intel_dig_port, dp_connector);
1516 }