drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34 };
  35
  36 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  37  * them for both DP and FDI transports, allowing those ports to
  38  * automatically adapt to HDMI connections as well
  39  */
  40 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  41         { 0x00FFFFFF, 0x0006000E },
  42         { 0x00D75FFF, 0x0005000A },
  43         { 0x00C30FFF, 0x00040006 },
  44         { 0x80AAAFFF, 0x000B0000 },
  45         { 0x00FFFFFF, 0x0005000A },
  46         { 0x00D75FFF, 0x000C0004 },
  47         { 0x80C30FFF, 0x000B0000 },
  48         { 0x00FFFFFF, 0x00040006 },
  49         { 0x80D75FFF, 0x000B0000 },
  50 };
  51
  52 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  53         { 0x00FFFFFF, 0x0007000E },
  54         { 0x00D75FFF, 0x000F000A },
  55         { 0x00C30FFF, 0x00060006 },
  56         { 0x00AAAFFF, 0x001E0000 },
  57         { 0x00FFFFFF, 0x000F000A },
  58         { 0x00D75FFF, 0x00160004 },
  59         { 0x00C30FFF, 0x001E0000 },
  60         { 0x00FFFFFF, 0x00060006 },
  61         { 0x00D75FFF, 0x001E0000 },
  62 };
  63
  64 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  65                                         /* Idx  NT mV d T mV d  db      */
  66         { 0x00FFFFFF, 0x0006000E },     /* 0:   400     400     0       */
  67         { 0x00E79FFF, 0x000E000C },     /* 1:   400     500     2       */
  68         { 0x00D75FFF, 0x0005000A },     /* 2:   400     600     3.5     */
  69         { 0x00FFFFFF, 0x0005000A },     /* 3:   600     600     0       */
  70         { 0x00E79FFF, 0x001D0007 },     /* 4:   600     750     2       */
  71         { 0x00D75FFF, 0x000C0004 },     /* 5:   600     900     3.5     */
  72         { 0x00FFFFFF, 0x00040006 },     /* 6:   800     800     0       */
  73         { 0x80E79FFF, 0x00030002 },     /* 7:   800     1000    2       */
  74         { 0x00FFFFFF, 0x00140005 },     /* 8:   850     850     0       */
  75         { 0x00FFFFFF, 0x000C0004 },     /* 9:   900     900     0       */
  76         { 0x00FFFFFF, 0x001C0003 },     /* 10:  950     950     0       */
  77         { 0x80FFFFFF, 0x00030002 },     /* 11:  1000    1000    0       */
  78 };
  79
  80 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  81         { 0x00FFFFFF, 0x00000012 },
  82         { 0x00EBAFFF, 0x00020011 },
  83         { 0x00C71FFF, 0x0006000F },
  84         { 0x00AAAFFF, 0x000E000A },
  85         { 0x00FFFFFF, 0x00020011 },
  86         { 0x00DB6FFF, 0x0005000F },
  87         { 0x00BEEFFF, 0x000A000C },
  88         { 0x00FFFFFF, 0x0005000F },
  89         { 0x00DB6FFF, 0x000A000C },
  90 };
  91
  92 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  93         { 0x00FFFFFF, 0x0007000E },
  94         { 0x00D75FFF, 0x000E000A },
  95         { 0x00BEFFFF, 0x00140006 },
  96         { 0x80B2CFFF, 0x001B0002 },
  97         { 0x00FFFFFF, 0x000E000A },
  98         { 0x00DB6FFF, 0x00160005 },
  99         { 0x80C71FFF, 0x001A0002 },
 100         { 0x00F7DFFF, 0x00180004 },
 101         { 0x80D75FFF, 0x001B0002 },
 102 };
 103
 104 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 105         { 0x00FFFFFF, 0x0001000E },
 106         { 0x00D75FFF, 0x0004000A },
 107         { 0x00C30FFF, 0x00070006 },
 108         { 0x00AAAFFF, 0x000C0000 },
 109         { 0x00FFFFFF, 0x0004000A },
 110         { 0x00D75FFF, 0x00090004 },
 111         { 0x00C30FFF, 0x000C0000 },
 112         { 0x00FFFFFF, 0x00070006 },
 113         { 0x00D75FFF, 0x000C0000 },
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 117                                         /* Idx  NT mV d T mV df db      */
 118         { 0x00FFFFFF, 0x0007000E },     /* 0:   400     400     0       */
 119         { 0x00D75FFF, 0x000E000A },     /* 1:   400     600     3.5     */
 120         { 0x00BEFFFF, 0x00140006 },     /* 2:   400     800     6       */
 121         { 0x00FFFFFF, 0x0009000D },     /* 3:   450     450     0       */
 122         { 0x00FFFFFF, 0x000E000A },     /* 4:   600     600     0       */
 123         { 0x00D7FFFF, 0x00140006 },     /* 5:   600     800     2.5     */
 124         { 0x80CB2FFF, 0x001B0002 },     /* 6:   600     1000    4.5     */
 125         { 0x00FFFFFF, 0x00140006 },     /* 7:   800     800     0       */
 126         { 0x80E79FFF, 0x001B0002 },     /* 8:   800     1000    2       */
 127         { 0x80FFFFFF, 0x001B0002 },     /* 9:   1000    1000    0       */
 128 };
 129
 130 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 131         { 0x00000018, 0x000000a2 },
 132         { 0x00004014, 0x0000009B },
 133         { 0x00006012, 0x00000088 },
 134         { 0x00008010, 0x00000087 },
 135         { 0x00000018, 0x0000009B },
 136         { 0x00004014, 0x00000088 },
 137         { 0x00006012, 0x00000087 },
 138         { 0x00000018, 0x00000088 },
 139         { 0x00004014, 0x00000087 },
 140 };
 141
 142 /* eDP 1.4 low vswing translation parameters */
 143 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 144         { 0x00000018, 0x000000a8 },
 145         { 0x00002016, 0x000000ab },
 146         { 0x00006012, 0x000000a2 },
 147         { 0x00008010, 0x00000088 },
 148         { 0x00000018, 0x000000ab },
 149         { 0x00004014, 0x000000a2 },
 150         { 0x00006012, 0x000000a6 },
 151         { 0x00000018, 0x000000a2 },
 152         { 0x00005013, 0x0000009c },
 153         { 0x00000018, 0x00000088 },
 154 };
 155
 156
 157 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 158         { 0x00000018, 0x000000ac },
 159         { 0x00005012, 0x0000009d },
 160         { 0x00007011, 0x00000088 },
 161         { 0x00000018, 0x000000a1 },
 162         { 0x00000018, 0x00000098 },
 163         { 0x00004013, 0x00000088 },
 164         { 0x00006012, 0x00000087 },
 165         { 0x00000018, 0x000000df },
 166         { 0x00003015, 0x00000087 },
 167         { 0x00003015, 0x000000c7 },
 168         { 0x00000018, 0x000000c7 },
 169 };
 170
 171 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 172 {
 173         struct drm_encoder *encoder = &intel_encoder->base;
 174         int type = intel_encoder->type;
 175
 176         if (type == INTEL_OUTPUT_DP_MST) {
 177                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 178                 return intel_dig_port->port;
 179         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 180             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 181                 struct intel_digital_port *intel_dig_port =
 182                         enc_to_dig_port(encoder);
 183                 return intel_dig_port->port;
 184
 185         } else if (type == INTEL_OUTPUT_ANALOG) {
 186                 return PORT_E;
 187
 188         } else {
 189                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 190                 BUG();
 191         }
 192 }
 193
 194 /*
 195  * Starting with Haswell, DDI port buffers must be programmed with correct
 196  * values in advance. The buffer values are different for FDI and DP modes,
 197  * but the HDMI/DVI fields are shared among those. So we program the DDI
 198  * in either FDI or DP modes only, as HDMI connections will work with both
 199  * of those
 200  */
 201 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 202 {
 203         struct drm_i915_private *dev_priv = dev->dev_private;
 204         u32 reg;
 205         int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 206             size;
 207         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 208         const struct ddi_buf_trans *ddi_translations_fdi;
 209         const struct ddi_buf_trans *ddi_translations_dp;
 210         const struct ddi_buf_trans *ddi_translations_edp;
 211         const struct ddi_buf_trans *ddi_translations_hdmi;
 212         const struct ddi_buf_trans *ddi_translations;
 213
 214         if (IS_SKYLAKE(dev)) {
 215                 ddi_translations_fdi = NULL;
 216                 ddi_translations_dp = skl_ddi_translations_dp;
 217                 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 218                 if (dev_priv->vbt.edp_low_vswing) {
 219                         ddi_translations_edp = skl_ddi_translations_edp;
 220                         n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 221                 } else {
 222                         ddi_translations_edp = skl_ddi_translations_dp;
 223                         n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 224                 }
 225
 226                 ddi_translations_hdmi = skl_ddi_translations_hdmi;
 227                 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 228                 hdmi_default_entry = 7;
 229         } else if (IS_BROADWELL(dev)) {
 230                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 231                 ddi_translations_dp = bdw_ddi_translations_dp;
 232                 ddi_translations_edp = bdw_ddi_translations_edp;
 233                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 234                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 235                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 236                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 237                 hdmi_default_entry = 7;
 238         } else if (IS_HASWELL(dev)) {
 239                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 240                 ddi_translations_dp = hsw_ddi_translations_dp;
 241                 ddi_translations_edp = hsw_ddi_translations_dp;
 242                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 243                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 244                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 245                 hdmi_default_entry = 6;
 246         } else {
 247                 WARN(1, "ddi translation table missing\n");
 248                 ddi_translations_edp = bdw_ddi_translations_dp;
 249                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 250                 ddi_translations_dp = bdw_ddi_translations_dp;
 251                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 252                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 253                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 254                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 255                 hdmi_default_entry = 7;
 256         }
 257
 258         switch (port) {
 259         case PORT_A:
 260                 ddi_translations = ddi_translations_edp;
 261                 size = n_edp_entries;
 262                 break;
 263         case PORT_B:
 264         case PORT_C:
 265                 ddi_translations = ddi_translations_dp;
 266                 size = n_dp_entries;
 267                 break;
 268         case PORT_D:
 269                 if (intel_dp_is_edp(dev, PORT_D)) {
 270                         ddi_translations = ddi_translations_edp;
 271                         size = n_edp_entries;
 272                 } else {
 273                         ddi_translations = ddi_translations_dp;
 274                         size = n_dp_entries;
 275                 }
 276                 break;
 277         case PORT_E:
 278                 if (ddi_translations_fdi)
 279                         ddi_translations = ddi_translations_fdi;
 280                 else
 281                         ddi_translations = ddi_translations_dp;
 282                 size = n_dp_entries;
 283                 break;
 284         default:
 285                 BUG();
 286         }
 287
 288         for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
 289                 I915_WRITE(reg, ddi_translations[i].trans1);
 290                 reg += 4;
 291                 I915_WRITE(reg, ddi_translations[i].trans2);
 292                 reg += 4;
 293         }
 294
 295         /* Choose a good default if VBT is badly populated */
 296         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 297             hdmi_level >= n_hdmi_entries)
 298                 hdmi_level = hdmi_default_entry;
 299
 300         /* Entry 9 is for HDMI: */
 301         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
 302         reg += 4;
 303         I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
 304         reg += 4;
 305 }
 306
 307 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 308  * mode and port E for FDI.
 309  */
 310 void intel_prepare_ddi(struct drm_device *dev)
 311 {
 312         int port;
 313
 314         if (!HAS_DDI(dev))
 315                 return;
 316
 317         for (port = PORT_A; port <= PORT_E; port++)
 318                 intel_prepare_ddi_buffers(dev, port);
 319 }
 320
 321 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 322                                     enum port port)
 323 {
 324         uint32_t reg = DDI_BUF_CTL(port);
 325         int i;
 326
 327         for (i = 0; i < 16; i++) {
 328                 udelay(1);
 329                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 330                         return;
 331         }
 332         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 333 }
 334
 335 /* Starting with Haswell, different DDI ports can work in FDI mode for
 336  * connection to the PCH-located connectors. For this, it is necessary to train
 337  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 338  *
 339  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 340  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 341  * DDI A (which is used for eDP)
 342  */
 343
 344 void hsw_fdi_link_train(struct drm_crtc *crtc)
 345 {
 346         struct drm_device *dev = crtc->dev;
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 349         u32 temp, i, rx_ctl_val;
 350
 351         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 352          * mode set "sequence for CRT port" document:
 353          * - TP1 to TP2 time with the default value
 354          * - FDI delay to 90h
 355          *
 356          * WaFDIAutoLinkSetTimingOverrride:hsw
 357          */
 358         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 359                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 360                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 361
 362         /* Enable the PCH Receiver FDI PLL */
 363         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 364                      FDI_RX_PLL_ENABLE |
 365                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 366         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 367         POSTING_READ(_FDI_RXA_CTL);
 368         udelay(220);
 369
 370         /* Switch from Rawclk to PCDclk */
 371         rx_ctl_val |= FDI_PCDCLK;
 372         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 373
 374         /* Configure Port Clock Select */
 375         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 376         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 377
 378         /* Start the training iterating through available voltages and emphasis,
 379          * testing each value twice. */
 380         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 381                 /* Configure DP_TP_CTL with auto-training */
 382                 I915_WRITE(DP_TP_CTL(PORT_E),
 383                                         DP_TP_CTL_FDI_AUTOTRAIN |
 384                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 385                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 386                                         DP_TP_CTL_ENABLE);
 387
 388                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 389                  * DDI E does not support port reversal, the functionality is
 390                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 391                  * port reversal bit */
 392                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 393                            DDI_BUF_CTL_ENABLE |
 394                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 395                            DDI_BUF_TRANS_SELECT(i / 2));
 396                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 397
 398                 udelay(600);
 399
 400                 /* Program PCH FDI Receiver TU */
 401                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 402
 403                 /* Enable PCH FDI Receiver with auto-training */
 404                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 405                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 406                 POSTING_READ(_FDI_RXA_CTL);
 407
 408                 /* Wait for FDI receiver lane calibration */
 409                 udelay(30);
 410
 411                 /* Unset FDI_RX_MISC pwrdn lanes */
 412                 temp = I915_READ(_FDI_RXA_MISC);
 413                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 414                 I915_WRITE(_FDI_RXA_MISC, temp);
 415                 POSTING_READ(_FDI_RXA_MISC);
 416
 417                 /* Wait for FDI auto training time */
 418                 udelay(5);
 419
 420                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 421                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 422                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 423
 424                         /* Enable normal pixel sending for FDI */
 425                         I915_WRITE(DP_TP_CTL(PORT_E),
 426                                    DP_TP_CTL_FDI_AUTOTRAIN |
 427                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 428                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 429                                    DP_TP_CTL_ENABLE);
 430
 431                         return;
 432                 }
 433
 434                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 435                 temp &= ~DDI_BUF_CTL_ENABLE;
 436                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 437                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 438
 439                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 440                 temp = I915_READ(DP_TP_CTL(PORT_E));
 441                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 442                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 443                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 444                 POSTING_READ(DP_TP_CTL(PORT_E));
 445
 446                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 447
 448                 rx_ctl_val &= ~FDI_RX_ENABLE;
 449                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 450                 POSTING_READ(_FDI_RXA_CTL);
 451
 452                 /* Reset FDI_RX_MISC pwrdn lanes */
 453                 temp = I915_READ(_FDI_RXA_MISC);
 454                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 455                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 456                 I915_WRITE(_FDI_RXA_MISC, temp);
 457                 POSTING_READ(_FDI_RXA_MISC);
 458         }
 459
 460         DRM_ERROR("FDI link training failed!\n");
 461 }
 462
 463 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 464 {
 465         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 466         struct intel_digital_port *intel_dig_port =
 467                 enc_to_dig_port(&encoder->base);
 468
 469         intel_dp->DP = intel_dig_port->saved_port_bits |
 470                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 471         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 472
 473 }
 474
 475 static struct intel_encoder *
 476 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 477 {
 478         struct drm_device *dev = crtc->dev;
 479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 480         struct intel_encoder *intel_encoder, *ret = NULL;
 481         int num_encoders = 0;
 482
 483         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 484                 ret = intel_encoder;
 485                 num_encoders++;
 486         }
 487
 488         if (num_encoders != 1)
 489                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 490                      pipe_name(intel_crtc->pipe));
 491
 492         BUG_ON(ret == NULL);
 493         return ret;
 494 }
 495
 496 static struct intel_encoder *
 497 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 498 {
 499         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 500         struct intel_encoder *ret = NULL;
 501         struct drm_atomic_state *state;
 502         int num_encoders = 0;
 503         int i;
 504
 505         state = crtc_state->base.state;
 506
 507         for (i = 0; i < state->num_connector; i++) {
 508                 if (!state->connectors[i] ||
 509                     state->connector_states[i]->crtc != crtc_state->base.crtc)
 510                         continue;
 511
 512                 ret = to_intel_encoder(state->connector_states[i]->best_encoder);
 513                 num_encoders++;
 514         }
 515
 516         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 517              pipe_name(crtc->pipe));
 518
 519         BUG_ON(ret == NULL);
 520         return ret;
 521 }
 522
 523 #define LC_FREQ 2700
 524 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 525
 526 #define P_MIN 2
 527 #define P_MAX 64
 528 #define P_INC 2
 529
 530 /* Constraints for PLL good behavior */
 531 #define REF_MIN 48
 532 #define REF_MAX 400
 533 #define VCO_MIN 2400
 534 #define VCO_MAX 4800
 535
 536 #define abs_diff(a, b) ({                       \
 537         typeof(a) __a = (a);                    \
 538         typeof(b) __b = (b);                    \
 539         (void) (&__a == &__b);                  \
 540         __a > __b ? (__a - __b) : (__b - __a); })
 541
 542 struct wrpll_rnp {
 543         unsigned p, n2, r2;
 544 };
 545
 546 static unsigned wrpll_get_budget_for_freq(int clock)
 547 {
 548         unsigned budget;
 549
 550         switch (clock) {
 551         case 25175000:
 552         case 25200000:
 553         case 27000000:
 554         case 27027000:
 555         case 37762500:
 556         case 37800000:
 557         case 40500000:
 558         case 40541000:
 559         case 54000000:
 560         case 54054000:
 561         case 59341000:
 562         case 59400000:
 563         case 72000000:
 564         case 74176000:
 565         case 74250000:
 566         case 81000000:
 567         case 81081000:
 568         case 89012000:
 569         case 89100000:
 570         case 108000000:
 571         case 108108000:
 572         case 111264000:
 573         case 111375000:
 574         case 148352000:
 575         case 148500000:
 576         case 162000000:
 577         case 162162000:
 578         case 222525000:
 579         case 222750000:
 580         case 296703000:
 581         case 297000000:
 582                 budget = 0;
 583                 break;
 584         case 233500000:
 585         case 245250000:
 586         case 247750000:
 587         case 253250000:
 588         case 298000000:
 589                 budget = 1500;
 590                 break;
 591         case 169128000:
 592         case 169500000:
 593         case 179500000:
 594         case 202000000:
 595                 budget = 2000;
 596                 break;
 597         case 256250000:
 598         case 262500000:
 599         case 270000000:
 600         case 272500000:
 601         case 273750000:
 602         case 280750000:
 603         case 281250000:
 604         case 286000000:
 605         case 291750000:
 606                 budget = 4000;
 607                 break;
 608         case 267250000:
 609         case 268500000:
 610                 budget = 5000;
 611                 break;
 612         default:
 613                 budget = 1000;
 614                 break;
 615         }
 616
 617         return budget;
 618 }
 619
 620 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 621                              unsigned r2, unsigned n2, unsigned p,
 622                              struct wrpll_rnp *best)
 623 {
 624         uint64_t a, b, c, d, diff, diff_best;
 625
 626         /* No best (r,n,p) yet */
 627         if (best->p == 0) {
 628                 best->p = p;
 629                 best->n2 = n2;
 630                 best->r2 = r2;
 631                 return;
 632         }
 633
 634         /*
 635          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 636          * freq2k.
 637          *
 638          * delta = 1e6 *
 639          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 640          *         freq2k;
 641          *
 642          * and we would like delta <= budget.
 643          *
 644          * If the discrepancy is above the PPM-based budget, always prefer to
 645          * improve upon the previous solution.  However, if you're within the
 646          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 647          */
 648         a = freq2k * budget * p * r2;
 649         b = freq2k * budget * best->p * best->r2;
 650         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 651         diff_best = abs_diff(freq2k * best->p * best->r2,
 652                              LC_FREQ_2K * best->n2);
 653         c = 1000000 * diff;
 654         d = 1000000 * diff_best;
 655
 656         if (a < c && b < d) {
 657                 /* If both are above the budget, pick the closer */
 658                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 659                         best->p = p;
 660                         best->n2 = n2;
 661                         best->r2 = r2;
 662                 }
 663         } else if (a >= c && b < d) {
 664                 /* If A is below the threshold but B is above it?  Update. */
 665                 best->p = p;
 666                 best->n2 = n2;
 667                 best->r2 = r2;
 668         } else if (a >= c && b >= d) {
 669                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 670                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 671                         best->p = p;
 672                         best->n2 = n2;
 673                         best->r2 = r2;
 674                 }
 675         }
 676         /* Otherwise a < c && b >= d, do nothing */
 677 }
 678
 679 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 680                                      int reg)
 681 {
 682         int refclk = LC_FREQ;
 683         int n, p, r;
 684         u32 wrpll;
 685
 686         wrpll = I915_READ(reg);
 687         switch (wrpll & WRPLL_PLL_REF_MASK) {
 688         case WRPLL_PLL_SSC:
 689         case WRPLL_PLL_NON_SSC:
 690                 /*
 691                  * We could calculate spread here, but our checking
 692                  * code only cares about 5% accuracy, and spread is a max of
 693                  * 0.5% downspread.
 694                  */
 695                 refclk = 135;
 696                 break;
 697         case WRPLL_PLL_LCPLL:
 698                 refclk = LC_FREQ;
 699                 break;
 700         default:
 701                 WARN(1, "bad wrpll refclk\n");
 702                 return 0;
 703         }
 704
 705         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 706         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 707         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 708
 709         /* Convert to KHz, p & r have a fixed point portion */
 710         return (refclk * n * 100) / (p * r);
 711 }
 712
 713 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 714                                uint32_t dpll)
 715 {
 716         uint32_t cfgcr1_reg, cfgcr2_reg;
 717         uint32_t cfgcr1_val, cfgcr2_val;
 718         uint32_t p0, p1, p2, dco_freq;
 719
 720         cfgcr1_reg = GET_CFG_CR1_REG(dpll);
 721         cfgcr2_reg = GET_CFG_CR2_REG(dpll);
 722
 723         cfgcr1_val = I915_READ(cfgcr1_reg);
 724         cfgcr2_val = I915_READ(cfgcr2_reg);
 725
 726         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 727         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 728
 729         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 730                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 731         else
 732                 p1 = 1;
 733
 734
 735         switch (p0) {
 736         case DPLL_CFGCR2_PDIV_1:
 737                 p0 = 1;
 738                 break;
 739         case DPLL_CFGCR2_PDIV_2:
 740                 p0 = 2;
 741                 break;
 742         case DPLL_CFGCR2_PDIV_3:
 743                 p0 = 3;
 744                 break;
 745         case DPLL_CFGCR2_PDIV_7:
 746                 p0 = 7;
 747                 break;
 748         }
 749
 750         switch (p2) {
 751         case DPLL_CFGCR2_KDIV_5:
 752                 p2 = 5;
 753                 break;
 754         case DPLL_CFGCR2_KDIV_2:
 755                 p2 = 2;
 756                 break;
 757         case DPLL_CFGCR2_KDIV_3:
 758                 p2 = 3;
 759                 break;
 760         case DPLL_CFGCR2_KDIV_1:
 761                 p2 = 1;
 762                 break;
 763         }
 764
 765         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 766
 767         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 768                 1000) / 0x8000;
 769
 770         return dco_freq / (p0 * p1 * p2 * 5);
 771 }
 772
 773
 774 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 775                                 struct intel_crtc_state *pipe_config)
 776 {
 777         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 778         int link_clock = 0;
 779         uint32_t dpll_ctl1, dpll;
 780
 781         dpll = pipe_config->ddi_pll_sel;
 782
 783         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 784
 785         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 786                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 787         } else {
 788                 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
 789                 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
 790
 791                 switch (link_clock) {
 792                 case DPLL_CRTL1_LINK_RATE_810:
 793                         link_clock = 81000;
 794                         break;
 795                 case DPLL_CRTL1_LINK_RATE_1080:
 796                         link_clock = 108000;
 797                         break;
 798                 case DPLL_CRTL1_LINK_RATE_1350:
 799                         link_clock = 135000;
 800                         break;
 801                 case DPLL_CRTL1_LINK_RATE_1620:
 802                         link_clock = 162000;
 803                         break;
 804                 case DPLL_CRTL1_LINK_RATE_2160:
 805                         link_clock = 216000;
 806                         break;
 807                 case DPLL_CRTL1_LINK_RATE_2700:
 808                         link_clock = 270000;
 809                         break;
 810                 default:
 811                         WARN(1, "Unsupported link rate\n");
 812                         break;
 813                 }
 814                 link_clock *= 2;
 815         }
 816
 817         pipe_config->port_clock = link_clock;
 818
 819         if (pipe_config->has_dp_encoder)
 820                 pipe_config->base.adjusted_mode.crtc_clock =
 821                         intel_dotclock_calculate(pipe_config->port_clock,
 822                                                  &pipe_config->dp_m_n);
 823         else
 824                 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 825 }
 826
 827 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 828                               struct intel_crtc_state *pipe_config)
 829 {
 830         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 831         int link_clock = 0;
 832         u32 val, pll;
 833
 834         val = pipe_config->ddi_pll_sel;
 835         switch (val & PORT_CLK_SEL_MASK) {
 836         case PORT_CLK_SEL_LCPLL_810:
 837                 link_clock = 81000;
 838                 break;
 839         case PORT_CLK_SEL_LCPLL_1350:
 840                 link_clock = 135000;
 841                 break;
 842         case PORT_CLK_SEL_LCPLL_2700:
 843                 link_clock = 270000;
 844                 break;
 845         case PORT_CLK_SEL_WRPLL1:
 846                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 847                 break;
 848         case PORT_CLK_SEL_WRPLL2:
 849                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 850                 break;
 851         case PORT_CLK_SEL_SPLL:
 852                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 853                 if (pll == SPLL_PLL_FREQ_810MHz)
 854                         link_clock = 81000;
 855                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 856                         link_clock = 135000;
 857                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 858                         link_clock = 270000;
 859                 else {
 860                         WARN(1, "bad spll freq\n");
 861                         return;
 862                 }
 863                 break;
 864         default:
 865                 WARN(1, "bad port clock sel\n");
 866                 return;
 867         }
 868
 869         pipe_config->port_clock = link_clock * 2;
 870
 871         if (pipe_config->has_pch_encoder)
 872                 pipe_config->base.adjusted_mode.crtc_clock =
 873                         intel_dotclock_calculate(pipe_config->port_clock,
 874                                                  &pipe_config->fdi_m_n);
 875         else if (pipe_config->has_dp_encoder)
 876                 pipe_config->base.adjusted_mode.crtc_clock =
 877                         intel_dotclock_calculate(pipe_config->port_clock,
 878                                                  &pipe_config->dp_m_n);
 879         else
 880                 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 881 }
 882
 883 void intel_ddi_clock_get(struct intel_encoder *encoder,
 884                          struct intel_crtc_state *pipe_config)
 885 {
 886         struct drm_device *dev = encoder->base.dev;
 887
 888         if (INTEL_INFO(dev)->gen <= 8)
 889                 hsw_ddi_clock_get(encoder, pipe_config);
 890         else
 891                 skl_ddi_clock_get(encoder, pipe_config);
 892 }
 893
 894 static void
 895 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 896                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 897 {
 898         uint64_t freq2k;
 899         unsigned p, n2, r2;
 900         struct wrpll_rnp best = { 0, 0, 0 };
 901         unsigned budget;
 902
 903         freq2k = clock / 100;
 904
 905         budget = wrpll_get_budget_for_freq(clock);
 906
 907         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 908          * and directly pass the LC PLL to it. */
 909         if (freq2k == 5400000) {
 910                 *n2_out = 2;
 911                 *p_out = 1;
 912                 *r2_out = 2;
 913                 return;
 914         }
 915
 916         /*
 917          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 918          * the WR PLL.
 919          *
 920          * We want R so that REF_MIN <= Ref <= REF_MAX.
 921          * Injecting R2 = 2 * R gives:
 922          *   REF_MAX * r2 > LC_FREQ * 2 and
 923          *   REF_MIN * r2 < LC_FREQ * 2
 924          *
 925          * Which means the desired boundaries for r2 are:
 926          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 927          *
 928          */
 929         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 930              r2 <= LC_FREQ * 2 / REF_MIN;
 931              r2++) {
 932
 933                 /*
 934                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 935                  *
 936                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 937                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 938                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 939                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 940                  *
 941                  * Which means the desired boundaries for n2 are:
 942                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 943                  */
 944                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 945                      n2 <= VCO_MAX * r2 / LC_FREQ;
 946                      n2++) {
 947
 948                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 949                                 wrpll_update_rnp(freq2k, budget,
 950                                                  r2, n2, p, &best);
 951                 }
 952         }
 953
 954         *n2_out = best.n2;
 955         *p_out = best.p;
 956         *r2_out = best.r2;
 957 }
 958
 959 static bool
 960 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 961                    struct intel_crtc_state *crtc_state,
 962                    struct intel_encoder *intel_encoder,
 963                    int clock)
 964 {
 965         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 966                 struct intel_shared_dpll *pll;
 967                 uint32_t val;
 968                 unsigned p, n2, r2;
 969
 970                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 971
 972                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 973                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 974                       WRPLL_DIVIDER_POST(p);
 975
 976                 crtc_state->dpll_hw_state.wrpll = val;
 977
 978                 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
 979                 if (pll == NULL) {
 980                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 981                                          pipe_name(intel_crtc->pipe));
 982                         return false;
 983                 }
 984
 985                 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 986         }
 987
 988         return true;
 989 }
 990
 991 struct skl_wrpll_params {
 992         uint32_t        dco_fraction;
 993         uint32_t        dco_integer;
 994         uint32_t        qdiv_ratio;
 995         uint32_t        qdiv_mode;
 996         uint32_t        kdiv;
 997         uint32_t        pdiv;
 998         uint32_t        central_freq;
 999 };
1000
1001 static void
1002 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1003                         struct skl_wrpll_params *wrpll_params)
1004 {
1005         uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1006         uint64_t dco_central_freq[3] = {8400000000ULL,
1007                                         9000000000ULL,
1008                                         9600000000ULL};
1009         uint32_t min_dco_deviation = 400;
1010         uint32_t min_dco_index = 3;
1011         uint32_t P0[4] = {1, 2, 3, 7};
1012         uint32_t P2[4] = {1, 2, 3, 5};
1013         bool found = false;
1014         uint32_t candidate_p = 0;
1015         uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1016         uint32_t candidate_p2[3] = {0};
1017         uint32_t dco_central_freq_deviation[3];
1018         uint32_t i, P1, k, dco_count;
1019         bool retry_with_odd = false;
1020         uint64_t dco_freq;
1021
1022         /* Determine P0, P1 or P2 */
1023         for (dco_count = 0; dco_count < 3; dco_count++) {
1024                 found = false;
1025                 candidate_p =
1026                         div64_u64(dco_central_freq[dco_count], afe_clock);
1027                 if (retry_with_odd == false)
1028                         candidate_p = (candidate_p % 2 == 0 ?
1029                                 candidate_p : candidate_p + 1);
1030
1031                 for (P1 = 1; P1 < candidate_p; P1++) {
1032                         for (i = 0; i < 4; i++) {
1033                                 if (!(P0[i] != 1 || P1 == 1))
1034                                         continue;
1035
1036                                 for (k = 0; k < 4; k++) {
1037                                         if (P1 != 1 && P2[k] != 2)
1038                                                 continue;
1039
1040                                         if (candidate_p == P0[i] * P1 * P2[k]) {
1041                                                 /* Found possible P0, P1, P2 */
1042                                                 found = true;
1043                                                 candidate_p0[dco_count] = P0[i];
1044                                                 candidate_p1[dco_count] = P1;
1045                                                 candidate_p2[dco_count] = P2[k];
1046                                                 goto found;
1047                                         }
1048
1049                                 }
1050                         }
1051                 }
1052
1053 found:
1054                 if (found) {
1055                         dco_central_freq_deviation[dco_count] =
1056                                 div64_u64(10000 *
1057                                           abs_diff((candidate_p * afe_clock),
1058                                                    dco_central_freq[dco_count]),
1059                                           dco_central_freq[dco_count]);
1060
1061                         if (dco_central_freq_deviation[dco_count] <
1062                                 min_dco_deviation) {
1063                                 min_dco_deviation =
1064                                         dco_central_freq_deviation[dco_count];
1065                                 min_dco_index = dco_count;
1066                         }
1067                 }
1068
1069                 if (min_dco_index > 2 && dco_count == 2) {
1070                         retry_with_odd = true;
1071                         dco_count = 0;
1072                 }
1073         }
1074
1075         if (min_dco_index > 2) {
1076                 WARN(1, "No valid values found for the given pixel clock\n");
1077         } else {
1078                  wrpll_params->central_freq = dco_central_freq[min_dco_index];
1079
1080                  switch (dco_central_freq[min_dco_index]) {
1081                  case 9600000000ULL:
1082                         wrpll_params->central_freq = 0;
1083                         break;
1084                  case 9000000000ULL:
1085                         wrpll_params->central_freq = 1;
1086                         break;
1087                  case 8400000000ULL:
1088                         wrpll_params->central_freq = 3;
1089                  }
1090
1091                  switch (candidate_p0[min_dco_index]) {
1092                  case 1:
1093                         wrpll_params->pdiv = 0;
1094                         break;
1095                  case 2:
1096                         wrpll_params->pdiv = 1;
1097                         break;
1098                  case 3:
1099                         wrpll_params->pdiv = 2;
1100                         break;
1101                  case 7:
1102                         wrpll_params->pdiv = 4;
1103                         break;
1104                  default:
1105                         WARN(1, "Incorrect PDiv\n");
1106                  }
1107
1108                  switch (candidate_p2[min_dco_index]) {
1109                  case 5:
1110                         wrpll_params->kdiv = 0;
1111                         break;
1112                  case 2:
1113                         wrpll_params->kdiv = 1;
1114                         break;
1115                  case 3:
1116                         wrpll_params->kdiv = 2;
1117                         break;
1118                  case 1:
1119                         wrpll_params->kdiv = 3;
1120                         break;
1121                  default:
1122                         WARN(1, "Incorrect KDiv\n");
1123                  }
1124
1125                  wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1126                  wrpll_params->qdiv_mode =
1127                         (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1128
1129                  dco_freq = candidate_p0[min_dco_index] *
1130                          candidate_p1[min_dco_index] *
1131                          candidate_p2[min_dco_index] * afe_clock;
1132
1133                 /*
1134                 * Intermediate values are in Hz.
1135                 * Divide by MHz to match bsepc
1136                 */
1137                  wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1138                  wrpll_params->dco_fraction =
1139                          div_u64(((div_u64(dco_freq, 24) -
1140                                    wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1141
1142         }
1143 }
1144
1145
1146 static bool
1147 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1148                    struct intel_crtc_state *crtc_state,
1149                    struct intel_encoder *intel_encoder,
1150                    int clock)
1151 {
1152         struct intel_shared_dpll *pll;
1153         uint32_t ctrl1, cfgcr1, cfgcr2;
1154
1155         /*
1156          * See comment in intel_dpll_hw_state to understand why we always use 0
1157          * as the DPLL id in this function.
1158          */
1159
1160         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1161
1162         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1163                 struct skl_wrpll_params wrpll_params = { 0, };
1164
1165                 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1166
1167                 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1168
1169                 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1170                          DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1171                          wrpll_params.dco_integer;
1172
1173                 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1174                          DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1175                          DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1176                          DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1177                          wrpll_params.central_freq;
1178         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1179                 struct drm_encoder *encoder = &intel_encoder->base;
1180                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1181
1182                 switch (intel_dp->link_bw) {
1183                 case DP_LINK_BW_1_62:
1184                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1185                         break;
1186                 case DP_LINK_BW_2_7:
1187                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1188                         break;
1189                 case DP_LINK_BW_5_4:
1190                         ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1191                         break;
1192                 }
1193
1194                 cfgcr1 = cfgcr2 = 0;
1195         } else /* eDP */
1196                 return true;
1197
1198         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1199         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1200         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1201
1202         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1203         if (pll == NULL) {
1204                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1205                                  pipe_name(intel_crtc->pipe));
1206                 return false;
1207         }
1208
1209         /* shared DPLL id 0 is DPLL 1 */
1210         crtc_state->ddi_pll_sel = pll->id + 1;
1211
1212         return true;
1213 }
1214
1215 /* bxt clock parameters */
1216 struct bxt_clk_div {
1217         uint32_t p1;
1218         uint32_t p2;
1219         uint32_t m2_int;
1220         uint32_t m2_frac;
1221         bool m2_frac_en;
1222         uint32_t n;
1223         uint32_t prop_coef;
1224         uint32_t int_coef;
1225         uint32_t gain_ctl;
1226         uint32_t targ_cnt;
1227         uint32_t lanestagger;
1228 };
1229
1230 /* pre-calculated values for DP linkrates */
1231 static struct bxt_clk_div bxt_dp_clk_val[7] = {
1232         /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1233         /* 270 */ {4, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0xd},
1234         /* 540 */ {2, 1, 27,       0, 0, 1, 3,  8, 1, 9, 0x18},
1235         /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1236         /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
1237         /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
1238         /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
1239 };
1240
1241 static bool
1242 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1243                    struct intel_crtc_state *crtc_state,
1244                    struct intel_encoder *intel_encoder,
1245                    int clock)
1246 {
1247         struct intel_shared_dpll *pll;
1248         struct bxt_clk_div clk_div = {0};
1249
1250         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1251                 intel_clock_t best_clock;
1252
1253                 /* Calculate HDMI div */
1254                 /*
1255                  * FIXME: tie the following calculation into
1256                  * i9xx_crtc_compute_clock
1257                  */
1258                 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1259                         DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1260                                          clock, pipe_name(intel_crtc->pipe));
1261                         return false;
1262                 }
1263
1264                 clk_div.p1 = best_clock.p1;
1265                 clk_div.p2 = best_clock.p2;
1266                 WARN_ON(best_clock.m1 != 2);
1267                 clk_div.n = best_clock.n;
1268                 clk_div.m2_int = best_clock.m2 >> 22;
1269                 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1270                 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1271
1272                 /* FIXME: set coef, gain, targcnt based on freq band */
1273                 clk_div.prop_coef = 5;
1274                 clk_div.int_coef = 11;
1275                 clk_div.gain_ctl = 2;
1276                 clk_div.targ_cnt = 9;
1277                 if (clock > 270000)
1278                         clk_div.lanestagger = 0x18;
1279                 else if (clock > 135000)
1280                         clk_div.lanestagger = 0x0d;
1281                 else if (clock > 67000)
1282                         clk_div.lanestagger = 0x07;
1283                 else if (clock > 33000)
1284                         clk_div.lanestagger = 0x04;
1285                 else
1286                         clk_div.lanestagger = 0x02;
1287         } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1288                         intel_encoder->type == INTEL_OUTPUT_EDP) {
1289                 struct drm_encoder *encoder = &intel_encoder->base;
1290                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1291
1292                 switch (intel_dp->link_bw) {
1293                 case DP_LINK_BW_1_62:
1294                         clk_div = bxt_dp_clk_val[0];
1295                         break;
1296                 case DP_LINK_BW_2_7:
1297                         clk_div = bxt_dp_clk_val[1];
1298                         break;
1299                 case DP_LINK_BW_5_4:
1300                         clk_div = bxt_dp_clk_val[2];
1301                         break;
1302                 default:
1303                         clk_div = bxt_dp_clk_val[0];
1304                         DRM_ERROR("Unknown link rate\n");
1305                 }
1306         }
1307
1308         crtc_state->dpll_hw_state.ebb0 =
1309                 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1310         crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1311         crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1312         crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1313
1314         if (clk_div.m2_frac_en)
1315                 crtc_state->dpll_hw_state.pll3 =
1316                         PORT_PLL_M2_FRAC_ENABLE;
1317
1318         crtc_state->dpll_hw_state.pll6 =
1319                 clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
1320         crtc_state->dpll_hw_state.pll6 |=
1321                 PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
1322
1323         crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
1324
1325         crtc_state->dpll_hw_state.pcsdw12 =
1326                 LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
1327
1328         pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1329         if (pll == NULL) {
1330                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1331                         pipe_name(intel_crtc->pipe));
1332                 return false;
1333         }
1334
1335         /* shared DPLL id 0 is DPLL A */
1336         crtc_state->ddi_pll_sel = pll->id;
1337
1338         return true;
1339 }
1340
1341 /*
1342  * Tries to find a *shared* PLL for the CRTC and store it in
1343  * intel_crtc->ddi_pll_sel.
1344  *
1345  * For private DPLLs, compute_config() should do the selection for us. This
1346  * function should be folded into compute_config() eventually.
1347  */
1348 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1349                           struct intel_crtc_state *crtc_state)
1350 {
1351         struct drm_device *dev = intel_crtc->base.dev;
1352         struct intel_encoder *intel_encoder =
1353                 intel_ddi_get_crtc_new_encoder(crtc_state);
1354         int clock = crtc_state->port_clock;
1355
1356         if (IS_SKYLAKE(dev))
1357                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1358                                           intel_encoder, clock);
1359         else if (IS_BROXTON(dev))
1360                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1361                                           intel_encoder, clock);
1362         else
1363                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1364                                           intel_encoder, clock);
1365 }
1366
1367 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1368 {
1369         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1371         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1372         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1373         int type = intel_encoder->type;
1374         uint32_t temp;
1375
1376         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1377                 temp = TRANS_MSA_SYNC_CLK;
1378                 switch (intel_crtc->config->pipe_bpp) {
1379                 case 18:
1380                         temp |= TRANS_MSA_6_BPC;
1381                         break;
1382                 case 24:
1383                         temp |= TRANS_MSA_8_BPC;
1384                         break;
1385                 case 30:
1386                         temp |= TRANS_MSA_10_BPC;
1387                         break;
1388                 case 36:
1389                         temp |= TRANS_MSA_12_BPC;
1390                         break;
1391                 default:
1392                         BUG();
1393                 }
1394                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1395         }
1396 }
1397
1398 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1399 {
1400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1401         struct drm_device *dev = crtc->dev;
1402         struct drm_i915_private *dev_priv = dev->dev_private;
1403         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1404         uint32_t temp;
1405         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1406         if (state == true)
1407                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1408         else
1409                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1410         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1411 }
1412
1413 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1414 {
1415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1416         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1417         struct drm_encoder *encoder = &intel_encoder->base;
1418         struct drm_device *dev = crtc->dev;
1419         struct drm_i915_private *dev_priv = dev->dev_private;
1420         enum pipe pipe = intel_crtc->pipe;
1421         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1422         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1423         int type = intel_encoder->type;
1424         uint32_t temp;
1425
1426         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1427         temp = TRANS_DDI_FUNC_ENABLE;
1428         temp |= TRANS_DDI_SELECT_PORT(port);
1429
1430         switch (intel_crtc->config->pipe_bpp) {
1431         case 18:
1432                 temp |= TRANS_DDI_BPC_6;
1433                 break;
1434         case 24:
1435                 temp |= TRANS_DDI_BPC_8;
1436                 break;
1437         case 30:
1438                 temp |= TRANS_DDI_BPC_10;
1439                 break;
1440         case 36:
1441                 temp |= TRANS_DDI_BPC_12;
1442                 break;
1443         default:
1444                 BUG();
1445         }
1446
1447         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1448                 temp |= TRANS_DDI_PVSYNC;
1449         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1450                 temp |= TRANS_DDI_PHSYNC;
1451
1452         if (cpu_transcoder == TRANSCODER_EDP) {
1453                 switch (pipe) {
1454                 case PIPE_A:
1455                         /* On Haswell, can only use the always-on power well for
1456                          * eDP when not using the panel fitter, and when not
1457                          * using motion blur mitigation (which we don't
1458                          * support). */
1459                         if (IS_HASWELL(dev) &&
1460                             (intel_crtc->config->pch_pfit.enabled ||
1461                              intel_crtc->config->pch_pfit.force_thru))
1462                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1463                         else
1464                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1465                         break;
1466                 case PIPE_B:
1467                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1468                         break;
1469                 case PIPE_C:
1470                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1471                         break;
1472                 default:
1473                         BUG();
1474                         break;
1475                 }
1476         }
1477
1478         if (type == INTEL_OUTPUT_HDMI) {
1479                 if (intel_crtc->config->has_hdmi_sink)
1480                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1481                 else
1482                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1483
1484         } else if (type == INTEL_OUTPUT_ANALOG) {
1485                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1486                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1487
1488         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1489                    type == INTEL_OUTPUT_EDP) {
1490                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1491
1492                 if (intel_dp->is_mst) {
1493                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1494                 } else
1495                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1496
1497                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1498         } else if (type == INTEL_OUTPUT_DP_MST) {
1499                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1500
1501                 if (intel_dp->is_mst) {
1502                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1503                 } else
1504                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1505
1506                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1507         } else {
1508                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1509                      intel_encoder->type, pipe_name(pipe));
1510         }
1511
1512         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1513 }
1514
1515 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1516                                        enum transcoder cpu_transcoder)
1517 {
1518         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1519         uint32_t val = I915_READ(reg);
1520
1521         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1522         val |= TRANS_DDI_PORT_NONE;
1523         I915_WRITE(reg, val);
1524 }
1525
1526 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1527 {
1528         struct drm_device *dev = intel_connector->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         struct intel_encoder *intel_encoder = intel_connector->encoder;
1531         int type = intel_connector->base.connector_type;
1532         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1533         enum pipe pipe = 0;
1534         enum transcoder cpu_transcoder;
1535         enum intel_display_power_domain power_domain;
1536         uint32_t tmp;
1537
1538         power_domain = intel_display_port_power_domain(intel_encoder);
1539         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1540                 return false;
1541
1542         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1543                 return false;
1544
1545         if (port == PORT_A)
1546                 cpu_transcoder = TRANSCODER_EDP;
1547         else
1548                 cpu_transcoder = (enum transcoder) pipe;
1549
1550         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1551
1552         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1553         case TRANS_DDI_MODE_SELECT_HDMI:
1554         case TRANS_DDI_MODE_SELECT_DVI:
1555                 return (type == DRM_MODE_CONNECTOR_HDMIA);
1556
1557         case TRANS_DDI_MODE_SELECT_DP_SST:
1558                 if (type == DRM_MODE_CONNECTOR_eDP)
1559                         return true;
1560                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1561         case TRANS_DDI_MODE_SELECT_DP_MST:
1562                 /* if the transcoder is in MST state then
1563                  * connector isn't connected */
1564                 return false;
1565
1566         case TRANS_DDI_MODE_SELECT_FDI:
1567                 return (type == DRM_MODE_CONNECTOR_VGA);
1568
1569         default:
1570                 return false;
1571         }
1572 }
1573
1574 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1575                             enum pipe *pipe)
1576 {
1577         struct drm_device *dev = encoder->base.dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         enum port port = intel_ddi_get_encoder_port(encoder);
1580         enum intel_display_power_domain power_domain;
1581         u32 tmp;
1582         int i;
1583
1584         power_domain = intel_display_port_power_domain(encoder);
1585         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1586                 return false;
1587
1588         tmp = I915_READ(DDI_BUF_CTL(port));
1589
1590         if (!(tmp & DDI_BUF_CTL_ENABLE))
1591                 return false;
1592
1593         if (port == PORT_A) {
1594                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1595
1596                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1597                 case TRANS_DDI_EDP_INPUT_A_ON:
1598                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1599                         *pipe = PIPE_A;
1600                         break;
1601                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1602                         *pipe = PIPE_B;
1603                         break;
1604                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1605                         *pipe = PIPE_C;
1606                         break;
1607                 }
1608
1609                 return true;
1610         } else {
1611                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1612                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1613
1614                         if ((tmp & TRANS_DDI_PORT_MASK)
1615                             == TRANS_DDI_SELECT_PORT(port)) {
1616                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1617                                         return false;
1618
1619                                 *pipe = i;
1620                                 return true;
1621                         }
1622                 }
1623         }
1624
1625         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1626
1627         return false;
1628 }
1629
1630 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1631 {
1632         struct drm_crtc *crtc = &intel_crtc->base;
1633         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1634         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1635         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1636         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1637
1638         if (cpu_transcoder != TRANSCODER_EDP)
1639                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1640                            TRANS_CLK_SEL_PORT(port));
1641 }
1642
1643 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1644 {
1645         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1646         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1647
1648         if (cpu_transcoder != TRANSCODER_EDP)
1649                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1650                            TRANS_CLK_SEL_DISABLED);
1651 }
1652
1653 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1654 {
1655         struct drm_encoder *encoder = &intel_encoder->base;
1656         struct drm_device *dev = encoder->dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1659         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1660         int type = intel_encoder->type;
1661
1662         if (type == INTEL_OUTPUT_EDP) {
1663                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1664                 intel_edp_panel_on(intel_dp);
1665         }
1666
1667         if (IS_SKYLAKE(dev)) {
1668                 uint32_t dpll = crtc->config->ddi_pll_sel;
1669                 uint32_t val;
1670
1671                 /*
1672                  * DPLL0 is used for eDP and is the only "private" DPLL (as
1673                  * opposed to shared) on SKL
1674                  */
1675                 if (type == INTEL_OUTPUT_EDP) {
1676                         WARN_ON(dpll != SKL_DPLL0);
1677
1678                         val = I915_READ(DPLL_CTRL1);
1679
1680                         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1681                                  DPLL_CTRL1_SSC(dpll) |
1682                                  DPLL_CRTL1_LINK_RATE_MASK(dpll));
1683                         val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
1684
1685                         I915_WRITE(DPLL_CTRL1, val);
1686                         POSTING_READ(DPLL_CTRL1);
1687                 }
1688
1689                 /* DDI -> PLL mapping  */
1690                 val = I915_READ(DPLL_CTRL2);
1691
1692                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1693                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1694                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1695                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1696
1697                 I915_WRITE(DPLL_CTRL2, val);
1698
1699         } else if (INTEL_INFO(dev)->gen < 9) {
1700                 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1701                 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
1702         }
1703
1704         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1705                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1706
1707                 intel_ddi_init_dp_buf_reg(intel_encoder);
1708
1709                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1710                 intel_dp_start_link_train(intel_dp);
1711                 intel_dp_complete_link_train(intel_dp);
1712                 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
1713                         intel_dp_stop_link_train(intel_dp);
1714         } else if (type == INTEL_OUTPUT_HDMI) {
1715                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1716
1717                 intel_hdmi->set_infoframes(encoder,
1718                                            crtc->config->has_hdmi_sink,
1719                                            &crtc->config->base.adjusted_mode);
1720         }
1721 }
1722
1723 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1724 {
1725         struct drm_encoder *encoder = &intel_encoder->base;
1726         struct drm_device *dev = encoder->dev;
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1729         int type = intel_encoder->type;
1730         uint32_t val;
1731         bool wait = false;
1732
1733         val = I915_READ(DDI_BUF_CTL(port));
1734         if (val & DDI_BUF_CTL_ENABLE) {
1735                 val &= ~DDI_BUF_CTL_ENABLE;
1736                 I915_WRITE(DDI_BUF_CTL(port), val);
1737                 wait = true;
1738         }
1739
1740         val = I915_READ(DP_TP_CTL(port));
1741         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1742         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1743         I915_WRITE(DP_TP_CTL(port), val);
1744
1745         if (wait)
1746                 intel_wait_ddi_buf_idle(dev_priv, port);
1747
1748         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1749                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1750                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1751                 intel_edp_panel_vdd_on(intel_dp);
1752                 intel_edp_panel_off(intel_dp);
1753         }
1754
1755         if (IS_SKYLAKE(dev))
1756                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1757                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1758         else if (INTEL_INFO(dev)->gen < 9)
1759                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1760 }
1761
1762 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1763 {
1764         struct drm_encoder *encoder = &intel_encoder->base;
1765         struct drm_crtc *crtc = encoder->crtc;
1766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1767         struct drm_device *dev = encoder->dev;
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1770         int type = intel_encoder->type;
1771
1772         if (type == INTEL_OUTPUT_HDMI) {
1773                 struct intel_digital_port *intel_dig_port =
1774                         enc_to_dig_port(encoder);
1775
1776                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1777                  * are ignored so nothing special needs to be done besides
1778                  * enabling the port.
1779                  */
1780                 I915_WRITE(DDI_BUF_CTL(port),
1781                            intel_dig_port->saved_port_bits |
1782                            DDI_BUF_CTL_ENABLE);
1783         } else if (type == INTEL_OUTPUT_EDP) {
1784                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1785
1786                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1787                         intel_dp_stop_link_train(intel_dp);
1788
1789                 intel_edp_backlight_on(intel_dp);
1790                 intel_psr_enable(intel_dp);
1791                 intel_edp_drrs_enable(intel_dp);
1792         }
1793
1794         if (intel_crtc->config->has_audio) {
1795                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1796                 intel_audio_codec_enable(intel_encoder);
1797         }
1798 }
1799
1800 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1801 {
1802         struct drm_encoder *encoder = &intel_encoder->base;
1803         struct drm_crtc *crtc = encoder->crtc;
1804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1805         int type = intel_encoder->type;
1806         struct drm_device *dev = encoder->dev;
1807         struct drm_i915_private *dev_priv = dev->dev_private;
1808
1809         if (intel_crtc->config->has_audio) {
1810                 intel_audio_codec_disable(intel_encoder);
1811                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1812         }
1813
1814         if (type == INTEL_OUTPUT_EDP) {
1815                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1816
1817                 intel_edp_drrs_disable(intel_dp);
1818                 intel_psr_disable(intel_dp);
1819                 intel_edp_backlight_off(intel_dp);
1820         }
1821 }
1822
1823 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1824                                struct intel_shared_dpll *pll)
1825 {
1826         I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
1827         POSTING_READ(WRPLL_CTL(pll->id));
1828         udelay(20);
1829 }
1830
1831 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1832                                 struct intel_shared_dpll *pll)
1833 {
1834         uint32_t val;
1835
1836         val = I915_READ(WRPLL_CTL(pll->id));
1837         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1838         POSTING_READ(WRPLL_CTL(pll->id));
1839 }
1840
1841 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1842                                      struct intel_shared_dpll *pll,
1843                                      struct intel_dpll_hw_state *hw_state)
1844 {
1845         uint32_t val;
1846
1847         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1848                 return false;
1849
1850         val = I915_READ(WRPLL_CTL(pll->id));
1851         hw_state->wrpll = val;
1852
1853         return val & WRPLL_PLL_ENABLE;
1854 }
1855
1856 static const char * const hsw_ddi_pll_names[] = {
1857         "WRPLL 1",
1858         "WRPLL 2",
1859 };
1860
1861 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1862 {
1863         int i;
1864
1865         dev_priv->num_shared_dpll = 2;
1866
1867         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1868                 dev_priv->shared_dplls[i].id = i;
1869                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1870                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1871                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1872                 dev_priv->shared_dplls[i].get_hw_state =
1873                         hsw_ddi_pll_get_hw_state;
1874         }
1875 }
1876
1877 static const char * const skl_ddi_pll_names[] = {
1878         "DPLL 1",
1879         "DPLL 2",
1880         "DPLL 3",
1881 };
1882
1883 struct skl_dpll_regs {
1884         u32 ctl, cfgcr1, cfgcr2;
1885 };
1886
1887 /* this array is indexed by the *shared* pll id */
1888 static const struct skl_dpll_regs skl_dpll_regs[3] = {
1889         {
1890                 /* DPLL 1 */
1891                 .ctl = LCPLL2_CTL,
1892                 .cfgcr1 = DPLL1_CFGCR1,
1893                 .cfgcr2 = DPLL1_CFGCR2,
1894         },
1895         {
1896                 /* DPLL 2 */
1897                 .ctl = WRPLL_CTL1,
1898                 .cfgcr1 = DPLL2_CFGCR1,
1899                 .cfgcr2 = DPLL2_CFGCR2,
1900         },
1901         {
1902                 /* DPLL 3 */
1903                 .ctl = WRPLL_CTL2,
1904                 .cfgcr1 = DPLL3_CFGCR1,
1905                 .cfgcr2 = DPLL3_CFGCR2,
1906         },
1907 };
1908
1909 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1910                                struct intel_shared_dpll *pll)
1911 {
1912         uint32_t val;
1913         unsigned int dpll;
1914         const struct skl_dpll_regs *regs = skl_dpll_regs;
1915
1916         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1917         dpll = pll->id + 1;
1918
1919         val = I915_READ(DPLL_CTRL1);
1920
1921         val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1922                  DPLL_CRTL1_LINK_RATE_MASK(dpll));
1923         val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1924
1925         I915_WRITE(DPLL_CTRL1, val);
1926         POSTING_READ(DPLL_CTRL1);
1927
1928         I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1929         I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1930         POSTING_READ(regs[pll->id].cfgcr1);
1931         POSTING_READ(regs[pll->id].cfgcr2);
1932
1933         /* the enable bit is always bit 31 */
1934         I915_WRITE(regs[pll->id].ctl,
1935                    I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1936
1937         if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1938                 DRM_ERROR("DPLL %d not locked\n", dpll);
1939 }
1940
1941 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1942                                 struct intel_shared_dpll *pll)
1943 {
1944         const struct skl_dpll_regs *regs = skl_dpll_regs;
1945
1946         /* the enable bit is always bit 31 */
1947         I915_WRITE(regs[pll->id].ctl,
1948                    I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1949         POSTING_READ(regs[pll->id].ctl);
1950 }
1951
1952 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1953                                      struct intel_shared_dpll *pll,
1954                                      struct intel_dpll_hw_state *hw_state)
1955 {
1956         uint32_t val;
1957         unsigned int dpll;
1958         const struct skl_dpll_regs *regs = skl_dpll_regs;
1959
1960         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1961                 return false;
1962
1963         /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1964         dpll = pll->id + 1;
1965
1966         val = I915_READ(regs[pll->id].ctl);
1967         if (!(val & LCPLL_PLL_ENABLE))
1968                 return false;
1969
1970         val = I915_READ(DPLL_CTRL1);
1971         hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1972
1973         /* avoid reading back stale values if HDMI mode is not enabled */
1974         if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1975                 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1976                 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1977         }
1978
1979         return true;
1980 }
1981
1982 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1983 {
1984         int i;
1985
1986         dev_priv->num_shared_dpll = 3;
1987
1988         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1989                 dev_priv->shared_dplls[i].id = i;
1990                 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1991                 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1992                 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1993                 dev_priv->shared_dplls[i].get_hw_state =
1994                         skl_ddi_pll_get_hw_state;
1995         }
1996 }
1997
1998 static void broxton_phy_init(struct drm_i915_private *dev_priv,
1999                              enum dpio_phy phy)
2000 {
2001         enum port port;
2002         uint32_t val;
2003
2004         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2005         val |= GT_DISPLAY_POWER_ON(phy);
2006         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2007
2008         /* Considering 10ms timeout until BSpec is updated */
2009         if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2010                 DRM_ERROR("timeout during PHY%d power on\n", phy);
2011
2012         for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2013              port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2014                 int lane;
2015
2016                 for (lane = 0; lane < 4; lane++) {
2017                         val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2018                         /*
2019                          * Note that on CHV this flag is called UPAR, but has
2020                          * the same function.
2021                          */
2022                         val &= ~LATENCY_OPTIM;
2023                         if (lane != 1)
2024                                 val |= LATENCY_OPTIM;
2025
2026                         I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2027                 }
2028         }
2029
2030         /* Program PLL Rcomp code offset */
2031         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2032         val &= ~IREF0RC_OFFSET_MASK;
2033         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2034         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2035
2036         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2037         val &= ~IREF1RC_OFFSET_MASK;
2038         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2039         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2040
2041         /* Program power gating */
2042         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2043         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2044                 SUS_CLK_CONFIG;
2045         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2046
2047         if (phy == DPIO_PHY0) {
2048                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2049                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2050                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2051         }
2052
2053         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2054         val &= ~OCL2_LDOFUSE_PWR_DIS;
2055         /*
2056          * On PHY1 disable power on the second channel, since no port is
2057          * connected there. On PHY0 both channels have a port, so leave it
2058          * enabled.
2059          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2060          * power down the second channel on PHY0 as well.
2061          */
2062         if (phy == DPIO_PHY1)
2063                 val |= OCL2_LDOFUSE_PWR_DIS;
2064         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2065
2066         if (phy == DPIO_PHY0) {
2067                 uint32_t grc_code;
2068                 /*
2069                  * PHY0 isn't connected to an RCOMP resistor so copy over
2070                  * the corresponding calibrated value from PHY1, and disable
2071                  * the automatic calibration on PHY0.
2072                  */
2073                 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2074                              10))
2075                         DRM_ERROR("timeout waiting for PHY1 GRC\n");
2076
2077                 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2078                 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2079                 grc_code = val << GRC_CODE_FAST_SHIFT |
2080                            val << GRC_CODE_SLOW_SHIFT |
2081                            val;
2082                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2083
2084                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2085                 val |= GRC_DIS | GRC_RDY_OVRD;
2086                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2087         }
2088
2089         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2090         val |= COMMON_RESET_DIS;
2091         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2092 }
2093
2094 void broxton_ddi_phy_init(struct drm_device *dev)
2095 {
2096         /* Enable PHY1 first since it provides Rcomp for PHY0 */
2097         broxton_phy_init(dev->dev_private, DPIO_PHY1);
2098         broxton_phy_init(dev->dev_private, DPIO_PHY0);
2099 }
2100
2101 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2102                                enum dpio_phy phy)
2103 {
2104         uint32_t val;
2105
2106         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2107         val &= ~COMMON_RESET_DIS;
2108         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2109 }
2110
2111 void broxton_ddi_phy_uninit(struct drm_device *dev)
2112 {
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114
2115         broxton_phy_uninit(dev_priv, DPIO_PHY1);
2116         broxton_phy_uninit(dev_priv, DPIO_PHY0);
2117
2118         /* FIXME: do this in broxton_phy_uninit per phy */
2119         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2120 }
2121
2122 static const char * const bxt_ddi_pll_names[] = {
2123         "PORT PLL A",
2124         "PORT PLL B",
2125         "PORT PLL C",
2126 };
2127
2128 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2129                                 struct intel_shared_dpll *pll)
2130 {
2131         uint32_t temp;
2132         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2133
2134         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2135         temp &= ~PORT_PLL_REF_SEL;
2136         /* Non-SSC reference */
2137         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2138
2139         /* Disable 10 bit clock */
2140         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2141         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2142         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2143
2144         /* Write P1 & P2 */
2145         temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2146         temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2147         temp |= pll->config.hw_state.ebb0;
2148         I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2149
2150         /* Write M2 integer */
2151         temp = I915_READ(BXT_PORT_PLL(port, 0));
2152         temp &= ~PORT_PLL_M2_MASK;
2153         temp |= pll->config.hw_state.pll0;
2154         I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2155
2156         /* Write N */
2157         temp = I915_READ(BXT_PORT_PLL(port, 1));
2158         temp &= ~PORT_PLL_N_MASK;
2159         temp |= pll->config.hw_state.pll1;
2160         I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2161
2162         /* Write M2 fraction */
2163         temp = I915_READ(BXT_PORT_PLL(port, 2));
2164         temp &= ~PORT_PLL_M2_FRAC_MASK;
2165         temp |= pll->config.hw_state.pll2;
2166         I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2167
2168         /* Write M2 fraction enable */
2169         temp = I915_READ(BXT_PORT_PLL(port, 3));
2170         temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2171         temp |= pll->config.hw_state.pll3;
2172         I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2173
2174         /* Write coeff */
2175         temp = I915_READ(BXT_PORT_PLL(port, 6));
2176         temp &= ~PORT_PLL_PROP_COEFF_MASK;
2177         temp &= ~PORT_PLL_INT_COEFF_MASK;
2178         temp &= ~PORT_PLL_GAIN_CTL_MASK;
2179         temp |= pll->config.hw_state.pll6;
2180         I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2181
2182         /* Write calibration val */
2183         temp = I915_READ(BXT_PORT_PLL(port, 8));
2184         temp &= ~PORT_PLL_TARGET_CNT_MASK;
2185         temp |= pll->config.hw_state.pll8;
2186         I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2187
2188         /*
2189          * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
2190          * specification update.
2191          */
2192
2193         /* Recalibrate with new settings */
2194         temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2195         temp |= PORT_PLL_RECALIBRATE;
2196         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2197         /* Enable 10 bit clock */
2198         temp |= PORT_PLL_10BIT_CLK_ENABLE;
2199         I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2200
2201         /* Enable PLL */
2202         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2203         temp |= PORT_PLL_ENABLE;
2204         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2205         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2206
2207         if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2208                         PORT_PLL_LOCK), 200))
2209                 DRM_ERROR("PLL %d not locked\n", port);
2210
2211         /*
2212          * While we write to the group register to program all lanes at once we
2213          * can read only lane registers and we pick lanes 0/1 for that.
2214          */
2215         temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2216         temp &= ~LANE_STAGGER_MASK;
2217         temp &= ~LANESTAGGER_STRAP_OVRD;
2218         temp |= pll->config.hw_state.pcsdw12;
2219         I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2220 }
2221
2222 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2223                                         struct intel_shared_dpll *pll)
2224 {
2225         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2226         uint32_t temp;
2227
2228         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2229         temp &= ~PORT_PLL_ENABLE;
2230         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2231         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2232 }
2233
2234 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2235                                         struct intel_shared_dpll *pll,
2236                                         struct intel_dpll_hw_state *hw_state)
2237 {
2238         enum port port = (enum port)pll->id;    /* 1:1 port->PLL mapping */
2239         uint32_t val;
2240
2241         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2242                 return false;
2243
2244         val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2245         if (!(val & PORT_PLL_ENABLE))
2246                 return false;
2247
2248         hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2249         hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2250         hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2251         hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2252         hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2253         hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2254         hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2255         /*
2256          * While we write to the group register to program all lanes at once we
2257          * can read only lane registers. We configure all lanes the same way, so
2258          * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2259          */
2260         hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2261         if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2262                 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2263                                  hw_state->pcsdw12,
2264                                  I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2265
2266         return true;
2267 }
2268
2269 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2270 {
2271         int i;
2272
2273         dev_priv->num_shared_dpll = 3;
2274
2275         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2276                 dev_priv->shared_dplls[i].id = i;
2277                 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2278                 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2279                 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2280                 dev_priv->shared_dplls[i].get_hw_state =
2281                         bxt_ddi_pll_get_hw_state;
2282         }
2283 }
2284
2285 void intel_ddi_pll_init(struct drm_device *dev)
2286 {
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         uint32_t val = I915_READ(LCPLL_CTL);
2289
2290         if (IS_SKYLAKE(dev))
2291                 skl_shared_dplls_init(dev_priv);
2292         else if (IS_BROXTON(dev))
2293                 bxt_shared_dplls_init(dev_priv);
2294         else
2295                 hsw_shared_dplls_init(dev_priv);
2296
2297         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
2298                       dev_priv->display.get_display_clock_speed(dev));
2299
2300         if (IS_SKYLAKE(dev)) {
2301                 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2302                         DRM_ERROR("LCPLL1 is disabled\n");
2303         } else if (IS_BROXTON(dev)) {
2304                 broxton_init_cdclk(dev);
2305                 broxton_ddi_phy_init(dev);
2306         } else {
2307                 /*
2308                  * The LCPLL register should be turned on by the BIOS. For now
2309                  * let's just check its state and print errors in case
2310                  * something is wrong.  Don't even try to turn it on.
2311                  */
2312
2313                 if (val & LCPLL_CD_SOURCE_FCLK)
2314                         DRM_ERROR("CDCLK source is not LCPLL\n");
2315
2316                 if (val & LCPLL_PLL_DISABLE)
2317                         DRM_ERROR("LCPLL is disabled\n");
2318         }
2319 }
2320
2321 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2322 {
2323         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2324         struct intel_dp *intel_dp = &intel_dig_port->dp;
2325         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
2326         enum port port = intel_dig_port->port;
2327         uint32_t val;
2328         bool wait = false;
2329
2330         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2331                 val = I915_READ(DDI_BUF_CTL(port));
2332                 if (val & DDI_BUF_CTL_ENABLE) {
2333                         val &= ~DDI_BUF_CTL_ENABLE;
2334                         I915_WRITE(DDI_BUF_CTL(port), val);
2335                         wait = true;
2336                 }
2337
2338                 val = I915_READ(DP_TP_CTL(port));
2339                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2340                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2341                 I915_WRITE(DP_TP_CTL(port), val);
2342                 POSTING_READ(DP_TP_CTL(port));
2343
2344                 if (wait)
2345                         intel_wait_ddi_buf_idle(dev_priv, port);
2346         }
2347
2348         val = DP_TP_CTL_ENABLE |
2349               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2350         if (intel_dp->is_mst)
2351                 val |= DP_TP_CTL_MODE_MST;
2352         else {
2353                 val |= DP_TP_CTL_MODE_SST;
2354                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2355                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2356         }
2357         I915_WRITE(DP_TP_CTL(port), val);
2358         POSTING_READ(DP_TP_CTL(port));
2359
2360         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2361         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2362         POSTING_READ(DDI_BUF_CTL(port));
2363
2364         udelay(600);
2365 }
2366
2367 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2368 {
2369         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2370         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2371         uint32_t val;
2372
2373         intel_ddi_post_disable(intel_encoder);
2374
2375         val = I915_READ(_FDI_RXA_CTL);
2376         val &= ~FDI_RX_ENABLE;
2377         I915_WRITE(_FDI_RXA_CTL, val);
2378
2379         val = I915_READ(_FDI_RXA_MISC);
2380         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2381         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2382         I915_WRITE(_FDI_RXA_MISC, val);
2383
2384         val = I915_READ(_FDI_RXA_CTL);
2385         val &= ~FDI_PCDCLK;
2386         I915_WRITE(_FDI_RXA_CTL, val);
2387
2388         val = I915_READ(_FDI_RXA_CTL);
2389         val &= ~FDI_RX_PLL_ENABLE;
2390         I915_WRITE(_FDI_RXA_CTL, val);
2391 }
2392
2393 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2394 {
2395         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2396         int type = intel_dig_port->base.type;
2397
2398         if (type != INTEL_OUTPUT_DISPLAYPORT &&
2399             type != INTEL_OUTPUT_EDP &&
2400             type != INTEL_OUTPUT_UNKNOWN) {
2401                 return;
2402         }
2403
2404         intel_dp_hot_plug(intel_encoder);
2405 }
2406
2407 void intel_ddi_get_config(struct intel_encoder *encoder,
2408                           struct intel_crtc_state *pipe_config)
2409 {
2410         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2411         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2412         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2413         struct intel_hdmi *intel_hdmi;
2414         u32 temp, flags = 0;
2415
2416         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2417         if (temp & TRANS_DDI_PHSYNC)
2418                 flags |= DRM_MODE_FLAG_PHSYNC;
2419         else
2420                 flags |= DRM_MODE_FLAG_NHSYNC;
2421         if (temp & TRANS_DDI_PVSYNC)
2422                 flags |= DRM_MODE_FLAG_PVSYNC;
2423         else
2424                 flags |= DRM_MODE_FLAG_NVSYNC;
2425
2426         pipe_config->base.adjusted_mode.flags |= flags;
2427
2428         switch (temp & TRANS_DDI_BPC_MASK) {
2429         case TRANS_DDI_BPC_6:
2430                 pipe_config->pipe_bpp = 18;
2431                 break;
2432         case TRANS_DDI_BPC_8:
2433                 pipe_config->pipe_bpp = 24;
2434                 break;
2435         case TRANS_DDI_BPC_10:
2436                 pipe_config->pipe_bpp = 30;
2437                 break;
2438         case TRANS_DDI_BPC_12:
2439                 pipe_config->pipe_bpp = 36;
2440                 break;
2441         default:
2442                 break;
2443         }
2444
2445         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2446         case TRANS_DDI_MODE_SELECT_HDMI:
2447                 pipe_config->has_hdmi_sink = true;
2448                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2449
2450                 if (intel_hdmi->infoframe_enabled(&encoder->base))
2451                         pipe_config->has_infoframe = true;
2452                 break;
2453         case TRANS_DDI_MODE_SELECT_DVI:
2454         case TRANS_DDI_MODE_SELECT_FDI:
2455                 break;
2456         case TRANS_DDI_MODE_SELECT_DP_SST:
2457         case TRANS_DDI_MODE_SELECT_DP_MST:
2458                 pipe_config->has_dp_encoder = true;
2459                 intel_dp_get_m_n(intel_crtc, pipe_config);
2460                 break;
2461         default:
2462                 break;
2463         }
2464
2465         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2466                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2467                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2468                         pipe_config->has_audio = true;
2469         }
2470
2471         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2472             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2473                 /*
2474                  * This is a big fat ugly hack.
2475                  *
2476                  * Some machines in UEFI boot mode provide us a VBT that has 18
2477                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2478                  * unknown we fail to light up. Yet the same BIOS boots up with
2479                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2480                  * max, not what it tells us to use.
2481                  *
2482                  * Note: This will still be broken if the eDP panel is not lit
2483                  * up by the BIOS, and thus we can't get the mode at module
2484                  * load.
2485                  */
2486                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2487                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2488                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2489         }
2490
2491         intel_ddi_clock_get(encoder, pipe_config);
2492 }
2493
2494 static void intel_ddi_destroy(struct drm_encoder *encoder)
2495 {
2496         /* HDMI has nothing special to destroy, so we can go with this. */
2497         intel_dp_encoder_destroy(encoder);
2498 }
2499
2500 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2501                                      struct intel_crtc_state *pipe_config)
2502 {
2503         int type = encoder->type;
2504         int port = intel_ddi_get_encoder_port(encoder);
2505
2506         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2507
2508         if (port == PORT_A)
2509                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2510
2511         if (type == INTEL_OUTPUT_HDMI)
2512                 return intel_hdmi_compute_config(encoder, pipe_config);
2513         else
2514                 return intel_dp_compute_config(encoder, pipe_config);
2515 }
2516
2517 static const struct drm_encoder_funcs intel_ddi_funcs = {
2518         .destroy = intel_ddi_destroy,
2519 };
2520
2521 static struct intel_connector *
2522 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2523 {
2524         struct intel_connector *connector;
2525         enum port port = intel_dig_port->port;
2526
2527         connector = intel_connector_alloc();
2528         if (!connector)
2529                 return NULL;
2530
2531         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2532         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2533                 kfree(connector);
2534                 return NULL;
2535         }
2536
2537         return connector;
2538 }
2539
2540 static struct intel_connector *
2541 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2542 {
2543         struct intel_connector *connector;
2544         enum port port = intel_dig_port->port;
2545
2546         connector = intel_connector_alloc();
2547         if (!connector)
2548                 return NULL;
2549
2550         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2551         intel_hdmi_init_connector(intel_dig_port, connector);
2552
2553         return connector;
2554 }
2555
2556 void intel_ddi_init(struct drm_device *dev, enum port port)
2557 {
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct intel_digital_port *intel_dig_port;
2560         struct intel_encoder *intel_encoder;
2561         struct drm_encoder *encoder;
2562         bool init_hdmi, init_dp;
2563
2564         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2565                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2566         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2567         if (!init_dp && !init_hdmi) {
2568                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
2569                               port_name(port));
2570                 init_hdmi = true;
2571                 init_dp = true;
2572         }
2573
2574         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2575         if (!intel_dig_port)
2576                 return;
2577
2578         intel_encoder = &intel_dig_port->base;
2579         encoder = &intel_encoder->base;
2580
2581         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2582                          DRM_MODE_ENCODER_TMDS);
2583
2584         intel_encoder->compute_config = intel_ddi_compute_config;
2585         intel_encoder->enable = intel_enable_ddi;
2586         intel_encoder->pre_enable = intel_ddi_pre_enable;
2587         intel_encoder->disable = intel_disable_ddi;
2588         intel_encoder->post_disable = intel_ddi_post_disable;
2589         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2590         intel_encoder->get_config = intel_ddi_get_config;
2591
2592         intel_dig_port->port = port;
2593         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2594                                           (DDI_BUF_PORT_REVERSAL |
2595                                            DDI_A_4_LANES);
2596
2597         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2598         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2599         intel_encoder->cloneable = 0;
2600         intel_encoder->hot_plug = intel_ddi_hot_plug;
2601
2602         if (init_dp) {
2603                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2604                         goto err;
2605
2606                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2607                 dev_priv->hpd_irq_port[port] = intel_dig_port;
2608         }
2609
2610         /* In theory we don't need the encoder->type check, but leave it just in
2611          * case we have some really bad VBTs... */
2612         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2613                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2614                         goto err;
2615         }
2616
2617         return;
2618
2619 err:
2620         drm_encoder_cleanup(encoder);
2621         kfree(intel_dig_port);
2622 }