2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
34 #include "intel_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
40 #include "drm_crtc_helper.h"
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
90 #define I8XX_M2_MAX 16
92 #define I8XX_P_MAX 128
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
253 /* We have parameter ranges for different type of outputs. */
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
428 .find_pll = intel_g4x_find_best_PLL,
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
444 .find_pll = intel_g4x_find_best_PLL,
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
468 .find_pll = intel_g4x_find_best_PLL,
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
492 .find_pll = intel_g4x_find_best_PLL,
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 const intel_limit_t *limit;
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100000)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
659 limit = &intel_limits_ironlake_dual_lvds;
661 if (refclk == 100000)
662 limit = &intel_limits_ironlake_single_lvds_100m;
664 limit = &intel_limits_ironlake_single_lvds;
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
668 limit = &intel_limits_ironlake_display_port;
670 limit = &intel_limits_ironlake_dac;
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc, refclk);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
720 limit = &intel_limits_i9xx_sdvo;
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
725 limit = &intel_limits_i8xx_dvo;
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
752 * Returns whether any output on the specified pipe is of the specified type
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
773 static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813 (I915_READ(LVDS)) != 0) {
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
822 clock.p2 = limit->p2.p2_fast;
824 clock.p2 = limit->p2.p2_slow;
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
829 clock.p2 = limit->p2.p2_fast;
832 memset (best_clock, 0, sizeof (*best_clock));
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
847 intel_clock(dev, refclk, &clock);
848 if (!intel_PLL_is_valid(dev, limit,
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
862 return (err != target);
866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
881 if (HAS_PCH_SPLIT(dev))
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
887 clock.p2 = limit->p2.p2_fast;
889 clock.p2 = limit->p2.p2_slow;
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
894 clock.p2 = limit->p2.p2_fast;
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
910 intel_clock(dev, refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit,
915 this_err = abs(clock.dot - target);
916 if (this_err < err_most) {
930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
933 struct drm_device *dev = crtc->dev;
936 if (target < 200000) {
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
960 if (target < 200000) {
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
982 * intel_wait_for_vblank - wait for vblank on a given pipe
984 * @pipe: pipe to wait for
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = PIPESTAT(pipe);
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1020 * @pipe: pipe to wait for
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1038 if (INTEL_INFO(dev)->gen >= 4) {
1039 int reg = PIPECONF(pipe);
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 int reg = PIPEDSL(pipe);
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1050 /* Wait for the display line to settle */
1052 last_line = I915_READ(reg) & DSL_LINEMASK;
1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1061 static const char *state_string(bool enabled)
1063 return enabled ? "on" : "off";
1066 /* Only for pre-ILK configs */
1067 static void assert_pll(struct drm_i915_private *dev_priv,
1068 enum pipe pipe, bool state)
1075 val = I915_READ(reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state), state_string(cur_state));
1081 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1085 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1092 reg = PCH_DPLL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1099 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1102 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1109 reg = FDI_TX_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & FDI_TX_ENABLE);
1112 WARN(cur_state != state,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state), state_string(cur_state));
1116 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1119 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1126 reg = FDI_RX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_RX_ENABLE);
1129 WARN(cur_state != state,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1133 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1136 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv->info->gen == 5)
1146 reg = FDI_TX_CTL(pipe);
1147 val = I915_READ(reg);
1148 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1151 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1157 reg = FDI_RX_CTL(pipe);
1158 val = I915_READ(reg);
1159 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1162 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1165 int pp_reg, lvds_reg;
1167 enum pipe panel_pipe = PIPE_A;
1168 bool locked = locked;
1170 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 lvds_reg = PCH_LVDS;
1174 pp_reg = PP_CONTROL;
1178 val = I915_READ(pp_reg);
1179 if (!(val & PANEL_POWER_ON) ||
1180 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1183 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n",
1191 static void assert_pipe(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
1198 reg = PIPECONF(pipe);
1199 val = I915_READ(reg);
1200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe_name(pipe), state_string(state), state_string(cur_state));
1205 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1208 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1214 reg = DSPCNTR(plane);
1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n",
1221 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1228 /* Planes are fixed to pipes on ILK+ */
1229 if (HAS_PCH_SPLIT(dev_priv->dev))
1232 /* Need to check both planes against the pipe */
1233 for (i = 0; i < 2; i++) {
1235 val = I915_READ(reg);
1236 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237 DISPPLANE_SEL_PIPE_SHIFT;
1238 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1239 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240 plane_name(i), pipe_name(pipe));
1244 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1249 val = I915_READ(PCH_DREF_CONTROL);
1250 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1251 DREF_SUPERSPREAD_SOURCE_MASK));
1252 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1255 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1262 reg = TRANSCONF(pipe);
1263 val = I915_READ(reg);
1264 enabled = !!(val & TRANS_ENABLE);
1266 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271 enum pipe pipe, int reg)
1273 u32 val = I915_READ(reg);
1274 WARN(DP_PIPE_ENABLED(val, pipe),
1275 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276 reg, pipe_name(pipe));
1279 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, int reg)
1282 u32 val = I915_READ(reg);
1283 WARN(HDMI_PIPE_ENABLED(val, pipe),
1284 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1285 reg, pipe_name(pipe));
1288 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1299 val = I915_READ(reg);
1300 WARN(ADPA_PIPE_ENABLED(val, pipe),
1301 "PCH VGA enabled on transcoder %c, should be disabled\n",
1305 val = I915_READ(reg);
1306 WARN(LVDS_PIPE_ENABLED(val, pipe),
1307 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1310 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1316 * intel_enable_pll - enable a PLL
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe PLL to enable
1320 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1321 * make sure the PLL reg is writable first though, since the panel write
1322 * protect mechanism may be enabled.
1324 * Note! This is for pre-ILK only.
1326 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1331 /* No really, not for ILK+ */
1332 BUG_ON(dev_priv->info->gen >= 5);
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336 assert_panel_unlocked(dev_priv, pipe);
1339 val = I915_READ(reg);
1340 val |= DPLL_VCO_ENABLE;
1342 /* We do this three times for luck */
1343 I915_WRITE(reg, val);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg, val);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1351 udelay(150); /* wait for warmup */
1355 * intel_disable_pll - disable a PLL
1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe PLL to disable
1359 * Disable the PLL for @pipe, making sure the pipe is off first.
1361 * Note! This is for pre-ILK only.
1363 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1368 /* Don't disable pipe A or pipe A PLLs if needed */
1369 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1372 /* Make sure the pipe isn't still relying on us */
1373 assert_pipe_disabled(dev_priv, pipe);
1376 val = I915_READ(reg);
1377 val &= ~DPLL_VCO_ENABLE;
1378 I915_WRITE(reg, val);
1383 * intel_enable_pch_pll - enable PCH PLL
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe PLL to enable
1387 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388 * drives the transcoder clock.
1390 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1396 /* PCH only available on ILK+ */
1397 BUG_ON(dev_priv->info->gen < 5);
1399 /* PCH refclock must be enabled first */
1400 assert_pch_refclk_enabled(dev_priv);
1402 reg = PCH_DPLL(pipe);
1403 val = I915_READ(reg);
1404 val |= DPLL_VCO_ENABLE;
1405 I915_WRITE(reg, val);
1410 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
1419 /* Make sure transcoder isn't still depending on us */
1420 assert_transcoder_disabled(dev_priv, pipe);
1422 reg = PCH_DPLL(pipe);
1423 val = I915_READ(reg);
1424 val &= ~DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1430 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1436 /* PCH only available on ILK+ */
1437 BUG_ON(dev_priv->info->gen < 5);
1439 /* Make sure PCH DPLL is enabled */
1440 assert_pch_pll_enabled(dev_priv, pipe);
1442 /* FDI must be feeding us bits for PCH ports */
1443 assert_fdi_tx_enabled(dev_priv, pipe);
1444 assert_fdi_rx_enabled(dev_priv, pipe);
1446 reg = TRANSCONF(pipe);
1447 val = I915_READ(reg);
1449 * make the BPC in transcoder be consistent with
1450 * that in pipeconf reg.
1452 val &= ~PIPE_BPC_MASK;
1453 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454 I915_WRITE(reg, val | TRANS_ENABLE);
1455 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1459 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1465 /* FDI relies on the transcoder */
1466 assert_fdi_tx_disabled(dev_priv, pipe);
1467 assert_fdi_rx_disabled(dev_priv, pipe);
1469 /* Ports must be off as well */
1470 assert_pch_ports_disabled(dev_priv, pipe);
1472 reg = TRANSCONF(pipe);
1473 val = I915_READ(reg);
1474 val &= ~TRANS_ENABLE;
1475 I915_WRITE(reg, val);
1476 /* wait for PCH transcoder off, transcoder state */
1477 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478 DRM_ERROR("failed to disable transcoder\n");
1482 * intel_enable_pipe - enable a pipe, asserting requirements
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to enable
1485 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1487 * Enable @pipe, making sure that various hardware specific requirements
1488 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1490 * @pipe should be %PIPE_A or %PIPE_B.
1492 * Will wait until the pipe is actually running (i.e. first vblank) before
1495 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1502 * A pipe without a PLL won't actually be able to drive bits from
1503 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1506 if (!HAS_PCH_SPLIT(dev_priv->dev))
1507 assert_pll_enabled(dev_priv, pipe);
1510 /* if driving the PCH, we need FDI enabled */
1511 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1514 /* FIXME: assert CPU port conditions for SNB+ */
1517 reg = PIPECONF(pipe);
1518 val = I915_READ(reg);
1519 val |= PIPECONF_ENABLE;
1520 I915_WRITE(reg, val);
1521 intel_wait_for_vblank(dev_priv->dev, pipe);
1525 * intel_disable_pipe - disable a pipe, asserting requirements
1526 * @dev_priv: i915 private structure
1527 * @pipe: pipe to disable
1529 * Disable @pipe, making sure that various hardware specific requirements
1530 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1532 * @pipe should be %PIPE_A or %PIPE_B.
1534 * Will wait until the pipe has shut down before returning.
1536 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1543 * Make sure planes won't keep trying to pump pixels to us,
1544 * or we might hang the display.
1546 assert_planes_disabled(dev_priv, pipe);
1548 /* Don't disable pipe A or pipe A PLLs if needed */
1549 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1552 reg = PIPECONF(pipe);
1553 val = I915_READ(reg);
1554 val &= ~PIPECONF_ENABLE;
1555 I915_WRITE(reg, val);
1556 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1560 * intel_enable_plane - enable a display plane on a given pipe
1561 * @dev_priv: i915 private structure
1562 * @plane: plane to enable
1563 * @pipe: pipe being fed
1565 * Enable @plane on @pipe, making sure that @pipe is running first.
1567 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1568 enum plane plane, enum pipe pipe)
1573 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1574 assert_pipe_enabled(dev_priv, pipe);
1576 reg = DSPCNTR(plane);
1577 val = I915_READ(reg);
1578 val |= DISPLAY_PLANE_ENABLE;
1579 I915_WRITE(reg, val);
1580 intel_wait_for_vblank(dev_priv->dev, pipe);
1584 * Plane regs are double buffered, going from enabled->disabled needs a
1585 * trigger in order to latch. The display address reg provides this.
1587 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1590 u32 reg = DSPADDR(plane);
1591 I915_WRITE(reg, I915_READ(reg));
1595 * intel_disable_plane - disable a display plane
1596 * @dev_priv: i915 private structure
1597 * @plane: plane to disable
1598 * @pipe: pipe consuming the data
1600 * Disable @plane; should be an independent operation.
1602 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1603 enum plane plane, enum pipe pipe)
1608 reg = DSPCNTR(plane);
1609 val = I915_READ(reg);
1610 val &= ~DISPLAY_PLANE_ENABLE;
1611 I915_WRITE(reg, val);
1612 intel_flush_display_plane(dev_priv, plane);
1613 intel_wait_for_vblank(dev_priv->dev, pipe);
1616 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1617 enum pipe pipe, int reg)
1619 u32 val = I915_READ(reg);
1620 if (DP_PIPE_ENABLED(val, pipe))
1621 I915_WRITE(reg, val & ~DP_PORT_EN);
1624 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1625 enum pipe pipe, int reg)
1627 u32 val = I915_READ(reg);
1628 if (HDMI_PIPE_ENABLED(val, pipe))
1629 I915_WRITE(reg, val & ~PORT_ENABLE);
1632 /* Disable any ports connected to this transcoder */
1633 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1638 val = I915_READ(PCH_PP_CONTROL);
1639 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1641 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1642 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1643 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1646 val = I915_READ(reg);
1647 if (ADPA_PIPE_ENABLED(val, pipe))
1648 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1651 val = I915_READ(reg);
1652 if (LVDS_PIPE_ENABLED(val, pipe)) {
1653 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1658 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1659 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1660 disable_pch_hdmi(dev_priv, pipe, HDMID);
1663 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1665 struct drm_device *dev = crtc->dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 struct drm_framebuffer *fb = crtc->fb;
1668 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1669 struct drm_i915_gem_object *obj = intel_fb->obj;
1670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1672 u32 fbc_ctl, fbc_ctl2;
1674 if (fb->pitch == dev_priv->cfb_pitch &&
1675 obj->fence_reg == dev_priv->cfb_fence &&
1676 intel_crtc->plane == dev_priv->cfb_plane &&
1677 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1680 i8xx_disable_fbc(dev);
1682 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1684 if (fb->pitch < dev_priv->cfb_pitch)
1685 dev_priv->cfb_pitch = fb->pitch;
1687 /* FBC_CTL wants 64B units */
1688 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1689 dev_priv->cfb_fence = obj->fence_reg;
1690 dev_priv->cfb_plane = intel_crtc->plane;
1691 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1693 /* Clear old tags */
1694 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1695 I915_WRITE(FBC_TAG + (i * 4), 0);
1698 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1699 if (obj->tiling_mode != I915_TILING_NONE)
1700 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1701 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1702 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1705 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1707 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1708 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1709 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1710 if (obj->tiling_mode != I915_TILING_NONE)
1711 fbc_ctl |= dev_priv->cfb_fence;
1712 I915_WRITE(FBC_CONTROL, fbc_ctl);
1714 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1715 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1718 void i8xx_disable_fbc(struct drm_device *dev)
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1723 /* Disable compression */
1724 fbc_ctl = I915_READ(FBC_CONTROL);
1725 if ((fbc_ctl & FBC_CTL_EN) == 0)
1728 fbc_ctl &= ~FBC_CTL_EN;
1729 I915_WRITE(FBC_CONTROL, fbc_ctl);
1731 /* Wait for compressing bit to clear */
1732 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1733 DRM_DEBUG_KMS("FBC idle timed out\n");
1737 DRM_DEBUG_KMS("disabled FBC\n");
1740 static bool i8xx_fbc_enabled(struct drm_device *dev)
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1744 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1747 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1749 struct drm_device *dev = crtc->dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 struct drm_framebuffer *fb = crtc->fb;
1752 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1753 struct drm_i915_gem_object *obj = intel_fb->obj;
1754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1755 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1756 unsigned long stall_watermark = 200;
1759 dpfc_ctl = I915_READ(DPFC_CONTROL);
1760 if (dpfc_ctl & DPFC_CTL_EN) {
1761 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1762 dev_priv->cfb_fence == obj->fence_reg &&
1763 dev_priv->cfb_plane == intel_crtc->plane &&
1764 dev_priv->cfb_y == crtc->y)
1767 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1768 intel_wait_for_vblank(dev, intel_crtc->pipe);
1771 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1772 dev_priv->cfb_fence = obj->fence_reg;
1773 dev_priv->cfb_plane = intel_crtc->plane;
1774 dev_priv->cfb_y = crtc->y;
1776 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1777 if (obj->tiling_mode != I915_TILING_NONE) {
1778 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1779 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1781 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1784 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1785 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1786 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1787 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1790 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1792 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1795 void g4x_disable_fbc(struct drm_device *dev)
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1800 /* Disable compression */
1801 dpfc_ctl = I915_READ(DPFC_CONTROL);
1802 if (dpfc_ctl & DPFC_CTL_EN) {
1803 dpfc_ctl &= ~DPFC_CTL_EN;
1804 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1806 DRM_DEBUG_KMS("disabled FBC\n");
1810 static bool g4x_fbc_enabled(struct drm_device *dev)
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1814 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1817 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1822 /* Make sure blitter notifies FBC of writes */
1823 __gen6_gt_force_wake_get(dev_priv);
1824 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1825 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1826 GEN6_BLITTER_LOCK_SHIFT;
1827 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1828 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1829 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1830 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1831 GEN6_BLITTER_LOCK_SHIFT);
1832 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1833 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1834 __gen6_gt_force_wake_put(dev_priv);
1837 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1839 struct drm_device *dev = crtc->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct drm_framebuffer *fb = crtc->fb;
1842 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1843 struct drm_i915_gem_object *obj = intel_fb->obj;
1844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1845 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1846 unsigned long stall_watermark = 200;
1849 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1850 if (dpfc_ctl & DPFC_CTL_EN) {
1851 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1852 dev_priv->cfb_fence == obj->fence_reg &&
1853 dev_priv->cfb_plane == intel_crtc->plane &&
1854 dev_priv->cfb_offset == obj->gtt_offset &&
1855 dev_priv->cfb_y == crtc->y)
1858 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1859 intel_wait_for_vblank(dev, intel_crtc->pipe);
1862 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1863 dev_priv->cfb_fence = obj->fence_reg;
1864 dev_priv->cfb_plane = intel_crtc->plane;
1865 dev_priv->cfb_offset = obj->gtt_offset;
1866 dev_priv->cfb_y = crtc->y;
1868 dpfc_ctl &= DPFC_RESERVED;
1869 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1870 if (obj->tiling_mode != I915_TILING_NONE) {
1871 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1872 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1874 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1877 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1878 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1879 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1880 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1881 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1883 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1886 I915_WRITE(SNB_DPFC_CTL_SA,
1887 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1888 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1889 sandybridge_blit_fbc_update(dev);
1892 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1895 void ironlake_disable_fbc(struct drm_device *dev)
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1900 /* Disable compression */
1901 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1902 if (dpfc_ctl & DPFC_CTL_EN) {
1903 dpfc_ctl &= ~DPFC_CTL_EN;
1904 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1906 DRM_DEBUG_KMS("disabled FBC\n");
1910 static bool ironlake_fbc_enabled(struct drm_device *dev)
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1914 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1917 bool intel_fbc_enabled(struct drm_device *dev)
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1921 if (!dev_priv->display.fbc_enabled)
1924 return dev_priv->display.fbc_enabled(dev);
1927 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1929 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1931 if (!dev_priv->display.enable_fbc)
1934 dev_priv->display.enable_fbc(crtc, interval);
1937 void intel_disable_fbc(struct drm_device *dev)
1939 struct drm_i915_private *dev_priv = dev->dev_private;
1941 if (!dev_priv->display.disable_fbc)
1944 dev_priv->display.disable_fbc(dev);
1948 * intel_update_fbc - enable/disable FBC as needed
1949 * @dev: the drm_device
1951 * Set up the framebuffer compression hardware at mode set time. We
1952 * enable it if possible:
1953 * - plane A only (on pre-965)
1954 * - no pixel mulitply/line duplication
1955 * - no alpha buffer discard
1957 * - framebuffer <= 2048 in width, 1536 in height
1959 * We can't assume that any compression will take place (worst case),
1960 * so the compressed buffer has to be the same size as the uncompressed
1961 * one. It also must reside (along with the line length buffer) in
1964 * We need to enable/disable FBC on a global basis.
1966 static void intel_update_fbc(struct drm_device *dev)
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1969 struct drm_crtc *crtc = NULL, *tmp_crtc;
1970 struct intel_crtc *intel_crtc;
1971 struct drm_framebuffer *fb;
1972 struct intel_framebuffer *intel_fb;
1973 struct drm_i915_gem_object *obj;
1975 DRM_DEBUG_KMS("\n");
1977 if (!i915_powersave)
1980 if (!I915_HAS_FBC(dev))
1984 * If FBC is already on, we just have to verify that we can
1985 * keep it that way...
1986 * Need to disable if:
1987 * - more than one pipe is active
1988 * - changing FBC params (stride, fence, mode)
1989 * - new fb is too large to fit in compressed buffer
1990 * - going to an unsupported config (interlace, pixel multiply, etc.)
1992 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1993 if (tmp_crtc->enabled && tmp_crtc->fb) {
1995 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1996 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
2003 if (!crtc || crtc->fb == NULL) {
2004 DRM_DEBUG_KMS("no output, disabling\n");
2005 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
2009 intel_crtc = to_intel_crtc(crtc);
2011 intel_fb = to_intel_framebuffer(fb);
2012 obj = intel_fb->obj;
2014 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2015 DRM_DEBUG_KMS("framebuffer too large, disabling "
2017 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
2020 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2021 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
2022 DRM_DEBUG_KMS("mode incompatible with compression, "
2024 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
2027 if ((crtc->mode.hdisplay > 2048) ||
2028 (crtc->mode.vdisplay > 1536)) {
2029 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
2030 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
2033 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
2034 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
2035 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
2038 if (obj->tiling_mode != I915_TILING_X) {
2039 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
2040 dev_priv->no_fbc_reason = FBC_NOT_TILED;
2044 /* If the kernel debugger is active, always disable compression */
2045 if (in_dbg_master())
2048 intel_enable_fbc(crtc, 500);
2052 /* Multiple disables should be harmless */
2053 if (intel_fbc_enabled(dev)) {
2054 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2055 intel_disable_fbc(dev);
2060 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2061 struct drm_i915_gem_object *obj,
2062 struct intel_ring_buffer *pipelined)
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2068 switch (obj->tiling_mode) {
2069 case I915_TILING_NONE:
2070 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2071 alignment = 128 * 1024;
2072 else if (INTEL_INFO(dev)->gen >= 4)
2073 alignment = 4 * 1024;
2075 alignment = 64 * 1024;
2078 /* pin() will align the object as required by fence */
2082 /* FIXME: Is this true? */
2083 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2089 dev_priv->mm.interruptible = false;
2090 ret = i915_gem_object_pin(obj, alignment, true);
2092 goto err_interruptible;
2094 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2098 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2099 * fence, whereas 965+ only requires a fence if using
2100 * framebuffer compression. For simplicity, we always install
2101 * a fence as the cost is not that onerous.
2103 if (obj->tiling_mode != I915_TILING_NONE) {
2104 ret = i915_gem_object_get_fence(obj, pipelined);
2109 dev_priv->mm.interruptible = true;
2113 i915_gem_object_unpin(obj);
2115 dev_priv->mm.interruptible = true;
2119 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2121 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2122 int x, int y, enum mode_set_atomic state)
2124 struct drm_device *dev = crtc->dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127 struct intel_framebuffer *intel_fb;
2128 struct drm_i915_gem_object *obj;
2129 int plane = intel_crtc->plane;
2130 unsigned long Start, Offset;
2139 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2143 intel_fb = to_intel_framebuffer(fb);
2144 obj = intel_fb->obj;
2146 reg = DSPCNTR(plane);
2147 dspcntr = I915_READ(reg);
2148 /* Mask out pixel format bits in case we change it */
2149 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2150 switch (fb->bits_per_pixel) {
2152 dspcntr |= DISPPLANE_8BPP;
2155 if (fb->depth == 15)
2156 dspcntr |= DISPPLANE_15_16BPP;
2158 dspcntr |= DISPPLANE_16BPP;
2162 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2165 DRM_ERROR("Unknown color depth\n");
2168 if (INTEL_INFO(dev)->gen >= 4) {
2169 if (obj->tiling_mode != I915_TILING_NONE)
2170 dspcntr |= DISPPLANE_TILED;
2172 dspcntr &= ~DISPPLANE_TILED;
2175 if (HAS_PCH_SPLIT(dev))
2177 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2179 I915_WRITE(reg, dspcntr);
2181 Start = obj->gtt_offset;
2182 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2184 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2185 Start, Offset, x, y, fb->pitch);
2186 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2187 if (INTEL_INFO(dev)->gen >= 4) {
2188 I915_WRITE(DSPSURF(plane), Start);
2189 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2190 I915_WRITE(DSPADDR(plane), Offset);
2192 I915_WRITE(DSPADDR(plane), Start + Offset);
2195 intel_update_fbc(dev);
2196 intel_increase_pllclock(crtc);
2202 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2203 struct drm_framebuffer *old_fb)
2205 struct drm_device *dev = crtc->dev;
2206 struct drm_i915_master_private *master_priv;
2207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212 DRM_DEBUG_KMS("No FB bound\n");
2216 switch (intel_crtc->plane) {
2224 mutex_lock(&dev->struct_mutex);
2225 ret = intel_pin_and_fence_fb_obj(dev,
2226 to_intel_framebuffer(crtc->fb)->obj,
2229 mutex_unlock(&dev->struct_mutex);
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237 wait_event(dev_priv->pending_flip_queue,
2238 atomic_read(&dev_priv->mm.wedged) ||
2239 atomic_read(&obj->pending_flip) == 0);
2241 /* Big Hammer, we also need to ensure that any pending
2242 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2243 * current scanout is retired before unpinning the old
2246 * This should only fail upon a hung GPU, in which case we
2247 * can safely continue.
2249 ret = i915_gem_object_flush_gpu(obj);
2253 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2254 LEAVE_ATOMIC_MODE_SET);
2256 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2257 mutex_unlock(&dev->struct_mutex);
2262 intel_wait_for_vblank(dev, intel_crtc->pipe);
2263 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2266 mutex_unlock(&dev->struct_mutex);
2268 if (!dev->primary->master)
2271 master_priv = dev->primary->master->driver_priv;
2272 if (!master_priv->sarea_priv)
2275 if (intel_crtc->pipe) {
2276 master_priv->sarea_priv->pipeB_x = x;
2277 master_priv->sarea_priv->pipeB_y = y;
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
2286 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2292 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2293 dpa_ctl = I915_READ(DP_A);
2294 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2296 if (clock < 200000) {
2298 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2299 /* workaround for 160Mhz:
2300 1) program 0x4600c bits 15:0 = 0x8124
2301 2) program 0x46010 bit 0 = 1
2302 3) program 0x46034 bit 24 = 1
2303 4) program 0x64000 bit 14 = 1
2305 temp = I915_READ(0x4600c);
2307 I915_WRITE(0x4600c, temp | 0x8124);
2309 temp = I915_READ(0x46010);
2310 I915_WRITE(0x46010, temp | 1);
2312 temp = I915_READ(0x46034);
2313 I915_WRITE(0x46034, temp | (1 << 24));
2315 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2317 I915_WRITE(DP_A, dpa_ctl);
2323 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2325 struct drm_device *dev = crtc->dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328 int pipe = intel_crtc->pipe;
2331 /* enable normal train */
2332 reg = FDI_TX_CTL(pipe);
2333 temp = I915_READ(reg);
2334 temp &= ~FDI_LINK_TRAIN_NONE;
2335 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2336 I915_WRITE(reg, temp);
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2349 /* wait one idle pattern time */
2354 /* The FDI link training functions for ILK/Ibexpeak. */
2355 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2357 struct drm_device *dev = crtc->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2360 int pipe = intel_crtc->pipe;
2361 int plane = intel_crtc->plane;
2362 u32 reg, temp, tries;
2364 /* FDI needs bits from pipe & plane first */
2365 assert_pipe_enabled(dev_priv, pipe);
2366 assert_plane_enabled(dev_priv, plane);
2368 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2370 reg = FDI_RX_IMR(pipe);
2371 temp = I915_READ(reg);
2372 temp &= ~FDI_RX_SYMBOL_LOCK;
2373 temp &= ~FDI_RX_BIT_LOCK;
2374 I915_WRITE(reg, temp);
2378 /* enable CPU FDI TX and PCH FDI RX */
2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
2382 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_1;
2385 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
2391 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2396 /* Ironlake workaround, enable clock pointer after FDI enable*/
2397 if (HAS_PCH_IBX(dev)) {
2398 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2399 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2400 FDI_RX_PHASE_SYNC_POINTER_EN);
2403 reg = FDI_RX_IIR(pipe);
2404 for (tries = 0; tries < 5; tries++) {
2405 temp = I915_READ(reg);
2406 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408 if ((temp & FDI_RX_BIT_LOCK)) {
2409 DRM_DEBUG_KMS("FDI train 1 done.\n");
2410 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2415 DRM_ERROR("FDI train 1 fail!\n");
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 temp &= ~FDI_LINK_TRAIN_NONE;
2421 temp |= FDI_LINK_TRAIN_PATTERN_2;
2422 I915_WRITE(reg, temp);
2424 reg = FDI_RX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_2;
2428 I915_WRITE(reg, temp);
2433 reg = FDI_RX_IIR(pipe);
2434 for (tries = 0; tries < 5; tries++) {
2435 temp = I915_READ(reg);
2436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438 if (temp & FDI_RX_SYMBOL_LOCK) {
2439 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2440 DRM_DEBUG_KMS("FDI train 2 done.\n");
2445 DRM_ERROR("FDI train 2 fail!\n");
2447 DRM_DEBUG_KMS("FDI train done\n");
2451 static const int snb_b_fdi_train_param [] = {
2452 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2453 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2454 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2455 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2458 /* The FDI link training functions for SNB/Cougarpoint. */
2459 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2461 struct drm_device *dev = crtc->dev;
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464 int pipe = intel_crtc->pipe;
2467 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 reg = FDI_RX_IMR(pipe);
2470 temp = I915_READ(reg);
2471 temp &= ~FDI_RX_SYMBOL_LOCK;
2472 temp &= ~FDI_RX_BIT_LOCK;
2473 I915_WRITE(reg, temp);
2478 /* enable CPU FDI TX and PCH FDI RX */
2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
2482 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
2485 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2488 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 if (HAS_PCH_CPT(dev)) {
2493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2494 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2504 for (i = 0; i < 4; i++ ) {
2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
2507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 temp |= snb_b_fdi_train_param[i];
2509 I915_WRITE(reg, temp);
2514 reg = FDI_RX_IIR(pipe);
2515 temp = I915_READ(reg);
2516 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518 if (temp & FDI_RX_BIT_LOCK) {
2519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2520 DRM_DEBUG_KMS("FDI train 1 done.\n");
2525 DRM_ERROR("FDI train 1 fail!\n");
2528 reg = FDI_TX_CTL(pipe);
2529 temp = I915_READ(reg);
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2;
2533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2537 I915_WRITE(reg, temp);
2539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
2541 if (HAS_PCH_CPT(dev)) {
2542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2543 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2548 I915_WRITE(reg, temp);
2553 for (i = 0; i < 4; i++ ) {
2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2557 temp |= snb_b_fdi_train_param[i];
2558 I915_WRITE(reg, temp);
2563 reg = FDI_RX_IIR(pipe);
2564 temp = I915_READ(reg);
2565 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2567 if (temp & FDI_RX_SYMBOL_LOCK) {
2568 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2569 DRM_DEBUG_KMS("FDI train 2 done.\n");
2574 DRM_ERROR("FDI train 2 fail!\n");
2576 DRM_DEBUG_KMS("FDI train done.\n");
2579 static void ironlake_fdi_enable(struct drm_crtc *crtc)
2581 struct drm_device *dev = crtc->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2584 int pipe = intel_crtc->pipe;
2587 /* Write the TU size bits so error detection works */
2588 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2589 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2591 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
2594 temp &= ~((0x7 << 19) | (0x7 << 16));
2595 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2596 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2597 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2602 /* Switch from Rawclk to PCDclk */
2603 temp = I915_READ(reg);
2604 I915_WRITE(reg, temp | FDI_PCDCLK);
2609 /* Enable CPU FDI TX PLL, always on for Ironlake */
2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
2612 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2613 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2620 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2622 struct drm_device *dev = crtc->dev;
2623 struct drm_i915_private *dev_priv = dev->dev_private;
2624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2625 int pipe = intel_crtc->pipe;
2628 /* disable CPU FDI tx and PCH FDI rx */
2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~(0x7 << 16);
2637 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2638 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2643 /* Ironlake workaround, disable clock pointer after downing FDI */
2644 if (HAS_PCH_IBX(dev)) {
2645 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2646 I915_WRITE(FDI_RX_CHICKEN(pipe),
2647 I915_READ(FDI_RX_CHICKEN(pipe) &
2648 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2651 /* still set train pattern 1 */
2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_1;
2656 I915_WRITE(reg, temp);
2658 reg = FDI_RX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 if (HAS_PCH_CPT(dev)) {
2661 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2662 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2664 temp &= ~FDI_LINK_TRAIN_NONE;
2665 temp |= FDI_LINK_TRAIN_PATTERN_1;
2667 /* BPC in FDI rx is consistent with that in PIPECONF */
2668 temp &= ~(0x07 << 16);
2669 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2670 I915_WRITE(reg, temp);
2677 * When we disable a pipe, we need to clear any pending scanline wait events
2678 * to avoid hanging the ring, which we assume we are waiting on.
2680 static void intel_clear_scanline_wait(struct drm_device *dev)
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 struct intel_ring_buffer *ring;
2687 /* Can't break the hang on i8xx */
2690 ring = LP_RING(dev_priv);
2691 tmp = I915_READ_CTL(ring);
2692 if (tmp & RING_WAIT)
2693 I915_WRITE_CTL(ring, tmp);
2696 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2698 struct drm_i915_gem_object *obj;
2699 struct drm_i915_private *dev_priv;
2701 if (crtc->fb == NULL)
2704 obj = to_intel_framebuffer(crtc->fb)->obj;
2705 dev_priv = crtc->dev->dev_private;
2706 wait_event(dev_priv->pending_flip_queue,
2707 atomic_read(&obj->pending_flip) == 0);
2710 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_mode_config *mode_config = &dev->mode_config;
2714 struct intel_encoder *encoder;
2717 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2718 * must be driven by its own crtc; no sharing is possible.
2720 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2721 if (encoder->base.crtc != crtc)
2724 switch (encoder->type) {
2725 case INTEL_OUTPUT_EDP:
2726 if (!intel_encoder_is_pch_edp(&encoder->base))
2736 * Enable PCH resources required for PCH ports:
2738 * - FDI training & RX/TX
2739 * - update transcoder timings
2740 * - DP transcoding bits
2743 static void ironlake_pch_enable(struct drm_crtc *crtc)
2745 struct drm_device *dev = crtc->dev;
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2748 int pipe = intel_crtc->pipe;
2751 /* For PCH output, training FDI link */
2753 gen6_fdi_link_train(crtc);
2755 ironlake_fdi_link_train(crtc);
2757 intel_enable_pch_pll(dev_priv, pipe);
2759 if (HAS_PCH_CPT(dev)) {
2760 /* Be sure PCH DPLL SEL is set */
2761 temp = I915_READ(PCH_DPLL_SEL);
2762 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2763 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2764 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2765 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2766 I915_WRITE(PCH_DPLL_SEL, temp);
2769 /* set transcoder timing, panel must allow it */
2770 assert_panel_unlocked(dev_priv, pipe);
2771 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2772 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2773 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2775 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2776 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2777 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2779 intel_fdi_normal_train(crtc);
2781 /* For PCH DP, enable TRANS_DP_CTL */
2782 if (HAS_PCH_CPT(dev) &&
2783 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2784 reg = TRANS_DP_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2787 TRANS_DP_SYNC_MASK |
2789 temp |= (TRANS_DP_OUTPUT_ENABLE |
2790 TRANS_DP_ENH_FRAMING);
2791 temp |= TRANS_DP_8BPC;
2793 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2794 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2795 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2796 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2798 switch (intel_trans_dp_port_sel(crtc)) {
2800 temp |= TRANS_DP_PORT_SEL_B;
2803 temp |= TRANS_DP_PORT_SEL_C;
2806 temp |= TRANS_DP_PORT_SEL_D;
2809 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2810 temp |= TRANS_DP_PORT_SEL_B;
2814 I915_WRITE(reg, temp);
2817 intel_enable_transcoder(dev_priv, pipe);
2820 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 int plane = intel_crtc->plane;
2830 if (intel_crtc->active)
2833 intel_crtc->active = true;
2834 intel_update_watermarks(dev);
2836 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2837 temp = I915_READ(PCH_LVDS);
2838 if ((temp & LVDS_PORT_EN) == 0)
2839 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2842 is_pch_port = intel_crtc_driving_pch(crtc);
2845 ironlake_fdi_enable(crtc);
2847 ironlake_fdi_disable(crtc);
2849 /* Enable panel fitting for LVDS */
2850 if (dev_priv->pch_pf_size &&
2851 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2852 /* Force use of hard-coded filter coefficients
2853 * as some pre-programmed values are broken,
2856 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2857 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2858 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2861 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2862 intel_enable_plane(dev_priv, plane, pipe);
2865 ironlake_pch_enable(crtc);
2867 intel_crtc_load_lut(crtc);
2868 intel_update_fbc(dev);
2869 intel_crtc_update_cursor(crtc, true);
2872 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2874 struct drm_device *dev = crtc->dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2877 int pipe = intel_crtc->pipe;
2878 int plane = intel_crtc->plane;
2881 if (!intel_crtc->active)
2884 intel_crtc_wait_for_pending_flips(crtc);
2885 drm_vblank_off(dev, pipe);
2886 intel_crtc_update_cursor(crtc, false);
2888 intel_disable_plane(dev_priv, plane, pipe);
2890 if (dev_priv->cfb_plane == plane &&
2891 dev_priv->display.disable_fbc)
2892 dev_priv->display.disable_fbc(dev);
2894 intel_disable_pipe(dev_priv, pipe);
2897 I915_WRITE(PF_CTL(pipe), 0);
2898 I915_WRITE(PF_WIN_SZ(pipe), 0);
2900 ironlake_fdi_disable(crtc);
2902 /* This is a horrible layering violation; we should be doing this in
2903 * the connector/encoder ->prepare instead, but we don't always have
2904 * enough information there about the config to know whether it will
2905 * actually be necessary or just cause undesired flicker.
2907 intel_disable_pch_ports(dev_priv, pipe);
2909 intel_disable_transcoder(dev_priv, pipe);
2911 if (HAS_PCH_CPT(dev)) {
2912 /* disable TRANS_DP_CTL */
2913 reg = TRANS_DP_CTL(pipe);
2914 temp = I915_READ(reg);
2915 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2916 temp |= TRANS_DP_PORT_SEL_NONE;
2917 I915_WRITE(reg, temp);
2919 /* disable DPLL_SEL */
2920 temp = I915_READ(PCH_DPLL_SEL);
2923 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2926 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2929 /* FIXME: manage transcoder PLLs? */
2930 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2935 I915_WRITE(PCH_DPLL_SEL, temp);
2938 /* disable PCH DPLL */
2939 intel_disable_pch_pll(dev_priv, pipe);
2941 /* Switch from PCDclk to Rawclk */
2942 reg = FDI_RX_CTL(pipe);
2943 temp = I915_READ(reg);
2944 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2946 /* Disable CPU FDI TX PLL */
2947 reg = FDI_TX_CTL(pipe);
2948 temp = I915_READ(reg);
2949 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2954 reg = FDI_RX_CTL(pipe);
2955 temp = I915_READ(reg);
2956 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2958 /* Wait for the clocks to turn off. */
2962 intel_crtc->active = false;
2963 intel_update_watermarks(dev);
2964 intel_update_fbc(dev);
2965 intel_clear_scanline_wait(dev);
2968 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 int pipe = intel_crtc->pipe;
2972 int plane = intel_crtc->plane;
2974 /* XXX: When our outputs are all unaware of DPMS modes other than off
2975 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2978 case DRM_MODE_DPMS_ON:
2979 case DRM_MODE_DPMS_STANDBY:
2980 case DRM_MODE_DPMS_SUSPEND:
2981 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2982 ironlake_crtc_enable(crtc);
2985 case DRM_MODE_DPMS_OFF:
2986 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2987 ironlake_crtc_disable(crtc);
2992 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2994 if (!enable && intel_crtc->overlay) {
2995 struct drm_device *dev = intel_crtc->base.dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2998 mutex_lock(&dev->struct_mutex);
2999 dev_priv->mm.interruptible = false;
3000 (void) intel_overlay_switch_off(intel_crtc->overlay);
3001 dev_priv->mm.interruptible = true;
3002 mutex_unlock(&dev->struct_mutex);
3005 /* Let userspace switch the overlay on again. In most cases userspace
3006 * has to recompute where to put it anyway.
3010 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3012 struct drm_device *dev = crtc->dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015 int pipe = intel_crtc->pipe;
3016 int plane = intel_crtc->plane;
3018 if (intel_crtc->active)
3021 intel_crtc->active = true;
3022 intel_update_watermarks(dev);
3024 intel_enable_pll(dev_priv, pipe);
3025 intel_enable_pipe(dev_priv, pipe, false);
3026 intel_enable_plane(dev_priv, plane, pipe);
3028 intel_crtc_load_lut(crtc);
3029 intel_update_fbc(dev);
3031 /* Give the overlay scaler a chance to enable if it's on this pipe */
3032 intel_crtc_dpms_overlay(intel_crtc, true);
3033 intel_crtc_update_cursor(crtc, true);
3036 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3038 struct drm_device *dev = crtc->dev;
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041 int pipe = intel_crtc->pipe;
3042 int plane = intel_crtc->plane;
3044 if (!intel_crtc->active)
3047 /* Give the overlay scaler a chance to disable if it's on this pipe */
3048 intel_crtc_wait_for_pending_flips(crtc);
3049 drm_vblank_off(dev, pipe);
3050 intel_crtc_dpms_overlay(intel_crtc, false);
3051 intel_crtc_update_cursor(crtc, false);
3053 if (dev_priv->cfb_plane == plane &&
3054 dev_priv->display.disable_fbc)
3055 dev_priv->display.disable_fbc(dev);
3057 intel_disable_plane(dev_priv, plane, pipe);
3058 intel_disable_pipe(dev_priv, pipe);
3059 intel_disable_pll(dev_priv, pipe);
3061 intel_crtc->active = false;
3062 intel_update_fbc(dev);
3063 intel_update_watermarks(dev);
3064 intel_clear_scanline_wait(dev);
3067 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3069 /* XXX: When our outputs are all unaware of DPMS modes other than off
3070 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3073 case DRM_MODE_DPMS_ON:
3074 case DRM_MODE_DPMS_STANDBY:
3075 case DRM_MODE_DPMS_SUSPEND:
3076 i9xx_crtc_enable(crtc);
3078 case DRM_MODE_DPMS_OFF:
3079 i9xx_crtc_disable(crtc);
3085 * Sets the power management mode of the pipe and plane.
3087 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3089 struct drm_device *dev = crtc->dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 struct drm_i915_master_private *master_priv;
3092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093 int pipe = intel_crtc->pipe;
3096 if (intel_crtc->dpms_mode == mode)
3099 intel_crtc->dpms_mode = mode;
3101 dev_priv->display.dpms(crtc, mode);
3103 if (!dev->primary->master)
3106 master_priv = dev->primary->master->driver_priv;
3107 if (!master_priv->sarea_priv)
3110 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3114 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3115 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3118 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3119 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3122 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3127 static void intel_crtc_disable(struct drm_crtc *crtc)
3129 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3130 struct drm_device *dev = crtc->dev;
3132 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3135 mutex_lock(&dev->struct_mutex);
3136 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3137 mutex_unlock(&dev->struct_mutex);
3141 /* Prepare for a mode set.
3143 * Note we could be a lot smarter here. We need to figure out which outputs
3144 * will be enabled, which disabled (in short, how the config will changes)
3145 * and perform the minimum necessary steps to accomplish that, e.g. updating
3146 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3147 * panel fitting is in the proper state, etc.
3149 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3151 i9xx_crtc_disable(crtc);
3154 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3156 i9xx_crtc_enable(crtc);
3159 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3161 ironlake_crtc_disable(crtc);
3164 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3166 ironlake_crtc_enable(crtc);
3169 void intel_encoder_prepare (struct drm_encoder *encoder)
3171 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3172 /* lvds has its own version of prepare see intel_lvds_prepare */
3173 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3176 void intel_encoder_commit (struct drm_encoder *encoder)
3178 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3179 /* lvds has its own version of commit see intel_lvds_commit */
3180 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3183 void intel_encoder_destroy(struct drm_encoder *encoder)
3185 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3187 drm_encoder_cleanup(encoder);
3188 kfree(intel_encoder);
3191 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3192 struct drm_display_mode *mode,
3193 struct drm_display_mode *adjusted_mode)
3195 struct drm_device *dev = crtc->dev;
3197 if (HAS_PCH_SPLIT(dev)) {
3198 /* FDI link clock is fixed at 2.7G */
3199 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3203 /* XXX some encoders set the crtcinfo, others don't.
3204 * Obviously we need some form of conflict resolution here...
3206 if (adjusted_mode->crtc_htotal == 0)
3207 drm_mode_set_crtcinfo(adjusted_mode, 0);
3212 static int i945_get_display_clock_speed(struct drm_device *dev)
3217 static int i915_get_display_clock_speed(struct drm_device *dev)
3222 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3227 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3231 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3233 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3236 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3237 case GC_DISPLAY_CLOCK_333_MHZ:
3240 case GC_DISPLAY_CLOCK_190_200_MHZ:
3246 static int i865_get_display_clock_speed(struct drm_device *dev)
3251 static int i855_get_display_clock_speed(struct drm_device *dev)
3254 /* Assume that the hardware is in the high speed state. This
3255 * should be the default.
3257 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3258 case GC_CLOCK_133_200:
3259 case GC_CLOCK_100_200:
3261 case GC_CLOCK_166_250:
3263 case GC_CLOCK_100_133:
3267 /* Shouldn't happen */
3271 static int i830_get_display_clock_speed(struct drm_device *dev)
3285 fdi_reduce_ratio(u32 *num, u32 *den)
3287 while (*num > 0xffffff || *den > 0xffffff) {
3294 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3295 int link_clock, struct fdi_m_n *m_n)
3297 m_n->tu = 64; /* default size */
3299 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3300 m_n->gmch_m = bits_per_pixel * pixel_clock;
3301 m_n->gmch_n = link_clock * nlanes * 8;
3302 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3304 m_n->link_m = pixel_clock;
3305 m_n->link_n = link_clock;
3306 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3310 struct intel_watermark_params {
3311 unsigned long fifo_size;
3312 unsigned long max_wm;
3313 unsigned long default_wm;
3314 unsigned long guard_size;
3315 unsigned long cacheline_size;
3318 /* Pineview has different values for various configs */
3319 static const struct intel_watermark_params pineview_display_wm = {
3320 PINEVIEW_DISPLAY_FIFO,
3324 PINEVIEW_FIFO_LINE_SIZE
3326 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3327 PINEVIEW_DISPLAY_FIFO,
3329 PINEVIEW_DFT_HPLLOFF_WM,
3331 PINEVIEW_FIFO_LINE_SIZE
3333 static const struct intel_watermark_params pineview_cursor_wm = {
3334 PINEVIEW_CURSOR_FIFO,
3335 PINEVIEW_CURSOR_MAX_WM,
3336 PINEVIEW_CURSOR_DFT_WM,
3337 PINEVIEW_CURSOR_GUARD_WM,
3338 PINEVIEW_FIFO_LINE_SIZE,
3340 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3341 PINEVIEW_CURSOR_FIFO,
3342 PINEVIEW_CURSOR_MAX_WM,
3343 PINEVIEW_CURSOR_DFT_WM,
3344 PINEVIEW_CURSOR_GUARD_WM,
3345 PINEVIEW_FIFO_LINE_SIZE
3347 static const struct intel_watermark_params g4x_wm_info = {
3354 static const struct intel_watermark_params g4x_cursor_wm_info = {
3361 static const struct intel_watermark_params i965_cursor_wm_info = {
3366 I915_FIFO_LINE_SIZE,
3368 static const struct intel_watermark_params i945_wm_info = {
3375 static const struct intel_watermark_params i915_wm_info = {
3382 static const struct intel_watermark_params i855_wm_info = {
3389 static const struct intel_watermark_params i830_wm_info = {
3397 static const struct intel_watermark_params ironlake_display_wm_info = {
3404 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3411 static const struct intel_watermark_params ironlake_display_srwm_info = {
3412 ILK_DISPLAY_SR_FIFO,
3413 ILK_DISPLAY_MAX_SRWM,
3414 ILK_DISPLAY_DFT_SRWM,
3418 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3420 ILK_CURSOR_MAX_SRWM,
3421 ILK_CURSOR_DFT_SRWM,
3426 static const struct intel_watermark_params sandybridge_display_wm_info = {
3433 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3440 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3441 SNB_DISPLAY_SR_FIFO,
3442 SNB_DISPLAY_MAX_SRWM,
3443 SNB_DISPLAY_DFT_SRWM,
3447 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3449 SNB_CURSOR_MAX_SRWM,
3450 SNB_CURSOR_DFT_SRWM,
3457 * intel_calculate_wm - calculate watermark level
3458 * @clock_in_khz: pixel clock
3459 * @wm: chip FIFO params
3460 * @pixel_size: display pixel size
3461 * @latency_ns: memory latency for the platform
3463 * Calculate the watermark level (the level at which the display plane will
3464 * start fetching from memory again). Each chip has a different display
3465 * FIFO size and allocation, so the caller needs to figure that out and pass
3466 * in the correct intel_watermark_params structure.
3468 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3469 * on the pixel size. When it reaches the watermark level, it'll start
3470 * fetching FIFO line sized based chunks from memory until the FIFO fills
3471 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3472 * will occur, and a display engine hang could result.
3474 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3475 const struct intel_watermark_params *wm,
3478 unsigned long latency_ns)
3480 long entries_required, wm_size;
3483 * Note: we need to make sure we don't overflow for various clock &
3485 * clocks go from a few thousand to several hundred thousand.
3486 * latency is usually a few thousand
3488 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3490 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3492 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
3494 wm_size = fifo_size - (entries_required + wm->guard_size);
3496 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
3498 /* Don't promote wm_size to unsigned... */
3499 if (wm_size > (long)wm->max_wm)
3500 wm_size = wm->max_wm;
3502 wm_size = wm->default_wm;
3506 struct cxsr_latency {
3509 unsigned long fsb_freq;
3510 unsigned long mem_freq;
3511 unsigned long display_sr;
3512 unsigned long display_hpll_disable;
3513 unsigned long cursor_sr;
3514 unsigned long cursor_hpll_disable;
3517 static const struct cxsr_latency cxsr_latency_table[] = {
3518 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3519 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3520 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3521 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3522 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3524 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3525 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3526 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3527 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3528 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3530 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3531 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3532 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3533 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3534 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3536 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3537 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3538 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3539 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3540 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3542 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3543 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3544 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3545 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3546 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3548 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3549 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3550 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3551 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3552 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3555 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3560 const struct cxsr_latency *latency;
3563 if (fsb == 0 || mem == 0)
3566 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3567 latency = &cxsr_latency_table[i];
3568 if (is_desktop == latency->is_desktop &&
3569 is_ddr3 == latency->is_ddr3 &&
3570 fsb == latency->fsb_freq && mem == latency->mem_freq)
3574 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3579 static void pineview_disable_cxsr(struct drm_device *dev)
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3583 /* deactivate cxsr */
3584 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3588 * Latency for FIFO fetches is dependent on several factors:
3589 * - memory configuration (speed, channels)
3591 * - current MCH state
3592 * It can be fairly high in some situations, so here we assume a fairly
3593 * pessimal value. It's a tradeoff between extra memory fetches (if we
3594 * set this value too high, the FIFO will fetch frequently to stay full)
3595 * and power consumption (set it too low to save power and we might see
3596 * FIFO underruns and display "flicker").
3598 * A value of 5us seems to be a good balance; safe for very low end
3599 * platforms but not overly aggressive on lower latency configs.
3601 static const int latency_ns = 5000;
3603 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 uint32_t dsparb = I915_READ(DSPARB);
3609 size = dsparb & 0x7f;
3611 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3613 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3614 plane ? "B" : "A", size);
3619 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 uint32_t dsparb = I915_READ(DSPARB);
3625 size = dsparb & 0x1ff;
3627 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3628 size >>= 1; /* Convert to cachelines */
3630 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3631 plane ? "B" : "A", size);
3636 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 uint32_t dsparb = I915_READ(DSPARB);
3642 size = dsparb & 0x7f;
3643 size >>= 2; /* Convert to cachelines */
3645 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3652 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 uint32_t dsparb = I915_READ(DSPARB);
3658 size = dsparb & 0x7f;
3659 size >>= 1; /* Convert to cachelines */
3661 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3662 plane ? "B" : "A", size);
3667 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3669 struct drm_crtc *crtc, *enabled = NULL;
3671 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3672 if (crtc->enabled && crtc->fb) {
3682 static void pineview_update_wm(struct drm_device *dev)
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct drm_crtc *crtc;
3686 const struct cxsr_latency *latency;
3690 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3691 dev_priv->fsb_freq, dev_priv->mem_freq);
3693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3694 pineview_disable_cxsr(dev);
3698 crtc = single_enabled_crtc(dev);
3700 int clock = crtc->mode.clock;
3701 int pixel_size = crtc->fb->bits_per_pixel / 8;
3704 wm = intel_calculate_wm(clock, &pineview_display_wm,
3705 pineview_display_wm.fifo_size,
3706 pixel_size, latency->display_sr);
3707 reg = I915_READ(DSPFW1);
3708 reg &= ~DSPFW_SR_MASK;
3709 reg |= wm << DSPFW_SR_SHIFT;
3710 I915_WRITE(DSPFW1, reg);
3711 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3714 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3715 pineview_display_wm.fifo_size,
3716 pixel_size, latency->cursor_sr);
3717 reg = I915_READ(DSPFW3);
3718 reg &= ~DSPFW_CURSOR_SR_MASK;
3719 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3720 I915_WRITE(DSPFW3, reg);
3722 /* Display HPLL off SR */
3723 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3724 pineview_display_hplloff_wm.fifo_size,
3725 pixel_size, latency->display_hpll_disable);
3726 reg = I915_READ(DSPFW3);
3727 reg &= ~DSPFW_HPLL_SR_MASK;
3728 reg |= wm & DSPFW_HPLL_SR_MASK;
3729 I915_WRITE(DSPFW3, reg);
3731 /* cursor HPLL off SR */
3732 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3733 pineview_display_hplloff_wm.fifo_size,
3734 pixel_size, latency->cursor_hpll_disable);
3735 reg = I915_READ(DSPFW3);
3736 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3737 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3738 I915_WRITE(DSPFW3, reg);
3739 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3743 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3744 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3746 pineview_disable_cxsr(dev);
3747 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3751 static bool g4x_compute_wm0(struct drm_device *dev,
3753 const struct intel_watermark_params *display,
3754 int display_latency_ns,
3755 const struct intel_watermark_params *cursor,
3756 int cursor_latency_ns,
3760 struct drm_crtc *crtc;
3761 int htotal, hdisplay, clock, pixel_size;
3762 int line_time_us, line_count;
3763 int entries, tlb_miss;
3765 crtc = intel_get_crtc_for_plane(dev, plane);
3766 if (crtc->fb == NULL || !crtc->enabled)
3769 htotal = crtc->mode.htotal;
3770 hdisplay = crtc->mode.hdisplay;
3771 clock = crtc->mode.clock;
3772 pixel_size = crtc->fb->bits_per_pixel / 8;
3774 /* Use the small buffer method to calculate plane watermark */
3775 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3776 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3778 entries += tlb_miss;
3779 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3780 *plane_wm = entries + display->guard_size;
3781 if (*plane_wm > (int)display->max_wm)
3782 *plane_wm = display->max_wm;
3784 /* Use the large buffer method to calculate cursor watermark */
3785 line_time_us = ((htotal * 1000) / clock);
3786 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3787 entries = line_count * 64 * pixel_size;
3788 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3790 entries += tlb_miss;
3791 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3792 *cursor_wm = entries + cursor->guard_size;
3793 if (*cursor_wm > (int)cursor->max_wm)
3794 *cursor_wm = (int)cursor->max_wm;
3800 * Check the wm result.
3802 * If any calculated watermark values is larger than the maximum value that
3803 * can be programmed into the associated watermark register, that watermark
3806 static bool g4x_check_srwm(struct drm_device *dev,
3807 int display_wm, int cursor_wm,
3808 const struct intel_watermark_params *display,
3809 const struct intel_watermark_params *cursor)
3811 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3812 display_wm, cursor_wm);
3814 if (display_wm > display->max_wm) {
3815 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3816 display_wm, display->max_wm);
3820 if (cursor_wm > cursor->max_wm) {
3821 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3822 cursor_wm, cursor->max_wm);
3826 if (!(display_wm || cursor_wm)) {
3827 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3834 static bool g4x_compute_srwm(struct drm_device *dev,
3837 const struct intel_watermark_params *display,
3838 const struct intel_watermark_params *cursor,
3839 int *display_wm, int *cursor_wm)
3841 struct drm_crtc *crtc;
3842 int hdisplay, htotal, pixel_size, clock;
3843 unsigned long line_time_us;
3844 int line_count, line_size;
3849 *display_wm = *cursor_wm = 0;
3853 crtc = intel_get_crtc_for_plane(dev, plane);
3854 hdisplay = crtc->mode.hdisplay;
3855 htotal = crtc->mode.htotal;
3856 clock = crtc->mode.clock;
3857 pixel_size = crtc->fb->bits_per_pixel / 8;
3859 line_time_us = (htotal * 1000) / clock;
3860 line_count = (latency_ns / line_time_us + 1000) / 1000;
3861 line_size = hdisplay * pixel_size;
3863 /* Use the minimum of the small and large buffer method for primary */
3864 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3865 large = line_count * line_size;
3867 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3868 *display_wm = entries + display->guard_size;
3870 /* calculate the self-refresh watermark for display cursor */
3871 entries = line_count * pixel_size * 64;
3872 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3873 *cursor_wm = entries + cursor->guard_size;
3875 return g4x_check_srwm(dev,
3876 *display_wm, *cursor_wm,
3880 static inline bool single_plane_enabled(unsigned int mask)
3882 return mask && (mask & -mask) == 0;
3885 static void g4x_update_wm(struct drm_device *dev)
3887 static const int sr_latency_ns = 12000;
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3890 int plane_sr, cursor_sr;
3891 unsigned int enabled = 0;
3893 if (g4x_compute_wm0(dev, 0,
3894 &g4x_wm_info, latency_ns,
3895 &g4x_cursor_wm_info, latency_ns,
3896 &planea_wm, &cursora_wm))
3899 if (g4x_compute_wm0(dev, 1,
3900 &g4x_wm_info, latency_ns,
3901 &g4x_cursor_wm_info, latency_ns,
3902 &planeb_wm, &cursorb_wm))
3905 plane_sr = cursor_sr = 0;
3906 if (single_plane_enabled(enabled) &&
3907 g4x_compute_srwm(dev, ffs(enabled) - 1,
3910 &g4x_cursor_wm_info,
3911 &plane_sr, &cursor_sr))
3912 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3914 I915_WRITE(FW_BLC_SELF,
3915 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3917 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3918 planea_wm, cursora_wm,
3919 planeb_wm, cursorb_wm,
3920 plane_sr, cursor_sr);
3923 (plane_sr << DSPFW_SR_SHIFT) |
3924 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3925 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3928 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3929 (cursora_wm << DSPFW_CURSORA_SHIFT));
3930 /* HPLL off in SR has some issues on G4x... disable it */
3932 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3933 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3936 static void i965_update_wm(struct drm_device *dev)
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939 struct drm_crtc *crtc;
3943 /* Calc sr entries for one plane configs */
3944 crtc = single_enabled_crtc(dev);
3946 /* self-refresh has much higher latency */
3947 static const int sr_latency_ns = 12000;
3948 int clock = crtc->mode.clock;
3949 int htotal = crtc->mode.htotal;
3950 int hdisplay = crtc->mode.hdisplay;
3951 int pixel_size = crtc->fb->bits_per_pixel / 8;
3952 unsigned long line_time_us;
3955 line_time_us = ((htotal * 1000) / clock);
3957 /* Use ns/us then divide to preserve precision */
3958 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3959 pixel_size * hdisplay;
3960 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3961 srwm = I965_FIFO_SIZE - entries;
3965 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3968 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3970 entries = DIV_ROUND_UP(entries,
3971 i965_cursor_wm_info.cacheline_size);
3972 cursor_sr = i965_cursor_wm_info.fifo_size -
3973 (entries + i965_cursor_wm_info.guard_size);
3975 if (cursor_sr > i965_cursor_wm_info.max_wm)
3976 cursor_sr = i965_cursor_wm_info.max_wm;
3978 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3979 "cursor %d\n", srwm, cursor_sr);
3981 if (IS_CRESTLINE(dev))
3982 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3984 /* Turn off self refresh if both pipes are enabled */
3985 if (IS_CRESTLINE(dev))
3986 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3990 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3993 /* 965 has limitations... */
3994 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3995 (8 << 16) | (8 << 8) | (8 << 0));
3996 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3997 /* update cursor SR watermark */
3998 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4001 static void i9xx_update_wm(struct drm_device *dev)
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004 const struct intel_watermark_params *wm_info;
4009 int planea_wm, planeb_wm;
4010 struct drm_crtc *crtc, *enabled = NULL;
4013 wm_info = &i945_wm_info;
4014 else if (!IS_GEN2(dev))
4015 wm_info = &i915_wm_info;
4017 wm_info = &i855_wm_info;
4019 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4020 crtc = intel_get_crtc_for_plane(dev, 0);
4021 if (crtc->enabled && crtc->fb) {
4022 planea_wm = intel_calculate_wm(crtc->mode.clock,
4024 crtc->fb->bits_per_pixel / 8,
4028 planea_wm = fifo_size - wm_info->guard_size;
4030 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4031 crtc = intel_get_crtc_for_plane(dev, 1);
4032 if (crtc->enabled && crtc->fb) {
4033 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4035 crtc->fb->bits_per_pixel / 8,
4037 if (enabled == NULL)
4042 planeb_wm = fifo_size - wm_info->guard_size;
4044 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4047 * Overlay gets an aggressive default since video jitter is bad.
4051 /* Play safe and disable self-refresh before adjusting watermarks. */
4052 if (IS_I945G(dev) || IS_I945GM(dev))
4053 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4054 else if (IS_I915GM(dev))
4055 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4057 /* Calc sr entries for one plane configs */
4058 if (HAS_FW_BLC(dev) && enabled) {
4059 /* self-refresh has much higher latency */
4060 static const int sr_latency_ns = 6000;
4061 int clock = enabled->mode.clock;
4062 int htotal = enabled->mode.htotal;
4063 int hdisplay = enabled->mode.hdisplay;
4064 int pixel_size = enabled->fb->bits_per_pixel / 8;
4065 unsigned long line_time_us;
4068 line_time_us = (htotal * 1000) / clock;
4070 /* Use ns/us then divide to preserve precision */
4071 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4072 pixel_size * hdisplay;
4073 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4074 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4075 srwm = wm_info->fifo_size - entries;
4079 if (IS_I945G(dev) || IS_I945GM(dev))
4080 I915_WRITE(FW_BLC_SELF,
4081 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4082 else if (IS_I915GM(dev))
4083 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4086 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4087 planea_wm, planeb_wm, cwm, srwm);
4089 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4090 fwater_hi = (cwm & 0x1f);
4092 /* Set request length to 8 cachelines per fetch */
4093 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4094 fwater_hi = fwater_hi | (1 << 8);
4096 I915_WRITE(FW_BLC, fwater_lo);
4097 I915_WRITE(FW_BLC2, fwater_hi);
4099 if (HAS_FW_BLC(dev)) {
4101 if (IS_I945G(dev) || IS_I945GM(dev))
4102 I915_WRITE(FW_BLC_SELF,
4103 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4104 else if (IS_I915GM(dev))
4105 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4106 DRM_DEBUG_KMS("memory self refresh enabled\n");
4108 DRM_DEBUG_KMS("memory self refresh disabled\n");
4112 static void i830_update_wm(struct drm_device *dev)
4114 struct drm_i915_private *dev_priv = dev->dev_private;
4115 struct drm_crtc *crtc;
4119 crtc = single_enabled_crtc(dev);
4123 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4124 dev_priv->display.get_fifo_size(dev, 0),
4125 crtc->fb->bits_per_pixel / 8,
4127 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4128 fwater_lo |= (3<<8) | planea_wm;
4130 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4132 I915_WRITE(FW_BLC, fwater_lo);
4135 #define ILK_LP0_PLANE_LATENCY 700
4136 #define ILK_LP0_CURSOR_LATENCY 1300
4138 static bool ironlake_compute_wm0(struct drm_device *dev,
4140 const struct intel_watermark_params *display,
4141 int display_latency_ns,
4142 const struct intel_watermark_params *cursor,
4143 int cursor_latency_ns,
4147 struct drm_crtc *crtc;
4148 int htotal, hdisplay, clock, pixel_size;
4149 int line_time_us, line_count;
4150 int entries, tlb_miss;
4152 crtc = intel_get_crtc_for_pipe(dev, pipe);
4153 if (crtc->fb == NULL || !crtc->enabled)
4156 htotal = crtc->mode.htotal;
4157 hdisplay = crtc->mode.hdisplay;
4158 clock = crtc->mode.clock;
4159 pixel_size = crtc->fb->bits_per_pixel / 8;
4161 /* Use the small buffer method to calculate plane watermark */
4162 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4163 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4165 entries += tlb_miss;
4166 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4167 *plane_wm = entries + display->guard_size;
4168 if (*plane_wm > (int)display->max_wm)
4169 *plane_wm = display->max_wm;
4171 /* Use the large buffer method to calculate cursor watermark */
4172 line_time_us = ((htotal * 1000) / clock);
4173 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4174 entries = line_count * 64 * pixel_size;
4175 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4177 entries += tlb_miss;
4178 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4179 *cursor_wm = entries + cursor->guard_size;
4180 if (*cursor_wm > (int)cursor->max_wm)
4181 *cursor_wm = (int)cursor->max_wm;
4187 * Check the wm result.
4189 * If any calculated watermark values is larger than the maximum value that
4190 * can be programmed into the associated watermark register, that watermark
4193 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4194 int fbc_wm, int display_wm, int cursor_wm,
4195 const struct intel_watermark_params *display,
4196 const struct intel_watermark_params *cursor)
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4200 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4201 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4203 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4204 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4205 fbc_wm, SNB_FBC_MAX_SRWM, level);
4207 /* fbc has it's own way to disable FBC WM */
4208 I915_WRITE(DISP_ARB_CTL,
4209 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4213 if (display_wm > display->max_wm) {
4214 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4215 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4219 if (cursor_wm > cursor->max_wm) {
4220 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4221 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4225 if (!(fbc_wm || display_wm || cursor_wm)) {
4226 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4234 * Compute watermark values of WM[1-3],
4236 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4238 const struct intel_watermark_params *display,
4239 const struct intel_watermark_params *cursor,
4240 int *fbc_wm, int *display_wm, int *cursor_wm)
4242 struct drm_crtc *crtc;
4243 unsigned long line_time_us;
4244 int hdisplay, htotal, pixel_size, clock;
4245 int line_count, line_size;
4250 *fbc_wm = *display_wm = *cursor_wm = 0;
4254 crtc = intel_get_crtc_for_plane(dev, plane);
4255 hdisplay = crtc->mode.hdisplay;
4256 htotal = crtc->mode.htotal;
4257 clock = crtc->mode.clock;
4258 pixel_size = crtc->fb->bits_per_pixel / 8;
4260 line_time_us = (htotal * 1000) / clock;
4261 line_count = (latency_ns / line_time_us + 1000) / 1000;
4262 line_size = hdisplay * pixel_size;
4264 /* Use the minimum of the small and large buffer method for primary */
4265 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4266 large = line_count * line_size;
4268 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4269 *display_wm = entries + display->guard_size;
4273 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4275 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4277 /* calculate the self-refresh watermark for display cursor */
4278 entries = line_count * pixel_size * 64;
4279 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4280 *cursor_wm = entries + cursor->guard_size;
4282 return ironlake_check_srwm(dev, level,
4283 *fbc_wm, *display_wm, *cursor_wm,
4287 static void ironlake_update_wm(struct drm_device *dev)
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 int fbc_wm, plane_wm, cursor_wm;
4291 unsigned int enabled;
4294 if (ironlake_compute_wm0(dev, 0,
4295 &ironlake_display_wm_info,
4296 ILK_LP0_PLANE_LATENCY,
4297 &ironlake_cursor_wm_info,
4298 ILK_LP0_CURSOR_LATENCY,
4299 &plane_wm, &cursor_wm)) {
4300 I915_WRITE(WM0_PIPEA_ILK,
4301 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4302 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4303 " plane %d, " "cursor: %d\n",
4304 plane_wm, cursor_wm);
4308 if (ironlake_compute_wm0(dev, 1,
4309 &ironlake_display_wm_info,
4310 ILK_LP0_PLANE_LATENCY,
4311 &ironlake_cursor_wm_info,
4312 ILK_LP0_CURSOR_LATENCY,
4313 &plane_wm, &cursor_wm)) {
4314 I915_WRITE(WM0_PIPEB_ILK,
4315 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4316 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4317 " plane %d, cursor: %d\n",
4318 plane_wm, cursor_wm);
4323 * Calculate and update the self-refresh watermark only when one
4324 * display plane is used.
4326 I915_WRITE(WM3_LP_ILK, 0);
4327 I915_WRITE(WM2_LP_ILK, 0);
4328 I915_WRITE(WM1_LP_ILK, 0);
4330 if (!single_plane_enabled(enabled))
4332 enabled = ffs(enabled) - 1;
4335 if (!ironlake_compute_srwm(dev, 1, enabled,
4336 ILK_READ_WM1_LATENCY() * 500,
4337 &ironlake_display_srwm_info,
4338 &ironlake_cursor_srwm_info,
4339 &fbc_wm, &plane_wm, &cursor_wm))
4342 I915_WRITE(WM1_LP_ILK,
4344 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4345 (fbc_wm << WM1_LP_FBC_SHIFT) |
4346 (plane_wm << WM1_LP_SR_SHIFT) |
4350 if (!ironlake_compute_srwm(dev, 2, enabled,
4351 ILK_READ_WM2_LATENCY() * 500,
4352 &ironlake_display_srwm_info,
4353 &ironlake_cursor_srwm_info,
4354 &fbc_wm, &plane_wm, &cursor_wm))
4357 I915_WRITE(WM2_LP_ILK,
4359 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4360 (fbc_wm << WM1_LP_FBC_SHIFT) |
4361 (plane_wm << WM1_LP_SR_SHIFT) |
4365 * WM3 is unsupported on ILK, probably because we don't have latency
4366 * data for that power state
4370 static void sandybridge_update_wm(struct drm_device *dev)
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4374 int fbc_wm, plane_wm, cursor_wm;
4375 unsigned int enabled;
4378 if (ironlake_compute_wm0(dev, 0,
4379 &sandybridge_display_wm_info, latency,
4380 &sandybridge_cursor_wm_info, latency,
4381 &plane_wm, &cursor_wm)) {
4382 I915_WRITE(WM0_PIPEA_ILK,
4383 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4384 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4385 " plane %d, " "cursor: %d\n",
4386 plane_wm, cursor_wm);
4390 if (ironlake_compute_wm0(dev, 1,
4391 &sandybridge_display_wm_info, latency,
4392 &sandybridge_cursor_wm_info, latency,
4393 &plane_wm, &cursor_wm)) {
4394 I915_WRITE(WM0_PIPEB_ILK,
4395 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4396 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4397 " plane %d, cursor: %d\n",
4398 plane_wm, cursor_wm);
4403 * Calculate and update the self-refresh watermark only when one
4404 * display plane is used.
4406 * SNB support 3 levels of watermark.
4408 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4409 * and disabled in the descending order
4412 I915_WRITE(WM3_LP_ILK, 0);
4413 I915_WRITE(WM2_LP_ILK, 0);
4414 I915_WRITE(WM1_LP_ILK, 0);
4416 if (!single_plane_enabled(enabled))
4418 enabled = ffs(enabled) - 1;
4421 if (!ironlake_compute_srwm(dev, 1, enabled,
4422 SNB_READ_WM1_LATENCY() * 500,
4423 &sandybridge_display_srwm_info,
4424 &sandybridge_cursor_srwm_info,
4425 &fbc_wm, &plane_wm, &cursor_wm))
4428 I915_WRITE(WM1_LP_ILK,
4430 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4431 (fbc_wm << WM1_LP_FBC_SHIFT) |
4432 (plane_wm << WM1_LP_SR_SHIFT) |
4436 if (!ironlake_compute_srwm(dev, 2, enabled,
4437 SNB_READ_WM2_LATENCY() * 500,
4438 &sandybridge_display_srwm_info,
4439 &sandybridge_cursor_srwm_info,
4440 &fbc_wm, &plane_wm, &cursor_wm))
4443 I915_WRITE(WM2_LP_ILK,
4445 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4446 (fbc_wm << WM1_LP_FBC_SHIFT) |
4447 (plane_wm << WM1_LP_SR_SHIFT) |
4451 if (!ironlake_compute_srwm(dev, 3, enabled,
4452 SNB_READ_WM3_LATENCY() * 500,
4453 &sandybridge_display_srwm_info,
4454 &sandybridge_cursor_srwm_info,
4455 &fbc_wm, &plane_wm, &cursor_wm))
4458 I915_WRITE(WM3_LP_ILK,
4460 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4461 (fbc_wm << WM1_LP_FBC_SHIFT) |
4462 (plane_wm << WM1_LP_SR_SHIFT) |
4467 * intel_update_watermarks - update FIFO watermark values based on current modes
4469 * Calculate watermark values for the various WM regs based on current mode
4470 * and plane configuration.
4472 * There are several cases to deal with here:
4473 * - normal (i.e. non-self-refresh)
4474 * - self-refresh (SR) mode
4475 * - lines are large relative to FIFO size (buffer can hold up to 2)
4476 * - lines are small relative to FIFO size (buffer can hold more than 2
4477 * lines), so need to account for TLB latency
4479 * The normal calculation is:
4480 * watermark = dotclock * bytes per pixel * latency
4481 * where latency is platform & configuration dependent (we assume pessimal
4484 * The SR calculation is:
4485 * watermark = (trunc(latency/line time)+1) * surface width *
4488 * line time = htotal / dotclock
4489 * surface width = hdisplay for normal plane and 64 for cursor
4490 * and latency is assumed to be high, as above.
4492 * The final value programmed to the register should always be rounded up,
4493 * and include an extra 2 entries to account for clock crossings.
4495 * We don't use the sprite, so we can ignore that. And on Crestline we have
4496 * to set the non-SR watermarks to 8.
4498 static void intel_update_watermarks(struct drm_device *dev)
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4502 if (dev_priv->display.update_wm)
4503 dev_priv->display.update_wm(dev);
4506 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4508 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4511 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4512 struct drm_display_mode *mode,
4513 struct drm_display_mode *adjusted_mode,
4515 struct drm_framebuffer *old_fb)
4517 struct drm_device *dev = crtc->dev;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4520 int pipe = intel_crtc->pipe;
4521 int plane = intel_crtc->plane;
4522 u32 fp_reg, dpll_reg;
4523 int refclk, num_connectors = 0;
4524 intel_clock_t clock, reduced_clock;
4525 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4526 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4527 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4528 struct intel_encoder *has_edp_encoder = NULL;
4529 struct drm_mode_config *mode_config = &dev->mode_config;
4530 struct intel_encoder *encoder;
4531 const intel_limit_t *limit;
4533 struct fdi_m_n m_n = {0};
4538 drm_vblank_pre_modeset(dev, pipe);
4540 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4541 if (encoder->base.crtc != crtc)
4544 switch (encoder->type) {
4545 case INTEL_OUTPUT_LVDS:
4548 case INTEL_OUTPUT_SDVO:
4549 case INTEL_OUTPUT_HDMI:
4551 if (encoder->needs_tv_clock)
4554 case INTEL_OUTPUT_DVO:
4557 case INTEL_OUTPUT_TVOUT:
4560 case INTEL_OUTPUT_ANALOG:
4563 case INTEL_OUTPUT_DISPLAYPORT:
4566 case INTEL_OUTPUT_EDP:
4567 has_edp_encoder = encoder;
4574 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4575 refclk = dev_priv->lvds_ssc_freq * 1000;
4576 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4578 } else if (!IS_GEN2(dev)) {
4580 if (HAS_PCH_SPLIT(dev) &&
4581 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4582 refclk = 120000; /* 120Mhz refclk */
4588 * Returns a set of divisors for the desired target clock with the given
4589 * refclk, or FALSE. The returned values represent the clock equation:
4590 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4592 limit = intel_limit(crtc, refclk);
4593 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4595 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4596 drm_vblank_post_modeset(dev, pipe);
4600 /* Ensure that the cursor is valid for the new mode before changing... */
4601 intel_crtc_update_cursor(crtc, true);
4603 if (is_lvds && dev_priv->lvds_downclock_avail) {
4604 has_reduced_clock = limit->find_pll(limit, crtc,
4605 dev_priv->lvds_downclock,
4608 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4610 * If the different P is found, it means that we can't
4611 * switch the display clock by using the FP0/FP1.
4612 * In such case we will disable the LVDS downclock
4615 DRM_DEBUG_KMS("Different P is found for "
4616 "LVDS clock/downclock\n");
4617 has_reduced_clock = 0;
4620 /* SDVO TV has fixed PLL values depend on its clock range,
4621 this mirrors vbios setting. */
4622 if (is_sdvo && is_tv) {
4623 if (adjusted_mode->clock >= 100000
4624 && adjusted_mode->clock < 140500) {
4630 } else if (adjusted_mode->clock >= 140500
4631 && adjusted_mode->clock <= 200000) {
4641 if (HAS_PCH_SPLIT(dev)) {
4642 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4643 int lane = 0, link_bw, bpp;
4644 /* CPU eDP doesn't require FDI link, so just set DP M/N
4645 according to current link config */
4646 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4647 target_clock = mode->clock;
4648 intel_edp_link_config(has_edp_encoder,
4651 /* [e]DP over FDI requires target mode clock
4652 instead of link clock */
4653 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4654 target_clock = mode->clock;
4656 target_clock = adjusted_mode->clock;
4658 /* FDI is a binary signal running at ~2.7GHz, encoding
4659 * each output octet as 10 bits. The actual frequency
4660 * is stored as a divider into a 100MHz clock, and the
4661 * mode pixel clock is stored in units of 1KHz.
4662 * Hence the bw of each lane in terms of the mode signal
4665 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4668 /* determine panel color depth */
4669 temp = I915_READ(PIPECONF(pipe));
4670 temp &= ~PIPE_BPC_MASK;
4672 /* the BPC will be 6 if it is 18-bit LVDS panel */
4673 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4677 } else if (has_edp_encoder) {
4678 switch (dev_priv->edp.bpp/3) {
4694 I915_WRITE(PIPECONF(pipe), temp);
4696 switch (temp & PIPE_BPC_MASK) {
4710 DRM_ERROR("unknown pipe bpc value\n");
4716 * Account for spread spectrum to avoid
4717 * oversubscribing the link. Max center spread
4718 * is 2.5%; use 5% for safety's sake.
4720 u32 bps = target_clock * bpp * 21 / 20;
4721 lane = bps / (link_bw * 8) + 1;
4724 intel_crtc->fdi_lanes = lane;
4726 if (pixel_multiplier > 1)
4727 link_bw *= pixel_multiplier;
4728 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4731 /* Ironlake: try to setup display ref clock before DPLL
4732 * enabling. This is only under driver's control after
4733 * PCH B stepping, previous chipset stepping should be
4734 * ignoring this setting.
4736 if (HAS_PCH_SPLIT(dev)) {
4737 temp = I915_READ(PCH_DREF_CONTROL);
4738 /* Always enable nonspread source */
4739 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4740 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4741 temp &= ~DREF_SSC_SOURCE_MASK;
4742 temp |= DREF_SSC_SOURCE_ENABLE;
4743 I915_WRITE(PCH_DREF_CONTROL, temp);
4745 POSTING_READ(PCH_DREF_CONTROL);
4748 if (has_edp_encoder) {
4749 if (intel_panel_use_ssc(dev_priv)) {
4750 temp |= DREF_SSC1_ENABLE;
4751 I915_WRITE(PCH_DREF_CONTROL, temp);
4753 POSTING_READ(PCH_DREF_CONTROL);
4756 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4758 /* Enable CPU source on CPU attached eDP */
4759 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4760 if (intel_panel_use_ssc(dev_priv))
4761 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4763 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4765 /* Enable SSC on PCH eDP if needed */
4766 if (intel_panel_use_ssc(dev_priv)) {
4767 DRM_ERROR("enabling SSC on PCH\n");
4768 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4771 I915_WRITE(PCH_DREF_CONTROL, temp);
4772 POSTING_READ(PCH_DREF_CONTROL);
4777 if (IS_PINEVIEW(dev)) {
4778 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4779 if (has_reduced_clock)
4780 fp2 = (1 << reduced_clock.n) << 16 |
4781 reduced_clock.m1 << 8 | reduced_clock.m2;
4783 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4784 if (has_reduced_clock)
4785 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4789 /* Enable autotuning of the PLL clock (if permissible) */
4790 if (HAS_PCH_SPLIT(dev)) {
4794 if ((intel_panel_use_ssc(dev_priv) &&
4795 dev_priv->lvds_ssc_freq == 100) ||
4796 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4798 } else if (is_sdvo && is_tv)
4801 if (clock.m1 < factor * clock.n)
4806 if (!HAS_PCH_SPLIT(dev))
4807 dpll = DPLL_VGA_MODE_DIS;
4809 if (!IS_GEN2(dev)) {
4811 dpll |= DPLLB_MODE_LVDS;
4813 dpll |= DPLLB_MODE_DAC_SERIAL;
4815 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4816 if (pixel_multiplier > 1) {
4817 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4818 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4819 else if (HAS_PCH_SPLIT(dev))
4820 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4822 dpll |= DPLL_DVO_HIGH_SPEED;
4824 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4825 dpll |= DPLL_DVO_HIGH_SPEED;
4827 /* compute bitmask from p1 value */
4828 if (IS_PINEVIEW(dev))
4829 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4831 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4833 if (HAS_PCH_SPLIT(dev))
4834 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4835 if (IS_G4X(dev) && has_reduced_clock)
4836 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4846 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4849 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4852 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4853 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4856 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4859 dpll |= PLL_P1_DIVIDE_BY_TWO;
4861 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4863 dpll |= PLL_P2_DIVIDE_BY_4;
4867 if (is_sdvo && is_tv)
4868 dpll |= PLL_REF_INPUT_TVCLKINBC;
4870 /* XXX: just matching BIOS for now */
4871 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4873 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4874 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4876 dpll |= PLL_REF_INPUT_DREFCLK;
4878 /* setup pipeconf */
4879 pipeconf = I915_READ(PIPECONF(pipe));
4881 /* Set up the display plane register */
4882 dspcntr = DISPPLANE_GAMMA_ENABLE;
4884 /* Ironlake's plane is forced to pipe, bit 24 is to
4885 enable color space conversion */
4886 if (!HAS_PCH_SPLIT(dev)) {
4888 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4890 dspcntr |= DISPPLANE_SEL_PIPE_B;
4893 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4894 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4897 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4901 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4902 pipeconf |= PIPECONF_DOUBLE_WIDE;
4904 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4907 if (!HAS_PCH_SPLIT(dev))
4908 dpll |= DPLL_VCO_ENABLE;
4910 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4911 drm_mode_debug_printmodeline(mode);
4913 /* assign to Ironlake registers */
4914 if (HAS_PCH_SPLIT(dev)) {
4915 fp_reg = PCH_FP0(pipe);
4916 dpll_reg = PCH_DPLL(pipe);
4919 dpll_reg = DPLL(pipe);
4922 /* PCH eDP needs FDI, but CPU eDP does not */
4923 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4924 I915_WRITE(fp_reg, fp);
4925 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4927 POSTING_READ(dpll_reg);
4931 /* enable transcoder DPLL */
4932 if (HAS_PCH_CPT(dev)) {
4933 temp = I915_READ(PCH_DPLL_SEL);
4936 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4939 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4942 /* FIXME: manage transcoder PLLs? */
4943 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4948 I915_WRITE(PCH_DPLL_SEL, temp);
4950 POSTING_READ(PCH_DPLL_SEL);
4954 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4955 * This is an exception to the general rule that mode_set doesn't turn
4960 if (HAS_PCH_SPLIT(dev))
4963 temp = I915_READ(reg);
4964 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4966 if (HAS_PCH_CPT(dev))
4967 temp |= PORT_TRANS_B_SEL_CPT;
4969 temp |= LVDS_PIPEB_SELECT;
4971 if (HAS_PCH_CPT(dev))
4972 temp &= ~PORT_TRANS_SEL_MASK;
4974 temp &= ~LVDS_PIPEB_SELECT;
4976 /* set the corresponsding LVDS_BORDER bit */
4977 temp |= dev_priv->lvds_border_bits;
4978 /* Set the B0-B3 data pairs corresponding to whether we're going to
4979 * set the DPLLs for dual-channel mode or not.
4982 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4984 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4986 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4987 * appropriately here, but we need to look more thoroughly into how
4988 * panels behave in the two modes.
4990 /* set the dithering flag on non-PCH LVDS as needed */
4991 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4992 if (dev_priv->lvds_dither)
4993 temp |= LVDS_ENABLE_DITHER;
4995 temp &= ~LVDS_ENABLE_DITHER;
4997 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4998 lvds_sync |= LVDS_HSYNC_POLARITY;
4999 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5000 lvds_sync |= LVDS_VSYNC_POLARITY;
5001 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5003 char flags[2] = "-+";
5004 DRM_INFO("Changing LVDS panel from "
5005 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5006 flags[!(temp & LVDS_HSYNC_POLARITY)],
5007 flags[!(temp & LVDS_VSYNC_POLARITY)],
5008 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5009 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5010 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5013 I915_WRITE(reg, temp);
5016 /* set the dithering flag and clear for anything other than a panel. */
5017 if (HAS_PCH_SPLIT(dev)) {
5018 pipeconf &= ~PIPECONF_DITHER_EN;
5019 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5020 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5021 pipeconf |= PIPECONF_DITHER_EN;
5022 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5026 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5027 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5028 } else if (HAS_PCH_SPLIT(dev)) {
5029 /* For non-DP output, clear any trans DP clock recovery setting.*/
5030 I915_WRITE(TRANSDATA_M1(pipe), 0);
5031 I915_WRITE(TRANSDATA_N1(pipe), 0);
5032 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5033 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5036 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5037 I915_WRITE(dpll_reg, dpll);
5039 /* Wait for the clocks to stabilize. */
5040 POSTING_READ(dpll_reg);
5043 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5046 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5048 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5052 I915_WRITE(DPLL_MD(pipe), temp);
5054 /* The pixel multiplier can only be updated once the
5055 * DPLL is enabled and the clocks are stable.
5057 * So write it again.
5059 I915_WRITE(dpll_reg, dpll);
5063 intel_crtc->lowfreq_avail = false;
5064 if (is_lvds && has_reduced_clock && i915_powersave) {
5065 I915_WRITE(fp_reg + 4, fp2);
5066 intel_crtc->lowfreq_avail = true;
5067 if (HAS_PIPE_CXSR(dev)) {
5068 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5069 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5072 I915_WRITE(fp_reg + 4, fp);
5073 if (HAS_PIPE_CXSR(dev)) {
5074 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5075 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5079 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5080 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5081 /* the chip adds 2 halflines automatically */
5082 adjusted_mode->crtc_vdisplay -= 1;
5083 adjusted_mode->crtc_vtotal -= 1;
5084 adjusted_mode->crtc_vblank_start -= 1;
5085 adjusted_mode->crtc_vblank_end -= 1;
5086 adjusted_mode->crtc_vsync_end -= 1;
5087 adjusted_mode->crtc_vsync_start -= 1;
5089 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5091 I915_WRITE(HTOTAL(pipe),
5092 (adjusted_mode->crtc_hdisplay - 1) |
5093 ((adjusted_mode->crtc_htotal - 1) << 16));
5094 I915_WRITE(HBLANK(pipe),
5095 (adjusted_mode->crtc_hblank_start - 1) |
5096 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5097 I915_WRITE(HSYNC(pipe),
5098 (adjusted_mode->crtc_hsync_start - 1) |
5099 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5101 I915_WRITE(VTOTAL(pipe),
5102 (adjusted_mode->crtc_vdisplay - 1) |
5103 ((adjusted_mode->crtc_vtotal - 1) << 16));
5104 I915_WRITE(VBLANK(pipe),
5105 (adjusted_mode->crtc_vblank_start - 1) |
5106 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5107 I915_WRITE(VSYNC(pipe),
5108 (adjusted_mode->crtc_vsync_start - 1) |
5109 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5111 /* pipesrc and dspsize control the size that is scaled from,
5112 * which should always be the user's requested size.
5114 if (!HAS_PCH_SPLIT(dev)) {
5115 I915_WRITE(DSPSIZE(plane),
5116 ((mode->vdisplay - 1) << 16) |
5117 (mode->hdisplay - 1));
5118 I915_WRITE(DSPPOS(plane), 0);
5120 I915_WRITE(PIPESRC(pipe),
5121 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5123 if (HAS_PCH_SPLIT(dev)) {
5124 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5125 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5126 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5127 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5129 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5130 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5134 I915_WRITE(PIPECONF(pipe), pipeconf);
5135 POSTING_READ(PIPECONF(pipe));
5136 if (!HAS_PCH_SPLIT(dev))
5137 intel_enable_pipe(dev_priv, pipe, false);
5139 intel_wait_for_vblank(dev, pipe);
5142 /* enable address swizzle for tiling buffer */
5143 temp = I915_READ(DISP_ARB_CTL);
5144 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5147 I915_WRITE(DSPCNTR(plane), dspcntr);
5148 POSTING_READ(DSPCNTR(plane));
5149 if (!HAS_PCH_SPLIT(dev))
5150 intel_enable_plane(dev_priv, plane, pipe);
5152 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5154 intel_update_watermarks(dev);
5156 drm_vblank_post_modeset(dev, pipe);
5161 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5162 void intel_crtc_load_lut(struct drm_crtc *crtc)
5164 struct drm_device *dev = crtc->dev;
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5167 int palreg = PALETTE(intel_crtc->pipe);
5170 /* The clocks have to be on to load the palette. */
5174 /* use legacy palette for Ironlake */
5175 if (HAS_PCH_SPLIT(dev))
5176 palreg = LGC_PALETTE(intel_crtc->pipe);
5178 for (i = 0; i < 256; i++) {
5179 I915_WRITE(palreg + 4 * i,
5180 (intel_crtc->lut_r[i] << 16) |
5181 (intel_crtc->lut_g[i] << 8) |
5182 intel_crtc->lut_b[i]);
5186 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5188 struct drm_device *dev = crtc->dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191 bool visible = base != 0;
5194 if (intel_crtc->cursor_visible == visible)
5197 cntl = I915_READ(_CURACNTR);
5199 /* On these chipsets we can only modify the base whilst
5200 * the cursor is disabled.
5202 I915_WRITE(_CURABASE, base);
5204 cntl &= ~(CURSOR_FORMAT_MASK);
5205 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5206 cntl |= CURSOR_ENABLE |
5207 CURSOR_GAMMA_ENABLE |
5210 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5211 I915_WRITE(_CURACNTR, cntl);
5213 intel_crtc->cursor_visible = visible;
5216 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5218 struct drm_device *dev = crtc->dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221 int pipe = intel_crtc->pipe;
5222 bool visible = base != 0;
5224 if (intel_crtc->cursor_visible != visible) {
5225 uint32_t cntl = I915_READ(CURCNTR(pipe));
5227 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5228 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5229 cntl |= pipe << 28; /* Connect to correct pipe */
5231 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5232 cntl |= CURSOR_MODE_DISABLE;
5234 I915_WRITE(CURCNTR(pipe), cntl);
5236 intel_crtc->cursor_visible = visible;
5238 /* and commit changes on next vblank */
5239 I915_WRITE(CURBASE(pipe), base);
5242 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5243 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5246 struct drm_device *dev = crtc->dev;
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 int pipe = intel_crtc->pipe;
5250 int x = intel_crtc->cursor_x;
5251 int y = intel_crtc->cursor_y;
5257 if (on && crtc->enabled && crtc->fb) {
5258 base = intel_crtc->cursor_addr;
5259 if (x > (int) crtc->fb->width)
5262 if (y > (int) crtc->fb->height)
5268 if (x + intel_crtc->cursor_width < 0)
5271 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5274 pos |= x << CURSOR_X_SHIFT;
5277 if (y + intel_crtc->cursor_height < 0)
5280 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5283 pos |= y << CURSOR_Y_SHIFT;
5285 visible = base != 0;
5286 if (!visible && !intel_crtc->cursor_visible)
5289 I915_WRITE(CURPOS(pipe), pos);
5290 if (IS_845G(dev) || IS_I865G(dev))
5291 i845_update_cursor(crtc, base);
5293 i9xx_update_cursor(crtc, base);
5296 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5299 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5300 struct drm_file *file,
5302 uint32_t width, uint32_t height)
5304 struct drm_device *dev = crtc->dev;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5307 struct drm_i915_gem_object *obj;
5311 DRM_DEBUG_KMS("\n");
5313 /* if we want to turn off the cursor ignore width and height */
5315 DRM_DEBUG_KMS("cursor off\n");
5318 mutex_lock(&dev->struct_mutex);
5322 /* Currently we only support 64x64 cursors */
5323 if (width != 64 || height != 64) {
5324 DRM_ERROR("we currently only support 64x64 cursors\n");
5328 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5329 if (&obj->base == NULL)
5332 if (obj->base.size < width * height * 4) {
5333 DRM_ERROR("buffer is to small\n");
5338 /* we only need to pin inside GTT if cursor is non-phy */
5339 mutex_lock(&dev->struct_mutex);
5340 if (!dev_priv->info->cursor_needs_physical) {
5341 if (obj->tiling_mode) {
5342 DRM_ERROR("cursor cannot be tiled\n");
5347 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
5349 DRM_ERROR("failed to pin cursor bo\n");
5353 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
5355 DRM_ERROR("failed to move cursor bo into the GTT\n");
5359 ret = i915_gem_object_put_fence(obj);
5361 DRM_ERROR("failed to move cursor bo into the GTT\n");
5365 addr = obj->gtt_offset;
5367 int align = IS_I830(dev) ? 16 * 1024 : 256;
5368 ret = i915_gem_attach_phys_object(dev, obj,
5369 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5372 DRM_ERROR("failed to attach phys object\n");
5375 addr = obj->phys_obj->handle->busaddr;
5379 I915_WRITE(CURSIZE, (height << 12) | width);
5382 if (intel_crtc->cursor_bo) {
5383 if (dev_priv->info->cursor_needs_physical) {
5384 if (intel_crtc->cursor_bo != obj)
5385 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5387 i915_gem_object_unpin(intel_crtc->cursor_bo);
5388 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5391 mutex_unlock(&dev->struct_mutex);
5393 intel_crtc->cursor_addr = addr;
5394 intel_crtc->cursor_bo = obj;
5395 intel_crtc->cursor_width = width;
5396 intel_crtc->cursor_height = height;
5398 intel_crtc_update_cursor(crtc, true);
5402 i915_gem_object_unpin(obj);
5404 mutex_unlock(&dev->struct_mutex);
5406 drm_gem_object_unreference_unlocked(&obj->base);
5410 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414 intel_crtc->cursor_x = x;
5415 intel_crtc->cursor_y = y;
5417 intel_crtc_update_cursor(crtc, true);
5422 /** Sets the color ramps on behalf of RandR */
5423 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5424 u16 blue, int regno)
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5428 intel_crtc->lut_r[regno] = red >> 8;
5429 intel_crtc->lut_g[regno] = green >> 8;
5430 intel_crtc->lut_b[regno] = blue >> 8;
5433 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5434 u16 *blue, int regno)
5436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5438 *red = intel_crtc->lut_r[regno] << 8;
5439 *green = intel_crtc->lut_g[regno] << 8;
5440 *blue = intel_crtc->lut_b[regno] << 8;
5443 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5444 u16 *blue, uint32_t start, uint32_t size)
5446 int end = (start + size > 256) ? 256 : start + size, i;
5447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5449 for (i = start; i < end; i++) {
5450 intel_crtc->lut_r[i] = red[i] >> 8;
5451 intel_crtc->lut_g[i] = green[i] >> 8;
5452 intel_crtc->lut_b[i] = blue[i] >> 8;
5455 intel_crtc_load_lut(crtc);
5459 * Get a pipe with a simple mode set on it for doing load-based monitor
5462 * It will be up to the load-detect code to adjust the pipe as appropriate for
5463 * its requirements. The pipe will be connected to no other encoders.
5465 * Currently this code will only succeed if there is a pipe with no encoders
5466 * configured for it. In the future, it could choose to temporarily disable
5467 * some outputs to free up a pipe for its use.
5469 * \return crtc, or NULL if no pipes are available.
5472 /* VESA 640x480x72Hz mode to set on the pipe */
5473 static struct drm_display_mode load_detect_mode = {
5474 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5475 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5478 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5479 struct drm_connector *connector,
5480 struct drm_display_mode *mode,
5483 struct intel_crtc *intel_crtc;
5484 struct drm_crtc *possible_crtc;
5485 struct drm_crtc *supported_crtc =NULL;
5486 struct drm_encoder *encoder = &intel_encoder->base;
5487 struct drm_crtc *crtc = NULL;
5488 struct drm_device *dev = encoder->dev;
5489 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5490 struct drm_crtc_helper_funcs *crtc_funcs;
5494 * Algorithm gets a little messy:
5495 * - if the connector already has an assigned crtc, use it (but make
5496 * sure it's on first)
5497 * - try to find the first unused crtc that can drive this connector,
5498 * and use that if we find one
5499 * - if there are no unused crtcs available, try to use the first
5500 * one we found that supports the connector
5503 /* See if we already have a CRTC for this connector */
5504 if (encoder->crtc) {
5505 crtc = encoder->crtc;
5506 /* Make sure the crtc and connector are running */
5507 intel_crtc = to_intel_crtc(crtc);
5508 *dpms_mode = intel_crtc->dpms_mode;
5509 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5510 crtc_funcs = crtc->helper_private;
5511 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5512 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5517 /* Find an unused one (if possible) */
5518 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5520 if (!(encoder->possible_crtcs & (1 << i)))
5522 if (!possible_crtc->enabled) {
5523 crtc = possible_crtc;
5526 if (!supported_crtc)
5527 supported_crtc = possible_crtc;
5531 * If we didn't find an unused CRTC, don't use any.
5537 encoder->crtc = crtc;
5538 connector->encoder = encoder;
5539 intel_encoder->load_detect_temp = true;
5541 intel_crtc = to_intel_crtc(crtc);
5542 *dpms_mode = intel_crtc->dpms_mode;
5544 if (!crtc->enabled) {
5546 mode = &load_detect_mode;
5547 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5549 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5550 crtc_funcs = crtc->helper_private;
5551 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5554 /* Add this connector to the crtc */
5555 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5556 encoder_funcs->commit(encoder);
5558 /* let the connector get through one full cycle before testing */
5559 intel_wait_for_vblank(dev, intel_crtc->pipe);
5564 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5565 struct drm_connector *connector, int dpms_mode)
5567 struct drm_encoder *encoder = &intel_encoder->base;
5568 struct drm_device *dev = encoder->dev;
5569 struct drm_crtc *crtc = encoder->crtc;
5570 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5571 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5573 if (intel_encoder->load_detect_temp) {
5574 encoder->crtc = NULL;
5575 connector->encoder = NULL;
5576 intel_encoder->load_detect_temp = false;
5577 crtc->enabled = drm_helper_crtc_in_use(crtc);
5578 drm_helper_disable_unused_functions(dev);
5581 /* Switch crtc and encoder back off if necessary */
5582 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5583 if (encoder->crtc == crtc)
5584 encoder_funcs->dpms(encoder, dpms_mode);
5585 crtc_funcs->dpms(crtc, dpms_mode);
5589 /* Returns the clock of the currently programmed mode of the given pipe. */
5590 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5594 int pipe = intel_crtc->pipe;
5595 u32 dpll = I915_READ(DPLL(pipe));
5597 intel_clock_t clock;
5599 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5604 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5605 if (IS_PINEVIEW(dev)) {
5606 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5607 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5609 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5610 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5613 if (!IS_GEN2(dev)) {
5614 if (IS_PINEVIEW(dev))
5615 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5616 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5619 DPLL_FPA01_P1_POST_DIV_SHIFT);
5621 switch (dpll & DPLL_MODE_MASK) {
5622 case DPLLB_MODE_DAC_SERIAL:
5623 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5626 case DPLLB_MODE_LVDS:
5627 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5631 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5632 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5636 /* XXX: Handle the 100Mhz refclk */
5637 intel_clock(dev, 96000, &clock);
5639 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5642 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5643 DPLL_FPA01_P1_POST_DIV_SHIFT);
5646 if ((dpll & PLL_REF_INPUT_MASK) ==
5647 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5648 /* XXX: might not be 66MHz */
5649 intel_clock(dev, 66000, &clock);
5651 intel_clock(dev, 48000, &clock);
5653 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5656 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5657 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5659 if (dpll & PLL_P2_DIVIDE_BY_4)
5664 intel_clock(dev, 48000, &clock);
5668 /* XXX: It would be nice to validate the clocks, but we can't reuse
5669 * i830PllIsValid() because it relies on the xf86_config connector
5670 * configuration being accurate, which it isn't necessarily.
5676 /** Returns the currently programmed mode of the given pipe. */
5677 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5678 struct drm_crtc *crtc)
5680 struct drm_i915_private *dev_priv = dev->dev_private;
5681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5682 int pipe = intel_crtc->pipe;
5683 struct drm_display_mode *mode;
5684 int htot = I915_READ(HTOTAL(pipe));
5685 int hsync = I915_READ(HSYNC(pipe));
5686 int vtot = I915_READ(VTOTAL(pipe));
5687 int vsync = I915_READ(VSYNC(pipe));
5689 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5693 mode->clock = intel_crtc_clock_get(dev, crtc);
5694 mode->hdisplay = (htot & 0xffff) + 1;
5695 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5696 mode->hsync_start = (hsync & 0xffff) + 1;
5697 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5698 mode->vdisplay = (vtot & 0xffff) + 1;
5699 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5700 mode->vsync_start = (vsync & 0xffff) + 1;
5701 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5703 drm_mode_set_name(mode);
5704 drm_mode_set_crtcinfo(mode, 0);
5709 #define GPU_IDLE_TIMEOUT 500 /* ms */
5711 /* When this timer fires, we've been idle for awhile */
5712 static void intel_gpu_idle_timer(unsigned long arg)
5714 struct drm_device *dev = (struct drm_device *)arg;
5715 drm_i915_private_t *dev_priv = dev->dev_private;
5717 if (!list_empty(&dev_priv->mm.active_list)) {
5718 /* Still processing requests, so just re-arm the timer. */
5719 mod_timer(&dev_priv->idle_timer, jiffies +
5720 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5724 dev_priv->busy = false;
5725 queue_work(dev_priv->wq, &dev_priv->idle_work);
5728 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5730 static void intel_crtc_idle_timer(unsigned long arg)
5732 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5733 struct drm_crtc *crtc = &intel_crtc->base;
5734 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5735 struct intel_framebuffer *intel_fb;
5737 intel_fb = to_intel_framebuffer(crtc->fb);
5738 if (intel_fb && intel_fb->obj->active) {
5739 /* The framebuffer is still being accessed by the GPU. */
5740 mod_timer(&intel_crtc->idle_timer, jiffies +
5741 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5745 intel_crtc->busy = false;
5746 queue_work(dev_priv->wq, &dev_priv->idle_work);
5749 static void intel_increase_pllclock(struct drm_crtc *crtc)
5751 struct drm_device *dev = crtc->dev;
5752 drm_i915_private_t *dev_priv = dev->dev_private;
5753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5754 int pipe = intel_crtc->pipe;
5755 int dpll_reg = DPLL(pipe);
5758 if (HAS_PCH_SPLIT(dev))
5761 if (!dev_priv->lvds_downclock_avail)
5764 dpll = I915_READ(dpll_reg);
5765 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5766 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5768 /* Unlock panel regs */
5769 I915_WRITE(PP_CONTROL,
5770 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5772 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5773 I915_WRITE(dpll_reg, dpll);
5774 intel_wait_for_vblank(dev, pipe);
5776 dpll = I915_READ(dpll_reg);
5777 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5778 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5780 /* ...and lock them again */
5781 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5784 /* Schedule downclock */
5785 mod_timer(&intel_crtc->idle_timer, jiffies +
5786 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5789 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5791 struct drm_device *dev = crtc->dev;
5792 drm_i915_private_t *dev_priv = dev->dev_private;
5793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5794 int pipe = intel_crtc->pipe;
5795 int dpll_reg = DPLL(pipe);
5796 int dpll = I915_READ(dpll_reg);
5798 if (HAS_PCH_SPLIT(dev))
5801 if (!dev_priv->lvds_downclock_avail)
5805 * Since this is called by a timer, we should never get here in
5808 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5809 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5811 /* Unlock panel regs */
5812 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5815 dpll |= DISPLAY_RATE_SELECT_FPA1;
5816 I915_WRITE(dpll_reg, dpll);
5817 intel_wait_for_vblank(dev, pipe);
5818 dpll = I915_READ(dpll_reg);
5819 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5820 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5822 /* ...and lock them again */
5823 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5829 * intel_idle_update - adjust clocks for idleness
5830 * @work: work struct
5832 * Either the GPU or display (or both) went idle. Check the busy status
5833 * here and adjust the CRTC and GPU clocks as necessary.
5835 static void intel_idle_update(struct work_struct *work)
5837 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5839 struct drm_device *dev = dev_priv->dev;
5840 struct drm_crtc *crtc;
5841 struct intel_crtc *intel_crtc;
5843 if (!i915_powersave)
5846 mutex_lock(&dev->struct_mutex);
5848 i915_update_gfx_val(dev_priv);
5850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5851 /* Skip inactive CRTCs */
5855 intel_crtc = to_intel_crtc(crtc);
5856 if (!intel_crtc->busy)
5857 intel_decrease_pllclock(crtc);
5861 mutex_unlock(&dev->struct_mutex);
5865 * intel_mark_busy - mark the GPU and possibly the display busy
5867 * @obj: object we're operating on
5869 * Callers can use this function to indicate that the GPU is busy processing
5870 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5871 * buffer), we'll also mark the display as busy, so we know to increase its
5874 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5876 drm_i915_private_t *dev_priv = dev->dev_private;
5877 struct drm_crtc *crtc = NULL;
5878 struct intel_framebuffer *intel_fb;
5879 struct intel_crtc *intel_crtc;
5881 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5884 if (!dev_priv->busy)
5885 dev_priv->busy = true;
5887 mod_timer(&dev_priv->idle_timer, jiffies +
5888 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5890 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5894 intel_crtc = to_intel_crtc(crtc);
5895 intel_fb = to_intel_framebuffer(crtc->fb);
5896 if (intel_fb->obj == obj) {
5897 if (!intel_crtc->busy) {
5898 /* Non-busy -> busy, upclock */
5899 intel_increase_pllclock(crtc);
5900 intel_crtc->busy = true;
5902 /* Busy -> busy, put off timer */
5903 mod_timer(&intel_crtc->idle_timer, jiffies +
5904 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5910 static void intel_crtc_destroy(struct drm_crtc *crtc)
5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5913 struct drm_device *dev = crtc->dev;
5914 struct intel_unpin_work *work;
5915 unsigned long flags;
5917 spin_lock_irqsave(&dev->event_lock, flags);
5918 work = intel_crtc->unpin_work;
5919 intel_crtc->unpin_work = NULL;
5920 spin_unlock_irqrestore(&dev->event_lock, flags);
5923 cancel_work_sync(&work->work);
5927 drm_crtc_cleanup(crtc);
5932 static void intel_unpin_work_fn(struct work_struct *__work)
5934 struct intel_unpin_work *work =
5935 container_of(__work, struct intel_unpin_work, work);
5937 mutex_lock(&work->dev->struct_mutex);
5938 i915_gem_object_unpin(work->old_fb_obj);
5939 drm_gem_object_unreference(&work->pending_flip_obj->base);
5940 drm_gem_object_unreference(&work->old_fb_obj->base);
5942 mutex_unlock(&work->dev->struct_mutex);
5946 static void do_intel_finish_page_flip(struct drm_device *dev,
5947 struct drm_crtc *crtc)
5949 drm_i915_private_t *dev_priv = dev->dev_private;
5950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951 struct intel_unpin_work *work;
5952 struct drm_i915_gem_object *obj;
5953 struct drm_pending_vblank_event *e;
5954 struct timeval tnow, tvbl;
5955 unsigned long flags;
5957 /* Ignore early vblank irqs */
5958 if (intel_crtc == NULL)
5961 do_gettimeofday(&tnow);
5963 spin_lock_irqsave(&dev->event_lock, flags);
5964 work = intel_crtc->unpin_work;
5965 if (work == NULL || !work->pending) {
5966 spin_unlock_irqrestore(&dev->event_lock, flags);
5970 intel_crtc->unpin_work = NULL;
5974 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5976 /* Called before vblank count and timestamps have
5977 * been updated for the vblank interval of flip
5978 * completion? Need to increment vblank count and
5979 * add one videorefresh duration to returned timestamp
5980 * to account for this. We assume this happened if we
5981 * get called over 0.9 frame durations after the last
5982 * timestamped vblank.
5984 * This calculation can not be used with vrefresh rates
5985 * below 5Hz (10Hz to be on the safe side) without
5986 * promoting to 64 integers.
5988 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5989 9 * crtc->framedur_ns) {
5990 e->event.sequence++;
5991 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5995 e->event.tv_sec = tvbl.tv_sec;
5996 e->event.tv_usec = tvbl.tv_usec;
5998 list_add_tail(&e->base.link,
5999 &e->base.file_priv->event_list);
6000 wake_up_interruptible(&e->base.file_priv->event_wait);
6003 drm_vblank_put(dev, intel_crtc->pipe);
6005 spin_unlock_irqrestore(&dev->event_lock, flags);
6007 obj = work->old_fb_obj;
6009 atomic_clear_mask(1 << intel_crtc->plane,
6010 &obj->pending_flip.counter);
6011 if (atomic_read(&obj->pending_flip) == 0)
6012 wake_up(&dev_priv->pending_flip_queue);
6014 schedule_work(&work->work);
6016 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6019 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6021 drm_i915_private_t *dev_priv = dev->dev_private;
6022 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6024 do_intel_finish_page_flip(dev, crtc);
6027 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6029 drm_i915_private_t *dev_priv = dev->dev_private;
6030 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6032 do_intel_finish_page_flip(dev, crtc);
6035 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6037 drm_i915_private_t *dev_priv = dev->dev_private;
6038 struct intel_crtc *intel_crtc =
6039 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6040 unsigned long flags;
6042 spin_lock_irqsave(&dev->event_lock, flags);
6043 if (intel_crtc->unpin_work) {
6044 if ((++intel_crtc->unpin_work->pending) > 1)
6045 DRM_ERROR("Prepared flip multiple times\n");
6047 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6049 spin_unlock_irqrestore(&dev->event_lock, flags);
6052 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6053 struct drm_framebuffer *fb,
6054 struct drm_pending_vblank_event *event)
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct intel_framebuffer *intel_fb;
6059 struct drm_i915_gem_object *obj;
6060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061 struct intel_unpin_work *work;
6062 unsigned long flags, offset;
6063 int pipe = intel_crtc->pipe;
6067 work = kzalloc(sizeof *work, GFP_KERNEL);
6071 work->event = event;
6072 work->dev = crtc->dev;
6073 intel_fb = to_intel_framebuffer(crtc->fb);
6074 work->old_fb_obj = intel_fb->obj;
6075 INIT_WORK(&work->work, intel_unpin_work_fn);
6077 /* We borrow the event spin lock for protecting unpin_work */
6078 spin_lock_irqsave(&dev->event_lock, flags);
6079 if (intel_crtc->unpin_work) {
6080 spin_unlock_irqrestore(&dev->event_lock, flags);
6083 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6086 intel_crtc->unpin_work = work;
6087 spin_unlock_irqrestore(&dev->event_lock, flags);
6089 intel_fb = to_intel_framebuffer(fb);
6090 obj = intel_fb->obj;
6092 mutex_lock(&dev->struct_mutex);
6093 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6097 /* Reference the objects for the scheduled work. */
6098 drm_gem_object_reference(&work->old_fb_obj->base);
6099 drm_gem_object_reference(&obj->base);
6103 ret = drm_vblank_get(dev, intel_crtc->pipe);
6107 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6110 /* Can't queue multiple flips, so wait for the previous
6111 * one to finish before executing the next.
6113 ret = BEGIN_LP_RING(2);
6117 if (intel_crtc->plane)
6118 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6120 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6121 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6126 work->pending_flip_obj = obj;
6128 work->enable_stall_check = true;
6130 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6131 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6133 ret = BEGIN_LP_RING(4);
6137 /* Block clients from rendering to the new back buffer until
6138 * the flip occurs and the object is no longer visible.
6140 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6142 switch (INTEL_INFO(dev)->gen) {
6144 OUT_RING(MI_DISPLAY_FLIP |
6145 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6146 OUT_RING(fb->pitch);
6147 OUT_RING(obj->gtt_offset + offset);
6152 OUT_RING(MI_DISPLAY_FLIP_I915 |
6153 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6154 OUT_RING(fb->pitch);
6155 OUT_RING(obj->gtt_offset + offset);
6161 /* i965+ uses the linear or tiled offsets from the
6162 * Display Registers (which do not change across a page-flip)
6163 * so we need only reprogram the base address.
6165 OUT_RING(MI_DISPLAY_FLIP |
6166 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6167 OUT_RING(fb->pitch);
6168 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6170 /* XXX Enabling the panel-fitter across page-flip is so far
6171 * untested on non-native modes, so ignore it for now.
6172 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6175 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6176 OUT_RING(pf | pipesrc);
6180 OUT_RING(MI_DISPLAY_FLIP |
6181 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6182 OUT_RING(fb->pitch | obj->tiling_mode);
6183 OUT_RING(obj->gtt_offset);
6185 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6186 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
6187 OUT_RING(pf | pipesrc);
6192 mutex_unlock(&dev->struct_mutex);
6194 trace_i915_flip_request(intel_crtc->plane, obj);
6199 drm_gem_object_unreference(&work->old_fb_obj->base);
6200 drm_gem_object_unreference(&obj->base);
6202 mutex_unlock(&dev->struct_mutex);
6204 spin_lock_irqsave(&dev->event_lock, flags);
6205 intel_crtc->unpin_work = NULL;
6206 spin_unlock_irqrestore(&dev->event_lock, flags);
6213 static void intel_crtc_reset(struct drm_crtc *crtc)
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217 /* Reset flags back to the 'unknown' status so that they
6218 * will be correctly set on the initial modeset.
6220 intel_crtc->dpms_mode = -1;
6223 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6224 .dpms = intel_crtc_dpms,
6225 .mode_fixup = intel_crtc_mode_fixup,
6226 .mode_set = intel_crtc_mode_set,
6227 .mode_set_base = intel_pipe_set_base,
6228 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6229 .load_lut = intel_crtc_load_lut,
6230 .disable = intel_crtc_disable,
6233 static const struct drm_crtc_funcs intel_crtc_funcs = {
6234 .reset = intel_crtc_reset,
6235 .cursor_set = intel_crtc_cursor_set,
6236 .cursor_move = intel_crtc_cursor_move,
6237 .gamma_set = intel_crtc_gamma_set,
6238 .set_config = drm_crtc_helper_set_config,
6239 .destroy = intel_crtc_destroy,
6240 .page_flip = intel_crtc_page_flip,
6243 static void intel_sanitize_modesetting(struct drm_device *dev,
6244 int pipe, int plane)
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6249 if (HAS_PCH_SPLIT(dev))
6252 /* Who knows what state these registers were left in by the BIOS or
6255 * If we leave the registers in a conflicting state (e.g. with the
6256 * display plane reading from the other pipe than the one we intend
6257 * to use) then when we attempt to teardown the active mode, we will
6258 * not disable the pipes and planes in the correct order -- leaving
6259 * a plane reading from a disabled pipe and possibly leading to
6260 * undefined behaviour.
6263 reg = DSPCNTR(plane);
6264 val = I915_READ(reg);
6266 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6268 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6271 /* This display plane is active and attached to the other CPU pipe. */
6274 /* Disable the plane and wait for it to stop reading from the pipe. */
6275 intel_disable_plane(dev_priv, plane, pipe);
6276 intel_disable_pipe(dev_priv, pipe);
6279 static void intel_crtc_init(struct drm_device *dev, int pipe)
6281 drm_i915_private_t *dev_priv = dev->dev_private;
6282 struct intel_crtc *intel_crtc;
6285 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6286 if (intel_crtc == NULL)
6289 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6291 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6292 for (i = 0; i < 256; i++) {
6293 intel_crtc->lut_r[i] = i;
6294 intel_crtc->lut_g[i] = i;
6295 intel_crtc->lut_b[i] = i;
6298 /* Swap pipes & planes for FBC on pre-965 */
6299 intel_crtc->pipe = pipe;
6300 intel_crtc->plane = pipe;
6301 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6302 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6303 intel_crtc->plane = !pipe;
6306 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6307 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6308 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6309 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6311 intel_crtc_reset(&intel_crtc->base);
6312 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6314 if (HAS_PCH_SPLIT(dev)) {
6315 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6316 intel_helper_funcs.commit = ironlake_crtc_commit;
6318 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6319 intel_helper_funcs.commit = i9xx_crtc_commit;
6322 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6324 intel_crtc->busy = false;
6326 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6327 (unsigned long)intel_crtc);
6329 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6332 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6333 struct drm_file *file)
6335 drm_i915_private_t *dev_priv = dev->dev_private;
6336 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6337 struct drm_mode_object *drmmode_obj;
6338 struct intel_crtc *crtc;
6341 DRM_ERROR("called with no initialization\n");
6345 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6346 DRM_MODE_OBJECT_CRTC);
6349 DRM_ERROR("no such CRTC id\n");
6353 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6354 pipe_from_crtc_id->pipe = crtc->pipe;
6359 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6361 struct intel_encoder *encoder;
6365 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6366 if (type_mask & encoder->clone_mask)
6367 index_mask |= (1 << entry);
6374 static bool has_edp_a(struct drm_device *dev)
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6378 if (!IS_MOBILE(dev))
6381 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6385 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6391 static void intel_setup_outputs(struct drm_device *dev)
6393 struct drm_i915_private *dev_priv = dev->dev_private;
6394 struct intel_encoder *encoder;
6395 bool dpd_is_edp = false;
6396 bool has_lvds = false;
6398 if (IS_MOBILE(dev) && !IS_I830(dev))
6399 has_lvds = intel_lvds_init(dev);
6400 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6401 /* disable the panel fitter on everything but LVDS */
6402 I915_WRITE(PFIT_CONTROL, 0);
6405 if (HAS_PCH_SPLIT(dev)) {
6406 dpd_is_edp = intel_dpd_is_edp(dev);
6409 intel_dp_init(dev, DP_A);
6411 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6412 intel_dp_init(dev, PCH_DP_D);
6415 intel_crt_init(dev);
6417 if (HAS_PCH_SPLIT(dev)) {
6420 if (I915_READ(HDMIB) & PORT_DETECTED) {
6421 /* PCH SDVOB multiplex with HDMIB */
6422 found = intel_sdvo_init(dev, PCH_SDVOB);
6424 intel_hdmi_init(dev, HDMIB);
6425 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6426 intel_dp_init(dev, PCH_DP_B);
6429 if (I915_READ(HDMIC) & PORT_DETECTED)
6430 intel_hdmi_init(dev, HDMIC);
6432 if (I915_READ(HDMID) & PORT_DETECTED)
6433 intel_hdmi_init(dev, HDMID);
6435 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6436 intel_dp_init(dev, PCH_DP_C);
6438 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6439 intel_dp_init(dev, PCH_DP_D);
6441 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6444 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6445 DRM_DEBUG_KMS("probing SDVOB\n");
6446 found = intel_sdvo_init(dev, SDVOB);
6447 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6448 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6449 intel_hdmi_init(dev, SDVOB);
6452 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6453 DRM_DEBUG_KMS("probing DP_B\n");
6454 intel_dp_init(dev, DP_B);
6458 /* Before G4X SDVOC doesn't have its own detect register */
6460 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6461 DRM_DEBUG_KMS("probing SDVOC\n");
6462 found = intel_sdvo_init(dev, SDVOC);
6465 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6467 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6468 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6469 intel_hdmi_init(dev, SDVOC);
6471 if (SUPPORTS_INTEGRATED_DP(dev)) {
6472 DRM_DEBUG_KMS("probing DP_C\n");
6473 intel_dp_init(dev, DP_C);
6477 if (SUPPORTS_INTEGRATED_DP(dev) &&
6478 (I915_READ(DP_D) & DP_DETECTED)) {
6479 DRM_DEBUG_KMS("probing DP_D\n");
6480 intel_dp_init(dev, DP_D);
6482 } else if (IS_GEN2(dev))
6483 intel_dvo_init(dev);
6485 if (SUPPORTS_TV(dev))
6488 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6489 encoder->base.possible_crtcs = encoder->crtc_mask;
6490 encoder->base.possible_clones =
6491 intel_encoder_clones(dev, encoder->clone_mask);
6494 intel_panel_setup_backlight(dev);
6497 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6499 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6501 drm_framebuffer_cleanup(fb);
6502 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6507 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6508 struct drm_file *file,
6509 unsigned int *handle)
6511 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6512 struct drm_i915_gem_object *obj = intel_fb->obj;
6514 return drm_gem_handle_create(file, &obj->base, handle);
6517 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6518 .destroy = intel_user_framebuffer_destroy,
6519 .create_handle = intel_user_framebuffer_create_handle,
6522 int intel_framebuffer_init(struct drm_device *dev,
6523 struct intel_framebuffer *intel_fb,
6524 struct drm_mode_fb_cmd *mode_cmd,
6525 struct drm_i915_gem_object *obj)
6529 if (obj->tiling_mode == I915_TILING_Y)
6532 if (mode_cmd->pitch & 63)
6535 switch (mode_cmd->bpp) {
6545 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6547 DRM_ERROR("framebuffer init failed %d\n", ret);
6551 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6552 intel_fb->obj = obj;
6556 static struct drm_framebuffer *
6557 intel_user_framebuffer_create(struct drm_device *dev,
6558 struct drm_file *filp,
6559 struct drm_mode_fb_cmd *mode_cmd)
6561 struct drm_i915_gem_object *obj;
6562 struct intel_framebuffer *intel_fb;
6565 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6566 if (&obj->base == NULL)
6567 return ERR_PTR(-ENOENT);
6569 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6571 return ERR_PTR(-ENOMEM);
6573 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6575 drm_gem_object_unreference_unlocked(&obj->base);
6577 return ERR_PTR(ret);
6580 return &intel_fb->base;
6583 static const struct drm_mode_config_funcs intel_mode_funcs = {
6584 .fb_create = intel_user_framebuffer_create,
6585 .output_poll_changed = intel_fb_output_poll_changed,
6588 static struct drm_i915_gem_object *
6589 intel_alloc_context_page(struct drm_device *dev)
6591 struct drm_i915_gem_object *ctx;
6594 ctx = i915_gem_alloc_object(dev, 4096);
6596 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6600 mutex_lock(&dev->struct_mutex);
6601 ret = i915_gem_object_pin(ctx, 4096, true);
6603 DRM_ERROR("failed to pin power context: %d\n", ret);
6607 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
6609 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6612 mutex_unlock(&dev->struct_mutex);
6617 i915_gem_object_unpin(ctx);
6619 drm_gem_object_unreference(&ctx->base);
6620 mutex_unlock(&dev->struct_mutex);
6624 bool ironlake_set_drps(struct drm_device *dev, u8 val)
6626 struct drm_i915_private *dev_priv = dev->dev_private;
6629 rgvswctl = I915_READ16(MEMSWCTL);
6630 if (rgvswctl & MEMCTL_CMD_STS) {
6631 DRM_DEBUG("gpu busy, RCS change rejected\n");
6632 return false; /* still busy with another command */
6635 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6636 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6637 I915_WRITE16(MEMSWCTL, rgvswctl);
6638 POSTING_READ16(MEMSWCTL);
6640 rgvswctl |= MEMCTL_CMD_STS;
6641 I915_WRITE16(MEMSWCTL, rgvswctl);
6646 void ironlake_enable_drps(struct drm_device *dev)
6648 struct drm_i915_private *dev_priv = dev->dev_private;
6649 u32 rgvmodectl = I915_READ(MEMMODECTL);
6650 u8 fmax, fmin, fstart, vstart;
6652 /* Enable temp reporting */
6653 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6654 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6656 /* 100ms RC evaluation intervals */
6657 I915_WRITE(RCUPEI, 100000);
6658 I915_WRITE(RCDNEI, 100000);
6660 /* Set max/min thresholds to 90ms and 80ms respectively */
6661 I915_WRITE(RCBMAXAVG, 90000);
6662 I915_WRITE(RCBMINAVG, 80000);
6664 I915_WRITE(MEMIHYST, 1);
6666 /* Set up min, max, and cur for interrupt handling */
6667 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6668 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6669 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6670 MEMMODE_FSTART_SHIFT;
6672 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6675 dev_priv->fmax = fmax; /* IPS callback will increase this */
6676 dev_priv->fstart = fstart;
6678 dev_priv->max_delay = fstart;
6679 dev_priv->min_delay = fmin;
6680 dev_priv->cur_delay = fstart;
6682 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6683 fmax, fmin, fstart);
6685 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6688 * Interrupts will be enabled in ironlake_irq_postinstall
6691 I915_WRITE(VIDSTART, vstart);
6692 POSTING_READ(VIDSTART);
6694 rgvmodectl |= MEMMODE_SWMODE_EN;
6695 I915_WRITE(MEMMODECTL, rgvmodectl);
6697 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6698 DRM_ERROR("stuck trying to change perf mode\n");
6701 ironlake_set_drps(dev, fstart);
6703 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6705 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6706 dev_priv->last_count2 = I915_READ(0x112f4);
6707 getrawmonotonic(&dev_priv->last_time2);
6710 void ironlake_disable_drps(struct drm_device *dev)
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713 u16 rgvswctl = I915_READ16(MEMSWCTL);
6715 /* Ack interrupts, disable EFC interrupt */
6716 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6717 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6718 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6719 I915_WRITE(DEIIR, DE_PCU_EVENT);
6720 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6722 /* Go back to the starting frequency */
6723 ironlake_set_drps(dev, dev_priv->fstart);
6725 rgvswctl |= MEMCTL_CMD_STS;
6726 I915_WRITE(MEMSWCTL, rgvswctl);
6731 void gen6_set_rps(struct drm_device *dev, u8 val)
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6736 swreq = (val & 0x3ff) << 25;
6737 I915_WRITE(GEN6_RPNSWREQ, swreq);
6740 void gen6_disable_rps(struct drm_device *dev)
6742 struct drm_i915_private *dev_priv = dev->dev_private;
6744 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6745 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6746 I915_WRITE(GEN6_PMIER, 0);
6747 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6750 static unsigned long intel_pxfreq(u32 vidfreq)
6753 int div = (vidfreq & 0x3f0000) >> 16;
6754 int post = (vidfreq & 0x3000) >> 12;
6755 int pre = (vidfreq & 0x7);
6760 freq = ((div * 133333) / ((1<<post) * pre));
6765 void intel_init_emon(struct drm_device *dev)
6767 struct drm_i915_private *dev_priv = dev->dev_private;
6772 /* Disable to program */
6776 /* Program energy weights for various events */
6777 I915_WRITE(SDEW, 0x15040d00);
6778 I915_WRITE(CSIEW0, 0x007f0000);
6779 I915_WRITE(CSIEW1, 0x1e220004);
6780 I915_WRITE(CSIEW2, 0x04000004);
6782 for (i = 0; i < 5; i++)
6783 I915_WRITE(PEW + (i * 4), 0);
6784 for (i = 0; i < 3; i++)
6785 I915_WRITE(DEW + (i * 4), 0);
6787 /* Program P-state weights to account for frequency power adjustment */
6788 for (i = 0; i < 16; i++) {
6789 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6790 unsigned long freq = intel_pxfreq(pxvidfreq);
6791 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6796 val *= (freq / 1000);
6798 val /= (127*127*900);
6800 DRM_ERROR("bad pxval: %ld\n", val);
6803 /* Render standby states get 0 weight */
6807 for (i = 0; i < 4; i++) {
6808 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6809 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6810 I915_WRITE(PXW + (i * 4), val);
6813 /* Adjust magic regs to magic values (more experimental results) */
6814 I915_WRITE(OGW0, 0);
6815 I915_WRITE(OGW1, 0);
6816 I915_WRITE(EG0, 0x00007f00);
6817 I915_WRITE(EG1, 0x0000000e);
6818 I915_WRITE(EG2, 0x000e0000);
6819 I915_WRITE(EG3, 0x68000300);
6820 I915_WRITE(EG4, 0x42000000);
6821 I915_WRITE(EG5, 0x00140031);
6825 for (i = 0; i < 8; i++)
6826 I915_WRITE(PXWL + (i * 4), 0);
6828 /* Enable PMON + select events */
6829 I915_WRITE(ECR, 0x80000019);
6831 lcfuse = I915_READ(LCFUSE02);
6833 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6836 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6838 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6839 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6841 int cur_freq, min_freq, max_freq;
6844 /* Here begins a magic sequence of register writes to enable
6845 * auto-downclocking.
6847 * Perhaps there might be some value in exposing these to
6850 I915_WRITE(GEN6_RC_STATE, 0);
6851 __gen6_gt_force_wake_get(dev_priv);
6853 /* disable the counters and set deterministic thresholds */
6854 I915_WRITE(GEN6_RC_CONTROL, 0);
6856 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6857 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6858 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6859 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6860 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6862 for (i = 0; i < I915_NUM_RINGS; i++)
6863 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6865 I915_WRITE(GEN6_RC_SLEEP, 0);
6866 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6867 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6868 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6869 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6871 I915_WRITE(GEN6_RC_CONTROL,
6872 GEN6_RC_CTL_RC6p_ENABLE |
6873 GEN6_RC_CTL_RC6_ENABLE |
6874 GEN6_RC_CTL_EI_MODE(1) |
6875 GEN6_RC_CTL_HW_ENABLE);
6877 I915_WRITE(GEN6_RPNSWREQ,
6878 GEN6_FREQUENCY(10) |
6880 GEN6_AGGRESSIVE_TURBO);
6881 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6882 GEN6_FREQUENCY(12));
6884 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6885 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6888 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6889 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
6890 I915_WRITE(GEN6_RP_UP_EI, 100000);
6891 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
6892 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6893 I915_WRITE(GEN6_RP_CONTROL,
6894 GEN6_RP_MEDIA_TURBO |
6895 GEN6_RP_USE_NORMAL_FREQ |
6896 GEN6_RP_MEDIA_IS_GFX |
6898 GEN6_RP_UP_BUSY_AVG |
6899 GEN6_RP_DOWN_IDLE_CONT);
6901 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6903 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6905 I915_WRITE(GEN6_PCODE_DATA, 0);
6906 I915_WRITE(GEN6_PCODE_MAILBOX,
6908 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6911 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6913 min_freq = (rp_state_cap & 0xff0000) >> 16;
6914 max_freq = rp_state_cap & 0xff;
6915 cur_freq = (gt_perf_status & 0xff00) >> 8;
6917 /* Check for overclock support */
6918 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6920 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6921 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6922 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6923 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6925 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6926 if (pcu_mbox & (1<<31)) { /* OC supported */
6927 max_freq = pcu_mbox & 0xff;
6928 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6931 /* In units of 100MHz */
6932 dev_priv->max_delay = max_freq;
6933 dev_priv->min_delay = min_freq;
6934 dev_priv->cur_delay = cur_freq;
6936 /* requires MSI enabled */
6937 I915_WRITE(GEN6_PMIER,
6938 GEN6_PM_MBOX_EVENT |
6939 GEN6_PM_THERMAL_EVENT |
6940 GEN6_PM_RP_DOWN_TIMEOUT |
6941 GEN6_PM_RP_UP_THRESHOLD |
6942 GEN6_PM_RP_DOWN_THRESHOLD |
6943 GEN6_PM_RP_UP_EI_EXPIRED |
6944 GEN6_PM_RP_DOWN_EI_EXPIRED);
6945 I915_WRITE(GEN6_PMIMR, 0);
6946 /* enable all PM interrupts */
6947 I915_WRITE(GEN6_PMINTRMSK, 0);
6949 __gen6_gt_force_wake_put(dev_priv);
6952 void intel_enable_clock_gating(struct drm_device *dev)
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6958 * Disable clock gating reported to work incorrectly according to the
6959 * specs, but enable as much else as we can.
6961 if (HAS_PCH_SPLIT(dev)) {
6962 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6965 /* Required for FBC */
6966 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6967 DPFCRUNIT_CLOCK_GATE_DISABLE |
6968 DPFDUNIT_CLOCK_GATE_DISABLE;
6969 /* Required for CxSR */
6970 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6972 I915_WRITE(PCH_3DCGDIS0,
6973 MARIUNIT_CLOCK_GATE_DISABLE |
6974 SVSMUNIT_CLOCK_GATE_DISABLE);
6975 I915_WRITE(PCH_3DCGDIS1,
6976 VFMUNIT_CLOCK_GATE_DISABLE);
6979 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6982 * On Ibex Peak and Cougar Point, we need to disable clock
6983 * gating for the panel power sequencer or it will fail to
6984 * start up when no ports are active.
6986 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6989 * According to the spec the following bits should be set in
6990 * order to enable memory self-refresh
6991 * The bit 22/21 of 0x42004
6992 * The bit 5 of 0x42020
6993 * The bit 15 of 0x45000
6996 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6997 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6998 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6999 I915_WRITE(ILK_DSPCLK_GATE,
7000 (I915_READ(ILK_DSPCLK_GATE) |
7001 ILK_DPARB_CLK_GATE));
7002 I915_WRITE(DISP_ARB_CTL,
7003 (I915_READ(DISP_ARB_CTL) |
7005 I915_WRITE(WM3_LP_ILK, 0);
7006 I915_WRITE(WM2_LP_ILK, 0);
7007 I915_WRITE(WM1_LP_ILK, 0);
7010 * Based on the document from hardware guys the following bits
7011 * should be set unconditionally in order to enable FBC.
7012 * The bit 22 of 0x42000
7013 * The bit 22 of 0x42004
7014 * The bit 7,8,9 of 0x42020.
7016 if (IS_IRONLAKE_M(dev)) {
7017 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7018 I915_READ(ILK_DISPLAY_CHICKEN1) |
7020 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7021 I915_READ(ILK_DISPLAY_CHICKEN2) |
7023 I915_WRITE(ILK_DSPCLK_GATE,
7024 I915_READ(ILK_DSPCLK_GATE) |
7030 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7031 I915_READ(ILK_DISPLAY_CHICKEN2) |
7032 ILK_ELPIN_409_SELECT);
7035 I915_WRITE(_3D_CHICKEN2,
7036 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7037 _3D_CHICKEN2_WM_READ_PIPELINED);
7041 I915_WRITE(WM3_LP_ILK, 0);
7042 I915_WRITE(WM2_LP_ILK, 0);
7043 I915_WRITE(WM1_LP_ILK, 0);
7046 * According to the spec the following bits should be
7047 * set in order to enable memory self-refresh and fbc:
7048 * The bit21 and bit22 of 0x42000
7049 * The bit21 and bit22 of 0x42004
7050 * The bit5 and bit7 of 0x42020
7051 * The bit14 of 0x70180
7052 * The bit14 of 0x71180
7054 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7055 I915_READ(ILK_DISPLAY_CHICKEN1) |
7056 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7057 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7058 I915_READ(ILK_DISPLAY_CHICKEN2) |
7059 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7060 I915_WRITE(ILK_DSPCLK_GATE,
7061 I915_READ(ILK_DSPCLK_GATE) |
7062 ILK_DPARB_CLK_GATE |
7066 I915_WRITE(DSPCNTR(pipe),
7067 I915_READ(DSPCNTR(pipe)) |
7068 DISPPLANE_TRICKLE_FEED_DISABLE);
7070 } else if (IS_G4X(dev)) {
7071 uint32_t dspclk_gate;
7072 I915_WRITE(RENCLK_GATE_D1, 0);
7073 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7074 GS_UNIT_CLOCK_GATE_DISABLE |
7075 CL_UNIT_CLOCK_GATE_DISABLE);
7076 I915_WRITE(RAMCLK_GATE_D, 0);
7077 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7078 OVRUNIT_CLOCK_GATE_DISABLE |
7079 OVCUNIT_CLOCK_GATE_DISABLE;
7081 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7082 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7083 } else if (IS_CRESTLINE(dev)) {
7084 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7085 I915_WRITE(RENCLK_GATE_D2, 0);
7086 I915_WRITE(DSPCLK_GATE_D, 0);
7087 I915_WRITE(RAMCLK_GATE_D, 0);
7088 I915_WRITE16(DEUC, 0);
7089 } else if (IS_BROADWATER(dev)) {
7090 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7091 I965_RCC_CLOCK_GATE_DISABLE |
7092 I965_RCPB_CLOCK_GATE_DISABLE |
7093 I965_ISC_CLOCK_GATE_DISABLE |
7094 I965_FBC_CLOCK_GATE_DISABLE);
7095 I915_WRITE(RENCLK_GATE_D2, 0);
7096 } else if (IS_GEN3(dev)) {
7097 u32 dstate = I915_READ(D_STATE);
7099 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7100 DSTATE_DOT_CLOCK_GATING;
7101 I915_WRITE(D_STATE, dstate);
7102 } else if (IS_I85X(dev) || IS_I865G(dev)) {
7103 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7104 } else if (IS_I830(dev)) {
7105 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7109 static void ironlake_teardown_rc6(struct drm_device *dev)
7111 struct drm_i915_private *dev_priv = dev->dev_private;
7113 if (dev_priv->renderctx) {
7114 i915_gem_object_unpin(dev_priv->renderctx);
7115 drm_gem_object_unreference(&dev_priv->renderctx->base);
7116 dev_priv->renderctx = NULL;
7119 if (dev_priv->pwrctx) {
7120 i915_gem_object_unpin(dev_priv->pwrctx);
7121 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7122 dev_priv->pwrctx = NULL;
7126 static void ironlake_disable_rc6(struct drm_device *dev)
7128 struct drm_i915_private *dev_priv = dev->dev_private;
7130 if (I915_READ(PWRCTXA)) {
7131 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7132 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7133 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7136 I915_WRITE(PWRCTXA, 0);
7137 POSTING_READ(PWRCTXA);
7139 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7140 POSTING_READ(RSTDBYCTL);
7143 ironlake_teardown_rc6(dev);
7146 static int ironlake_setup_rc6(struct drm_device *dev)
7148 struct drm_i915_private *dev_priv = dev->dev_private;
7150 if (dev_priv->renderctx == NULL)
7151 dev_priv->renderctx = intel_alloc_context_page(dev);
7152 if (!dev_priv->renderctx)
7155 if (dev_priv->pwrctx == NULL)
7156 dev_priv->pwrctx = intel_alloc_context_page(dev);
7157 if (!dev_priv->pwrctx) {
7158 ironlake_teardown_rc6(dev);
7165 void ironlake_enable_rc6(struct drm_device *dev)
7167 struct drm_i915_private *dev_priv = dev->dev_private;
7170 /* rc6 disabled by default due to repeated reports of hanging during
7173 if (!i915_enable_rc6)
7176 ret = ironlake_setup_rc6(dev);
7181 * GPU can automatically power down the render unit if given a page
7184 ret = BEGIN_LP_RING(6);
7186 ironlake_teardown_rc6(dev);
7190 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7191 OUT_RING(MI_SET_CONTEXT);
7192 OUT_RING(dev_priv->renderctx->gtt_offset |
7194 MI_SAVE_EXT_STATE_EN |
7195 MI_RESTORE_EXT_STATE_EN |
7196 MI_RESTORE_INHIBIT);
7197 OUT_RING(MI_SUSPEND_FLUSH);
7202 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7203 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7207 /* Set up chip specific display functions */
7208 static void intel_init_display(struct drm_device *dev)
7210 struct drm_i915_private *dev_priv = dev->dev_private;
7212 /* We always want a DPMS function */
7213 if (HAS_PCH_SPLIT(dev))
7214 dev_priv->display.dpms = ironlake_crtc_dpms;
7216 dev_priv->display.dpms = i9xx_crtc_dpms;
7218 if (I915_HAS_FBC(dev)) {
7219 if (HAS_PCH_SPLIT(dev)) {
7220 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7221 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7222 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7223 } else if (IS_GM45(dev)) {
7224 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7225 dev_priv->display.enable_fbc = g4x_enable_fbc;
7226 dev_priv->display.disable_fbc = g4x_disable_fbc;
7227 } else if (IS_CRESTLINE(dev)) {
7228 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7229 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7230 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7232 /* 855GM needs testing */
7235 /* Returns the core display clock speed */
7236 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7237 dev_priv->display.get_display_clock_speed =
7238 i945_get_display_clock_speed;
7239 else if (IS_I915G(dev))
7240 dev_priv->display.get_display_clock_speed =
7241 i915_get_display_clock_speed;
7242 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7243 dev_priv->display.get_display_clock_speed =
7244 i9xx_misc_get_display_clock_speed;
7245 else if (IS_I915GM(dev))
7246 dev_priv->display.get_display_clock_speed =
7247 i915gm_get_display_clock_speed;
7248 else if (IS_I865G(dev))
7249 dev_priv->display.get_display_clock_speed =
7250 i865_get_display_clock_speed;
7251 else if (IS_I85X(dev))
7252 dev_priv->display.get_display_clock_speed =
7253 i855_get_display_clock_speed;
7255 dev_priv->display.get_display_clock_speed =
7256 i830_get_display_clock_speed;
7258 /* For FIFO watermark updates */
7259 if (HAS_PCH_SPLIT(dev)) {
7261 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7262 dev_priv->display.update_wm = ironlake_update_wm;
7264 DRM_DEBUG_KMS("Failed to get proper latency. "
7266 dev_priv->display.update_wm = NULL;
7268 } else if (IS_GEN6(dev)) {
7269 if (SNB_READ_WM0_LATENCY()) {
7270 dev_priv->display.update_wm = sandybridge_update_wm;
7272 DRM_DEBUG_KMS("Failed to read display plane latency. "
7274 dev_priv->display.update_wm = NULL;
7277 dev_priv->display.update_wm = NULL;
7278 } else if (IS_PINEVIEW(dev)) {
7279 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7282 dev_priv->mem_freq)) {
7283 DRM_INFO("failed to find known CxSR latency "
7284 "(found ddr%s fsb freq %d, mem freq %d), "
7286 (dev_priv->is_ddr3 == 1) ? "3": "2",
7287 dev_priv->fsb_freq, dev_priv->mem_freq);
7288 /* Disable CxSR and never update its watermark again */
7289 pineview_disable_cxsr(dev);
7290 dev_priv->display.update_wm = NULL;
7292 dev_priv->display.update_wm = pineview_update_wm;
7293 } else if (IS_G4X(dev))
7294 dev_priv->display.update_wm = g4x_update_wm;
7295 else if (IS_GEN4(dev))
7296 dev_priv->display.update_wm = i965_update_wm;
7297 else if (IS_GEN3(dev)) {
7298 dev_priv->display.update_wm = i9xx_update_wm;
7299 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7300 } else if (IS_I85X(dev)) {
7301 dev_priv->display.update_wm = i9xx_update_wm;
7302 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7304 dev_priv->display.update_wm = i830_update_wm;
7306 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7308 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7313 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7314 * resume, or other times. This quirk makes sure that's the case for
7317 static void quirk_pipea_force (struct drm_device *dev)
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7321 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7322 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7325 struct intel_quirk {
7327 int subsystem_vendor;
7328 int subsystem_device;
7329 void (*hook)(struct drm_device *dev);
7332 struct intel_quirk intel_quirks[] = {
7333 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7334 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7335 /* HP Mini needs pipe A force quirk (LP: #322104) */
7336 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7338 /* Thinkpad R31 needs pipe A force quirk */
7339 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7340 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7341 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7343 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7344 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7345 /* ThinkPad X40 needs pipe A force quirk */
7347 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7348 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7350 /* 855 & before need to leave pipe A & dpll A up */
7351 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7352 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7355 static void intel_init_quirks(struct drm_device *dev)
7357 struct pci_dev *d = dev->pdev;
7360 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7361 struct intel_quirk *q = &intel_quirks[i];
7363 if (d->device == q->device &&
7364 (d->subsystem_vendor == q->subsystem_vendor ||
7365 q->subsystem_vendor == PCI_ANY_ID) &&
7366 (d->subsystem_device == q->subsystem_device ||
7367 q->subsystem_device == PCI_ANY_ID))
7372 /* Disable the VGA plane that we never use */
7373 static void i915_disable_vga(struct drm_device *dev)
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7379 if (HAS_PCH_SPLIT(dev))
7380 vga_reg = CPU_VGACNTRL;
7384 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7385 outb(1, VGA_SR_INDEX);
7386 sr1 = inb(VGA_SR_DATA);
7387 outb(sr1 | 1<<5, VGA_SR_DATA);
7388 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7391 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7392 POSTING_READ(vga_reg);
7395 void intel_modeset_init(struct drm_device *dev)
7397 struct drm_i915_private *dev_priv = dev->dev_private;
7400 drm_mode_config_init(dev);
7402 dev->mode_config.min_width = 0;
7403 dev->mode_config.min_height = 0;
7405 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7407 intel_init_quirks(dev);
7409 intel_init_display(dev);
7412 dev->mode_config.max_width = 2048;
7413 dev->mode_config.max_height = 2048;
7414 } else if (IS_GEN3(dev)) {
7415 dev->mode_config.max_width = 4096;
7416 dev->mode_config.max_height = 4096;
7418 dev->mode_config.max_width = 8192;
7419 dev->mode_config.max_height = 8192;
7421 dev->mode_config.fb_base = dev->agp->base;
7423 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7424 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7426 for (i = 0; i < dev_priv->num_pipe; i++) {
7427 intel_crtc_init(dev, i);
7430 intel_setup_outputs(dev);
7432 intel_enable_clock_gating(dev);
7434 /* Just disable it once at startup */
7435 i915_disable_vga(dev);
7437 if (IS_IRONLAKE_M(dev)) {
7438 ironlake_enable_drps(dev);
7439 intel_init_emon(dev);
7443 gen6_enable_rps(dev_priv);
7445 if (IS_IRONLAKE_M(dev))
7446 ironlake_enable_rc6(dev);
7448 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7449 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7450 (unsigned long)dev);
7452 intel_setup_overlay(dev);
7455 void intel_modeset_cleanup(struct drm_device *dev)
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458 struct drm_crtc *crtc;
7459 struct intel_crtc *intel_crtc;
7461 drm_kms_helper_poll_fini(dev);
7462 mutex_lock(&dev->struct_mutex);
7464 intel_unregister_dsm_handler();
7467 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7468 /* Skip inactive CRTCs */
7472 intel_crtc = to_intel_crtc(crtc);
7473 intel_increase_pllclock(crtc);
7476 if (dev_priv->display.disable_fbc)
7477 dev_priv->display.disable_fbc(dev);
7479 if (IS_IRONLAKE_M(dev))
7480 ironlake_disable_drps(dev);
7482 gen6_disable_rps(dev);
7484 if (IS_IRONLAKE_M(dev))
7485 ironlake_disable_rc6(dev);
7487 mutex_unlock(&dev->struct_mutex);
7489 /* Disable the irq before mode object teardown, for the irq might
7490 * enqueue unpin/hotplug work. */
7491 drm_irq_uninstall(dev);
7492 cancel_work_sync(&dev_priv->hotplug_work);
7494 /* Shut off idle work before the crtcs get freed. */
7495 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7496 intel_crtc = to_intel_crtc(crtc);
7497 del_timer_sync(&intel_crtc->idle_timer);
7499 del_timer_sync(&dev_priv->idle_timer);
7500 cancel_work_sync(&dev_priv->idle_work);
7502 drm_mode_config_cleanup(dev);
7506 * Return which encoder is currently attached for connector.
7508 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7510 return &intel_attached_encoder(connector)->base;
7513 void intel_connector_attach_encoder(struct intel_connector *connector,
7514 struct intel_encoder *encoder)
7516 connector->encoder = encoder;
7517 drm_mode_connector_attach_encoder(&connector->base,
7522 * set vga decode state - true == enable VGA decode
7524 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7529 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7531 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7533 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7534 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7538 #ifdef CONFIG_DEBUG_FS
7539 #include <linux/seq_file.h>
7541 struct intel_display_error_state {
7542 struct intel_cursor_error_state {
7549 struct intel_pipe_error_state {
7561 struct intel_plane_error_state {
7572 struct intel_display_error_state *
7573 intel_display_capture_error_state(struct drm_device *dev)
7575 drm_i915_private_t *dev_priv = dev->dev_private;
7576 struct intel_display_error_state *error;
7579 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7583 for (i = 0; i < 2; i++) {
7584 error->cursor[i].control = I915_READ(CURCNTR(i));
7585 error->cursor[i].position = I915_READ(CURPOS(i));
7586 error->cursor[i].base = I915_READ(CURBASE(i));
7588 error->plane[i].control = I915_READ(DSPCNTR(i));
7589 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7590 error->plane[i].size = I915_READ(DSPSIZE(i));
7591 error->plane[i].pos= I915_READ(DSPPOS(i));
7592 error->plane[i].addr = I915_READ(DSPADDR(i));
7593 if (INTEL_INFO(dev)->gen >= 4) {
7594 error->plane[i].surface = I915_READ(DSPSURF(i));
7595 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7598 error->pipe[i].conf = I915_READ(PIPECONF(i));
7599 error->pipe[i].source = I915_READ(PIPESRC(i));
7600 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7601 error->pipe[i].hblank = I915_READ(HBLANK(i));
7602 error->pipe[i].hsync = I915_READ(HSYNC(i));
7603 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7604 error->pipe[i].vblank = I915_READ(VBLANK(i));
7605 error->pipe[i].vsync = I915_READ(VSYNC(i));
7612 intel_display_print_error_state(struct seq_file *m,
7613 struct drm_device *dev,
7614 struct intel_display_error_state *error)
7618 for (i = 0; i < 2; i++) {
7619 seq_printf(m, "Pipe [%d]:\n", i);
7620 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7621 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7622 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7623 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7624 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7625 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7626 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7627 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7629 seq_printf(m, "Plane [%d]:\n", i);
7630 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7631 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7632 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7633 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7634 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7635 if (INTEL_INFO(dev)->gen >= 4) {
7636 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7637 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7640 seq_printf(m, "Cursor [%d]:\n", i);
7641 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7642 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7643 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);