drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  46 #define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp)
  47
  48 struct intel_dp_priv {
  49         uint32_t output_reg;
  50         uint32_t DP;
  51         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  52         bool has_audio;
  53         int dpms_mode;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[4];
  57         struct intel_encoder *intel_encoder;
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61 };
  62
  63 static void
  64 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  65                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  66
  67 static void
  68 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  69
  70 void
  71 intel_edp_link_config (struct intel_encoder *intel_encoder,
  72                 int *lane_num, int *link_bw)
  73 {
  74         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  75
  76         *lane_num = dp_priv->lane_count;
  77         if (dp_priv->link_bw == DP_LINK_BW_1_62)
  78                 *link_bw = 162000;
  79         else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  80                 *link_bw = 270000;
  81 }
  82
  83 static int
  84 intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  85 {
  86         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
  87         int max_lane_count = 4;
  88
  89         if (dp_priv->dpcd[0] >= 0x11) {
  90                 max_lane_count = dp_priv->dpcd[2] & 0x1f;
  91                 switch (max_lane_count) {
  92                 case 1: case 2: case 4:
  93                         break;
  94                 default:
  95                         max_lane_count = 4;
  96                 }
  97         }
  98         return max_lane_count;
  99 }
 100
 101 static int
 102 intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
 103 {
 104         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 105         int max_link_bw = dp_priv->dpcd[1];
 106
 107         switch (max_link_bw) {
 108         case DP_LINK_BW_1_62:
 109         case DP_LINK_BW_2_7:
 110                 break;
 111         default:
 112                 max_link_bw = DP_LINK_BW_1_62;
 113                 break;
 114         }
 115         return max_link_bw;
 116 }
 117
 118 static int
 119 intel_dp_link_clock(uint8_t link_bw)
 120 {
 121         if (link_bw == DP_LINK_BW_2_7)
 122                 return 270000;
 123         else
 124                 return 162000;
 125 }
 126
 127 /* I think this is a fiction */
 128 static int
 129 intel_dp_link_required(struct drm_device *dev,
 130                        struct intel_encoder *intel_encoder, int pixel_clock)
 131 {
 132         struct drm_i915_private *dev_priv = dev->dev_private;
 133         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 134
 135         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
 136                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 137         else
 138                 return pixel_clock * 3;
 139 }
 140
 141 static int
 142 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 143 {
 144         return (max_link_clock * max_lanes * 8) / 10;
 145 }
 146
 147 static int
 148 intel_dp_mode_valid(struct drm_connector *connector,
 149                     struct drm_display_mode *mode)
 150 {
 151         struct drm_encoder *encoder = intel_attached_encoder(connector);
 152         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 153         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
 154         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 155
 156         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 157            which are outside spec tolerances but somehow work by magic */
 158         if (!IS_eDP(intel_encoder) &&
 159             (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
 160              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 161                 return MODE_CLOCK_HIGH;
 162
 163         if (mode->clock < 10000)
 164                 return MODE_CLOCK_LOW;
 165
 166         return MODE_OK;
 167 }
 168
 169 static uint32_t
 170 pack_aux(uint8_t *src, int src_bytes)
 171 {
 172         int     i;
 173         uint32_t v = 0;
 174
 175         if (src_bytes > 4)
 176                 src_bytes = 4;
 177         for (i = 0; i < src_bytes; i++)
 178                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 179         return v;
 180 }
 181
 182 static void
 183 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 184 {
 185         int i;
 186         if (dst_bytes > 4)
 187                 dst_bytes = 4;
 188         for (i = 0; i < dst_bytes; i++)
 189                 dst[i] = src >> ((3-i) * 8);
 190 }
 191
 192 /* hrawclock is 1/4 the FSB frequency */
 193 static int
 194 intel_hrawclk(struct drm_device *dev)
 195 {
 196         struct drm_i915_private *dev_priv = dev->dev_private;
 197         uint32_t clkcfg;
 198
 199         clkcfg = I915_READ(CLKCFG);
 200         switch (clkcfg & CLKCFG_FSB_MASK) {
 201         case CLKCFG_FSB_400:
 202                 return 100;
 203         case CLKCFG_FSB_533:
 204                 return 133;
 205         case CLKCFG_FSB_667:
 206                 return 166;
 207         case CLKCFG_FSB_800:
 208                 return 200;
 209         case CLKCFG_FSB_1067:
 210                 return 266;
 211         case CLKCFG_FSB_1333:
 212                 return 333;
 213         /* these two are just a guess; one of them might be right */
 214         case CLKCFG_FSB_1600:
 215         case CLKCFG_FSB_1600_ALT:
 216                 return 400;
 217         default:
 218                 return 133;
 219         }
 220 }
 221
 222 static int
 223 intel_dp_aux_ch(struct intel_encoder *intel_encoder,
 224                 uint8_t *send, int send_bytes,
 225                 uint8_t *recv, int recv_size)
 226 {
 227         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 228         uint32_t output_reg = dp_priv->output_reg;
 229         struct drm_device *dev = intel_encoder->enc.dev;
 230         struct drm_i915_private *dev_priv = dev->dev_private;
 231         uint32_t ch_ctl = output_reg + 0x10;
 232         uint32_t ch_data = ch_ctl + 4;
 233         int i;
 234         int recv_bytes;
 235         uint32_t ctl;
 236         uint32_t status;
 237         uint32_t aux_clock_divider;
 238         int try, precharge;
 239
 240         /* The clock divider is based off the hrawclk,
 241          * and would like to run at 2MHz. So, take the
 242          * hrawclk value and divide by 2 and use that
 243          */
 244         if (IS_eDP(intel_encoder)) {
 245                 if (IS_GEN6(dev))
 246                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 247                 else
 248                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 249         } else if (HAS_PCH_SPLIT(dev))
 250                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 251         else
 252                 aux_clock_divider = intel_hrawclk(dev) / 2;
 253
 254         if (IS_GEN6(dev))
 255                 precharge = 3;
 256         else
 257                 precharge = 5;
 258
 259         /* Must try at least 3 times according to DP spec */
 260         for (try = 0; try < 5; try++) {
 261                 /* Load the send data into the aux channel data registers */
 262                 for (i = 0; i < send_bytes; i += 4) {
 263                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 264
 265                         I915_WRITE(ch_data + i, d);
 266                 }
 267
 268                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 269                        DP_AUX_CH_CTL_TIME_OUT_400us |
 270                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 271                        (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 272                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 273                        DP_AUX_CH_CTL_DONE |
 274                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 275                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 276
 277                 /* Send the command and wait for it to complete */
 278                 I915_WRITE(ch_ctl, ctl);
 279                 (void) I915_READ(ch_ctl);
 280                 for (;;) {
 281                         udelay(100);
 282                         status = I915_READ(ch_ctl);
 283                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 284                                 break;
 285                 }
 286
 287                 /* Clear done status and any errors */
 288                 I915_WRITE(ch_ctl, (status |
 289                                 DP_AUX_CH_CTL_DONE |
 290                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 291                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 292                 (void) I915_READ(ch_ctl);
 293                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 294                         break;
 295         }
 296
 297         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 298                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 299                 return -EBUSY;
 300         }
 301
 302         /* Check for timeout or receive error.
 303          * Timeouts occur when the sink is not connected
 304          */
 305         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 306                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 307                 return -EIO;
 308         }
 309
 310         /* Timeouts occur when the device isn't connected, so they're
 311          * "normal" -- don't fill the kernel log with these */
 312         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 313                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 314                 return -ETIMEDOUT;
 315         }
 316
 317         /* Unload any bytes sent back from the other side */
 318         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 319                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 320
 321         if (recv_bytes > recv_size)
 322                 recv_bytes = recv_size;
 323
 324         for (i = 0; i < recv_bytes; i += 4) {
 325                 uint32_t    d = I915_READ(ch_data + i);
 326
 327                 unpack_aux(d, recv + i, recv_bytes - i);
 328         }
 329
 330         return recv_bytes;
 331 }
 332
 333 /* Write data to the aux channel in native mode */
 334 static int
 335 intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
 336                           uint16_t address, uint8_t *send, int send_bytes)
 337 {
 338         int ret;
 339         uint8_t msg[20];
 340         int msg_bytes;
 341         uint8_t ack;
 342
 343         if (send_bytes > 16)
 344                 return -1;
 345         msg[0] = AUX_NATIVE_WRITE << 4;
 346         msg[1] = address >> 8;
 347         msg[2] = address & 0xff;
 348         msg[3] = send_bytes - 1;
 349         memcpy(&msg[4], send, send_bytes);
 350         msg_bytes = send_bytes + 4;
 351         for (;;) {
 352                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
 353                 if (ret < 0)
 354                         return ret;
 355                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 356                         break;
 357                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 358                         udelay(100);
 359                 else
 360                         return -EIO;
 361         }
 362         return send_bytes;
 363 }
 364
 365 /* Write a single byte to the aux channel in native mode */
 366 static int
 367 intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
 368                             uint16_t address, uint8_t byte)
 369 {
 370         return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
 371 }
 372
 373 /* read bytes from a native aux channel */
 374 static int
 375 intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
 376                          uint16_t address, uint8_t *recv, int recv_bytes)
 377 {
 378         uint8_t msg[4];
 379         int msg_bytes;
 380         uint8_t reply[20];
 381         int reply_bytes;
 382         uint8_t ack;
 383         int ret;
 384
 385         msg[0] = AUX_NATIVE_READ << 4;
 386         msg[1] = address >> 8;
 387         msg[2] = address & 0xff;
 388         msg[3] = recv_bytes - 1;
 389
 390         msg_bytes = 4;
 391         reply_bytes = recv_bytes + 1;
 392
 393         for (;;) {
 394                 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
 395                                       reply, reply_bytes);
 396                 if (ret == 0)
 397                         return -EPROTO;
 398                 if (ret < 0)
 399                         return ret;
 400                 ack = reply[0];
 401                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 402                         memcpy(recv, reply + 1, ret - 1);
 403                         return ret - 1;
 404                 }
 405                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 406                         udelay(100);
 407                 else
 408                         return -EIO;
 409         }
 410 }
 411
 412 static int
 413 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 414                     uint8_t write_byte, uint8_t *read_byte)
 415 {
 416         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 417         struct intel_dp_priv *dp_priv = container_of(adapter,
 418                                                      struct intel_dp_priv,
 419                                                      adapter);
 420         struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
 421         uint16_t address = algo_data->address;
 422         uint8_t msg[5];
 423         uint8_t reply[2];
 424         int msg_bytes;
 425         int reply_bytes;
 426         int ret;
 427
 428         /* Set up the command byte */
 429         if (mode & MODE_I2C_READ)
 430                 msg[0] = AUX_I2C_READ << 4;
 431         else
 432                 msg[0] = AUX_I2C_WRITE << 4;
 433
 434         if (!(mode & MODE_I2C_STOP))
 435                 msg[0] |= AUX_I2C_MOT << 4;
 436
 437         msg[1] = address >> 8;
 438         msg[2] = address;
 439
 440         switch (mode) {
 441         case MODE_I2C_WRITE:
 442                 msg[3] = 0;
 443                 msg[4] = write_byte;
 444                 msg_bytes = 5;
 445                 reply_bytes = 1;
 446                 break;
 447         case MODE_I2C_READ:
 448                 msg[3] = 0;
 449                 msg_bytes = 4;
 450                 reply_bytes = 2;
 451                 break;
 452         default:
 453                 msg_bytes = 3;
 454                 reply_bytes = 1;
 455                 break;
 456         }
 457
 458         for (;;) {
 459           ret = intel_dp_aux_ch(intel_encoder,
 460                                 msg, msg_bytes,
 461                                 reply, reply_bytes);
 462                 if (ret < 0) {
 463                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 464                         return ret;
 465                 }
 466                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 467                 case AUX_I2C_REPLY_ACK:
 468                         if (mode == MODE_I2C_READ) {
 469                                 *read_byte = reply[1];
 470                         }
 471                         return reply_bytes - 1;
 472                 case AUX_I2C_REPLY_NACK:
 473                         DRM_DEBUG_KMS("aux_ch nack\n");
 474                         return -EREMOTEIO;
 475                 case AUX_I2C_REPLY_DEFER:
 476                         DRM_DEBUG_KMS("aux_ch defer\n");
 477                         udelay(100);
 478                         break;
 479                 default:
 480                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 481                         return -EREMOTEIO;
 482                 }
 483         }
 484 }
 485
 486 static int
 487 intel_dp_i2c_init(struct intel_encoder *intel_encoder,
 488                   struct intel_connector *intel_connector, const char *name)
 489 {
 490         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 491
 492         DRM_DEBUG_KMS("i2c_init %s\n", name);
 493         dp_priv->algo.running = false;
 494         dp_priv->algo.address = 0;
 495         dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
 496
 497         memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
 498         dp_priv->adapter.owner = THIS_MODULE;
 499         dp_priv->adapter.class = I2C_CLASS_DDC;
 500         strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
 501         dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
 502         dp_priv->adapter.algo_data = &dp_priv->algo;
 503         dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
 504
 505         return i2c_dp_aux_add_bus(&dp_priv->adapter);
 506 }
 507
 508 static bool
 509 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 510                     struct drm_display_mode *adjusted_mode)
 511 {
 512         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 513         struct intel_dp_priv   *dp_priv = intel_encoder->dev_priv;
 514         int lane_count, clock;
 515         int max_lane_count = intel_dp_max_lane_count(intel_encoder);
 516         int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 517         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 518
 519         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 520                 for (clock = 0; clock <= max_clock; clock++) {
 521                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 522
 523                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
 524                                         <= link_avail) {
 525                                 dp_priv->link_bw = bws[clock];
 526                                 dp_priv->lane_count = lane_count;
 527                                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 528                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 529                                                 "count %d clock %d\n",
 530                                        dp_priv->link_bw, dp_priv->lane_count,
 531                                        adjusted_mode->clock);
 532                                 return true;
 533                         }
 534                 }
 535         }
 536
 537         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
 538                 /* okay we failed just pick the highest */
 539                 dp_priv->lane_count = max_lane_count;
 540                 dp_priv->link_bw = bws[max_clock];
 541                 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
 542                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 543                               "count %d clock %d\n",
 544                               dp_priv->link_bw, dp_priv->lane_count,
 545                               adjusted_mode->clock);
 546                 return true;
 547         }
 548         return false;
 549 }
 550
 551 struct intel_dp_m_n {
 552         uint32_t        tu;
 553         uint32_t        gmch_m;
 554         uint32_t        gmch_n;
 555         uint32_t        link_m;
 556         uint32_t        link_n;
 557 };
 558
 559 static void
 560 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 561 {
 562         while (*num > 0xffffff || *den > 0xffffff) {
 563                 *num >>= 1;
 564                 *den >>= 1;
 565         }
 566 }
 567
 568 static void
 569 intel_dp_compute_m_n(int bpp,
 570                      int nlanes,
 571                      int pixel_clock,
 572                      int link_clock,
 573                      struct intel_dp_m_n *m_n)
 574 {
 575         m_n->tu = 64;
 576         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 577         m_n->gmch_n = link_clock * nlanes;
 578         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 579         m_n->link_m = pixel_clock;
 580         m_n->link_n = link_clock;
 581         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 582 }
 583
 584 bool intel_pch_has_edp(struct drm_crtc *crtc)
 585 {
 586         struct drm_device *dev = crtc->dev;
 587         struct drm_mode_config *mode_config = &dev->mode_config;
 588         struct drm_encoder *encoder;
 589
 590         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 591                 struct intel_encoder *intel_encoder;
 592                 struct intel_dp_priv *dp_priv;
 593
 594                 if (!encoder || encoder->crtc != crtc)
 595                         continue;
 596
 597                 intel_encoder = enc_to_intel_encoder(encoder);
 598                 dp_priv = intel_encoder->dev_priv;
 599
 600                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT)
 601                         return dp_priv->is_pch_edp;
 602         }
 603         return false;
 604 }
 605
 606 void
 607 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 608                  struct drm_display_mode *adjusted_mode)
 609 {
 610         struct drm_device *dev = crtc->dev;
 611         struct drm_mode_config *mode_config = &dev->mode_config;
 612         struct drm_encoder *encoder;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 615         int lane_count = 4, bpp = 24;
 616         struct intel_dp_m_n m_n;
 617
 618         /*
 619          * Find the lane count in the intel_encoder private
 620          */
 621         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 622                 struct intel_encoder *intel_encoder;
 623                 struct intel_dp_priv *dp_priv;
 624
 625                 if (encoder->crtc != crtc)
 626                         continue;
 627
 628                 intel_encoder = enc_to_intel_encoder(encoder);
 629                 dp_priv = intel_encoder->dev_priv;
 630
 631                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 632                         lane_count = dp_priv->lane_count;
 633                         if (IS_PCH_eDP(dp_priv))
 634                                 bpp = dev_priv->edp_bpp;
 635                         break;
 636                 }
 637         }
 638
 639         /*
 640          * Compute the GMCH and Link ratios. The '3' here is
 641          * the number of bytes_per_pixel post-LUT, which we always
 642          * set up for 8-bits of R/G/B, or 3 bytes total.
 643          */
 644         intel_dp_compute_m_n(bpp, lane_count,
 645                              mode->clock, adjusted_mode->clock, &m_n);
 646
 647         if (HAS_PCH_SPLIT(dev)) {
 648                 if (intel_crtc->pipe == 0) {
 649                         I915_WRITE(TRANSA_DATA_M1,
 650                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 651                                    m_n.gmch_m);
 652                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 653                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 654                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 655                 } else {
 656                         I915_WRITE(TRANSB_DATA_M1,
 657                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 658                                    m_n.gmch_m);
 659                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 660                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 661                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 662                 }
 663         } else {
 664                 if (intel_crtc->pipe == 0) {
 665                         I915_WRITE(PIPEA_GMCH_DATA_M,
 666                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 667                                    m_n.gmch_m);
 668                         I915_WRITE(PIPEA_GMCH_DATA_N,
 669                                    m_n.gmch_n);
 670                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 671                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 672                 } else {
 673                         I915_WRITE(PIPEB_GMCH_DATA_M,
 674                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 675                                    m_n.gmch_m);
 676                         I915_WRITE(PIPEB_GMCH_DATA_N,
 677                                         m_n.gmch_n);
 678                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 679                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 680                 }
 681         }
 682 }
 683
 684 static void
 685 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 686                   struct drm_display_mode *adjusted_mode)
 687 {
 688         struct drm_device *dev = encoder->dev;
 689         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 690         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 691         struct drm_crtc *crtc = intel_encoder->enc.crtc;
 692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 693
 694         dp_priv->DP = (DP_VOLTAGE_0_4 |
 695                        DP_PRE_EMPHASIS_0);
 696
 697         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 698                 dp_priv->DP |= DP_SYNC_HS_HIGH;
 699         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 700                 dp_priv->DP |= DP_SYNC_VS_HIGH;
 701
 702         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
 703                 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
 704         else
 705                 dp_priv->DP |= DP_LINK_TRAIN_OFF;
 706
 707         switch (dp_priv->lane_count) {
 708         case 1:
 709                 dp_priv->DP |= DP_PORT_WIDTH_1;
 710                 break;
 711         case 2:
 712                 dp_priv->DP |= DP_PORT_WIDTH_2;
 713                 break;
 714         case 4:
 715                 dp_priv->DP |= DP_PORT_WIDTH_4;
 716                 break;
 717         }
 718         if (dp_priv->has_audio)
 719                 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
 720
 721         memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 722         dp_priv->link_configuration[0] = dp_priv->link_bw;
 723         dp_priv->link_configuration[1] = dp_priv->lane_count;
 724
 725         /*
 726          * Check for DPCD version > 1.1 and enhanced framing support
 727          */
 728         if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 729                 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 730                 dp_priv->DP |= DP_ENHANCED_FRAMING;
 731         }
 732
 733         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 734         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 735                 dp_priv->DP |= DP_PIPEB_SELECT;
 736
 737         if (IS_eDP(intel_encoder)) {
 738                 /* don't miss out required setting for eDP */
 739                 dp_priv->DP |= DP_PLL_ENABLE;
 740                 if (adjusted_mode->clock < 200000)
 741                         dp_priv->DP |= DP_PLL_FREQ_160MHZ;
 742                 else
 743                         dp_priv->DP |= DP_PLL_FREQ_270MHZ;
 744         }
 745 }
 746
 747 static void ironlake_edp_panel_on (struct drm_device *dev)
 748 {
 749         struct drm_i915_private *dev_priv = dev->dev_private;
 750         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 751         u32 pp, pp_status;
 752
 753         pp_status = I915_READ(PCH_PP_STATUS);
 754         if (pp_status & PP_ON)
 755                 return;
 756
 757         pp = I915_READ(PCH_PP_CONTROL);
 758         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 759         I915_WRITE(PCH_PP_CONTROL, pp);
 760         do {
 761                 pp_status = I915_READ(PCH_PP_STATUS);
 762         } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
 763
 764         if (time_after(jiffies, timeout))
 765                 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
 766
 767         pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
 768         I915_WRITE(PCH_PP_CONTROL, pp);
 769 }
 770
 771 static void ironlake_edp_panel_off (struct drm_device *dev)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 775         u32 pp, pp_status;
 776
 777         pp = I915_READ(PCH_PP_CONTROL);
 778         pp &= ~POWER_TARGET_ON;
 779         I915_WRITE(PCH_PP_CONTROL, pp);
 780         do {
 781                 pp_status = I915_READ(PCH_PP_STATUS);
 782         } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
 783
 784         if (time_after(jiffies, timeout))
 785                 DRM_DEBUG_KMS("panel off wait timed out\n");
 786
 787         /* Make sure VDD is enabled so DP AUX will work */
 788         pp |= EDP_FORCE_VDD;
 789         I915_WRITE(PCH_PP_CONTROL, pp);
 790 }
 791
 792 static void ironlake_edp_backlight_on (struct drm_device *dev)
 793 {
 794         struct drm_i915_private *dev_priv = dev->dev_private;
 795         u32 pp;
 796
 797         DRM_DEBUG_KMS("\n");
 798         pp = I915_READ(PCH_PP_CONTROL);
 799         pp |= EDP_BLC_ENABLE;
 800         I915_WRITE(PCH_PP_CONTROL, pp);
 801 }
 802
 803 static void ironlake_edp_backlight_off (struct drm_device *dev)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         u32 pp;
 807
 808         DRM_DEBUG_KMS("\n");
 809         pp = I915_READ(PCH_PP_CONTROL);
 810         pp &= ~EDP_BLC_ENABLE;
 811         I915_WRITE(PCH_PP_CONTROL, pp);
 812 }
 813
 814 static void
 815 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 816 {
 817         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 818         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
 819         struct drm_device *dev = encoder->dev;
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         uint32_t dp_reg = I915_READ(dp_priv->output_reg);
 822
 823         if (mode != DRM_MODE_DPMS_ON) {
 824                 if (dp_reg & DP_PORT_EN) {
 825                         intel_dp_link_down(intel_encoder, dp_priv->DP);
 826                         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
 827                                 ironlake_edp_backlight_off(dev);
 828                                 ironlake_edp_panel_off(dev);
 829                         }
 830                 }
 831         } else {
 832                 if (!(dp_reg & DP_PORT_EN)) {
 833                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
 834                         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
 835                                 ironlake_edp_panel_on(dev);
 836                                 ironlake_edp_backlight_on(dev);
 837                         }
 838                 }
 839         }
 840         dp_priv->dpms_mode = mode;
 841 }
 842
 843 /*
 844  * Fetch AUX CH registers 0x202 - 0x207 which contain
 845  * link status information
 846  */
 847 static bool
 848 intel_dp_get_link_status(struct intel_encoder *intel_encoder,
 849                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 850 {
 851         int ret;
 852
 853         ret = intel_dp_aux_native_read(intel_encoder,
 854                                        DP_LANE0_1_STATUS,
 855                                        link_status, DP_LINK_STATUS_SIZE);
 856         if (ret != DP_LINK_STATUS_SIZE)
 857                 return false;
 858         return true;
 859 }
 860
 861 static uint8_t
 862 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 863                      int r)
 864 {
 865         return link_status[r - DP_LANE0_1_STATUS];
 866 }
 867
 868 static uint8_t
 869 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 870                                  int lane)
 871 {
 872         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 873         int         s = ((lane & 1) ?
 874                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 875                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 876         uint8_t l = intel_dp_link_status(link_status, i);
 877
 878         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 879 }
 880
 881 static uint8_t
 882 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 883                                       int lane)
 884 {
 885         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 886         int         s = ((lane & 1) ?
 887                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 888                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 889         uint8_t l = intel_dp_link_status(link_status, i);
 890
 891         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 892 }
 893
 894
 895 #if 0
 896 static char     *voltage_names[] = {
 897         "0.4V", "0.6V", "0.8V", "1.2V"
 898 };
 899 static char     *pre_emph_names[] = {
 900         "0dB", "3.5dB", "6dB", "9.5dB"
 901 };
 902 static char     *link_train_names[] = {
 903         "pattern 1", "pattern 2", "idle", "off"
 904 };
 905 #endif
 906
 907 /*
 908  * These are source-specific values; current Intel hardware supports
 909  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 910  */
 911 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 912
 913 static uint8_t
 914 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 915 {
 916         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 917         case DP_TRAIN_VOLTAGE_SWING_400:
 918                 return DP_TRAIN_PRE_EMPHASIS_6;
 919         case DP_TRAIN_VOLTAGE_SWING_600:
 920                 return DP_TRAIN_PRE_EMPHASIS_6;
 921         case DP_TRAIN_VOLTAGE_SWING_800:
 922                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 923         case DP_TRAIN_VOLTAGE_SWING_1200:
 924         default:
 925                 return DP_TRAIN_PRE_EMPHASIS_0;
 926         }
 927 }
 928
 929 static void
 930 intel_get_adjust_train(struct intel_encoder *intel_encoder,
 931                        uint8_t link_status[DP_LINK_STATUS_SIZE],
 932                        int lane_count,
 933                        uint8_t train_set[4])
 934 {
 935         uint8_t v = 0;
 936         uint8_t p = 0;
 937         int lane;
 938
 939         for (lane = 0; lane < lane_count; lane++) {
 940                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
 941                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
 942
 943                 if (this_v > v)
 944                         v = this_v;
 945                 if (this_p > p)
 946                         p = this_p;
 947         }
 948
 949         if (v >= I830_DP_VOLTAGE_MAX)
 950                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 951
 952         if (p >= intel_dp_pre_emphasis_max(v))
 953                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 954
 955         for (lane = 0; lane < 4; lane++)
 956                 train_set[lane] = v | p;
 957 }
 958
 959 static uint32_t
 960 intel_dp_signal_levels(uint8_t train_set, int lane_count)
 961 {
 962         uint32_t        signal_levels = 0;
 963
 964         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
 965         case DP_TRAIN_VOLTAGE_SWING_400:
 966         default:
 967                 signal_levels |= DP_VOLTAGE_0_4;
 968                 break;
 969         case DP_TRAIN_VOLTAGE_SWING_600:
 970                 signal_levels |= DP_VOLTAGE_0_6;
 971                 break;
 972         case DP_TRAIN_VOLTAGE_SWING_800:
 973                 signal_levels |= DP_VOLTAGE_0_8;
 974                 break;
 975         case DP_TRAIN_VOLTAGE_SWING_1200:
 976                 signal_levels |= DP_VOLTAGE_1_2;
 977                 break;
 978         }
 979         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
 980         case DP_TRAIN_PRE_EMPHASIS_0:
 981         default:
 982                 signal_levels |= DP_PRE_EMPHASIS_0;
 983                 break;
 984         case DP_TRAIN_PRE_EMPHASIS_3_5:
 985                 signal_levels |= DP_PRE_EMPHASIS_3_5;
 986                 break;
 987         case DP_TRAIN_PRE_EMPHASIS_6:
 988                 signal_levels |= DP_PRE_EMPHASIS_6;
 989                 break;
 990         case DP_TRAIN_PRE_EMPHASIS_9_5:
 991                 signal_levels |= DP_PRE_EMPHASIS_9_5;
 992                 break;
 993         }
 994         return signal_levels;
 995 }
 996
 997 /* Gen6's DP voltage swing and pre-emphasis control */
 998 static uint32_t
 999 intel_gen6_edp_signal_levels(uint8_t train_set)
1000 {
1001         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1002         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1003                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1004         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1005                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1006         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1007                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1008         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1009                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1010         default:
1011                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1012                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1013         }
1014 }
1015
1016 static uint8_t
1017 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1018                       int lane)
1019 {
1020         int i = DP_LANE0_1_STATUS + (lane >> 1);
1021         int s = (lane & 1) * 4;
1022         uint8_t l = intel_dp_link_status(link_status, i);
1023
1024         return (l >> s) & 0xf;
1025 }
1026
1027 /* Check for clock recovery is done on all channels */
1028 static bool
1029 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1030 {
1031         int lane;
1032         uint8_t lane_status;
1033
1034         for (lane = 0; lane < lane_count; lane++) {
1035                 lane_status = intel_get_lane_status(link_status, lane);
1036                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1037                         return false;
1038         }
1039         return true;
1040 }
1041
1042 /* Check to see if channel eq is done on all channels */
1043 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1044                          DP_LANE_CHANNEL_EQ_DONE|\
1045                          DP_LANE_SYMBOL_LOCKED)
1046 static bool
1047 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1048 {
1049         uint8_t lane_align;
1050         uint8_t lane_status;
1051         int lane;
1052
1053         lane_align = intel_dp_link_status(link_status,
1054                                           DP_LANE_ALIGN_STATUS_UPDATED);
1055         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1056                 return false;
1057         for (lane = 0; lane < lane_count; lane++) {
1058                 lane_status = intel_get_lane_status(link_status, lane);
1059                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1060                         return false;
1061         }
1062         return true;
1063 }
1064
1065 static bool
1066 intel_dp_set_link_train(struct intel_encoder *intel_encoder,
1067                         uint32_t dp_reg_value,
1068                         uint8_t dp_train_pat,
1069                         uint8_t train_set[4],
1070                         bool first)
1071 {
1072         struct drm_device *dev = intel_encoder->enc.dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1075         int ret;
1076
1077         I915_WRITE(dp_priv->output_reg, dp_reg_value);
1078         POSTING_READ(dp_priv->output_reg);
1079         if (first)
1080                 intel_wait_for_vblank(dev);
1081
1082         intel_dp_aux_native_write_1(intel_encoder,
1083                                     DP_TRAINING_PATTERN_SET,
1084                                     dp_train_pat);
1085
1086         ret = intel_dp_aux_native_write(intel_encoder,
1087                                         DP_TRAINING_LANE0_SET, train_set, 4);
1088         if (ret != 4)
1089                 return false;
1090
1091         return true;
1092 }
1093
1094 static void
1095 intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1096                     uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1097 {
1098         struct drm_device *dev = intel_encoder->enc.dev;
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1101         uint8_t train_set[4];
1102         uint8_t link_status[DP_LINK_STATUS_SIZE];
1103         int i;
1104         uint8_t voltage;
1105         bool clock_recovery = false;
1106         bool channel_eq = false;
1107         bool first = true;
1108         int tries;
1109         u32 reg;
1110
1111         /* Write the link configuration data */
1112         intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
1113                                   link_configuration, DP_LINK_CONFIGURATION_SIZE);
1114
1115         DP |= DP_PORT_EN;
1116         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1117                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1118         else
1119                 DP &= ~DP_LINK_TRAIN_MASK;
1120         memset(train_set, 0, 4);
1121         voltage = 0xff;
1122         tries = 0;
1123         clock_recovery = false;
1124         for (;;) {
1125                 /* Use train_set[0] to set the voltage and pre emphasis values */
1126                 uint32_t    signal_levels;
1127                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1128                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1129                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1130                 } else {
1131                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1132                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1133                 }
1134
1135                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1136                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1137                 else
1138                         reg = DP | DP_LINK_TRAIN_PAT_1;
1139
1140                 if (!intel_dp_set_link_train(intel_encoder, reg,
1141                                              DP_TRAINING_PATTERN_1, train_set, first))
1142                         break;
1143                 first = false;
1144                 /* Set training pattern 1 */
1145
1146                 udelay(100);
1147                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1148                         break;
1149
1150                 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1151                         clock_recovery = true;
1152                         break;
1153                 }
1154
1155                 /* Check to see if we've tried the max voltage */
1156                 for (i = 0; i < dp_priv->lane_count; i++)
1157                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1158                                 break;
1159                 if (i == dp_priv->lane_count)
1160                         break;
1161
1162                 /* Check to see if we've tried the same voltage 5 times */
1163                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1164                         ++tries;
1165                         if (tries == 5)
1166                                 break;
1167                 } else
1168                         tries = 0;
1169                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1170
1171                 /* Compute new train_set as requested by target */
1172                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1173         }
1174
1175         /* channel equalization */
1176         tries = 0;
1177         channel_eq = false;
1178         for (;;) {
1179                 /* Use train_set[0] to set the voltage and pre emphasis values */
1180                 uint32_t    signal_levels;
1181
1182                 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1183                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1184                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1185                 } else {
1186                         signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1187                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1188                 }
1189
1190                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1191                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1192                 else
1193                         reg = DP | DP_LINK_TRAIN_PAT_2;
1194
1195                 /* channel eq pattern */
1196                 if (!intel_dp_set_link_train(intel_encoder, reg,
1197                                              DP_TRAINING_PATTERN_2, train_set,
1198                                              false))
1199                         break;
1200
1201                 udelay(400);
1202                 if (!intel_dp_get_link_status(intel_encoder, link_status))
1203                         break;
1204
1205                 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1206                         channel_eq = true;
1207                         break;
1208                 }
1209
1210                 /* Try 5 times */
1211                 if (tries > 5)
1212                         break;
1213
1214                 /* Compute new train_set as requested by target */
1215                 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
1216                 ++tries;
1217         }
1218
1219         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1220                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1221         else
1222                 reg = DP | DP_LINK_TRAIN_OFF;
1223
1224         I915_WRITE(dp_priv->output_reg, reg);
1225         POSTING_READ(dp_priv->output_reg);
1226         intel_dp_aux_native_write_1(intel_encoder,
1227                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1228 }
1229
1230 static void
1231 intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1232 {
1233         struct drm_device *dev = intel_encoder->enc.dev;
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1236
1237         DRM_DEBUG_KMS("\n");
1238
1239         if (IS_eDP(intel_encoder)) {
1240                 DP &= ~DP_PLL_ENABLE;
1241                 I915_WRITE(dp_priv->output_reg, DP);
1242                 POSTING_READ(dp_priv->output_reg);
1243                 udelay(100);
1244         }
1245
1246         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1247                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1248                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1249                 POSTING_READ(dp_priv->output_reg);
1250         } else {
1251                 DP &= ~DP_LINK_TRAIN_MASK;
1252                 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1253                 POSTING_READ(dp_priv->output_reg);
1254         }
1255
1256         udelay(17000);
1257
1258         if (IS_eDP(intel_encoder))
1259                 DP |= DP_LINK_TRAIN_OFF;
1260         I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1261         POSTING_READ(dp_priv->output_reg);
1262 }
1263
1264 /*
1265  * According to DP spec
1266  * 5.1.2:
1267  *  1. Read DPCD
1268  *  2. Configure link according to Receiver Capabilities
1269  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1270  *  4. Check link status on receipt of hot-plug interrupt
1271  */
1272
1273 static void
1274 intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1275 {
1276         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1277         uint8_t link_status[DP_LINK_STATUS_SIZE];
1278
1279         if (!intel_encoder->enc.crtc)
1280                 return;
1281
1282         if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1283                 intel_dp_link_down(intel_encoder, dp_priv->DP);
1284                 return;
1285         }
1286
1287         if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1288                 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1289 }
1290
1291 static enum drm_connector_status
1292 ironlake_dp_detect(struct drm_connector *connector)
1293 {
1294         struct drm_encoder *encoder = intel_attached_encoder(connector);
1295         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1296         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1297         enum drm_connector_status status;
1298
1299         status = connector_status_disconnected;
1300         if (intel_dp_aux_native_read(intel_encoder,
1301                                      0x000, dp_priv->dpcd,
1302                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1303         {
1304                 if (dp_priv->dpcd[0] != 0)
1305                         status = connector_status_connected;
1306         }
1307         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
1308                       dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
1309         return status;
1310 }
1311
1312 /**
1313  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1314  *
1315  * \return true if DP port is connected.
1316  * \return false if DP port is disconnected.
1317  */
1318 static enum drm_connector_status
1319 intel_dp_detect(struct drm_connector *connector)
1320 {
1321         struct drm_encoder *encoder = intel_attached_encoder(connector);
1322         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1323         struct drm_device *dev = intel_encoder->enc.dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1326         uint32_t temp, bit;
1327         enum drm_connector_status status;
1328
1329         dp_priv->has_audio = false;
1330
1331         if (HAS_PCH_SPLIT(dev))
1332                 return ironlake_dp_detect(connector);
1333
1334         switch (dp_priv->output_reg) {
1335         case DP_B:
1336                 bit = DPB_HOTPLUG_INT_STATUS;
1337                 break;
1338         case DP_C:
1339                 bit = DPC_HOTPLUG_INT_STATUS;
1340                 break;
1341         case DP_D:
1342                 bit = DPD_HOTPLUG_INT_STATUS;
1343                 break;
1344         default:
1345                 return connector_status_unknown;
1346         }
1347
1348         temp = I915_READ(PORT_HOTPLUG_STAT);
1349
1350         if ((temp & bit) == 0)
1351                 return connector_status_disconnected;
1352
1353         status = connector_status_disconnected;
1354         if (intel_dp_aux_native_read(intel_encoder,
1355                                      0x000, dp_priv->dpcd,
1356                                      sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1357         {
1358                 if (dp_priv->dpcd[0] != 0)
1359                         status = connector_status_connected;
1360         }
1361         return status;
1362 }
1363
1364 static int intel_dp_get_modes(struct drm_connector *connector)
1365 {
1366         struct drm_encoder *encoder = intel_attached_encoder(connector);
1367         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1368         struct drm_device *dev = intel_encoder->enc.dev;
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1371         int ret;
1372
1373         /* We should parse the EDID data and find out if it has an audio sink
1374          */
1375
1376         ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1377         if (ret)
1378                 return ret;
1379
1380         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1381         if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
1382                 if (dev_priv->panel_fixed_mode != NULL) {
1383                         struct drm_display_mode *mode;
1384                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1385                         drm_mode_probed_add(connector, mode);
1386                         return 1;
1387                 }
1388         }
1389         return 0;
1390 }
1391
1392 static void
1393 intel_dp_destroy (struct drm_connector *connector)
1394 {
1395         drm_sysfs_connector_remove(connector);
1396         drm_connector_cleanup(connector);
1397         kfree(connector);
1398 }
1399
1400 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1401         .dpms = intel_dp_dpms,
1402         .mode_fixup = intel_dp_mode_fixup,
1403         .prepare = intel_encoder_prepare,
1404         .mode_set = intel_dp_mode_set,
1405         .commit = intel_encoder_commit,
1406 };
1407
1408 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1409         .dpms = drm_helper_connector_dpms,
1410         .detect = intel_dp_detect,
1411         .fill_modes = drm_helper_probe_single_connector_modes,
1412         .destroy = intel_dp_destroy,
1413 };
1414
1415 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1416         .get_modes = intel_dp_get_modes,
1417         .mode_valid = intel_dp_mode_valid,
1418         .best_encoder = intel_attached_encoder,
1419 };
1420
1421 static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1422 {
1423         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1424
1425         if (intel_encoder->i2c_bus)
1426                 intel_i2c_destroy(intel_encoder->i2c_bus);
1427         drm_encoder_cleanup(encoder);
1428         kfree(intel_encoder);
1429 }
1430
1431 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1432         .destroy = intel_dp_enc_destroy,
1433 };
1434
1435 void
1436 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1437 {
1438         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1439
1440         if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1441                 intel_dp_check_link_status(intel_encoder);
1442 }
1443
1444 /* Return which DP Port should be selected for Transcoder DP control */
1445 int
1446 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1447 {
1448         struct drm_device *dev = crtc->dev;
1449         struct drm_mode_config *mode_config = &dev->mode_config;
1450         struct drm_encoder *encoder;
1451         struct intel_encoder *intel_encoder = NULL;
1452
1453         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1454                 if (encoder->crtc != crtc)
1455                         continue;
1456
1457                 intel_encoder = enc_to_intel_encoder(encoder);
1458                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1459                         struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1460                         return dp_priv->output_reg;
1461                 }
1462         }
1463         return -1;
1464 }
1465
1466 /* check the VBT to see whether the eDP is on DP-D port */
1467 static bool intel_dpd_is_edp(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470         struct child_device_config *p_child;
1471         int i;
1472
1473         if (!dev_priv->child_dev_num)
1474                 return false;
1475
1476         for (i = 0; i < dev_priv->child_dev_num; i++) {
1477                 p_child = dev_priv->child_dev + i;
1478
1479                 if (p_child->dvo_port == PORT_IDPD &&
1480                     p_child->device_type == DEVICE_TYPE_eDP)
1481                         return true;
1482         }
1483         return false;
1484 }
1485
1486 void
1487 intel_dp_init(struct drm_device *dev, int output_reg)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         struct drm_connector *connector;
1491         struct intel_encoder *intel_encoder;
1492         struct intel_connector *intel_connector;
1493         struct intel_dp_priv *dp_priv;
1494         const char *name = NULL;
1495
1496         intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1497                                sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1498         if (!intel_encoder)
1499                 return;
1500
1501         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1502         if (!intel_connector) {
1503                 kfree(intel_encoder);
1504                 return;
1505         }
1506
1507         dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1508
1509         connector = &intel_connector->base;
1510         drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1511                            DRM_MODE_CONNECTOR_DisplayPort);
1512         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1513
1514         connector->polled = DRM_CONNECTOR_POLL_HPD;
1515
1516         if (output_reg == DP_A)
1517                 intel_encoder->type = INTEL_OUTPUT_EDP;
1518         else
1519                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1520
1521         if (output_reg == DP_B || output_reg == PCH_DP_B)
1522                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1523         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1524                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1525         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1526                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1527
1528         if (IS_eDP(intel_encoder))
1529                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1530
1531         if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D)) {
1532                 if (intel_dpd_is_edp(dev))
1533                         dp_priv->is_pch_edp = true;
1534         }
1535
1536         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1537         connector->interlace_allowed = true;
1538         connector->doublescan_allowed = 0;
1539
1540         dp_priv->intel_encoder = intel_encoder;
1541         dp_priv->output_reg = output_reg;
1542         dp_priv->has_audio = false;
1543         dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1544         intel_encoder->dev_priv = dp_priv;
1545
1546         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1547                          DRM_MODE_ENCODER_TMDS);
1548         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1549
1550         drm_mode_connector_attach_encoder(&intel_connector->base,
1551                                           &intel_encoder->enc);
1552         drm_sysfs_connector_add(connector);
1553
1554         /* Set up the DDC bus. */
1555         switch (output_reg) {
1556                 case DP_A:
1557                         name = "DPDDC-A";
1558                         break;
1559                 case DP_B:
1560                 case PCH_DP_B:
1561                         dev_priv->hotplug_supported_mask |=
1562                                 HDMIB_HOTPLUG_INT_STATUS;
1563                         name = "DPDDC-B";
1564                         break;
1565                 case DP_C:
1566                 case PCH_DP_C:
1567                         dev_priv->hotplug_supported_mask |=
1568                                 HDMIC_HOTPLUG_INT_STATUS;
1569                         name = "DPDDC-C";
1570                         break;
1571                 case DP_D:
1572                 case PCH_DP_D:
1573                         dev_priv->hotplug_supported_mask |=
1574                                 HDMID_HOTPLUG_INT_STATUS;
1575                         name = "DPDDC-D";
1576                         break;
1577         }
1578
1579         intel_dp_i2c_init(intel_encoder, intel_connector, name);
1580
1581         intel_encoder->ddc_bus = &dp_priv->adapter;
1582         intel_encoder->hot_plug = intel_dp_hot_plug;
1583
1584         if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
1585                 /* initialize panel mode from VBT if available for eDP */
1586                 if (dev_priv->lfp_lvds_vbt_mode) {
1587                         dev_priv->panel_fixed_mode =
1588                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1589                         if (dev_priv->panel_fixed_mode) {
1590                                 dev_priv->panel_fixed_mode->type |=
1591                                         DRM_MODE_TYPE_PREFERRED;
1592                         }
1593                 }
1594         }
1595
1596         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1597          * 0xd.  Failure to do so will result in spurious interrupts being
1598          * generated on the port when a cable is not attached.
1599          */
1600         if (IS_G4X(dev) && !IS_GM45(dev)) {
1601                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1602                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1603         }
1604 }