drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 117 static void vlv_steal_power_sequencer(struct drm_device *dev,
 118                                       enum pipe pipe);
 119
 120 int
 121 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 122 {
 123         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 124         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 125
 126         switch (max_link_bw) {
 127         case DP_LINK_BW_1_62:
 128         case DP_LINK_BW_2_7:
 129                 break;
 130         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 131                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 132                      INTEL_INFO(dev)->gen >= 8) &&
 133                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 134                         max_link_bw = DP_LINK_BW_5_4;
 135                 else
 136                         max_link_bw = DP_LINK_BW_2_7;
 137                 break;
 138         default:
 139                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 140                      max_link_bw);
 141                 max_link_bw = DP_LINK_BW_1_62;
 142                 break;
 143         }
 144         return max_link_bw;
 145 }
 146
 147 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 148 {
 149         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 150         struct drm_device *dev = intel_dig_port->base.base.dev;
 151         u8 source_max, sink_max;
 152
 153         source_max = 4;
 154         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 155             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 156                 source_max = 2;
 157
 158         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 159
 160         return min(source_max, sink_max);
 161 }
 162
 163 /*
 164  * The units on the numbers in the next two are... bizarre.  Examples will
 165  * make it clearer; this one parallels an example in the eDP spec.
 166  *
 167  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 168  *
 169  *     270000 * 1 * 8 / 10 == 216000
 170  *
 171  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 172  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 173  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 174  * 119000.  At 18bpp that's 2142000 kilobits per second.
 175  *
 176  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 177  * get the result in decakilobits instead of kilobits.
 178  */
 179
 180 static int
 181 intel_dp_link_required(int pixel_clock, int bpp)
 182 {
 183         return (pixel_clock * bpp + 9) / 10;
 184 }
 185
 186 static int
 187 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 188 {
 189         return (max_link_clock * max_lanes * 8) / 10;
 190 }
 191
 192 static enum drm_mode_status
 193 intel_dp_mode_valid(struct drm_connector *connector,
 194                     struct drm_display_mode *mode)
 195 {
 196         struct intel_dp *intel_dp = intel_attached_dp(connector);
 197         struct intel_connector *intel_connector = to_intel_connector(connector);
 198         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 199         int target_clock = mode->clock;
 200         int max_rate, mode_rate, max_lanes, max_link_clock;
 201
 202         if (is_edp(intel_dp) && fixed_mode) {
 203                 if (mode->hdisplay > fixed_mode->hdisplay)
 204                         return MODE_PANEL;
 205
 206                 if (mode->vdisplay > fixed_mode->vdisplay)
 207                         return MODE_PANEL;
 208
 209                 target_clock = fixed_mode->clock;
 210         }
 211
 212         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 213         max_lanes = intel_dp_max_lane_count(intel_dp);
 214
 215         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 216         mode_rate = intel_dp_link_required(target_clock, 18);
 217
 218         if (mode_rate > max_rate)
 219                 return MODE_CLOCK_HIGH;
 220
 221         if (mode->clock < 10000)
 222                 return MODE_CLOCK_LOW;
 223
 224         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 225                 return MODE_H_ILLEGAL;
 226
 227         return MODE_OK;
 228 }
 229
 230 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 231 {
 232         int     i;
 233         uint32_t v = 0;
 234
 235         if (src_bytes > 4)
 236                 src_bytes = 4;
 237         for (i = 0; i < src_bytes; i++)
 238                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 239         return v;
 240 }
 241
 242 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 243 {
 244         int i;
 245         if (dst_bytes > 4)
 246                 dst_bytes = 4;
 247         for (i = 0; i < dst_bytes; i++)
 248                 dst[i] = src >> ((3-i) * 8);
 249 }
 250
 251 /* hrawclock is 1/4 the FSB frequency */
 252 static int
 253 intel_hrawclk(struct drm_device *dev)
 254 {
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         uint32_t clkcfg;
 257
 258         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 259         if (IS_VALLEYVIEW(dev))
 260                 return 200;
 261
 262         clkcfg = I915_READ(CLKCFG);
 263         switch (clkcfg & CLKCFG_FSB_MASK) {
 264         case CLKCFG_FSB_400:
 265                 return 100;
 266         case CLKCFG_FSB_533:
 267                 return 133;
 268         case CLKCFG_FSB_667:
 269                 return 166;
 270         case CLKCFG_FSB_800:
 271                 return 200;
 272         case CLKCFG_FSB_1067:
 273                 return 266;
 274         case CLKCFG_FSB_1333:
 275                 return 333;
 276         /* these two are just a guess; one of them might be right */
 277         case CLKCFG_FSB_1600:
 278         case CLKCFG_FSB_1600_ALT:
 279                 return 400;
 280         default:
 281                 return 133;
 282         }
 283 }
 284
 285 static void
 286 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 287                                     struct intel_dp *intel_dp);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp);
 291
 292 static void pps_lock(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 295         struct intel_encoder *encoder = &intel_dig_port->base;
 296         struct drm_device *dev = encoder->base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         enum intel_display_power_domain power_domain;
 299
 300         /*
 301          * See vlv_power_sequencer_reset() why we need
 302          * a power domain reference here.
 303          */
 304         power_domain = intel_display_port_power_domain(encoder);
 305         intel_display_power_get(dev_priv, power_domain);
 306
 307         mutex_lock(&dev_priv->pps_mutex);
 308 }
 309
 310 static void pps_unlock(struct intel_dp *intel_dp)
 311 {
 312         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 313         struct intel_encoder *encoder = &intel_dig_port->base;
 314         struct drm_device *dev = encoder->base.dev;
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316         enum intel_display_power_domain power_domain;
 317
 318         mutex_unlock(&dev_priv->pps_mutex);
 319
 320         power_domain = intel_display_port_power_domain(encoder);
 321         intel_display_power_put(dev_priv, power_domain);
 322 }
 323
 324 static void
 325 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 326 {
 327         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 328         struct drm_device *dev = intel_dig_port->base.base.dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330         enum pipe pipe = intel_dp->pps_pipe;
 331         bool pll_enabled;
 332         uint32_t DP;
 333
 334         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 335                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 336                  pipe_name(pipe), port_name(intel_dig_port->port)))
 337                 return;
 338
 339         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 340                       pipe_name(pipe), port_name(intel_dig_port->port));
 341
 342         /* Preserve the BIOS-computed detected bit. This is
 343          * supposed to be read-only.
 344          */
 345         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 346         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 347         DP |= DP_PORT_WIDTH(1);
 348         DP |= DP_LINK_TRAIN_PAT_1;
 349
 350         if (IS_CHERRYVIEW(dev))
 351                 DP |= DP_PIPE_SELECT_CHV(pipe);
 352         else if (pipe == PIPE_B)
 353                 DP |= DP_PIPEB_SELECT;
 354
 355         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 356
 357         /*
 358          * The DPLL for the pipe must be enabled for this to work.
 359          * So enable temporarily it if it's not already enabled.
 360          */
 361         if (!pll_enabled)
 362                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 363                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 364
 365         /*
 366          * Similar magic as in intel_dp_enable_port().
 367          * We _must_ do this port enable + disable trick
 368          * to make this power seqeuencer lock onto the port.
 369          * Otherwise even VDD force bit won't work.
 370          */
 371         I915_WRITE(intel_dp->output_reg, DP);
 372         POSTING_READ(intel_dp->output_reg);
 373
 374         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 375         POSTING_READ(intel_dp->output_reg);
 376
 377         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 378         POSTING_READ(intel_dp->output_reg);
 379
 380         if (!pll_enabled)
 381                 vlv_force_pll_off(dev, pipe);
 382 }
 383
 384 static enum pipe
 385 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 386 {
 387         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 388         struct drm_device *dev = intel_dig_port->base.base.dev;
 389         struct drm_i915_private *dev_priv = dev->dev_private;
 390         struct intel_encoder *encoder;
 391         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 392         enum pipe pipe;
 393
 394         lockdep_assert_held(&dev_priv->pps_mutex);
 395
 396         /* We should never land here with regular DP ports */
 397         WARN_ON(!is_edp(intel_dp));
 398
 399         if (intel_dp->pps_pipe != INVALID_PIPE)
 400                 return intel_dp->pps_pipe;
 401
 402         /*
 403          * We don't have power sequencer currently.
 404          * Pick one that's not used by other ports.
 405          */
 406         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 407                             base.head) {
 408                 struct intel_dp *tmp;
 409
 410                 if (encoder->type != INTEL_OUTPUT_EDP)
 411                         continue;
 412
 413                 tmp = enc_to_intel_dp(&encoder->base);
 414
 415                 if (tmp->pps_pipe != INVALID_PIPE)
 416                         pipes &= ~(1 << tmp->pps_pipe);
 417         }
 418
 419         /*
 420          * Didn't find one. This should not happen since there
 421          * are two power sequencers and up to two eDP ports.
 422          */
 423         if (WARN_ON(pipes == 0))
 424                 pipe = PIPE_A;
 425         else
 426                 pipe = ffs(pipes) - 1;
 427
 428         vlv_steal_power_sequencer(dev, pipe);
 429         intel_dp->pps_pipe = pipe;
 430
 431         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 432                       pipe_name(intel_dp->pps_pipe),
 433                       port_name(intel_dig_port->port));
 434
 435         /* init power sequencer on this pipe and port */
 436         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 437         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 438
 439         /*
 440          * Even vdd force doesn't work until we've made
 441          * the power sequencer lock in on the port.
 442          */
 443         vlv_power_sequencer_kick(intel_dp);
 444
 445         return intel_dp->pps_pipe;
 446 }
 447
 448 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 449                                enum pipe pipe);
 450
 451 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 452                                enum pipe pipe)
 453 {
 454         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 455 }
 456
 457 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 458                                 enum pipe pipe)
 459 {
 460         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 461 }
 462
 463 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 464                          enum pipe pipe)
 465 {
 466         return true;
 467 }
 468
 469 static enum pipe
 470 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 471                      enum port port,
 472                      vlv_pipe_check pipe_check)
 473 {
 474         enum pipe pipe;
 475
 476         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 477                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 478                         PANEL_PORT_SELECT_MASK;
 479
 480                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 481                         continue;
 482
 483                 if (!pipe_check(dev_priv, pipe))
 484                         continue;
 485
 486                 return pipe;
 487         }
 488
 489         return INVALID_PIPE;
 490 }
 491
 492 static void
 493 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 494 {
 495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 496         struct drm_device *dev = intel_dig_port->base.base.dev;
 497         struct drm_i915_private *dev_priv = dev->dev_private;
 498         enum port port = intel_dig_port->port;
 499
 500         lockdep_assert_held(&dev_priv->pps_mutex);
 501
 502         /* try to find a pipe with this port selected */
 503         /* first pick one where the panel is on */
 504         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 505                                                   vlv_pipe_has_pp_on);
 506         /* didn't find one? pick one where vdd is on */
 507         if (intel_dp->pps_pipe == INVALID_PIPE)
 508                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 509                                                           vlv_pipe_has_vdd_on);
 510         /* didn't find one? pick one with just the correct port */
 511         if (intel_dp->pps_pipe == INVALID_PIPE)
 512                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 513                                                           vlv_pipe_any);
 514
 515         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 516         if (intel_dp->pps_pipe == INVALID_PIPE) {
 517                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 518                               port_name(port));
 519                 return;
 520         }
 521
 522         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 523                       port_name(port), pipe_name(intel_dp->pps_pipe));
 524
 525         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 526         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 527 }
 528
 529 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 530 {
 531         struct drm_device *dev = dev_priv->dev;
 532         struct intel_encoder *encoder;
 533
 534         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 535                 return;
 536
 537         /*
 538          * We can't grab pps_mutex here due to deadlock with power_domain
 539          * mutex when power_domain functions are called while holding pps_mutex.
 540          * That also means that in order to use pps_pipe the code needs to
 541          * hold both a power domain reference and pps_mutex, and the power domain
 542          * reference get/put must be done while _not_ holding pps_mutex.
 543          * pps_{lock,unlock}() do these steps in the correct order, so one
 544          * should use them always.
 545          */
 546
 547         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 548                 struct intel_dp *intel_dp;
 549
 550                 if (encoder->type != INTEL_OUTPUT_EDP)
 551                         continue;
 552
 553                 intel_dp = enc_to_intel_dp(&encoder->base);
 554                 intel_dp->pps_pipe = INVALID_PIPE;
 555         }
 556 }
 557
 558 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 559 {
 560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 561
 562         if (HAS_PCH_SPLIT(dev))
 563                 return PCH_PP_CONTROL;
 564         else
 565                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 566 }
 567
 568 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 569 {
 570         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 571
 572         if (HAS_PCH_SPLIT(dev))
 573                 return PCH_PP_STATUS;
 574         else
 575                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 576 }
 577
 578 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 579    This function only applicable when panel PM state is not to be tracked */
 580 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 581                               void *unused)
 582 {
 583         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 584                                                  edp_notifier);
 585         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 586         struct drm_i915_private *dev_priv = dev->dev_private;
 587         u32 pp_div;
 588         u32 pp_ctrl_reg, pp_div_reg;
 589
 590         if (!is_edp(intel_dp) || code != SYS_RESTART)
 591                 return 0;
 592
 593         pps_lock(intel_dp);
 594
 595         if (IS_VALLEYVIEW(dev)) {
 596                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 597
 598                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 599                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 600                 pp_div = I915_READ(pp_div_reg);
 601                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 602
 603                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 604                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 605                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 606                 msleep(intel_dp->panel_power_cycle_delay);
 607         }
 608
 609         pps_unlock(intel_dp);
 610
 611         return 0;
 612 }
 613
 614 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 615 {
 616         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618
 619         lockdep_assert_held(&dev_priv->pps_mutex);
 620
 621         if (IS_VALLEYVIEW(dev) &&
 622             intel_dp->pps_pipe == INVALID_PIPE)
 623                 return false;
 624
 625         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 626 }
 627
 628 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 629 {
 630         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632
 633         lockdep_assert_held(&dev_priv->pps_mutex);
 634
 635         if (IS_VALLEYVIEW(dev) &&
 636             intel_dp->pps_pipe == INVALID_PIPE)
 637                 return false;
 638
 639         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 640 }
 641
 642 static void
 643 intel_dp_check_edp(struct intel_dp *intel_dp)
 644 {
 645         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 646         struct drm_i915_private *dev_priv = dev->dev_private;
 647
 648         if (!is_edp(intel_dp))
 649                 return;
 650
 651         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 652                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 653                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 654                               I915_READ(_pp_stat_reg(intel_dp)),
 655                               I915_READ(_pp_ctrl_reg(intel_dp)));
 656         }
 657 }
 658
 659 static uint32_t
 660 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 661 {
 662         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 663         struct drm_device *dev = intel_dig_port->base.base.dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 666         uint32_t status;
 667         bool done;
 668
 669 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 670         if (has_aux_irq)
 671                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 672                                           msecs_to_jiffies_timeout(10));
 673         else
 674                 done = wait_for_atomic(C, 10) == 0;
 675         if (!done)
 676                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 677                           has_aux_irq);
 678 #undef C
 679
 680         return status;
 681 }
 682
 683 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 684 {
 685         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 686         struct drm_device *dev = intel_dig_port->base.base.dev;
 687
 688         /*
 689          * The clock divider is based off the hrawclk, and would like to run at
 690          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 691          */
 692         return index ? 0 : intel_hrawclk(dev) / 2;
 693 }
 694
 695 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 696 {
 697         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 698         struct drm_device *dev = intel_dig_port->base.base.dev;
 699
 700         if (index)
 701                 return 0;
 702
 703         if (intel_dig_port->port == PORT_A) {
 704                 if (IS_GEN6(dev) || IS_GEN7(dev))
 705                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 706                 else
 707                         return 225; /* eDP input clock at 450Mhz */
 708         } else {
 709                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 710         }
 711 }
 712
 713 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 714 {
 715         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 716         struct drm_device *dev = intel_dig_port->base.base.dev;
 717         struct drm_i915_private *dev_priv = dev->dev_private;
 718
 719         if (intel_dig_port->port == PORT_A) {
 720                 if (index)
 721                         return 0;
 722                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 723         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 724                 /* Workaround for non-ULT HSW */
 725                 switch (index) {
 726                 case 0: return 63;
 727                 case 1: return 72;
 728                 default: return 0;
 729                 }
 730         } else  {
 731                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 732         }
 733 }
 734
 735 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 736 {
 737         return index ? 0 : 100;
 738 }
 739
 740 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 741 {
 742         /*
 743          * SKL doesn't need us to program the AUX clock divider (Hardware will
 744          * derive the clock from CDCLK automatically). We still implement the
 745          * get_aux_clock_divider vfunc to plug-in into the existing code.
 746          */
 747         return index ? 0 : 1;
 748 }
 749
 750 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 751                                       bool has_aux_irq,
 752                                       int send_bytes,
 753                                       uint32_t aux_clock_divider)
 754 {
 755         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 756         struct drm_device *dev = intel_dig_port->base.base.dev;
 757         uint32_t precharge, timeout;
 758
 759         if (IS_GEN6(dev))
 760                 precharge = 3;
 761         else
 762                 precharge = 5;
 763
 764         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 765                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 766         else
 767                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 768
 769         return DP_AUX_CH_CTL_SEND_BUSY |
 770                DP_AUX_CH_CTL_DONE |
 771                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 772                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 773                timeout |
 774                DP_AUX_CH_CTL_RECEIVE_ERROR |
 775                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 776                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 777                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 778 }
 779
 780 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 781                                       bool has_aux_irq,
 782                                       int send_bytes,
 783                                       uint32_t unused)
 784 {
 785         return DP_AUX_CH_CTL_SEND_BUSY |
 786                DP_AUX_CH_CTL_DONE |
 787                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 788                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 789                DP_AUX_CH_CTL_TIME_OUT_1600us |
 790                DP_AUX_CH_CTL_RECEIVE_ERROR |
 791                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 792                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 793 }
 794
 795 static int
 796 intel_dp_aux_ch(struct intel_dp *intel_dp,
 797                 const uint8_t *send, int send_bytes,
 798                 uint8_t *recv, int recv_size)
 799 {
 800         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 801         struct drm_device *dev = intel_dig_port->base.base.dev;
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 804         uint32_t ch_data = ch_ctl + 4;
 805         uint32_t aux_clock_divider;
 806         int i, ret, recv_bytes;
 807         uint32_t status;
 808         int try, clock = 0;
 809         bool has_aux_irq = HAS_AUX_IRQ(dev);
 810         bool vdd;
 811
 812         pps_lock(intel_dp);
 813
 814         /*
 815          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 816          * In such cases we want to leave VDD enabled and it's up to upper layers
 817          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 818          * ourselves.
 819          */
 820         vdd = edp_panel_vdd_on(intel_dp);
 821
 822         /* dp aux is extremely sensitive to irq latency, hence request the
 823          * lowest possible wakeup latency and so prevent the cpu from going into
 824          * deep sleep states.
 825          */
 826         pm_qos_update_request(&dev_priv->pm_qos, 0);
 827
 828         intel_dp_check_edp(intel_dp);
 829
 830         intel_aux_display_runtime_get(dev_priv);
 831
 832         /* Try to wait for any previous AUX channel activity */
 833         for (try = 0; try < 3; try++) {
 834                 status = I915_READ_NOTRACE(ch_ctl);
 835                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 836                         break;
 837                 msleep(1);
 838         }
 839
 840         if (try == 3) {
 841                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 842                      I915_READ(ch_ctl));
 843                 ret = -EBUSY;
 844                 goto out;
 845         }
 846
 847         /* Only 5 data registers! */
 848         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 849                 ret = -E2BIG;
 850                 goto out;
 851         }
 852
 853         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 854                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 855                                                           has_aux_irq,
 856                                                           send_bytes,
 857                                                           aux_clock_divider);
 858
 859                 /* Must try at least 3 times according to DP spec */
 860                 for (try = 0; try < 5; try++) {
 861                         /* Load the send data into the aux channel data registers */
 862                         for (i = 0; i < send_bytes; i += 4)
 863                                 I915_WRITE(ch_data + i,
 864                                            intel_dp_pack_aux(send + i,
 865                                                              send_bytes - i));
 866
 867                         /* Send the command and wait for it to complete */
 868                         I915_WRITE(ch_ctl, send_ctl);
 869
 870                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 871
 872                         /* Clear done status and any errors */
 873                         I915_WRITE(ch_ctl,
 874                                    status |
 875                                    DP_AUX_CH_CTL_DONE |
 876                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 877                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 878
 879                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 880                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 881                                 continue;
 882                         if (status & DP_AUX_CH_CTL_DONE)
 883                                 break;
 884                 }
 885                 if (status & DP_AUX_CH_CTL_DONE)
 886                         break;
 887         }
 888
 889         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 890                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 891                 ret = -EBUSY;
 892                 goto out;
 893         }
 894
 895         /* Check for timeout or receive error.
 896          * Timeouts occur when the sink is not connected
 897          */
 898         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 899                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 900                 ret = -EIO;
 901                 goto out;
 902         }
 903
 904         /* Timeouts occur when the device isn't connected, so they're
 905          * "normal" -- don't fill the kernel log with these */
 906         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 907                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 908                 ret = -ETIMEDOUT;
 909                 goto out;
 910         }
 911
 912         /* Unload any bytes sent back from the other side */
 913         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 914                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 915         if (recv_bytes > recv_size)
 916                 recv_bytes = recv_size;
 917
 918         for (i = 0; i < recv_bytes; i += 4)
 919                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 920                                     recv + i, recv_bytes - i);
 921
 922         ret = recv_bytes;
 923 out:
 924         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 925         intel_aux_display_runtime_put(dev_priv);
 926
 927         if (vdd)
 928                 edp_panel_vdd_off(intel_dp, false);
 929
 930         pps_unlock(intel_dp);
 931
 932         return ret;
 933 }
 934
 935 #define BARE_ADDRESS_SIZE       3
 936 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 937 static ssize_t
 938 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 939 {
 940         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 941         uint8_t txbuf[20], rxbuf[20];
 942         size_t txsize, rxsize;
 943         int ret;
 944
 945         txbuf[0] = msg->request << 4;
 946         txbuf[1] = msg->address >> 8;
 947         txbuf[2] = msg->address & 0xff;
 948         txbuf[3] = msg->size - 1;
 949
 950         switch (msg->request & ~DP_AUX_I2C_MOT) {
 951         case DP_AUX_NATIVE_WRITE:
 952         case DP_AUX_I2C_WRITE:
 953                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 954                 rxsize = 1;
 955
 956                 if (WARN_ON(txsize > 20))
 957                         return -E2BIG;
 958
 959                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 960
 961                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 962                 if (ret > 0) {
 963                         msg->reply = rxbuf[0] >> 4;
 964
 965                         /* Return payload size. */
 966                         ret = msg->size;
 967                 }
 968                 break;
 969
 970         case DP_AUX_NATIVE_READ:
 971         case DP_AUX_I2C_READ:
 972                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 973                 rxsize = msg->size + 1;
 974
 975                 if (WARN_ON(rxsize > 20))
 976                         return -E2BIG;
 977
 978                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 979                 if (ret > 0) {
 980                         msg->reply = rxbuf[0] >> 4;
 981                         /*
 982                          * Assume happy day, and copy the data. The caller is
 983                          * expected to check msg->reply before touching it.
 984                          *
 985                          * Return payload size.
 986                          */
 987                         ret--;
 988                         memcpy(msg->buffer, rxbuf + 1, ret);
 989                 }
 990                 break;
 991
 992         default:
 993                 ret = -EINVAL;
 994                 break;
 995         }
 996
 997         return ret;
 998 }
 999
1000 static void
1001 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1002 {
1003         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1004         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005         enum port port = intel_dig_port->port;
1006         const char *name = NULL;
1007         int ret;
1008
1009         switch (port) {
1010         case PORT_A:
1011                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1012                 name = "DPDDC-A";
1013                 break;
1014         case PORT_B:
1015                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1016                 name = "DPDDC-B";
1017                 break;
1018         case PORT_C:
1019                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1020                 name = "DPDDC-C";
1021                 break;
1022         case PORT_D:
1023                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1024                 name = "DPDDC-D";
1025                 break;
1026         default:
1027                 BUG();
1028         }
1029
1030         /*
1031          * The AUX_CTL register is usually DP_CTL + 0x10.
1032          *
1033          * On Haswell and Broadwell though:
1034          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1036          *
1037          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1038          */
1039         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1040                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1041
1042         intel_dp->aux.name = name;
1043         intel_dp->aux.dev = dev->dev;
1044         intel_dp->aux.transfer = intel_dp_aux_transfer;
1045
1046         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1047                       connector->base.kdev->kobj.name);
1048
1049         ret = drm_dp_aux_register(&intel_dp->aux);
1050         if (ret < 0) {
1051                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1052                           name, ret);
1053                 return;
1054         }
1055
1056         ret = sysfs_create_link(&connector->base.kdev->kobj,
1057                                 &intel_dp->aux.ddc.dev.kobj,
1058                                 intel_dp->aux.ddc.dev.kobj.name);
1059         if (ret < 0) {
1060                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1061                 drm_dp_aux_unregister(&intel_dp->aux);
1062         }
1063 }
1064
1065 static void
1066 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067 {
1068         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1069
1070         if (!intel_connector->mst_port)
1071                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1072                                   intel_dp->aux.ddc.dev.kobj.name);
1073         intel_connector_unregister(intel_connector);
1074 }
1075
1076 static void
1077 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
1078 {
1079         u32 ctrl1;
1080
1081         pipe_config->ddi_pll_sel = SKL_DPLL0;
1082         pipe_config->dpll_hw_state.cfgcr1 = 0;
1083         pipe_config->dpll_hw_state.cfgcr2 = 0;
1084
1085         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1086         switch (link_bw) {
1087         case DP_LINK_BW_1_62:
1088                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1089                                               SKL_DPLL0);
1090                 break;
1091         case DP_LINK_BW_2_7:
1092                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1093                                               SKL_DPLL0);
1094                 break;
1095         case DP_LINK_BW_5_4:
1096                 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1097                                               SKL_DPLL0);
1098                 break;
1099         }
1100         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1101 }
1102
1103 static void
1104 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1105 {
1106         switch (link_bw) {
1107         case DP_LINK_BW_1_62:
1108                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1109                 break;
1110         case DP_LINK_BW_2_7:
1111                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1112                 break;
1113         case DP_LINK_BW_5_4:
1114                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1115                 break;
1116         }
1117 }
1118
1119 static void
1120 intel_dp_set_clock(struct intel_encoder *encoder,
1121                    struct intel_crtc_state *pipe_config, int link_bw)
1122 {
1123         struct drm_device *dev = encoder->base.dev;
1124         const struct dp_link_dpll *divisor = NULL;
1125         int i, count = 0;
1126
1127         if (IS_G4X(dev)) {
1128                 divisor = gen4_dpll;
1129                 count = ARRAY_SIZE(gen4_dpll);
1130         } else if (HAS_PCH_SPLIT(dev)) {
1131                 divisor = pch_dpll;
1132                 count = ARRAY_SIZE(pch_dpll);
1133         } else if (IS_CHERRYVIEW(dev)) {
1134                 divisor = chv_dpll;
1135                 count = ARRAY_SIZE(chv_dpll);
1136         } else if (IS_VALLEYVIEW(dev)) {
1137                 divisor = vlv_dpll;
1138                 count = ARRAY_SIZE(vlv_dpll);
1139         }
1140
1141         if (divisor && count) {
1142                 for (i = 0; i < count; i++) {
1143                         if (link_bw == divisor[i].link_bw) {
1144                                 pipe_config->dpll = divisor[i].dpll;
1145                                 pipe_config->clock_set = true;
1146                                 break;
1147                         }
1148                 }
1149         }
1150 }
1151
1152 bool
1153 intel_dp_compute_config(struct intel_encoder *encoder,
1154                         struct intel_crtc_state *pipe_config)
1155 {
1156         struct drm_device *dev = encoder->base.dev;
1157         struct drm_i915_private *dev_priv = dev->dev_private;
1158         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1159         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1160         enum port port = dp_to_dig_port(intel_dp)->port;
1161         struct intel_crtc *intel_crtc = encoder->new_crtc;
1162         struct intel_connector *intel_connector = intel_dp->attached_connector;
1163         int lane_count, clock;
1164         int min_lane_count = 1;
1165         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1166         /* Conveniently, the link BW constants become indices with a shift...*/
1167         int min_clock = 0;
1168         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1169         int bpp, mode_rate;
1170         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1171         int link_avail, link_clock;
1172
1173         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1174                 pipe_config->has_pch_encoder = true;
1175
1176         pipe_config->has_dp_encoder = true;
1177         pipe_config->has_drrs = false;
1178         pipe_config->has_audio = intel_dp->has_audio;
1179
1180         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1181                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1182                                        adjusted_mode);
1183                 if (!HAS_PCH_SPLIT(dev))
1184                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1185                                                  intel_connector->panel.fitting_mode);
1186                 else
1187                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1188                                                 intel_connector->panel.fitting_mode);
1189         }
1190
1191         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1192                 return false;
1193
1194         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195                       "max bw %02x pixel clock %iKHz\n",
1196                       max_lane_count, bws[max_clock],
1197                       adjusted_mode->crtc_clock);
1198
1199         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200          * bpc in between. */
1201         bpp = pipe_config->pipe_bpp;
1202         if (is_edp(intel_dp)) {
1203                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1204                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205                                       dev_priv->vbt.edp_bpp);
1206                         bpp = dev_priv->vbt.edp_bpp;
1207                 }
1208
1209                 /*
1210                  * Use the maximum clock and number of lanes the eDP panel
1211                  * advertizes being capable of. The panels are generally
1212                  * designed to support only a single clock and lane
1213                  * configuration, and typically these values correspond to the
1214                  * native resolution of the panel.
1215                  */
1216                 min_lane_count = max_lane_count;
1217                 min_clock = max_clock;
1218         }
1219
1220         for (; bpp >= 6*3; bpp -= 2*3) {
1221                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1222                                                    bpp);
1223
1224                 for (clock = min_clock; clock <= max_clock; clock++) {
1225                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1226                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1227                                 link_avail = intel_dp_max_data_rate(link_clock,
1228                                                                     lane_count);
1229
1230                                 if (mode_rate <= link_avail) {
1231                                         goto found;
1232                                 }
1233                         }
1234                 }
1235         }
1236
1237         return false;
1238
1239 found:
1240         if (intel_dp->color_range_auto) {
1241                 /*
1242                  * See:
1243                  * CEA-861-E - 5.1 Default Encoding Parameters
1244                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1245                  */
1246                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1247                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1248                 else
1249                         intel_dp->color_range = 0;
1250         }
1251
1252         if (intel_dp->color_range)
1253                 pipe_config->limited_color_range = true;
1254
1255         intel_dp->link_bw = bws[clock];
1256         intel_dp->lane_count = lane_count;
1257         pipe_config->pipe_bpp = bpp;
1258         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1259
1260         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261                       intel_dp->link_bw, intel_dp->lane_count,
1262                       pipe_config->port_clock, bpp);
1263         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264                       mode_rate, link_avail);
1265
1266         intel_link_compute_m_n(bpp, lane_count,
1267                                adjusted_mode->crtc_clock,
1268                                pipe_config->port_clock,
1269                                &pipe_config->dp_m_n);
1270
1271         if (intel_connector->panel.downclock_mode != NULL &&
1272                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1273                         pipe_config->has_drrs = true;
1274                         intel_link_compute_m_n(bpp, lane_count,
1275                                 intel_connector->panel.downclock_mode->clock,
1276                                 pipe_config->port_clock,
1277                                 &pipe_config->dp_m2_n2);
1278         }
1279
1280         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1281                 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1282         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1283                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1284         else
1285                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1286
1287         return true;
1288 }
1289
1290 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1291 {
1292         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1293         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1294         struct drm_device *dev = crtc->base.dev;
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         u32 dpa_ctl;
1297
1298         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1299                       crtc->config->port_clock);
1300         dpa_ctl = I915_READ(DP_A);
1301         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1302
1303         if (crtc->config->port_clock == 162000) {
1304                 /* For a long time we've carried around a ILK-DevA w/a for the
1305                  * 160MHz clock. If we're really unlucky, it's still required.
1306                  */
1307                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1308                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1309                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1310         } else {
1311                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1312                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1313         }
1314
1315         I915_WRITE(DP_A, dpa_ctl);
1316
1317         POSTING_READ(DP_A);
1318         udelay(500);
1319 }
1320
1321 static void intel_dp_prepare(struct intel_encoder *encoder)
1322 {
1323         struct drm_device *dev = encoder->base.dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1326         enum port port = dp_to_dig_port(intel_dp)->port;
1327         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1328         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1329
1330         /*
1331          * There are four kinds of DP registers:
1332          *
1333          *      IBX PCH
1334          *      SNB CPU
1335          *      IVB CPU
1336          *      CPT PCH
1337          *
1338          * IBX PCH and CPU are the same for almost everything,
1339          * except that the CPU DP PLL is configured in this
1340          * register
1341          *
1342          * CPT PCH is quite different, having many bits moved
1343          * to the TRANS_DP_CTL register instead. That
1344          * configuration happens (oddly) in ironlake_pch_enable
1345          */
1346
1347         /* Preserve the BIOS-computed detected bit. This is
1348          * supposed to be read-only.
1349          */
1350         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1351
1352         /* Handle DP bits in common between all three register formats */
1353         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1354         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1355
1356         if (crtc->config->has_audio)
1357                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1358
1359         /* Split out the IBX/CPU vs CPT settings */
1360
1361         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1362                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1363                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1364                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1365                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1366                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1367
1368                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1369                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1370
1371                 intel_dp->DP |= crtc->pipe << 29;
1372         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1373                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1374                         intel_dp->DP |= intel_dp->color_range;
1375
1376                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1377                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1378                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1379                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1380                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1381
1382                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1383                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1384
1385                 if (!IS_CHERRYVIEW(dev)) {
1386                         if (crtc->pipe == 1)
1387                                 intel_dp->DP |= DP_PIPEB_SELECT;
1388                 } else {
1389                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1390                 }
1391         } else {
1392                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1393         }
1394 }
1395
1396 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1397 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1398
1399 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1400 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1401
1402 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1403 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1404
1405 static void wait_panel_status(struct intel_dp *intel_dp,
1406                                        u32 mask,
1407                                        u32 value)
1408 {
1409         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1410         struct drm_i915_private *dev_priv = dev->dev_private;
1411         u32 pp_stat_reg, pp_ctrl_reg;
1412
1413         lockdep_assert_held(&dev_priv->pps_mutex);
1414
1415         pp_stat_reg = _pp_stat_reg(intel_dp);
1416         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1417
1418         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1419                         mask, value,
1420                         I915_READ(pp_stat_reg),
1421                         I915_READ(pp_ctrl_reg));
1422
1423         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1424                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1425                                 I915_READ(pp_stat_reg),
1426                                 I915_READ(pp_ctrl_reg));
1427         }
1428
1429         DRM_DEBUG_KMS("Wait complete\n");
1430 }
1431
1432 static void wait_panel_on(struct intel_dp *intel_dp)
1433 {
1434         DRM_DEBUG_KMS("Wait for panel power on\n");
1435         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1436 }
1437
1438 static void wait_panel_off(struct intel_dp *intel_dp)
1439 {
1440         DRM_DEBUG_KMS("Wait for panel power off time\n");
1441         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1442 }
1443
1444 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1445 {
1446         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1447
1448         /* When we disable the VDD override bit last we have to do the manual
1449          * wait. */
1450         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1451                                        intel_dp->panel_power_cycle_delay);
1452
1453         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1454 }
1455
1456 static void wait_backlight_on(struct intel_dp *intel_dp)
1457 {
1458         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1459                                        intel_dp->backlight_on_delay);
1460 }
1461
1462 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1463 {
1464         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1465                                        intel_dp->backlight_off_delay);
1466 }
1467
1468 /* Read the current pp_control value, unlocking the register if it
1469  * is locked
1470  */
1471
1472 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1473 {
1474         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476         u32 control;
1477
1478         lockdep_assert_held(&dev_priv->pps_mutex);
1479
1480         control = I915_READ(_pp_ctrl_reg(intel_dp));
1481         control &= ~PANEL_UNLOCK_MASK;
1482         control |= PANEL_UNLOCK_REGS;
1483         return control;
1484 }
1485
1486 /*
1487  * Must be paired with edp_panel_vdd_off().
1488  * Must hold pps_mutex around the whole on/off sequence.
1489  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1490  */
1491 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1492 {
1493         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1494         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1495         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         enum intel_display_power_domain power_domain;
1498         u32 pp;
1499         u32 pp_stat_reg, pp_ctrl_reg;
1500         bool need_to_disable = !intel_dp->want_panel_vdd;
1501
1502         lockdep_assert_held(&dev_priv->pps_mutex);
1503
1504         if (!is_edp(intel_dp))
1505                 return false;
1506
1507         cancel_delayed_work(&intel_dp->panel_vdd_work);
1508         intel_dp->want_panel_vdd = true;
1509
1510         if (edp_have_panel_vdd(intel_dp))
1511                 return need_to_disable;
1512
1513         power_domain = intel_display_port_power_domain(intel_encoder);
1514         intel_display_power_get(dev_priv, power_domain);
1515
1516         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1517                       port_name(intel_dig_port->port));
1518
1519         if (!edp_have_panel_power(intel_dp))
1520                 wait_panel_power_cycle(intel_dp);
1521
1522         pp = ironlake_get_pp_control(intel_dp);
1523         pp |= EDP_FORCE_VDD;
1524
1525         pp_stat_reg = _pp_stat_reg(intel_dp);
1526         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1527
1528         I915_WRITE(pp_ctrl_reg, pp);
1529         POSTING_READ(pp_ctrl_reg);
1530         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1531                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1532         /*
1533          * If the panel wasn't on, delay before accessing aux channel
1534          */
1535         if (!edp_have_panel_power(intel_dp)) {
1536                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1537                               port_name(intel_dig_port->port));
1538                 msleep(intel_dp->panel_power_up_delay);
1539         }
1540
1541         return need_to_disable;
1542 }
1543
1544 /*
1545  * Must be paired with intel_edp_panel_vdd_off() or
1546  * intel_edp_panel_off().
1547  * Nested calls to these functions are not allowed since
1548  * we drop the lock. Caller must use some higher level
1549  * locking to prevent nested calls from other threads.
1550  */
1551 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1552 {
1553         bool vdd;
1554
1555         if (!is_edp(intel_dp))
1556                 return;
1557
1558         pps_lock(intel_dp);
1559         vdd = edp_panel_vdd_on(intel_dp);
1560         pps_unlock(intel_dp);
1561
1562         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1563              port_name(dp_to_dig_port(intel_dp)->port));
1564 }
1565
1566 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1567 {
1568         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         struct intel_digital_port *intel_dig_port =
1571                 dp_to_dig_port(intel_dp);
1572         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1573         enum intel_display_power_domain power_domain;
1574         u32 pp;
1575         u32 pp_stat_reg, pp_ctrl_reg;
1576
1577         lockdep_assert_held(&dev_priv->pps_mutex);
1578
1579         WARN_ON(intel_dp->want_panel_vdd);
1580
1581         if (!edp_have_panel_vdd(intel_dp))
1582                 return;
1583
1584         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1585                       port_name(intel_dig_port->port));
1586
1587         pp = ironlake_get_pp_control(intel_dp);
1588         pp &= ~EDP_FORCE_VDD;
1589
1590         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1591         pp_stat_reg = _pp_stat_reg(intel_dp);
1592
1593         I915_WRITE(pp_ctrl_reg, pp);
1594         POSTING_READ(pp_ctrl_reg);
1595
1596         /* Make sure sequencer is idle before allowing subsequent activity */
1597         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1598         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1599
1600         if ((pp & POWER_TARGET_ON) == 0)
1601                 intel_dp->last_power_cycle = jiffies;
1602
1603         power_domain = intel_display_port_power_domain(intel_encoder);
1604         intel_display_power_put(dev_priv, power_domain);
1605 }
1606
1607 static void edp_panel_vdd_work(struct work_struct *__work)
1608 {
1609         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1610                                                  struct intel_dp, panel_vdd_work);
1611
1612         pps_lock(intel_dp);
1613         if (!intel_dp->want_panel_vdd)
1614                 edp_panel_vdd_off_sync(intel_dp);
1615         pps_unlock(intel_dp);
1616 }
1617
1618 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1619 {
1620         unsigned long delay;
1621
1622         /*
1623          * Queue the timer to fire a long time from now (relative to the power
1624          * down delay) to keep the panel power up across a sequence of
1625          * operations.
1626          */
1627         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1628         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1629 }
1630
1631 /*
1632  * Must be paired with edp_panel_vdd_on().
1633  * Must hold pps_mutex around the whole on/off sequence.
1634  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1635  */
1636 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1637 {
1638         struct drm_i915_private *dev_priv =
1639                 intel_dp_to_dev(intel_dp)->dev_private;
1640
1641         lockdep_assert_held(&dev_priv->pps_mutex);
1642
1643         if (!is_edp(intel_dp))
1644                 return;
1645
1646         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1647              port_name(dp_to_dig_port(intel_dp)->port));
1648
1649         intel_dp->want_panel_vdd = false;
1650
1651         if (sync)
1652                 edp_panel_vdd_off_sync(intel_dp);
1653         else
1654                 edp_panel_vdd_schedule_off(intel_dp);
1655 }
1656
1657 static void edp_panel_on(struct intel_dp *intel_dp)
1658 {
1659         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1660         struct drm_i915_private *dev_priv = dev->dev_private;
1661         u32 pp;
1662         u32 pp_ctrl_reg;
1663
1664         lockdep_assert_held(&dev_priv->pps_mutex);
1665
1666         if (!is_edp(intel_dp))
1667                 return;
1668
1669         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1670                       port_name(dp_to_dig_port(intel_dp)->port));
1671
1672         if (WARN(edp_have_panel_power(intel_dp),
1673                  "eDP port %c panel power already on\n",
1674                  port_name(dp_to_dig_port(intel_dp)->port)))
1675                 return;
1676
1677         wait_panel_power_cycle(intel_dp);
1678
1679         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1680         pp = ironlake_get_pp_control(intel_dp);
1681         if (IS_GEN5(dev)) {
1682                 /* ILK workaround: disable reset around power sequence */
1683                 pp &= ~PANEL_POWER_RESET;
1684                 I915_WRITE(pp_ctrl_reg, pp);
1685                 POSTING_READ(pp_ctrl_reg);
1686         }
1687
1688         pp |= POWER_TARGET_ON;
1689         if (!IS_GEN5(dev))
1690                 pp |= PANEL_POWER_RESET;
1691
1692         I915_WRITE(pp_ctrl_reg, pp);
1693         POSTING_READ(pp_ctrl_reg);
1694
1695         wait_panel_on(intel_dp);
1696         intel_dp->last_power_on = jiffies;
1697
1698         if (IS_GEN5(dev)) {
1699                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1700                 I915_WRITE(pp_ctrl_reg, pp);
1701                 POSTING_READ(pp_ctrl_reg);
1702         }
1703 }
1704
1705 void intel_edp_panel_on(struct intel_dp *intel_dp)
1706 {
1707         if (!is_edp(intel_dp))
1708                 return;
1709
1710         pps_lock(intel_dp);
1711         edp_panel_on(intel_dp);
1712         pps_unlock(intel_dp);
1713 }
1714
1715
1716 static void edp_panel_off(struct intel_dp *intel_dp)
1717 {
1718         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1719         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1720         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         enum intel_display_power_domain power_domain;
1723         u32 pp;
1724         u32 pp_ctrl_reg;
1725
1726         lockdep_assert_held(&dev_priv->pps_mutex);
1727
1728         if (!is_edp(intel_dp))
1729                 return;
1730
1731         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1732                       port_name(dp_to_dig_port(intel_dp)->port));
1733
1734         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1735              port_name(dp_to_dig_port(intel_dp)->port));
1736
1737         pp = ironlake_get_pp_control(intel_dp);
1738         /* We need to switch off panel power _and_ force vdd, for otherwise some
1739          * panels get very unhappy and cease to work. */
1740         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1741                 EDP_BLC_ENABLE);
1742
1743         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1744
1745         intel_dp->want_panel_vdd = false;
1746
1747         I915_WRITE(pp_ctrl_reg, pp);
1748         POSTING_READ(pp_ctrl_reg);
1749
1750         intel_dp->last_power_cycle = jiffies;
1751         wait_panel_off(intel_dp);
1752
1753         /* We got a reference when we enabled the VDD. */
1754         power_domain = intel_display_port_power_domain(intel_encoder);
1755         intel_display_power_put(dev_priv, power_domain);
1756 }
1757
1758 void intel_edp_panel_off(struct intel_dp *intel_dp)
1759 {
1760         if (!is_edp(intel_dp))
1761                 return;
1762
1763         pps_lock(intel_dp);
1764         edp_panel_off(intel_dp);
1765         pps_unlock(intel_dp);
1766 }
1767
1768 /* Enable backlight in the panel power control. */
1769 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1770 {
1771         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1772         struct drm_device *dev = intel_dig_port->base.base.dev;
1773         struct drm_i915_private *dev_priv = dev->dev_private;
1774         u32 pp;
1775         u32 pp_ctrl_reg;
1776
1777         /*
1778          * If we enable the backlight right away following a panel power
1779          * on, we may see slight flicker as the panel syncs with the eDP
1780          * link.  So delay a bit to make sure the image is solid before
1781          * allowing it to appear.
1782          */
1783         wait_backlight_on(intel_dp);
1784
1785         pps_lock(intel_dp);
1786
1787         pp = ironlake_get_pp_control(intel_dp);
1788         pp |= EDP_BLC_ENABLE;
1789
1790         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1791
1792         I915_WRITE(pp_ctrl_reg, pp);
1793         POSTING_READ(pp_ctrl_reg);
1794
1795         pps_unlock(intel_dp);
1796 }
1797
1798 /* Enable backlight PWM and backlight PP control. */
1799 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1800 {
1801         if (!is_edp(intel_dp))
1802                 return;
1803
1804         DRM_DEBUG_KMS("\n");
1805
1806         intel_panel_enable_backlight(intel_dp->attached_connector);
1807         _intel_edp_backlight_on(intel_dp);
1808 }
1809
1810 /* Disable backlight in the panel power control. */
1811 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1812 {
1813         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1814         struct drm_i915_private *dev_priv = dev->dev_private;
1815         u32 pp;
1816         u32 pp_ctrl_reg;
1817
1818         if (!is_edp(intel_dp))
1819                 return;
1820
1821         pps_lock(intel_dp);
1822
1823         pp = ironlake_get_pp_control(intel_dp);
1824         pp &= ~EDP_BLC_ENABLE;
1825
1826         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1827
1828         I915_WRITE(pp_ctrl_reg, pp);
1829         POSTING_READ(pp_ctrl_reg);
1830
1831         pps_unlock(intel_dp);
1832
1833         intel_dp->last_backlight_off = jiffies;
1834         edp_wait_backlight_off(intel_dp);
1835 }
1836
1837 /* Disable backlight PP control and backlight PWM. */
1838 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1839 {
1840         if (!is_edp(intel_dp))
1841                 return;
1842
1843         DRM_DEBUG_KMS("\n");
1844
1845         _intel_edp_backlight_off(intel_dp);
1846         intel_panel_disable_backlight(intel_dp->attached_connector);
1847 }
1848
1849 /*
1850  * Hook for controlling the panel power control backlight through the bl_power
1851  * sysfs attribute. Take care to handle multiple calls.
1852  */
1853 static void intel_edp_backlight_power(struct intel_connector *connector,
1854                                       bool enable)
1855 {
1856         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1857         bool is_enabled;
1858
1859         pps_lock(intel_dp);
1860         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1861         pps_unlock(intel_dp);
1862
1863         if (is_enabled == enable)
1864                 return;
1865
1866         DRM_DEBUG_KMS("panel power control backlight %s\n",
1867                       enable ? "enable" : "disable");
1868
1869         if (enable)
1870                 _intel_edp_backlight_on(intel_dp);
1871         else
1872                 _intel_edp_backlight_off(intel_dp);
1873 }
1874
1875 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1876 {
1877         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1878         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1879         struct drm_device *dev = crtc->dev;
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         u32 dpa_ctl;
1882
1883         assert_pipe_disabled(dev_priv,
1884                              to_intel_crtc(crtc)->pipe);
1885
1886         DRM_DEBUG_KMS("\n");
1887         dpa_ctl = I915_READ(DP_A);
1888         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1889         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1890
1891         /* We don't adjust intel_dp->DP while tearing down the link, to
1892          * facilitate link retraining (e.g. after hotplug). Hence clear all
1893          * enable bits here to ensure that we don't enable too much. */
1894         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1895         intel_dp->DP |= DP_PLL_ENABLE;
1896         I915_WRITE(DP_A, intel_dp->DP);
1897         POSTING_READ(DP_A);
1898         udelay(200);
1899 }
1900
1901 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1902 {
1903         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1904         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1905         struct drm_device *dev = crtc->dev;
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         u32 dpa_ctl;
1908
1909         assert_pipe_disabled(dev_priv,
1910                              to_intel_crtc(crtc)->pipe);
1911
1912         dpa_ctl = I915_READ(DP_A);
1913         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1914              "dp pll off, should be on\n");
1915         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1916
1917         /* We can't rely on the value tracked for the DP register in
1918          * intel_dp->DP because link_down must not change that (otherwise link
1919          * re-training will fail. */
1920         dpa_ctl &= ~DP_PLL_ENABLE;
1921         I915_WRITE(DP_A, dpa_ctl);
1922         POSTING_READ(DP_A);
1923         udelay(200);
1924 }
1925
1926 /* If the sink supports it, try to set the power state appropriately */
1927 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1928 {
1929         int ret, i;
1930
1931         /* Should have a valid DPCD by this point */
1932         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1933                 return;
1934
1935         if (mode != DRM_MODE_DPMS_ON) {
1936                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1937                                          DP_SET_POWER_D3);
1938         } else {
1939                 /*
1940                  * When turning on, we need to retry for 1ms to give the sink
1941                  * time to wake up.
1942                  */
1943                 for (i = 0; i < 3; i++) {
1944                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1945                                                  DP_SET_POWER_D0);
1946                         if (ret == 1)
1947                                 break;
1948                         msleep(1);
1949                 }
1950         }
1951
1952         if (ret != 1)
1953                 DRM_DEBUG_KMS("failed to %s sink power state\n",
1954                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1955 }
1956
1957 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1958                                   enum pipe *pipe)
1959 {
1960         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1961         enum port port = dp_to_dig_port(intel_dp)->port;
1962         struct drm_device *dev = encoder->base.dev;
1963         struct drm_i915_private *dev_priv = dev->dev_private;
1964         enum intel_display_power_domain power_domain;
1965         u32 tmp;
1966
1967         power_domain = intel_display_port_power_domain(encoder);
1968         if (!intel_display_power_is_enabled(dev_priv, power_domain))
1969                 return false;
1970
1971         tmp = I915_READ(intel_dp->output_reg);
1972
1973         if (!(tmp & DP_PORT_EN))
1974                 return false;
1975
1976         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1977                 *pipe = PORT_TO_PIPE_CPT(tmp);
1978         } else if (IS_CHERRYVIEW(dev)) {
1979                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1980         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1981                 *pipe = PORT_TO_PIPE(tmp);
1982         } else {
1983                 u32 trans_sel;
1984                 u32 trans_dp;
1985                 int i;
1986
1987                 switch (intel_dp->output_reg) {
1988                 case PCH_DP_B:
1989                         trans_sel = TRANS_DP_PORT_SEL_B;
1990                         break;
1991                 case PCH_DP_C:
1992                         trans_sel = TRANS_DP_PORT_SEL_C;
1993                         break;
1994                 case PCH_DP_D:
1995                         trans_sel = TRANS_DP_PORT_SEL_D;
1996                         break;
1997                 default:
1998                         return true;
1999                 }
2000
2001                 for_each_pipe(dev_priv, i) {
2002                         trans_dp = I915_READ(TRANS_DP_CTL(i));
2003                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2004                                 *pipe = i;
2005                                 return true;
2006                         }
2007                 }
2008
2009                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2010                               intel_dp->output_reg);
2011         }
2012
2013         return true;
2014 }
2015
2016 static void intel_dp_get_config(struct intel_encoder *encoder,
2017                                 struct intel_crtc_state *pipe_config)
2018 {
2019         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2020         u32 tmp, flags = 0;
2021         struct drm_device *dev = encoder->base.dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         enum port port = dp_to_dig_port(intel_dp)->port;
2024         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2025         int dotclock;
2026
2027         tmp = I915_READ(intel_dp->output_reg);
2028         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2029                 pipe_config->has_audio = true;
2030
2031         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2032                 if (tmp & DP_SYNC_HS_HIGH)
2033                         flags |= DRM_MODE_FLAG_PHSYNC;
2034                 else
2035                         flags |= DRM_MODE_FLAG_NHSYNC;
2036
2037                 if (tmp & DP_SYNC_VS_HIGH)
2038                         flags |= DRM_MODE_FLAG_PVSYNC;
2039                 else
2040                         flags |= DRM_MODE_FLAG_NVSYNC;
2041         } else {
2042                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2043                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2044                         flags |= DRM_MODE_FLAG_PHSYNC;
2045                 else
2046                         flags |= DRM_MODE_FLAG_NHSYNC;
2047
2048                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2049                         flags |= DRM_MODE_FLAG_PVSYNC;
2050                 else
2051                         flags |= DRM_MODE_FLAG_NVSYNC;
2052         }
2053
2054         pipe_config->base.adjusted_mode.flags |= flags;
2055
2056         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2057             tmp & DP_COLOR_RANGE_16_235)
2058                 pipe_config->limited_color_range = true;
2059
2060         pipe_config->has_dp_encoder = true;
2061
2062         intel_dp_get_m_n(crtc, pipe_config);
2063
2064         if (port == PORT_A) {
2065                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2066                         pipe_config->port_clock = 162000;
2067                 else
2068                         pipe_config->port_clock = 270000;
2069         }
2070
2071         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2072                                             &pipe_config->dp_m_n);
2073
2074         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2075                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2076
2077         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2078
2079         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2080             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2081                 /*
2082                  * This is a big fat ugly hack.
2083                  *
2084                  * Some machines in UEFI boot mode provide us a VBT that has 18
2085                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2086                  * unknown we fail to light up. Yet the same BIOS boots up with
2087                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2088                  * max, not what it tells us to use.
2089                  *
2090                  * Note: This will still be broken if the eDP panel is not lit
2091                  * up by the BIOS, and thus we can't get the mode at module
2092                  * load.
2093                  */
2094                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2095                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2096                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2097         }
2098 }
2099
2100 static void intel_disable_dp(struct intel_encoder *encoder)
2101 {
2102         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103         struct drm_device *dev = encoder->base.dev;
2104         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2105
2106         if (crtc->config->has_audio)
2107                 intel_audio_codec_disable(encoder);
2108
2109         if (HAS_PSR(dev) && !HAS_DDI(dev))
2110                 intel_psr_disable(intel_dp);
2111
2112         /* Make sure the panel is off before trying to change the mode. But also
2113          * ensure that we have vdd while we switch off the panel. */
2114         intel_edp_panel_vdd_on(intel_dp);
2115         intel_edp_backlight_off(intel_dp);
2116         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2117         intel_edp_panel_off(intel_dp);
2118
2119         /* disable the port before the pipe on g4x */
2120         if (INTEL_INFO(dev)->gen < 5)
2121                 intel_dp_link_down(intel_dp);
2122 }
2123
2124 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2125 {
2126         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2127         enum port port = dp_to_dig_port(intel_dp)->port;
2128
2129         intel_dp_link_down(intel_dp);
2130         if (port == PORT_A)
2131                 ironlake_edp_pll_off(intel_dp);
2132 }
2133
2134 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2135 {
2136         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2137
2138         intel_dp_link_down(intel_dp);
2139 }
2140
2141 static void chv_post_disable_dp(struct intel_encoder *encoder)
2142 {
2143         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2144         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2145         struct drm_device *dev = encoder->base.dev;
2146         struct drm_i915_private *dev_priv = dev->dev_private;
2147         struct intel_crtc *intel_crtc =
2148                 to_intel_crtc(encoder->base.crtc);
2149         enum dpio_channel ch = vlv_dport_to_channel(dport);
2150         enum pipe pipe = intel_crtc->pipe;
2151         u32 val;
2152
2153         intel_dp_link_down(intel_dp);
2154
2155         mutex_lock(&dev_priv->dpio_lock);
2156
2157         /* Propagate soft reset to data lane reset */
2158         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2159         val |= CHV_PCS_REQ_SOFTRESET_EN;
2160         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2161
2162         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2163         val |= CHV_PCS_REQ_SOFTRESET_EN;
2164         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2165
2166         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2167         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2168         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2169
2170         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2171         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2172         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2173
2174         mutex_unlock(&dev_priv->dpio_lock);
2175 }
2176
2177 static void
2178 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2179                          uint32_t *DP,
2180                          uint8_t dp_train_pat)
2181 {
2182         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2183         struct drm_device *dev = intel_dig_port->base.base.dev;
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         enum port port = intel_dig_port->port;
2186
2187         if (HAS_DDI(dev)) {
2188                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2189
2190                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2191                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2192                 else
2193                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2194
2195                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2196                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2197                 case DP_TRAINING_PATTERN_DISABLE:
2198                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2199
2200                         break;
2201                 case DP_TRAINING_PATTERN_1:
2202                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2203                         break;
2204                 case DP_TRAINING_PATTERN_2:
2205                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2206                         break;
2207                 case DP_TRAINING_PATTERN_3:
2208                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2209                         break;
2210                 }
2211                 I915_WRITE(DP_TP_CTL(port), temp);
2212
2213         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2214                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2215
2216                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2217                 case DP_TRAINING_PATTERN_DISABLE:
2218                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2219                         break;
2220                 case DP_TRAINING_PATTERN_1:
2221                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2222                         break;
2223                 case DP_TRAINING_PATTERN_2:
2224                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2225                         break;
2226                 case DP_TRAINING_PATTERN_3:
2227                         DRM_ERROR("DP training pattern 3 not supported\n");
2228                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2229                         break;
2230                 }
2231
2232         } else {
2233                 if (IS_CHERRYVIEW(dev))
2234                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2235                 else
2236                         *DP &= ~DP_LINK_TRAIN_MASK;
2237
2238                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2239                 case DP_TRAINING_PATTERN_DISABLE:
2240                         *DP |= DP_LINK_TRAIN_OFF;
2241                         break;
2242                 case DP_TRAINING_PATTERN_1:
2243                         *DP |= DP_LINK_TRAIN_PAT_1;
2244                         break;
2245                 case DP_TRAINING_PATTERN_2:
2246                         *DP |= DP_LINK_TRAIN_PAT_2;
2247                         break;
2248                 case DP_TRAINING_PATTERN_3:
2249                         if (IS_CHERRYVIEW(dev)) {
2250                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2251                         } else {
2252                                 DRM_ERROR("DP training pattern 3 not supported\n");
2253                                 *DP |= DP_LINK_TRAIN_PAT_2;
2254                         }
2255                         break;
2256                 }
2257         }
2258 }
2259
2260 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2261 {
2262         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2263         struct drm_i915_private *dev_priv = dev->dev_private;
2264
2265         /* enable with pattern 1 (as per spec) */
2266         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2267                                  DP_TRAINING_PATTERN_1);
2268
2269         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2270         POSTING_READ(intel_dp->output_reg);
2271
2272         /*
2273          * Magic for VLV/CHV. We _must_ first set up the register
2274          * without actually enabling the port, and then do another
2275          * write to enable the port. Otherwise link training will
2276          * fail when the power sequencer is freshly used for this port.
2277          */
2278         intel_dp->DP |= DP_PORT_EN;
2279
2280         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2281         POSTING_READ(intel_dp->output_reg);
2282 }
2283
2284 static void intel_enable_dp(struct intel_encoder *encoder)
2285 {
2286         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2287         struct drm_device *dev = encoder->base.dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2290         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2291
2292         if (WARN_ON(dp_reg & DP_PORT_EN))
2293                 return;
2294
2295         pps_lock(intel_dp);
2296
2297         if (IS_VALLEYVIEW(dev))
2298                 vlv_init_panel_power_sequencer(intel_dp);
2299
2300         intel_dp_enable_port(intel_dp);
2301
2302         edp_panel_vdd_on(intel_dp);
2303         edp_panel_on(intel_dp);
2304         edp_panel_vdd_off(intel_dp, true);
2305
2306         pps_unlock(intel_dp);
2307
2308         if (IS_VALLEYVIEW(dev))
2309                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2310
2311         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2312         intel_dp_start_link_train(intel_dp);
2313         intel_dp_complete_link_train(intel_dp);
2314         intel_dp_stop_link_train(intel_dp);
2315
2316         if (crtc->config->has_audio) {
2317                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2318                                  pipe_name(crtc->pipe));
2319                 intel_audio_codec_enable(encoder);
2320         }
2321 }
2322
2323 static void g4x_enable_dp(struct intel_encoder *encoder)
2324 {
2325         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2326
2327         intel_enable_dp(encoder);
2328         intel_edp_backlight_on(intel_dp);
2329 }
2330
2331 static void vlv_enable_dp(struct intel_encoder *encoder)
2332 {
2333         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2334
2335         intel_edp_backlight_on(intel_dp);
2336         intel_psr_enable(intel_dp);
2337 }
2338
2339 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2340 {
2341         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2342         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2343
2344         intel_dp_prepare(encoder);
2345
2346         /* Only ilk+ has port A */
2347         if (dport->port == PORT_A) {
2348                 ironlake_set_pll_cpu_edp(intel_dp);
2349                 ironlake_edp_pll_on(intel_dp);
2350         }
2351 }
2352
2353 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2354 {
2355         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2356         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2357         enum pipe pipe = intel_dp->pps_pipe;
2358         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2359
2360         edp_panel_vdd_off_sync(intel_dp);
2361
2362         /*
2363          * VLV seems to get confused when multiple power seqeuencers
2364          * have the same port selected (even if only one has power/vdd
2365          * enabled). The failure manifests as vlv_wait_port_ready() failing
2366          * CHV on the other hand doesn't seem to mind having the same port
2367          * selected in multiple power seqeuencers, but let's clear the
2368          * port select always when logically disconnecting a power sequencer
2369          * from a port.
2370          */
2371         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2372                       pipe_name(pipe), port_name(intel_dig_port->port));
2373         I915_WRITE(pp_on_reg, 0);
2374         POSTING_READ(pp_on_reg);
2375
2376         intel_dp->pps_pipe = INVALID_PIPE;
2377 }
2378
2379 static void vlv_steal_power_sequencer(struct drm_device *dev,
2380                                       enum pipe pipe)
2381 {
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         struct intel_encoder *encoder;
2384
2385         lockdep_assert_held(&dev_priv->pps_mutex);
2386
2387         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2388                 return;
2389
2390         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2391                             base.head) {
2392                 struct intel_dp *intel_dp;
2393                 enum port port;
2394
2395                 if (encoder->type != INTEL_OUTPUT_EDP)
2396                         continue;
2397
2398                 intel_dp = enc_to_intel_dp(&encoder->base);
2399                 port = dp_to_dig_port(intel_dp)->port;
2400
2401                 if (intel_dp->pps_pipe != pipe)
2402                         continue;
2403
2404                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2405                               pipe_name(pipe), port_name(port));
2406
2407                 WARN(encoder->connectors_active,
2408                      "stealing pipe %c power sequencer from active eDP port %c\n",
2409                      pipe_name(pipe), port_name(port));
2410
2411                 /* make sure vdd is off before we steal it */
2412                 vlv_detach_power_sequencer(intel_dp);
2413         }
2414 }
2415
2416 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2417 {
2418         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2419         struct intel_encoder *encoder = &intel_dig_port->base;
2420         struct drm_device *dev = encoder->base.dev;
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2423
2424         lockdep_assert_held(&dev_priv->pps_mutex);
2425
2426         if (!is_edp(intel_dp))
2427                 return;
2428
2429         if (intel_dp->pps_pipe == crtc->pipe)
2430                 return;
2431
2432         /*
2433          * If another power sequencer was being used on this
2434          * port previously make sure to turn off vdd there while
2435          * we still have control of it.
2436          */
2437         if (intel_dp->pps_pipe != INVALID_PIPE)
2438                 vlv_detach_power_sequencer(intel_dp);
2439
2440         /*
2441          * We may be stealing the power
2442          * sequencer from another port.
2443          */
2444         vlv_steal_power_sequencer(dev, crtc->pipe);
2445
2446         /* now it's all ours */
2447         intel_dp->pps_pipe = crtc->pipe;
2448
2449         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2450                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2451
2452         /* init power sequencer on this pipe and port */
2453         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2454         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2455 }
2456
2457 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2458 {
2459         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2460         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2461         struct drm_device *dev = encoder->base.dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2464         enum dpio_channel port = vlv_dport_to_channel(dport);
2465         int pipe = intel_crtc->pipe;
2466         u32 val;
2467
2468         mutex_lock(&dev_priv->dpio_lock);
2469
2470         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2471         val = 0;
2472         if (pipe)
2473                 val |= (1<<21);
2474         else
2475                 val &= ~(1<<21);
2476         val |= 0x001000c4;
2477         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2478         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2479         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2480
2481         mutex_unlock(&dev_priv->dpio_lock);
2482
2483         intel_enable_dp(encoder);
2484 }
2485
2486 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2487 {
2488         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2489         struct drm_device *dev = encoder->base.dev;
2490         struct drm_i915_private *dev_priv = dev->dev_private;
2491         struct intel_crtc *intel_crtc =
2492                 to_intel_crtc(encoder->base.crtc);
2493         enum dpio_channel port = vlv_dport_to_channel(dport);
2494         int pipe = intel_crtc->pipe;
2495
2496         intel_dp_prepare(encoder);
2497
2498         /* Program Tx lane resets to default */
2499         mutex_lock(&dev_priv->dpio_lock);
2500         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2501                          DPIO_PCS_TX_LANE2_RESET |
2502                          DPIO_PCS_TX_LANE1_RESET);
2503         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2504                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2505                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2506                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2507                                  DPIO_PCS_CLK_SOFT_RESET);
2508
2509         /* Fix up inter-pair skew failure */
2510         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2511         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2512         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2513         mutex_unlock(&dev_priv->dpio_lock);
2514 }
2515
2516 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2517 {
2518         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2519         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2520         struct drm_device *dev = encoder->base.dev;
2521         struct drm_i915_private *dev_priv = dev->dev_private;
2522         struct intel_crtc *intel_crtc =
2523                 to_intel_crtc(encoder->base.crtc);
2524         enum dpio_channel ch = vlv_dport_to_channel(dport);
2525         int pipe = intel_crtc->pipe;
2526         int data, i;
2527         u32 val;
2528
2529         mutex_lock(&dev_priv->dpio_lock);
2530
2531         /* allow hardware to manage TX FIFO reset source */
2532         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2533         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2534         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2535
2536         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2537         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2538         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2539
2540         /* Deassert soft data lane reset*/
2541         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2542         val |= CHV_PCS_REQ_SOFTRESET_EN;
2543         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2544
2545         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2546         val |= CHV_PCS_REQ_SOFTRESET_EN;
2547         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2548
2549         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2550         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2551         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2552
2553         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2554         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2555         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2556
2557         /* Program Tx lane latency optimal setting*/
2558         for (i = 0; i < 4; i++) {
2559                 /* Set the latency optimal bit */
2560                 data = (i == 1) ? 0x0 : 0x6;
2561                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2562                                 data << DPIO_FRC_LATENCY_SHFIT);
2563
2564                 /* Set the upar bit */
2565                 data = (i == 1) ? 0x0 : 0x1;
2566                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2567                                 data << DPIO_UPAR_SHIFT);
2568         }
2569
2570         /* Data lane stagger programming */
2571         /* FIXME: Fix up value only after power analysis */
2572
2573         mutex_unlock(&dev_priv->dpio_lock);
2574
2575         intel_enable_dp(encoder);
2576 }
2577
2578 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2579 {
2580         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2581         struct drm_device *dev = encoder->base.dev;
2582         struct drm_i915_private *dev_priv = dev->dev_private;
2583         struct intel_crtc *intel_crtc =
2584                 to_intel_crtc(encoder->base.crtc);
2585         enum dpio_channel ch = vlv_dport_to_channel(dport);
2586         enum pipe pipe = intel_crtc->pipe;
2587         u32 val;
2588
2589         intel_dp_prepare(encoder);
2590
2591         mutex_lock(&dev_priv->dpio_lock);
2592
2593         /* program left/right clock distribution */
2594         if (pipe != PIPE_B) {
2595                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2596                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2597                 if (ch == DPIO_CH0)
2598                         val |= CHV_BUFLEFTENA1_FORCE;
2599                 if (ch == DPIO_CH1)
2600                         val |= CHV_BUFRIGHTENA1_FORCE;
2601                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2602         } else {
2603                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2604                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2605                 if (ch == DPIO_CH0)
2606                         val |= CHV_BUFLEFTENA2_FORCE;
2607                 if (ch == DPIO_CH1)
2608                         val |= CHV_BUFRIGHTENA2_FORCE;
2609                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2610         }
2611
2612         /* program clock channel usage */
2613         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2614         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2615         if (pipe != PIPE_B)
2616                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2617         else
2618                 val |= CHV_PCS_USEDCLKCHANNEL;
2619         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2620
2621         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2622         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2623         if (pipe != PIPE_B)
2624                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2625         else
2626                 val |= CHV_PCS_USEDCLKCHANNEL;
2627         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2628
2629         /*
2630          * This a a bit weird since generally CL
2631          * matches the pipe, but here we need to
2632          * pick the CL based on the port.
2633          */
2634         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2635         if (pipe != PIPE_B)
2636                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2637         else
2638                 val |= CHV_CMN_USEDCLKCHANNEL;
2639         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2640
2641         mutex_unlock(&dev_priv->dpio_lock);
2642 }
2643
2644 /*
2645  * Native read with retry for link status and receiver capability reads for
2646  * cases where the sink may still be asleep.
2647  *
2648  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2649  * supposed to retry 3 times per the spec.
2650  */
2651 static ssize_t
2652 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2653                         void *buffer, size_t size)
2654 {
2655         ssize_t ret;
2656         int i;
2657
2658         /*
2659          * Sometime we just get the same incorrect byte repeated
2660          * over the entire buffer. Doing just one throw away read
2661          * initially seems to "solve" it.
2662          */
2663         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2664
2665         for (i = 0; i < 3; i++) {
2666                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2667                 if (ret == size)
2668                         return ret;
2669                 msleep(1);
2670         }
2671
2672         return ret;
2673 }
2674
2675 /*
2676  * Fetch AUX CH registers 0x202 - 0x207 which contain
2677  * link status information
2678  */
2679 static bool
2680 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2681 {
2682         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2683                                        DP_LANE0_1_STATUS,
2684                                        link_status,
2685                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2686 }
2687
2688 /* These are source-specific values. */
2689 static uint8_t
2690 intel_dp_voltage_max(struct intel_dp *intel_dp)
2691 {
2692         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2693         enum port port = dp_to_dig_port(intel_dp)->port;
2694
2695         if (INTEL_INFO(dev)->gen >= 9)
2696                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2697         else if (IS_VALLEYVIEW(dev))
2698                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2699         else if (IS_GEN7(dev) && port == PORT_A)
2700                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2701         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2702                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2703         else
2704                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2705 }
2706
2707 static uint8_t
2708 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2709 {
2710         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2711         enum port port = dp_to_dig_port(intel_dp)->port;
2712
2713         if (INTEL_INFO(dev)->gen >= 9) {
2714                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2716                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2717                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2718                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2720                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2721                 default:
2722                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2723                 }
2724         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2725                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2726                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2727                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2728                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2729                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2730                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2731                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2732                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2733                 default:
2734                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2735                 }
2736         } else if (IS_VALLEYVIEW(dev)) {
2737                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2738                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2739                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2740                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2741                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2742                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2743                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2744                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2745                 default:
2746                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2747                 }
2748         } else if (IS_GEN7(dev) && port == PORT_A) {
2749                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2750                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2751                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2752                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2753                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2754                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2755                 default:
2756                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2757                 }
2758         } else {
2759                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2760                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2761                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2762                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2763                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2764                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2765                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2766                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2767                 default:
2768                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2769                 }
2770         }
2771 }
2772
2773 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2774 {
2775         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2778         struct intel_crtc *intel_crtc =
2779                 to_intel_crtc(dport->base.base.crtc);
2780         unsigned long demph_reg_value, preemph_reg_value,
2781                 uniqtranscale_reg_value;
2782         uint8_t train_set = intel_dp->train_set[0];
2783         enum dpio_channel port = vlv_dport_to_channel(dport);
2784         int pipe = intel_crtc->pipe;
2785
2786         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2787         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2788                 preemph_reg_value = 0x0004000;
2789                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2790                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2791                         demph_reg_value = 0x2B405555;
2792                         uniqtranscale_reg_value = 0x552AB83A;
2793                         break;
2794                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2795                         demph_reg_value = 0x2B404040;
2796                         uniqtranscale_reg_value = 0x5548B83A;
2797                         break;
2798                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2799                         demph_reg_value = 0x2B245555;
2800                         uniqtranscale_reg_value = 0x5560B83A;
2801                         break;
2802                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2803                         demph_reg_value = 0x2B405555;
2804                         uniqtranscale_reg_value = 0x5598DA3A;
2805                         break;
2806                 default:
2807                         return 0;
2808                 }
2809                 break;
2810         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2811                 preemph_reg_value = 0x0002000;
2812                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2813                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2814                         demph_reg_value = 0x2B404040;
2815                         uniqtranscale_reg_value = 0x5552B83A;
2816                         break;
2817                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2818                         demph_reg_value = 0x2B404848;
2819                         uniqtranscale_reg_value = 0x5580B83A;
2820                         break;
2821                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2822                         demph_reg_value = 0x2B404040;
2823                         uniqtranscale_reg_value = 0x55ADDA3A;
2824                         break;
2825                 default:
2826                         return 0;
2827                 }
2828                 break;
2829         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2830                 preemph_reg_value = 0x0000000;
2831                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2832                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2833                         demph_reg_value = 0x2B305555;
2834                         uniqtranscale_reg_value = 0x5570B83A;
2835                         break;
2836                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2837                         demph_reg_value = 0x2B2B4040;
2838                         uniqtranscale_reg_value = 0x55ADDA3A;
2839                         break;
2840                 default:
2841                         return 0;
2842                 }
2843                 break;
2844         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2845                 preemph_reg_value = 0x0006000;
2846                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2847                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2848                         demph_reg_value = 0x1B405555;
2849                         uniqtranscale_reg_value = 0x55ADDA3A;
2850                         break;
2851                 default:
2852                         return 0;
2853                 }
2854                 break;
2855         default:
2856                 return 0;
2857         }
2858
2859         mutex_lock(&dev_priv->dpio_lock);
2860         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2861         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2862         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2863                          uniqtranscale_reg_value);
2864         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2865         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2866         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2867         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2868         mutex_unlock(&dev_priv->dpio_lock);
2869
2870         return 0;
2871 }
2872
2873 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2874 {
2875         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2878         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2879         u32 deemph_reg_value, margin_reg_value, val;
2880         uint8_t train_set = intel_dp->train_set[0];
2881         enum dpio_channel ch = vlv_dport_to_channel(dport);
2882         enum pipe pipe = intel_crtc->pipe;
2883         int i;
2884
2885         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2886         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2887                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2888                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2889                         deemph_reg_value = 128;
2890                         margin_reg_value = 52;
2891                         break;
2892                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2893                         deemph_reg_value = 128;
2894                         margin_reg_value = 77;
2895                         break;
2896                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2897                         deemph_reg_value = 128;
2898                         margin_reg_value = 102;
2899                         break;
2900                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2901                         deemph_reg_value = 128;
2902                         margin_reg_value = 154;
2903                         /* FIXME extra to set for 1200 */
2904                         break;
2905                 default:
2906                         return 0;
2907                 }
2908                 break;
2909         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2910                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2911                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2912                         deemph_reg_value = 85;
2913                         margin_reg_value = 78;
2914                         break;
2915                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2916                         deemph_reg_value = 85;
2917                         margin_reg_value = 116;
2918                         break;
2919                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2920                         deemph_reg_value = 85;
2921                         margin_reg_value = 154;
2922                         break;
2923                 default:
2924                         return 0;
2925                 }
2926                 break;
2927         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2928                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2929                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2930                         deemph_reg_value = 64;
2931                         margin_reg_value = 104;
2932                         break;
2933                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2934                         deemph_reg_value = 64;
2935                         margin_reg_value = 154;
2936                         break;
2937                 default:
2938                         return 0;
2939                 }
2940                 break;
2941         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2942                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2943                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2944                         deemph_reg_value = 43;
2945                         margin_reg_value = 154;
2946                         break;
2947                 default:
2948                         return 0;
2949                 }
2950                 break;
2951         default:
2952                 return 0;
2953         }
2954
2955         mutex_lock(&dev_priv->dpio_lock);
2956
2957         /* Clear calc init */
2958         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2959         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2960         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2961         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2962         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2963
2964         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2965         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2966         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2967         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
2968         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2969
2970         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2971         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2972         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2973         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2974
2975         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2976         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2977         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2978         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2979
2980         /* Program swing deemph */
2981         for (i = 0; i < 4; i++) {
2982                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2983                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2984                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2985                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2986         }
2987
2988         /* Program swing margin */
2989         for (i = 0; i < 4; i++) {
2990                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2991                 val &= ~DPIO_SWING_MARGIN000_MASK;
2992                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2993                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2994         }
2995
2996         /* Disable unique transition scale */
2997         for (i = 0; i < 4; i++) {
2998                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2999                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3000                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3001         }
3002
3003         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3004                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3005                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3006                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3007
3008                 /*
3009                  * The document said it needs to set bit 27 for ch0 and bit 26
3010                  * for ch1. Might be a typo in the doc.
3011                  * For now, for this unique transition scale selection, set bit
3012                  * 27 for ch0 and ch1.
3013                  */
3014                 for (i = 0; i < 4; i++) {
3015                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3016                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3017                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3018                 }
3019
3020                 for (i = 0; i < 4; i++) {
3021                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3022                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3023                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3024                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3025                 }
3026         }
3027
3028         /* Start swing calculation */
3029         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3030         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3031         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3032
3033         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3034         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3035         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3036
3037         /* LRC Bypass */
3038         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3039         val |= DPIO_LRC_BYPASS;
3040         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3041
3042         mutex_unlock(&dev_priv->dpio_lock);
3043
3044         return 0;
3045 }
3046
3047 static void
3048 intel_get_adjust_train(struct intel_dp *intel_dp,
3049                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3050 {
3051         uint8_t v = 0;
3052         uint8_t p = 0;
3053         int lane;
3054         uint8_t voltage_max;
3055         uint8_t preemph_max;
3056
3057         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3058                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3059                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3060
3061                 if (this_v > v)
3062                         v = this_v;
3063                 if (this_p > p)
3064                         p = this_p;
3065         }
3066
3067         voltage_max = intel_dp_voltage_max(intel_dp);
3068         if (v >= voltage_max)
3069                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3070
3071         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3072         if (p >= preemph_max)
3073                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3074
3075         for (lane = 0; lane < 4; lane++)
3076                 intel_dp->train_set[lane] = v | p;
3077 }
3078
3079 static uint32_t
3080 intel_gen4_signal_levels(uint8_t train_set)
3081 {
3082         uint32_t        signal_levels = 0;
3083
3084         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3085         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3086         default:
3087                 signal_levels |= DP_VOLTAGE_0_4;
3088                 break;
3089         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3090                 signal_levels |= DP_VOLTAGE_0_6;
3091                 break;
3092         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3093                 signal_levels |= DP_VOLTAGE_0_8;
3094                 break;
3095         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3096                 signal_levels |= DP_VOLTAGE_1_2;
3097                 break;
3098         }
3099         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3100         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3101         default:
3102                 signal_levels |= DP_PRE_EMPHASIS_0;
3103                 break;
3104         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3105                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3106                 break;
3107         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3108                 signal_levels |= DP_PRE_EMPHASIS_6;
3109                 break;
3110         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3111                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3112                 break;
3113         }
3114         return signal_levels;
3115 }
3116
3117 /* Gen6's DP voltage swing and pre-emphasis control */
3118 static uint32_t
3119 intel_gen6_edp_signal_levels(uint8_t train_set)
3120 {
3121         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3122                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3123         switch (signal_levels) {
3124         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3125         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3126                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3127         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3128                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3129         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3130         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3131                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3132         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3133         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3134                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3135         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3136         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3137                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3138         default:
3139                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3140                               "0x%x\n", signal_levels);
3141                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3142         }
3143 }
3144
3145 /* Gen7's DP voltage swing and pre-emphasis control */
3146 static uint32_t
3147 intel_gen7_edp_signal_levels(uint8_t train_set)
3148 {
3149         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3150                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3151         switch (signal_levels) {
3152         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3153                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3154         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3155                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3156         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3157                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3158
3159         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3160                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3161         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3162                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3163
3164         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3165                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3166         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3167                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3168
3169         default:
3170                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3171                               "0x%x\n", signal_levels);
3172                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3173         }
3174 }
3175
3176 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3177 static uint32_t
3178 intel_hsw_signal_levels(uint8_t train_set)
3179 {
3180         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3181                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3182         switch (signal_levels) {
3183         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3184                 return DDI_BUF_TRANS_SELECT(0);
3185         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3186                 return DDI_BUF_TRANS_SELECT(1);
3187         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3188                 return DDI_BUF_TRANS_SELECT(2);
3189         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3190                 return DDI_BUF_TRANS_SELECT(3);
3191
3192         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3193                 return DDI_BUF_TRANS_SELECT(4);
3194         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3195                 return DDI_BUF_TRANS_SELECT(5);
3196         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3197                 return DDI_BUF_TRANS_SELECT(6);
3198
3199         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3200                 return DDI_BUF_TRANS_SELECT(7);
3201         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3202                 return DDI_BUF_TRANS_SELECT(8);
3203         default:
3204                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3205                               "0x%x\n", signal_levels);
3206                 return DDI_BUF_TRANS_SELECT(0);
3207         }
3208 }
3209
3210 /* Properly updates "DP" with the correct signal levels. */
3211 static void
3212 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3213 {
3214         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3215         enum port port = intel_dig_port->port;
3216         struct drm_device *dev = intel_dig_port->base.base.dev;
3217         uint32_t signal_levels, mask;
3218         uint8_t train_set = intel_dp->train_set[0];
3219
3220         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3221                 signal_levels = intel_hsw_signal_levels(train_set);
3222                 mask = DDI_BUF_EMP_MASK;
3223         } else if (IS_CHERRYVIEW(dev)) {
3224                 signal_levels = intel_chv_signal_levels(intel_dp);
3225                 mask = 0;
3226         } else if (IS_VALLEYVIEW(dev)) {
3227                 signal_levels = intel_vlv_signal_levels(intel_dp);
3228                 mask = 0;
3229         } else if (IS_GEN7(dev) && port == PORT_A) {
3230                 signal_levels = intel_gen7_edp_signal_levels(train_set);
3231                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3232         } else if (IS_GEN6(dev) && port == PORT_A) {
3233                 signal_levels = intel_gen6_edp_signal_levels(train_set);
3234                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3235         } else {
3236                 signal_levels = intel_gen4_signal_levels(train_set);
3237                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3238         }
3239
3240         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3241
3242         *DP = (*DP & ~mask) | signal_levels;
3243 }
3244
3245 static bool
3246 intel_dp_set_link_train(struct intel_dp *intel_dp,
3247                         uint32_t *DP,
3248                         uint8_t dp_train_pat)
3249 {
3250         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3251         struct drm_device *dev = intel_dig_port->base.base.dev;
3252         struct drm_i915_private *dev_priv = dev->dev_private;
3253         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3254         int ret, len;
3255
3256         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3257
3258         I915_WRITE(intel_dp->output_reg, *DP);
3259         POSTING_READ(intel_dp->output_reg);
3260
3261         buf[0] = dp_train_pat;
3262         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3263             DP_TRAINING_PATTERN_DISABLE) {
3264                 /* don't write DP_TRAINING_LANEx_SET on disable */
3265                 len = 1;
3266         } else {
3267                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3268                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3269                 len = intel_dp->lane_count + 1;
3270         }
3271
3272         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3273                                 buf, len);
3274
3275         return ret == len;
3276 }
3277
3278 static bool
3279 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3280                         uint8_t dp_train_pat)
3281 {
3282         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3283         intel_dp_set_signal_levels(intel_dp, DP);
3284         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3285 }
3286
3287 static bool
3288 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3289                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3290 {
3291         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3292         struct drm_device *dev = intel_dig_port->base.base.dev;
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         int ret;
3295
3296         intel_get_adjust_train(intel_dp, link_status);
3297         intel_dp_set_signal_levels(intel_dp, DP);
3298
3299         I915_WRITE(intel_dp->output_reg, *DP);
3300         POSTING_READ(intel_dp->output_reg);
3301
3302         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3303                                 intel_dp->train_set, intel_dp->lane_count);
3304
3305         return ret == intel_dp->lane_count;
3306 }
3307
3308 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3309 {
3310         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3311         struct drm_device *dev = intel_dig_port->base.base.dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313         enum port port = intel_dig_port->port;
3314         uint32_t val;
3315
3316         if (!HAS_DDI(dev))
3317                 return;
3318
3319         val = I915_READ(DP_TP_CTL(port));
3320         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3321         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3322         I915_WRITE(DP_TP_CTL(port), val);
3323
3324         /*
3325          * On PORT_A we can have only eDP in SST mode. There the only reason
3326          * we need to set idle transmission mode is to work around a HW issue
3327          * where we enable the pipe while not in idle link-training mode.
3328          * In this case there is requirement to wait for a minimum number of
3329          * idle patterns to be sent.
3330          */
3331         if (port == PORT_A)
3332                 return;
3333
3334         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3335                      1))
3336                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3337 }
3338
3339 /* Enable corresponding port and start training pattern 1 */
3340 void
3341 intel_dp_start_link_train(struct intel_dp *intel_dp)
3342 {
3343         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3344         struct drm_device *dev = encoder->dev;
3345         int i;
3346         uint8_t voltage;
3347         int voltage_tries, loop_tries;
3348         uint32_t DP = intel_dp->DP;
3349         uint8_t link_config[2];
3350
3351         if (HAS_DDI(dev))
3352                 intel_ddi_prepare_link_retrain(encoder);
3353
3354         /* Write the link configuration data */
3355         link_config[0] = intel_dp->link_bw;
3356         link_config[1] = intel_dp->lane_count;
3357         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3358                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3359         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3360
3361         link_config[0] = 0;
3362         link_config[1] = DP_SET_ANSI_8B10B;
3363         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3364
3365         DP |= DP_PORT_EN;
3366
3367         /* clock recovery */
3368         if (!intel_dp_reset_link_train(intel_dp, &DP,
3369                                        DP_TRAINING_PATTERN_1 |
3370                                        DP_LINK_SCRAMBLING_DISABLE)) {
3371                 DRM_ERROR("failed to enable link training\n");
3372                 return;
3373         }
3374
3375         voltage = 0xff;
3376         voltage_tries = 0;
3377         loop_tries = 0;
3378         for (;;) {
3379                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3380
3381                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3382                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3383                         DRM_ERROR("failed to get link status\n");
3384                         break;
3385                 }
3386
3387                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3388                         DRM_DEBUG_KMS("clock recovery OK\n");
3389                         break;
3390                 }
3391
3392                 /* Check to see if we've tried the max voltage */
3393                 for (i = 0; i < intel_dp->lane_count; i++)
3394                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3395                                 break;
3396                 if (i == intel_dp->lane_count) {
3397                         ++loop_tries;
3398                         if (loop_tries == 5) {
3399                                 DRM_ERROR("too many full retries, give up\n");
3400                                 break;
3401                         }
3402                         intel_dp_reset_link_train(intel_dp, &DP,
3403                                                   DP_TRAINING_PATTERN_1 |
3404                                                   DP_LINK_SCRAMBLING_DISABLE);
3405                         voltage_tries = 0;
3406                         continue;
3407                 }
3408
3409                 /* Check to see if we've tried the same voltage 5 times */
3410                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3411                         ++voltage_tries;
3412                         if (voltage_tries == 5) {
3413                                 DRM_ERROR("too many voltage retries, give up\n");
3414                                 break;
3415                         }
3416                 } else
3417                         voltage_tries = 0;
3418                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3419
3420                 /* Update training set as requested by target */
3421                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3422                         DRM_ERROR("failed to update link training\n");
3423                         break;
3424                 }
3425         }
3426
3427         intel_dp->DP = DP;
3428 }
3429
3430 void
3431 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3432 {
3433         bool channel_eq = false;
3434         int tries, cr_tries;
3435         uint32_t DP = intel_dp->DP;
3436         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3437
3438         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3439         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3440                 training_pattern = DP_TRAINING_PATTERN_3;
3441
3442         /* channel equalization */
3443         if (!intel_dp_set_link_train(intel_dp, &DP,
3444                                      training_pattern |
3445                                      DP_LINK_SCRAMBLING_DISABLE)) {
3446                 DRM_ERROR("failed to start channel equalization\n");
3447                 return;
3448         }
3449
3450         tries = 0;
3451         cr_tries = 0;
3452         channel_eq = false;
3453         for (;;) {
3454                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3455
3456                 if (cr_tries > 5) {
3457                         DRM_ERROR("failed to train DP, aborting\n");
3458                         break;
3459                 }
3460
3461                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3462                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3463                         DRM_ERROR("failed to get link status\n");
3464                         break;
3465                 }
3466
3467                 /* Make sure clock is still ok */
3468                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3469                         intel_dp_start_link_train(intel_dp);
3470                         intel_dp_set_link_train(intel_dp, &DP,
3471                                                 training_pattern |
3472                                                 DP_LINK_SCRAMBLING_DISABLE);
3473                         cr_tries++;
3474                         continue;
3475                 }
3476
3477                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3478                         channel_eq = true;
3479                         break;
3480                 }
3481
3482                 /* Try 5 times, then try clock recovery if that fails */
3483                 if (tries > 5) {
3484                         intel_dp_start_link_train(intel_dp);
3485                         intel_dp_set_link_train(intel_dp, &DP,
3486                                                 training_pattern |
3487                                                 DP_LINK_SCRAMBLING_DISABLE);
3488                         tries = 0;
3489                         cr_tries++;
3490                         continue;
3491                 }
3492
3493                 /* Update training set as requested by target */
3494                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3495                         DRM_ERROR("failed to update link training\n");
3496                         break;
3497                 }
3498                 ++tries;
3499         }
3500
3501         intel_dp_set_idle_link_train(intel_dp);
3502
3503         intel_dp->DP = DP;
3504
3505         if (channel_eq)
3506                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3507
3508 }
3509
3510 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3511 {
3512         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3513                                 DP_TRAINING_PATTERN_DISABLE);
3514 }
3515
3516 static void
3517 intel_dp_link_down(struct intel_dp *intel_dp)
3518 {
3519         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3520         enum port port = intel_dig_port->port;
3521         struct drm_device *dev = intel_dig_port->base.base.dev;
3522         struct drm_i915_private *dev_priv = dev->dev_private;
3523         struct intel_crtc *intel_crtc =
3524                 to_intel_crtc(intel_dig_port->base.base.crtc);
3525         uint32_t DP = intel_dp->DP;
3526
3527         if (WARN_ON(HAS_DDI(dev)))
3528                 return;
3529
3530         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3531                 return;
3532
3533         DRM_DEBUG_KMS("\n");
3534
3535         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3536                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3537                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3538         } else {
3539                 if (IS_CHERRYVIEW(dev))
3540                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3541                 else
3542                         DP &= ~DP_LINK_TRAIN_MASK;
3543                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3544         }
3545         POSTING_READ(intel_dp->output_reg);
3546
3547         if (HAS_PCH_IBX(dev) &&
3548             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3549                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3550
3551                 /* Hardware workaround: leaving our transcoder select
3552                  * set to transcoder B while it's off will prevent the
3553                  * corresponding HDMI output on transcoder A.
3554                  *
3555                  * Combine this with another hardware workaround:
3556                  * transcoder select bit can only be cleared while the
3557                  * port is enabled.
3558                  */
3559                 DP &= ~DP_PIPEB_SELECT;
3560                 I915_WRITE(intel_dp->output_reg, DP);
3561
3562                 /* Changes to enable or select take place the vblank
3563                  * after being written.
3564                  */
3565                 if (WARN_ON(crtc == NULL)) {
3566                         /* We should never try to disable a port without a crtc
3567                          * attached. For paranoia keep the code around for a
3568                          * bit. */
3569                         POSTING_READ(intel_dp->output_reg);
3570                         msleep(50);
3571                 } else
3572                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3573         }
3574
3575         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3576         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3577         POSTING_READ(intel_dp->output_reg);
3578         msleep(intel_dp->panel_power_down_delay);
3579 }
3580
3581 static bool
3582 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3583 {
3584         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3585         struct drm_device *dev = dig_port->base.base.dev;
3586         struct drm_i915_private *dev_priv = dev->dev_private;
3587
3588         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3589                                     sizeof(intel_dp->dpcd)) < 0)
3590                 return false; /* aux transfer failed */
3591
3592         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3593
3594         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3595                 return false; /* DPCD not present */
3596
3597         /* Check if the panel supports PSR */
3598         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3599         if (is_edp(intel_dp)) {
3600                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3601                                         intel_dp->psr_dpcd,
3602                                         sizeof(intel_dp->psr_dpcd));
3603                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3604                         dev_priv->psr.sink_support = true;
3605                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3606                 }
3607         }
3608
3609         /* Training Pattern 3 support, both source and sink */
3610         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3611             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3612             (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3613                 intel_dp->use_tps3 = true;
3614                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3615         } else
3616                 intel_dp->use_tps3 = false;
3617
3618         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3619               DP_DWN_STRM_PORT_PRESENT))
3620                 return true; /* native DP sink */
3621
3622         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3623                 return true; /* no per-port downstream info */
3624
3625         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3626                                     intel_dp->downstream_ports,
3627                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3628                 return false; /* downstream port status fetch failed */
3629
3630         return true;
3631 }
3632
3633 static void
3634 intel_dp_probe_oui(struct intel_dp *intel_dp)
3635 {
3636         u8 buf[3];
3637
3638         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3639                 return;
3640
3641         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3642                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3643                               buf[0], buf[1], buf[2]);
3644
3645         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3646                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3647                               buf[0], buf[1], buf[2]);
3648 }
3649
3650 static bool
3651 intel_dp_probe_mst(struct intel_dp *intel_dp)
3652 {
3653         u8 buf[1];
3654
3655         if (!intel_dp->can_mst)
3656                 return false;
3657
3658         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3659                 return false;
3660
3661         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3662                 if (buf[0] & DP_MST_CAP) {
3663                         DRM_DEBUG_KMS("Sink is MST capable\n");
3664                         intel_dp->is_mst = true;
3665                 } else {
3666                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3667                         intel_dp->is_mst = false;
3668                 }
3669         }
3670
3671         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3672         return intel_dp->is_mst;
3673 }
3674
3675 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3676 {
3677         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3678         struct drm_device *dev = intel_dig_port->base.base.dev;
3679         struct intel_crtc *intel_crtc =
3680                 to_intel_crtc(intel_dig_port->base.base.crtc);
3681         u8 buf;
3682         int test_crc_count;
3683         int attempts = 6;
3684
3685         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3686                 return -EIO;
3687
3688         if (!(buf & DP_TEST_CRC_SUPPORTED))
3689                 return -ENOTTY;
3690
3691         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3692                 return -EIO;
3693
3694         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3695                                 buf | DP_TEST_SINK_START) < 0)
3696                 return -EIO;
3697
3698         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3699                 return -EIO;
3700         test_crc_count = buf & DP_TEST_COUNT_MASK;
3701
3702         do {
3703                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3704                                       DP_TEST_SINK_MISC, &buf) < 0)
3705                         return -EIO;
3706                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3707         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3708
3709         if (attempts == 0) {
3710                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3711                 return -ETIMEDOUT;
3712         }
3713
3714         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3715                 return -EIO;
3716
3717         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3718                 return -EIO;
3719         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3720                                buf & ~DP_TEST_SINK_START) < 0)
3721                 return -EIO;
3722
3723         return 0;
3724 }
3725
3726 static bool
3727 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3728 {
3729         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3730                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3731                                        sink_irq_vector, 1) == 1;
3732 }
3733
3734 static bool
3735 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3736 {
3737         int ret;
3738
3739         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3740                                              DP_SINK_COUNT_ESI,
3741                                              sink_irq_vector, 14);
3742         if (ret != 14)
3743                 return false;
3744
3745         return true;
3746 }
3747
3748 static void
3749 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3750 {
3751         /* NAK by default */
3752         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3753 }
3754
3755 static int
3756 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3757 {
3758         bool bret;
3759
3760         if (intel_dp->is_mst) {
3761                 u8 esi[16] = { 0 };
3762                 int ret = 0;
3763                 int retry;
3764                 bool handled;
3765                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3766 go_again:
3767                 if (bret == true) {
3768
3769                         /* check link status - esi[10] = 0x200c */
3770                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3771                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3772                                 intel_dp_start_link_train(intel_dp);
3773                                 intel_dp_complete_link_train(intel_dp);
3774                                 intel_dp_stop_link_train(intel_dp);
3775                         }
3776
3777                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3778                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3779
3780                         if (handled) {
3781                                 for (retry = 0; retry < 3; retry++) {
3782                                         int wret;
3783                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3784                                                                  DP_SINK_COUNT_ESI+1,
3785                                                                  &esi[1], 3);
3786                                         if (wret == 3) {
3787                                                 break;
3788                                         }
3789                                 }
3790
3791                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3792                                 if (bret == true) {
3793                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3794                                         goto go_again;
3795                                 }
3796                         } else
3797                                 ret = 0;
3798
3799                         return ret;
3800                 } else {
3801                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3802                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3803                         intel_dp->is_mst = false;
3804                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3805                         /* send a hotplug event */
3806                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3807                 }
3808         }
3809         return -EINVAL;
3810 }
3811
3812 /*
3813  * According to DP spec
3814  * 5.1.2:
3815  *  1. Read DPCD
3816  *  2. Configure link according to Receiver Capabilities
3817  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3818  *  4. Check link status on receipt of hot-plug interrupt
3819  */
3820 void
3821 intel_dp_check_link_status(struct intel_dp *intel_dp)
3822 {
3823         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3824         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3825         u8 sink_irq_vector;
3826         u8 link_status[DP_LINK_STATUS_SIZE];
3827
3828         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3829
3830         if (!intel_encoder->connectors_active)
3831                 return;
3832
3833         if (WARN_ON(!intel_encoder->base.crtc))
3834                 return;
3835
3836         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3837                 return;
3838
3839         /* Try to read receiver status if the link appears to be up */
3840         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3841                 return;
3842         }
3843
3844         /* Now read the DPCD to see if it's actually running */
3845         if (!intel_dp_get_dpcd(intel_dp)) {
3846                 return;
3847         }
3848
3849         /* Try to read the source of the interrupt */
3850         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3851             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3852                 /* Clear interrupt source */
3853                 drm_dp_dpcd_writeb(&intel_dp->aux,
3854                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3855                                    sink_irq_vector);
3856
3857                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3858                         intel_dp_handle_test_request(intel_dp);
3859                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3860                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3861         }
3862
3863         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3864                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3865                               intel_encoder->base.name);
3866                 intel_dp_start_link_train(intel_dp);
3867                 intel_dp_complete_link_train(intel_dp);
3868                 intel_dp_stop_link_train(intel_dp);
3869         }
3870 }
3871
3872 /* XXX this is probably wrong for multiple downstream ports */
3873 static enum drm_connector_status
3874 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3875 {
3876         uint8_t *dpcd = intel_dp->dpcd;
3877         uint8_t type;
3878
3879         if (!intel_dp_get_dpcd(intel_dp))
3880                 return connector_status_disconnected;
3881
3882         /* if there's no downstream port, we're done */
3883         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3884                 return connector_status_connected;
3885
3886         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3887         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3888             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3889                 uint8_t reg;
3890
3891                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3892                                             &reg, 1) < 0)
3893                         return connector_status_unknown;
3894
3895                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3896                                               : connector_status_disconnected;
3897         }
3898
3899         /* If no HPD, poke DDC gently */
3900         if (drm_probe_ddc(&intel_dp->aux.ddc))
3901                 return connector_status_connected;
3902
3903         /* Well we tried, say unknown for unreliable port types */
3904         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3905                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3906                 if (type == DP_DS_PORT_TYPE_VGA ||
3907                     type == DP_DS_PORT_TYPE_NON_EDID)
3908                         return connector_status_unknown;
3909         } else {
3910                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3911                         DP_DWN_STRM_PORT_TYPE_MASK;
3912                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3913                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3914                         return connector_status_unknown;
3915         }
3916
3917         /* Anything else is out of spec, warn and ignore */
3918         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3919         return connector_status_disconnected;
3920 }
3921
3922 static enum drm_connector_status
3923 edp_detect(struct intel_dp *intel_dp)
3924 {
3925         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3926         enum drm_connector_status status;
3927
3928         status = intel_panel_detect(dev);
3929         if (status == connector_status_unknown)
3930                 status = connector_status_connected;
3931
3932         return status;
3933 }
3934
3935 static enum drm_connector_status
3936 ironlake_dp_detect(struct intel_dp *intel_dp)
3937 {
3938         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3939         struct drm_i915_private *dev_priv = dev->dev_private;
3940         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3941
3942         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3943                 return connector_status_disconnected;
3944
3945         return intel_dp_detect_dpcd(intel_dp);
3946 }
3947
3948 static int g4x_digital_port_connected(struct drm_device *dev,
3949                                        struct intel_digital_port *intel_dig_port)
3950 {
3951         struct drm_i915_private *dev_priv = dev->dev_private;
3952         uint32_t bit;
3953
3954         if (IS_VALLEYVIEW(dev)) {
3955                 switch (intel_dig_port->port) {
3956                 case PORT_B:
3957                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3958                         break;
3959                 case PORT_C:
3960                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3961                         break;
3962                 case PORT_D:
3963                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3964                         break;
3965                 default:
3966                         return -EINVAL;
3967                 }
3968         } else {
3969                 switch (intel_dig_port->port) {
3970                 case PORT_B:
3971                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3972                         break;
3973                 case PORT_C:
3974                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3975                         break;
3976                 case PORT_D:
3977                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3978                         break;
3979                 default:
3980                         return -EINVAL;
3981                 }
3982         }
3983
3984         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3985                 return 0;
3986         return 1;
3987 }
3988
3989 static enum drm_connector_status
3990 g4x_dp_detect(struct intel_dp *intel_dp)
3991 {
3992         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3993         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3994         int ret;
3995
3996         /* Can't disconnect eDP, but you can close the lid... */
3997         if (is_edp(intel_dp)) {
3998                 enum drm_connector_status status;
3999
4000                 status = intel_panel_detect(dev);
4001                 if (status == connector_status_unknown)
4002                         status = connector_status_connected;
4003                 return status;
4004         }
4005
4006         ret = g4x_digital_port_connected(dev, intel_dig_port);
4007         if (ret == -EINVAL)
4008                 return connector_status_unknown;
4009         else if (ret == 0)
4010                 return connector_status_disconnected;
4011
4012         return intel_dp_detect_dpcd(intel_dp);
4013 }
4014
4015 static struct edid *
4016 intel_dp_get_edid(struct intel_dp *intel_dp)
4017 {
4018         struct intel_connector *intel_connector = intel_dp->attached_connector;
4019
4020         /* use cached edid if we have one */
4021         if (intel_connector->edid) {
4022                 /* invalid edid */
4023                 if (IS_ERR(intel_connector->edid))
4024                         return NULL;
4025
4026                 return drm_edid_duplicate(intel_connector->edid);
4027         } else
4028                 return drm_get_edid(&intel_connector->base,
4029                                     &intel_dp->aux.ddc);
4030 }
4031
4032 static void
4033 intel_dp_set_edid(struct intel_dp *intel_dp)
4034 {
4035         struct intel_connector *intel_connector = intel_dp->attached_connector;
4036         struct edid *edid;
4037
4038         edid = intel_dp_get_edid(intel_dp);
4039         intel_connector->detect_edid = edid;
4040
4041         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4042                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4043         else
4044                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4045 }
4046
4047 static void
4048 intel_dp_unset_edid(struct intel_dp *intel_dp)
4049 {
4050         struct intel_connector *intel_connector = intel_dp->attached_connector;
4051
4052         kfree(intel_connector->detect_edid);
4053         intel_connector->detect_edid = NULL;
4054
4055         intel_dp->has_audio = false;
4056 }
4057
4058 static enum intel_display_power_domain
4059 intel_dp_power_get(struct intel_dp *dp)
4060 {
4061         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4062         enum intel_display_power_domain power_domain;
4063
4064         power_domain = intel_display_port_power_domain(encoder);
4065         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4066
4067         return power_domain;
4068 }
4069
4070 static void
4071 intel_dp_power_put(struct intel_dp *dp,
4072                    enum intel_display_power_domain power_domain)
4073 {
4074         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4075         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4076 }
4077
4078 static enum drm_connector_status
4079 intel_dp_detect(struct drm_connector *connector, bool force)
4080 {
4081         struct intel_dp *intel_dp = intel_attached_dp(connector);
4082         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4083         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4084         struct drm_device *dev = connector->dev;
4085         enum drm_connector_status status;
4086         enum intel_display_power_domain power_domain;
4087         bool ret;
4088
4089         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4090                       connector->base.id, connector->name);
4091         intel_dp_unset_edid(intel_dp);
4092
4093         if (intel_dp->is_mst) {
4094                 /* MST devices are disconnected from a monitor POV */
4095                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4096                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4097                 return connector_status_disconnected;
4098         }
4099
4100         power_domain = intel_dp_power_get(intel_dp);
4101
4102         /* Can't disconnect eDP, but you can close the lid... */
4103         if (is_edp(intel_dp))
4104                 status = edp_detect(intel_dp);
4105         else if (HAS_PCH_SPLIT(dev))
4106                 status = ironlake_dp_detect(intel_dp);
4107         else
4108                 status = g4x_dp_detect(intel_dp);
4109         if (status != connector_status_connected)
4110                 goto out;
4111
4112         intel_dp_probe_oui(intel_dp);
4113
4114         ret = intel_dp_probe_mst(intel_dp);
4115         if (ret) {
4116                 /* if we are in MST mode then this connector
4117                    won't appear connected or have anything with EDID on it */
4118                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4119                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4120                 status = connector_status_disconnected;
4121                 goto out;
4122         }
4123
4124         intel_dp_set_edid(intel_dp);
4125
4126         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4127                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4128         status = connector_status_connected;
4129
4130 out:
4131         intel_dp_power_put(intel_dp, power_domain);
4132         return status;
4133 }
4134
4135 static void
4136 intel_dp_force(struct drm_connector *connector)
4137 {
4138         struct intel_dp *intel_dp = intel_attached_dp(connector);
4139         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4140         enum intel_display_power_domain power_domain;
4141
4142         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4143                       connector->base.id, connector->name);
4144         intel_dp_unset_edid(intel_dp);
4145
4146         if (connector->status != connector_status_connected)
4147                 return;
4148
4149         power_domain = intel_dp_power_get(intel_dp);
4150
4151         intel_dp_set_edid(intel_dp);
4152
4153         intel_dp_power_put(intel_dp, power_domain);
4154
4155         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4156                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4157 }
4158
4159 static int intel_dp_get_modes(struct drm_connector *connector)
4160 {
4161         struct intel_connector *intel_connector = to_intel_connector(connector);
4162         struct edid *edid;
4163
4164         edid = intel_connector->detect_edid;
4165         if (edid) {
4166                 int ret = intel_connector_update_modes(connector, edid);
4167                 if (ret)
4168                         return ret;
4169         }
4170
4171         /* if eDP has no EDID, fall back to fixed mode */
4172         if (is_edp(intel_attached_dp(connector)) &&
4173             intel_connector->panel.fixed_mode) {
4174                 struct drm_display_mode *mode;
4175
4176                 mode = drm_mode_duplicate(connector->dev,
4177                                           intel_connector->panel.fixed_mode);
4178                 if (mode) {
4179                         drm_mode_probed_add(connector, mode);
4180                         return 1;
4181                 }
4182         }
4183
4184         return 0;
4185 }
4186
4187 static bool
4188 intel_dp_detect_audio(struct drm_connector *connector)
4189 {
4190         bool has_audio = false;
4191         struct edid *edid;
4192
4193         edid = to_intel_connector(connector)->detect_edid;
4194         if (edid)
4195                 has_audio = drm_detect_monitor_audio(edid);
4196
4197         return has_audio;
4198 }
4199
4200 static int
4201 intel_dp_set_property(struct drm_connector *connector,
4202                       struct drm_property *property,
4203                       uint64_t val)
4204 {
4205         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4206         struct intel_connector *intel_connector = to_intel_connector(connector);
4207         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4208         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4209         int ret;
4210
4211         ret = drm_object_property_set_value(&connector->base, property, val);
4212         if (ret)
4213                 return ret;
4214
4215         if (property == dev_priv->force_audio_property) {
4216                 int i = val;
4217                 bool has_audio;
4218
4219                 if (i == intel_dp->force_audio)
4220                         return 0;
4221
4222                 intel_dp->force_audio = i;
4223
4224                 if (i == HDMI_AUDIO_AUTO)
4225                         has_audio = intel_dp_detect_audio(connector);
4226                 else
4227                         has_audio = (i == HDMI_AUDIO_ON);
4228
4229                 if (has_audio == intel_dp->has_audio)
4230                         return 0;
4231
4232                 intel_dp->has_audio = has_audio;
4233                 goto done;
4234         }
4235
4236         if (property == dev_priv->broadcast_rgb_property) {
4237                 bool old_auto = intel_dp->color_range_auto;
4238                 uint32_t old_range = intel_dp->color_range;
4239
4240                 switch (val) {
4241                 case INTEL_BROADCAST_RGB_AUTO:
4242                         intel_dp->color_range_auto = true;
4243                         break;
4244                 case INTEL_BROADCAST_RGB_FULL:
4245                         intel_dp->color_range_auto = false;
4246                         intel_dp->color_range = 0;
4247                         break;
4248                 case INTEL_BROADCAST_RGB_LIMITED:
4249                         intel_dp->color_range_auto = false;
4250                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4251                         break;
4252                 default:
4253                         return -EINVAL;
4254                 }
4255
4256                 if (old_auto == intel_dp->color_range_auto &&
4257                     old_range == intel_dp->color_range)
4258                         return 0;
4259
4260                 goto done;
4261         }
4262
4263         if (is_edp(intel_dp) &&
4264             property == connector->dev->mode_config.scaling_mode_property) {
4265                 if (val == DRM_MODE_SCALE_NONE) {
4266                         DRM_DEBUG_KMS("no scaling not supported\n");
4267                         return -EINVAL;
4268                 }
4269
4270                 if (intel_connector->panel.fitting_mode == val) {
4271                         /* the eDP scaling property is not changed */
4272                         return 0;
4273                 }
4274                 intel_connector->panel.fitting_mode = val;
4275
4276                 goto done;
4277         }
4278
4279         return -EINVAL;
4280
4281 done:
4282         if (intel_encoder->base.crtc)
4283                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4284
4285         return 0;
4286 }
4287
4288 static void
4289 intel_dp_connector_destroy(struct drm_connector *connector)
4290 {
4291         struct intel_connector *intel_connector = to_intel_connector(connector);
4292
4293         kfree(intel_connector->detect_edid);
4294
4295         if (!IS_ERR_OR_NULL(intel_connector->edid))
4296                 kfree(intel_connector->edid);
4297
4298         /* Can't call is_edp() since the encoder may have been destroyed
4299          * already. */
4300         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4301                 intel_panel_fini(&intel_connector->panel);
4302
4303         drm_connector_cleanup(connector);
4304         kfree(connector);
4305 }
4306
4307 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4308 {
4309         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4310         struct intel_dp *intel_dp = &intel_dig_port->dp;
4311
4312         drm_dp_aux_unregister(&intel_dp->aux);
4313         intel_dp_mst_encoder_cleanup(intel_dig_port);
4314         if (is_edp(intel_dp)) {
4315                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4316                 /*
4317                  * vdd might still be enabled do to the delayed vdd off.
4318                  * Make sure vdd is actually turned off here.
4319                  */
4320                 pps_lock(intel_dp);
4321                 edp_panel_vdd_off_sync(intel_dp);
4322                 pps_unlock(intel_dp);
4323
4324                 if (intel_dp->edp_notifier.notifier_call) {
4325                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4326                         intel_dp->edp_notifier.notifier_call = NULL;
4327                 }
4328         }
4329         drm_encoder_cleanup(encoder);
4330         kfree(intel_dig_port);
4331 }
4332
4333 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4334 {
4335         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4336
4337         if (!is_edp(intel_dp))
4338                 return;
4339
4340         /*
4341          * vdd might still be enabled do to the delayed vdd off.
4342          * Make sure vdd is actually turned off here.
4343          */
4344         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4345         pps_lock(intel_dp);
4346         edp_panel_vdd_off_sync(intel_dp);
4347         pps_unlock(intel_dp);
4348 }
4349
4350 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4351 {
4352         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4353         struct drm_device *dev = intel_dig_port->base.base.dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         enum intel_display_power_domain power_domain;
4356
4357         lockdep_assert_held(&dev_priv->pps_mutex);
4358
4359         if (!edp_have_panel_vdd(intel_dp))
4360                 return;
4361
4362         /*
4363          * The VDD bit needs a power domain reference, so if the bit is
4364          * already enabled when we boot or resume, grab this reference and
4365          * schedule a vdd off, so we don't hold on to the reference
4366          * indefinitely.
4367          */
4368         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4369         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4370         intel_display_power_get(dev_priv, power_domain);
4371
4372         edp_panel_vdd_schedule_off(intel_dp);
4373 }
4374
4375 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4376 {
4377         struct intel_dp *intel_dp;
4378
4379         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4380                 return;
4381
4382         intel_dp = enc_to_intel_dp(encoder);
4383
4384         pps_lock(intel_dp);
4385
4386         /*
4387          * Read out the current power sequencer assignment,
4388          * in case the BIOS did something with it.
4389          */
4390         if (IS_VALLEYVIEW(encoder->dev))
4391                 vlv_initial_power_sequencer_setup(intel_dp);
4392
4393         intel_edp_panel_vdd_sanitize(intel_dp);
4394
4395         pps_unlock(intel_dp);
4396 }
4397
4398 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4399         .dpms = intel_connector_dpms,
4400         .detect = intel_dp_detect,
4401         .force = intel_dp_force,
4402         .fill_modes = drm_helper_probe_single_connector_modes,
4403         .set_property = intel_dp_set_property,
4404         .destroy = intel_dp_connector_destroy,
4405 };
4406
4407 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4408         .get_modes = intel_dp_get_modes,
4409         .mode_valid = intel_dp_mode_valid,
4410         .best_encoder = intel_best_encoder,
4411 };
4412
4413 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4414         .reset = intel_dp_encoder_reset,
4415         .destroy = intel_dp_encoder_destroy,
4416 };
4417
4418 void
4419 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4420 {
4421         return;
4422 }
4423
4424 enum irqreturn
4425 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4426 {
4427         struct intel_dp *intel_dp = &intel_dig_port->dp;
4428         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4429         struct drm_device *dev = intel_dig_port->base.base.dev;
4430         struct drm_i915_private *dev_priv = dev->dev_private;
4431         enum intel_display_power_domain power_domain;
4432         enum irqreturn ret = IRQ_NONE;
4433
4434         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4435                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4436
4437         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4438                 /*
4439                  * vdd off can generate a long pulse on eDP which
4440                  * would require vdd on to handle it, and thus we
4441                  * would end up in an endless cycle of
4442                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4443                  */
4444                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4445                               port_name(intel_dig_port->port));
4446                 return false;
4447         }
4448
4449         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4450                       port_name(intel_dig_port->port),
4451                       long_hpd ? "long" : "short");
4452
4453         power_domain = intel_display_port_power_domain(intel_encoder);
4454         intel_display_power_get(dev_priv, power_domain);
4455
4456         if (long_hpd) {
4457
4458                 if (HAS_PCH_SPLIT(dev)) {
4459                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4460                                 goto mst_fail;
4461                 } else {
4462                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4463                                 goto mst_fail;
4464                 }
4465
4466                 if (!intel_dp_get_dpcd(intel_dp)) {
4467                         goto mst_fail;
4468                 }
4469
4470                 intel_dp_probe_oui(intel_dp);
4471
4472                 if (!intel_dp_probe_mst(intel_dp))
4473                         goto mst_fail;
4474
4475         } else {
4476                 if (intel_dp->is_mst) {
4477                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4478                                 goto mst_fail;
4479                 }
4480
4481                 if (!intel_dp->is_mst) {
4482                         /*
4483                          * we'll check the link status via the normal hot plug path later -
4484                          * but for short hpds we should check it now
4485                          */
4486                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4487                         intel_dp_check_link_status(intel_dp);
4488                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4489                 }
4490         }
4491
4492         ret = IRQ_HANDLED;
4493
4494         goto put_power;
4495 mst_fail:
4496         /* if we were in MST mode, and device is not there get out of MST mode */
4497         if (intel_dp->is_mst) {
4498                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4499                 intel_dp->is_mst = false;
4500                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4501         }
4502 put_power:
4503         intel_display_power_put(dev_priv, power_domain);
4504
4505         return ret;
4506 }
4507
4508 /* Return which DP Port should be selected for Transcoder DP control */
4509 int
4510 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4511 {
4512         struct drm_device *dev = crtc->dev;
4513         struct intel_encoder *intel_encoder;
4514         struct intel_dp *intel_dp;
4515
4516         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4517                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4518
4519                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4520                     intel_encoder->type == INTEL_OUTPUT_EDP)
4521                         return intel_dp->output_reg;
4522         }
4523
4524         return -1;
4525 }
4526
4527 /* check the VBT to see whether the eDP is on DP-D port */
4528 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4529 {
4530         struct drm_i915_private *dev_priv = dev->dev_private;
4531         union child_device_config *p_child;
4532         int i;
4533         static const short port_mapping[] = {
4534                 [PORT_B] = PORT_IDPB,
4535                 [PORT_C] = PORT_IDPC,
4536                 [PORT_D] = PORT_IDPD,
4537         };
4538
4539         if (port == PORT_A)
4540                 return true;
4541
4542         if (!dev_priv->vbt.child_dev_num)
4543                 return false;
4544
4545         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4546                 p_child = dev_priv->vbt.child_dev + i;
4547
4548                 if (p_child->common.dvo_port == port_mapping[port] &&
4549                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4550                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4551                         return true;
4552         }
4553         return false;
4554 }
4555
4556 void
4557 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4558 {
4559         struct intel_connector *intel_connector = to_intel_connector(connector);
4560
4561         intel_attach_force_audio_property(connector);
4562         intel_attach_broadcast_rgb_property(connector);
4563         intel_dp->color_range_auto = true;
4564
4565         if (is_edp(intel_dp)) {
4566                 drm_mode_create_scaling_mode_property(connector->dev);
4567                 drm_object_attach_property(
4568                         &connector->base,
4569                         connector->dev->mode_config.scaling_mode_property,
4570                         DRM_MODE_SCALE_ASPECT);
4571                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4572         }
4573 }
4574
4575 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4576 {
4577         intel_dp->last_power_cycle = jiffies;
4578         intel_dp->last_power_on = jiffies;
4579         intel_dp->last_backlight_off = jiffies;
4580 }
4581
4582 static void
4583 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4584                                     struct intel_dp *intel_dp)
4585 {
4586         struct drm_i915_private *dev_priv = dev->dev_private;
4587         struct edp_power_seq cur, vbt, spec,
4588                 *final = &intel_dp->pps_delays;
4589         u32 pp_on, pp_off, pp_div, pp;
4590         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4591
4592         lockdep_assert_held(&dev_priv->pps_mutex);
4593
4594         /* already initialized? */
4595         if (final->t11_t12 != 0)
4596                 return;
4597
4598         if (HAS_PCH_SPLIT(dev)) {
4599                 pp_ctrl_reg = PCH_PP_CONTROL;
4600                 pp_on_reg = PCH_PP_ON_DELAYS;
4601                 pp_off_reg = PCH_PP_OFF_DELAYS;
4602                 pp_div_reg = PCH_PP_DIVISOR;
4603         } else {
4604                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4605
4606                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4607                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4608                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4609                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4610         }
4611
4612         /* Workaround: Need to write PP_CONTROL with the unlock key as
4613          * the very first thing. */
4614         pp = ironlake_get_pp_control(intel_dp);
4615         I915_WRITE(pp_ctrl_reg, pp);
4616
4617         pp_on = I915_READ(pp_on_reg);
4618         pp_off = I915_READ(pp_off_reg);
4619         pp_div = I915_READ(pp_div_reg);
4620
4621         /* Pull timing values out of registers */
4622         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4623                 PANEL_POWER_UP_DELAY_SHIFT;
4624
4625         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4626                 PANEL_LIGHT_ON_DELAY_SHIFT;
4627
4628         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4629                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4630
4631         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4632                 PANEL_POWER_DOWN_DELAY_SHIFT;
4633
4634         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4635                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4636
4637         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4638                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4639
4640         vbt = dev_priv->vbt.edp_pps;
4641
4642         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4643          * our hw here, which are all in 100usec. */
4644         spec.t1_t3 = 210 * 10;
4645         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4646         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4647         spec.t10 = 500 * 10;
4648         /* This one is special and actually in units of 100ms, but zero
4649          * based in the hw (so we need to add 100 ms). But the sw vbt
4650          * table multiplies it with 1000 to make it in units of 100usec,
4651          * too. */
4652         spec.t11_t12 = (510 + 100) * 10;
4653
4654         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4655                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4656
4657         /* Use the max of the register settings and vbt. If both are
4658          * unset, fall back to the spec limits. */
4659 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4660                                        spec.field : \
4661                                        max(cur.field, vbt.field))
4662         assign_final(t1_t3);
4663         assign_final(t8);
4664         assign_final(t9);
4665         assign_final(t10);
4666         assign_final(t11_t12);
4667 #undef assign_final
4668
4669 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4670         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4671         intel_dp->backlight_on_delay = get_delay(t8);
4672         intel_dp->backlight_off_delay = get_delay(t9);
4673         intel_dp->panel_power_down_delay = get_delay(t10);
4674         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4675 #undef get_delay
4676
4677         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4678                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4679                       intel_dp->panel_power_cycle_delay);
4680
4681         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4682                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4683 }
4684
4685 static void
4686 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4687                                               struct intel_dp *intel_dp)
4688 {
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690         u32 pp_on, pp_off, pp_div, port_sel = 0;
4691         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4692         int pp_on_reg, pp_off_reg, pp_div_reg;
4693         enum port port = dp_to_dig_port(intel_dp)->port;
4694         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4695
4696         lockdep_assert_held(&dev_priv->pps_mutex);
4697
4698         if (HAS_PCH_SPLIT(dev)) {
4699                 pp_on_reg = PCH_PP_ON_DELAYS;
4700                 pp_off_reg = PCH_PP_OFF_DELAYS;
4701                 pp_div_reg = PCH_PP_DIVISOR;
4702         } else {
4703                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4704
4705                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4706                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4707                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4708         }
4709
4710         /*
4711          * And finally store the new values in the power sequencer. The
4712          * backlight delays are set to 1 because we do manual waits on them. For
4713          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4714          * we'll end up waiting for the backlight off delay twice: once when we
4715          * do the manual sleep, and once when we disable the panel and wait for
4716          * the PP_STATUS bit to become zero.
4717          */
4718         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4719                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4720         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4721                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4722         /* Compute the divisor for the pp clock, simply match the Bspec
4723          * formula. */
4724         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4725         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4726                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4727
4728         /* Haswell doesn't have any port selection bits for the panel
4729          * power sequencer any more. */
4730         if (IS_VALLEYVIEW(dev)) {
4731                 port_sel = PANEL_PORT_SELECT_VLV(port);
4732         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4733                 if (port == PORT_A)
4734                         port_sel = PANEL_PORT_SELECT_DPA;
4735                 else
4736                         port_sel = PANEL_PORT_SELECT_DPD;
4737         }
4738
4739         pp_on |= port_sel;
4740
4741         I915_WRITE(pp_on_reg, pp_on);
4742         I915_WRITE(pp_off_reg, pp_off);
4743         I915_WRITE(pp_div_reg, pp_div);
4744
4745         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4746                       I915_READ(pp_on_reg),
4747                       I915_READ(pp_off_reg),
4748                       I915_READ(pp_div_reg));
4749 }
4750
4751 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4752 {
4753         struct drm_i915_private *dev_priv = dev->dev_private;
4754         struct intel_encoder *encoder;
4755         struct intel_digital_port *dig_port = NULL;
4756         struct intel_dp *intel_dp = dev_priv->drrs.dp;
4757         struct intel_crtc_state *config = NULL;
4758         struct intel_crtc *intel_crtc = NULL;
4759         u32 reg, val;
4760         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4761
4762         if (refresh_rate <= 0) {
4763                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4764                 return;
4765         }
4766
4767         if (intel_dp == NULL) {
4768                 DRM_DEBUG_KMS("DRRS not supported.\n");
4769                 return;
4770         }
4771
4772         /*
4773          * FIXME: This needs proper synchronization with psr state for some
4774          * platforms that cannot have PSR and DRRS enabled at the same time.
4775          */
4776
4777         dig_port = dp_to_dig_port(intel_dp);
4778         encoder = &dig_port->base;
4779         intel_crtc = encoder->new_crtc;
4780
4781         if (!intel_crtc) {
4782                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4783                 return;
4784         }
4785
4786         config = intel_crtc->config;
4787
4788         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4789                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4790                 return;
4791         }
4792
4793         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4794                         refresh_rate)
4795                 index = DRRS_LOW_RR;
4796
4797         if (index == dev_priv->drrs.refresh_rate_type) {
4798                 DRM_DEBUG_KMS(
4799                         "DRRS requested for previously set RR...ignoring\n");
4800                 return;
4801         }
4802
4803         if (!intel_crtc->active) {
4804                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4805                 return;
4806         }
4807
4808         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4809                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4810                 val = I915_READ(reg);
4811                 if (index > DRRS_HIGH_RR) {
4812                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4813                         intel_dp_set_m_n(intel_crtc);
4814                 } else {
4815                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4816                 }
4817                 I915_WRITE(reg, val);
4818         }
4819
4820         dev_priv->drrs.refresh_rate_type = index;
4821
4822         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4823 }
4824
4825 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4826 {
4827         struct drm_i915_private *dev_priv =
4828                 container_of(work, typeof(*dev_priv), drrs.work.work);
4829         struct intel_dp *intel_dp;
4830
4831         mutex_lock(&dev_priv->drrs.mutex);
4832
4833         intel_dp = dev_priv->drrs.dp;
4834
4835         if (!intel_dp)
4836                 goto unlock;
4837
4838         /*
4839          * The delayed work can race with an invalidate hence we need to
4840          * recheck.
4841          */
4842
4843         if (dev_priv->drrs.busy_frontbuffer_bits)
4844                 goto unlock;
4845
4846         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
4847                 intel_dp_set_drrs_state(dev_priv->dev,
4848                         intel_dp->attached_connector->panel.
4849                         downclock_mode->vrefresh);
4850
4851 unlock:
4852
4853         mutex_unlock(&dev_priv->drrs.mutex);
4854 }
4855
4856 static struct drm_display_mode *
4857 intel_dp_drrs_init(struct intel_connector *intel_connector,
4858                 struct drm_display_mode *fixed_mode)
4859 {
4860         struct drm_connector *connector = &intel_connector->base;
4861         struct drm_device *dev = connector->dev;
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         struct drm_display_mode *downclock_mode = NULL;
4864
4865         if (INTEL_INFO(dev)->gen <= 6) {
4866                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4867                 return NULL;
4868         }
4869
4870         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4871                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4872                 return NULL;
4873         }
4874
4875         downclock_mode = intel_find_panel_downclock
4876                                         (dev, fixed_mode, connector);
4877
4878         if (!downclock_mode) {
4879                 DRM_DEBUG_KMS("DRRS not supported\n");
4880                 return NULL;
4881         }
4882
4883         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
4884
4885         mutex_init(&dev_priv->drrs.mutex);
4886
4887         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4888
4889         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4890         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4891         return downclock_mode;
4892 }
4893
4894 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4895                                      struct intel_connector *intel_connector)
4896 {
4897         struct drm_connector *connector = &intel_connector->base;
4898         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4899         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4900         struct drm_device *dev = intel_encoder->base.dev;
4901         struct drm_i915_private *dev_priv = dev->dev_private;
4902         struct drm_display_mode *fixed_mode = NULL;
4903         struct drm_display_mode *downclock_mode = NULL;
4904         bool has_dpcd;
4905         struct drm_display_mode *scan;
4906         struct edid *edid;
4907         enum pipe pipe = INVALID_PIPE;
4908
4909         dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
4910
4911         if (!is_edp(intel_dp))
4912                 return true;
4913
4914         pps_lock(intel_dp);
4915         intel_edp_panel_vdd_sanitize(intel_dp);
4916         pps_unlock(intel_dp);
4917
4918         /* Cache DPCD and EDID for edp. */
4919         has_dpcd = intel_dp_get_dpcd(intel_dp);
4920
4921         if (has_dpcd) {
4922                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4923                         dev_priv->no_aux_handshake =
4924                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4925                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4926         } else {
4927                 /* if this fails, presume the device is a ghost */
4928                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4929                 return false;
4930         }
4931
4932         /* We now know it's not a ghost, init power sequence regs. */
4933         pps_lock(intel_dp);
4934         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
4935         pps_unlock(intel_dp);
4936
4937         mutex_lock(&dev->mode_config.mutex);
4938         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4939         if (edid) {
4940                 if (drm_add_edid_modes(connector, edid)) {
4941                         drm_mode_connector_update_edid_property(connector,
4942                                                                 edid);
4943                         drm_edid_to_eld(connector, edid);
4944                 } else {
4945                         kfree(edid);
4946                         edid = ERR_PTR(-EINVAL);
4947                 }
4948         } else {
4949                 edid = ERR_PTR(-ENOENT);
4950         }
4951         intel_connector->edid = edid;
4952
4953         /* prefer fixed mode from EDID if available */
4954         list_for_each_entry(scan, &connector->probed_modes, head) {
4955                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4956                         fixed_mode = drm_mode_duplicate(dev, scan);
4957                         downclock_mode = intel_dp_drrs_init(
4958                                                 intel_connector, fixed_mode);
4959                         break;
4960                 }
4961         }
4962
4963         /* fallback to VBT if available for eDP */
4964         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4965                 fixed_mode = drm_mode_duplicate(dev,
4966                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4967                 if (fixed_mode)
4968                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4969         }
4970         mutex_unlock(&dev->mode_config.mutex);
4971
4972         if (IS_VALLEYVIEW(dev)) {
4973                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4974                 register_reboot_notifier(&intel_dp->edp_notifier);
4975
4976                 /*
4977                  * Figure out the current pipe for the initial backlight setup.
4978                  * If the current pipe isn't valid, try the PPS pipe, and if that
4979                  * fails just assume pipe A.
4980                  */
4981                 if (IS_CHERRYVIEW(dev))
4982                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4983                 else
4984                         pipe = PORT_TO_PIPE(intel_dp->DP);
4985
4986                 if (pipe != PIPE_A && pipe != PIPE_B)
4987                         pipe = intel_dp->pps_pipe;
4988
4989                 if (pipe != PIPE_A && pipe != PIPE_B)
4990                         pipe = PIPE_A;
4991
4992                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4993                               pipe_name(pipe));
4994         }
4995
4996         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4997         intel_connector->panel.backlight_power = intel_edp_backlight_power;
4998         intel_panel_setup_backlight(connector, pipe);
4999
5000         return true;
5001 }
5002
5003 bool
5004 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5005                         struct intel_connector *intel_connector)
5006 {
5007         struct drm_connector *connector = &intel_connector->base;
5008         struct intel_dp *intel_dp = &intel_dig_port->dp;
5009         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5010         struct drm_device *dev = intel_encoder->base.dev;
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         enum port port = intel_dig_port->port;
5013         int type;
5014
5015         intel_dp->pps_pipe = INVALID_PIPE;
5016
5017         /* intel_dp vfuncs */
5018         if (INTEL_INFO(dev)->gen >= 9)
5019                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5020         else if (IS_VALLEYVIEW(dev))
5021                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5022         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5023                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5024         else if (HAS_PCH_SPLIT(dev))
5025                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5026         else
5027                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5028
5029         if (INTEL_INFO(dev)->gen >= 9)
5030                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5031         else
5032                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5033
5034         /* Preserve the current hw state. */
5035         intel_dp->DP = I915_READ(intel_dp->output_reg);
5036         intel_dp->attached_connector = intel_connector;
5037
5038         if (intel_dp_is_edp(dev, port))
5039                 type = DRM_MODE_CONNECTOR_eDP;
5040         else
5041                 type = DRM_MODE_CONNECTOR_DisplayPort;
5042
5043         /*
5044          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5045          * for DP the encoder type can be set by the caller to
5046          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5047          */
5048         if (type == DRM_MODE_CONNECTOR_eDP)
5049                 intel_encoder->type = INTEL_OUTPUT_EDP;
5050
5051         /* eDP only on port B and/or C on vlv/chv */
5052         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5053                     port != PORT_B && port != PORT_C))
5054                 return false;
5055
5056         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5057                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5058                         port_name(port));
5059
5060         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5061         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5062
5063         connector->interlace_allowed = true;
5064         connector->doublescan_allowed = 0;
5065
5066         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5067                           edp_panel_vdd_work);
5068
5069         intel_connector_attach_encoder(intel_connector, intel_encoder);
5070         drm_connector_register(connector);
5071
5072         if (HAS_DDI(dev))
5073                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5074         else
5075                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5076         intel_connector->unregister = intel_dp_connector_unregister;
5077
5078         /* Set up the hotplug pin. */
5079         switch (port) {
5080         case PORT_A:
5081                 intel_encoder->hpd_pin = HPD_PORT_A;
5082                 break;
5083         case PORT_B:
5084                 intel_encoder->hpd_pin = HPD_PORT_B;
5085                 break;
5086         case PORT_C:
5087                 intel_encoder->hpd_pin = HPD_PORT_C;
5088                 break;
5089         case PORT_D:
5090                 intel_encoder->hpd_pin = HPD_PORT_D;
5091                 break;
5092         default:
5093                 BUG();
5094         }
5095
5096         if (is_edp(intel_dp)) {
5097                 pps_lock(intel_dp);
5098                 intel_dp_init_panel_power_timestamps(intel_dp);
5099                 if (IS_VALLEYVIEW(dev))
5100                         vlv_initial_power_sequencer_setup(intel_dp);
5101                 else
5102                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5103                 pps_unlock(intel_dp);
5104         }
5105
5106         intel_dp_aux_init(intel_dp, intel_connector);
5107
5108         /* init MST on ports that can support it */
5109         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
5110                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5111                         intel_dp_mst_encoder_init(intel_dig_port,
5112                                                   intel_connector->base.base.id);
5113                 }
5114         }
5115
5116         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5117                 drm_dp_aux_unregister(&intel_dp->aux);
5118                 if (is_edp(intel_dp)) {
5119                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5120                         /*
5121                          * vdd might still be enabled do to the delayed vdd off.
5122                          * Make sure vdd is actually turned off here.
5123                          */
5124                         pps_lock(intel_dp);
5125                         edp_panel_vdd_off_sync(intel_dp);
5126                         pps_unlock(intel_dp);
5127                 }
5128                 drm_connector_unregister(connector);
5129                 drm_connector_cleanup(connector);
5130                 return false;
5131         }
5132
5133         intel_dp_add_properties(intel_dp, connector);
5134
5135         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5136          * 0xd.  Failure to do so will result in spurious interrupts being
5137          * generated on the port when a cable is not attached.
5138          */
5139         if (IS_G4X(dev) && !IS_GM45(dev)) {
5140                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5141                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5142         }
5143
5144         return true;
5145 }
5146
5147 void
5148 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5149 {
5150         struct drm_i915_private *dev_priv = dev->dev_private;
5151         struct intel_digital_port *intel_dig_port;
5152         struct intel_encoder *intel_encoder;
5153         struct drm_encoder *encoder;
5154         struct intel_connector *intel_connector;
5155
5156         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5157         if (!intel_dig_port)
5158                 return;
5159
5160         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5161         if (!intel_connector) {
5162                 kfree(intel_dig_port);
5163                 return;
5164         }
5165
5166         intel_encoder = &intel_dig_port->base;
5167         encoder = &intel_encoder->base;
5168
5169         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5170                          DRM_MODE_ENCODER_TMDS);
5171
5172         intel_encoder->compute_config = intel_dp_compute_config;
5173         intel_encoder->disable = intel_disable_dp;
5174         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5175         intel_encoder->get_config = intel_dp_get_config;
5176         intel_encoder->suspend = intel_dp_encoder_suspend;
5177         if (IS_CHERRYVIEW(dev)) {
5178                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5179                 intel_encoder->pre_enable = chv_pre_enable_dp;
5180                 intel_encoder->enable = vlv_enable_dp;
5181                 intel_encoder->post_disable = chv_post_disable_dp;
5182         } else if (IS_VALLEYVIEW(dev)) {
5183                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5184                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5185                 intel_encoder->enable = vlv_enable_dp;
5186                 intel_encoder->post_disable = vlv_post_disable_dp;
5187         } else {
5188                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5189                 intel_encoder->enable = g4x_enable_dp;
5190                 if (INTEL_INFO(dev)->gen >= 5)
5191                         intel_encoder->post_disable = ilk_post_disable_dp;
5192         }
5193
5194         intel_dig_port->port = port;
5195         intel_dig_port->dp.output_reg = output_reg;
5196
5197         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5198         if (IS_CHERRYVIEW(dev)) {
5199                 if (port == PORT_D)
5200                         intel_encoder->crtc_mask = 1 << 2;
5201                 else
5202                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5203         } else {
5204                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5205         }
5206         intel_encoder->cloneable = 0;
5207         intel_encoder->hot_plug = intel_dp_hot_plug;
5208
5209         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5210         dev_priv->hpd_irq_port[port] = intel_dig_port;
5211
5212         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5213                 drm_encoder_cleanup(encoder);
5214                 kfree(intel_dig_port);
5215                 kfree(intel_connector);
5216         }
5217 }
5218
5219 void intel_dp_mst_suspend(struct drm_device *dev)
5220 {
5221         struct drm_i915_private *dev_priv = dev->dev_private;
5222         int i;
5223
5224         /* disable MST */
5225         for (i = 0; i < I915_MAX_PORTS; i++) {
5226                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5227                 if (!intel_dig_port)
5228                         continue;
5229
5230                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5231                         if (!intel_dig_port->dp.can_mst)
5232                                 continue;
5233                         if (intel_dig_port->dp.is_mst)
5234                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5235                 }
5236         }
5237 }
5238
5239 void intel_dp_mst_resume(struct drm_device *dev)
5240 {
5241         struct drm_i915_private *dev_priv = dev->dev_private;
5242         int i;
5243
5244         for (i = 0; i < I915_MAX_PORTS; i++) {
5245                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5246                 if (!intel_dig_port)
5247                         continue;
5248                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5249                         int ret;
5250
5251                         if (!intel_dig_port->dp.can_mst)
5252                                 continue;
5253
5254                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5255                         if (ret != 0) {
5256                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5257                         }
5258                 }
5259         }
5260 }