2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
40 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
41 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 #define _wait_for(COND, MS, W) ({ \
52 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
55 if (time_after(jiffies, timeout__)) { \
60 if ((W) && drm_can_sleep()) { \
61 usleep_range((W)*1000, (W)*2000); \
69 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
70 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
71 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
72 DIV_ROUND_UP((US), 1000), 0)
74 #define KHz(x) (1000 * (x))
75 #define MHz(x) KHz(1000 * (x))
78 * Display related stuff
81 /* store information about an Ixxx DVO */
82 /* The i830->i865 use multiple DVOs with multiple i2cs */
83 /* the i915, i945 have a single sDVO i2c bus - which is different */
85 /* maximum connectors per crtcs in the mode set */
87 /* Maximum cursor sizes */
88 #define GEN2_CURSOR_WIDTH 64
89 #define GEN2_CURSOR_HEIGHT 64
90 #define MAX_CURSOR_WIDTH 256
91 #define MAX_CURSOR_HEIGHT 256
93 #define INTEL_I2C_BUS_DVO 1
94 #define INTEL_I2C_BUS_SDVO 2
96 /* these are outputs from the chip - integrated only
97 external chips are via DVO or SDVO output */
98 enum intel_output_type {
99 INTEL_OUTPUT_UNUSED = 0,
100 INTEL_OUTPUT_ANALOG = 1,
101 INTEL_OUTPUT_DVO = 2,
102 INTEL_OUTPUT_SDVO = 3,
103 INTEL_OUTPUT_LVDS = 4,
104 INTEL_OUTPUT_TVOUT = 5,
105 INTEL_OUTPUT_HDMI = 6,
106 INTEL_OUTPUT_DISPLAYPORT = 7,
107 INTEL_OUTPUT_EDP = 8,
108 INTEL_OUTPUT_DSI = 9,
109 INTEL_OUTPUT_UNKNOWN = 10,
110 INTEL_OUTPUT_DP_MST = 11,
113 #define INTEL_DVO_CHIP_NONE 0
114 #define INTEL_DVO_CHIP_LVDS 1
115 #define INTEL_DVO_CHIP_TMDS 2
116 #define INTEL_DVO_CHIP_TVOUT 4
118 #define INTEL_DSI_VIDEO_MODE 0
119 #define INTEL_DSI_COMMAND_MODE 1
121 struct intel_framebuffer {
122 struct drm_framebuffer base;
123 struct drm_i915_gem_object *obj;
127 struct drm_fb_helper helper;
128 struct intel_framebuffer *fb;
129 struct list_head fbdev_list;
130 struct drm_display_mode *our_mode;
134 struct intel_encoder {
135 struct drm_encoder base;
137 * The new crtc this encoder will be driven from. Only differs from
138 * base->crtc while a modeset is in progress.
140 struct intel_crtc *new_crtc;
142 enum intel_output_type type;
143 unsigned int cloneable;
144 bool connectors_active;
145 void (*hot_plug)(struct intel_encoder *);
146 bool (*compute_config)(struct intel_encoder *,
147 struct intel_crtc_state *);
148 void (*pre_pll_enable)(struct intel_encoder *);
149 void (*pre_enable)(struct intel_encoder *);
150 void (*enable)(struct intel_encoder *);
151 void (*mode_set)(struct intel_encoder *intel_encoder);
152 void (*disable)(struct intel_encoder *);
153 void (*post_disable)(struct intel_encoder *);
154 /* Read out the current hw state of this connector, returning true if
155 * the encoder is active. If the encoder is enabled it also set the pipe
156 * it is connected to in the pipe parameter. */
157 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
158 /* Reconstructs the equivalent mode flags for the current hardware
159 * state. This must be called _after_ display->get_pipe_config has
160 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
161 * be set correctly before calling this function. */
162 void (*get_config)(struct intel_encoder *,
163 struct intel_crtc_state *pipe_config);
165 * Called during system suspend after all pending requests for the
166 * encoder are flushed (for example for DP AUX transactions) and
167 * device interrupts are disabled.
169 void (*suspend)(struct intel_encoder *);
171 enum hpd_pin hpd_pin;
175 struct drm_display_mode *fixed_mode;
176 struct drm_display_mode *downclock_mode;
186 bool combination_mode; /* gen 2/4 only */
188 struct backlight_device *device;
191 void (*backlight_power)(struct intel_connector *, bool enable);
194 struct intel_connector {
195 struct drm_connector base;
197 * The fixed encoder this connector is connected to.
199 struct intel_encoder *encoder;
202 * The new encoder this connector will be driven. Only differs from
203 * encoder while a modeset is in progress.
205 struct intel_encoder *new_encoder;
207 /* Reads out the current hw, returning true if the connector is enabled
208 * and active (i.e. dpms ON state). */
209 bool (*get_hw_state)(struct intel_connector *);
212 * Removes all interfaces through which the connector is accessible
213 * - like sysfs, debugfs entries -, so that no new operations can be
214 * started on the connector. Also makes sure all currently pending
215 * operations finish before returing.
217 void (*unregister)(struct intel_connector *);
219 /* Panel info for eDP and LVDS */
220 struct intel_panel panel;
222 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
224 struct edid *detect_edid;
226 /* since POLL and HPD connectors may use the same HPD line keep the native
227 state of connector->polled in case hotplug storm detection changes it */
230 void *port; /* store this opaque as its illegal to dereference it */
232 struct intel_dp *mst_port;
235 typedef struct dpll {
247 struct intel_plane_state {
248 struct drm_plane_state base;
251 struct drm_rect clip;
255 * used only for sprite planes to determine when to implicitly
256 * enable/disable the primary plane
261 struct intel_initial_plane_config {
262 struct intel_framebuffer *fb;
268 struct intel_crtc_state {
269 struct drm_crtc_state base;
272 * quirks - bitfield with hw state readout quirks
274 * For various reasons the hw state readout code might not be able to
275 * completely faithfully read out the current state. These cases are
276 * tracked with quirk flags so that fastboot and state checker can act
279 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
280 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
281 unsigned long quirks;
283 /* Pipe source size (ie. panel fitter input size)
284 * All planes will be positioned inside this space,
285 * and get clipped at the edges. */
286 int pipe_src_w, pipe_src_h;
288 /* Whether to set up the PCH/FDI. Note that we never allow sharing
289 * between pch encoders and cpu encoders. */
290 bool has_pch_encoder;
292 /* Are we sending infoframes on the attached port */
295 /* CPU Transcoder for the pipe. Currently this can only differ from the
296 * pipe on Haswell (where we have a special eDP transcoder). */
297 enum transcoder cpu_transcoder;
300 * Use reduced/limited/broadcast rbg range, compressing from the full
301 * range fed into the crtcs.
303 bool limited_color_range;
305 /* DP has a bunch of special case unfortunately, so mark the pipe
309 /* Whether we should send NULL infoframes. Required for audio. */
312 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
313 * has_dp_encoder is set. */
317 * Enable dithering, used when the selected pipe bpp doesn't match the
322 /* Controls for the clock computation, to override various stages. */
325 /* SDVO TV has a bunch of special case. To make multifunction encoders
326 * work correctly, we need to track this at runtime.*/
330 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
331 * required. This is set in the 2nd loop of calling encoder's
332 * ->compute_config if the first pick doesn't work out.
336 /* Settings for the intel dpll used on pretty much everything but
340 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
341 enum intel_dpll_id shared_dpll;
344 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
345 * - enum skl_dpll on SKL
347 uint32_t ddi_pll_sel;
349 /* Actual register state of the dpll, for shared dpll cross-checking. */
350 struct intel_dpll_hw_state dpll_hw_state;
353 struct intel_link_m_n dp_m_n;
355 /* m2_n2 for eDP downclock */
356 struct intel_link_m_n dp_m2_n2;
360 * Frequence the dpll for the port should run at. Differs from the
361 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
362 * already multiplied by pixel_multiplier.
366 /* Used by SDVO (and if we ever fix it, HDMI). */
367 unsigned pixel_multiplier;
369 /* Panel fitter controls for gen2-gen4 + VLV */
373 u32 lvds_border_bits;
376 /* Panel fitter placement and size for Ironlake+ */
384 /* FDI configuration, only valid if has_pch_encoder is set. */
386 struct intel_link_m_n fdi_m_n;
392 bool dp_encoder_is_mst;
396 struct intel_pipe_wm {
397 struct intel_wm_level wm[5];
401 bool sprites_enabled;
405 struct intel_mmio_flip {
406 struct drm_i915_gem_request *req;
407 struct work_struct work;
411 struct skl_wm_level wm[8];
412 struct skl_wm_level trans_wm;
417 * Tracking of operations that need to be performed at the beginning/end of an
418 * atomic commit, outside the atomic section where interrupts are disabled.
419 * These are generally operations that grab mutexes or might otherwise sleep
420 * and thus can't be run with interrupts disabled.
422 struct intel_crtc_atomic_commit {
425 unsigned start_vbl_count;
427 /* Sleepable operations to perform before commit */
430 bool pre_disable_primary;
432 unsigned disabled_planes;
434 /* Sleepable operations to perform after commit */
438 bool post_enable_primary;
439 unsigned update_sprite_watermarks;
443 struct drm_crtc base;
446 u8 lut_r[256], lut_g[256], lut_b[256];
448 * Whether the crtc and the connected output pipeline is active. Implies
449 * that crtc->enabled is set, i.e. the current mode configuration has
450 * some outputs connected to this crtc.
453 unsigned long enabled_power_domains;
454 bool primary_enabled; /* is the primary plane (partially) visible? */
456 struct intel_overlay *overlay;
457 struct intel_unpin_work *unpin_work;
459 atomic_t unpin_work_count;
461 /* Display surface base address adjustement for pageflips. Note that on
462 * gen4+ this only adjusts up to a tile, offsets within a tile are
463 * handled in the hw itself (with the TILEOFF register). */
464 unsigned long dspaddr_offset;
466 struct drm_i915_gem_object *cursor_bo;
467 uint32_t cursor_addr;
468 uint32_t cursor_cntl;
469 uint32_t cursor_size;
470 uint32_t cursor_base;
472 struct intel_initial_plane_config plane_config;
473 struct intel_crtc_state *config;
476 /* reset counter value when the last flip was submitted */
477 unsigned int reset_counter;
479 /* Access to these should be protected by dev_priv->irq_lock. */
480 bool cpu_fifo_underrun_disabled;
481 bool pch_fifo_underrun_disabled;
483 /* per-pipe watermark state */
485 /* watermarks currently being used */
486 struct intel_pipe_wm active;
487 /* SKL wm values currently in use */
488 struct skl_pipe_wm skl_active;
492 struct intel_mmio_flip mmio_flip;
494 struct intel_crtc_atomic_commit atomic;
497 struct intel_plane_wm_parameters {
498 uint32_t horiz_pixels;
499 uint32_t vert_pixels;
500 uint8_t bytes_per_pixel;
504 unsigned int rotation;
508 struct drm_plane base;
514 /* FIXME convert to properties */
515 struct drm_intel_sprite_colorkey ckey;
517 /* Since we need to change the watermarks before/after
518 * enabling/disabling the planes, we need to store the parameters here
519 * as the other pieces of the struct may not reflect the values we want
520 * for the watermark calculations. Currently only Haswell uses this.
522 struct intel_plane_wm_parameters wm;
525 * NOTE: Do not place new plane state fields here (e.g., when adding
526 * new plane properties). New runtime state should now be placed in
527 * the intel_plane_state structure and accessed via drm_plane->state.
530 void (*update_plane)(struct drm_plane *plane,
531 struct drm_crtc *crtc,
532 struct drm_framebuffer *fb,
533 int crtc_x, int crtc_y,
534 unsigned int crtc_w, unsigned int crtc_h,
535 uint32_t x, uint32_t y,
536 uint32_t src_w, uint32_t src_h);
537 void (*disable_plane)(struct drm_plane *plane,
538 struct drm_crtc *crtc);
539 int (*check_plane)(struct drm_plane *plane,
540 struct intel_plane_state *state);
541 void (*commit_plane)(struct drm_plane *plane,
542 struct intel_plane_state *state);
545 struct intel_watermark_params {
546 unsigned long fifo_size;
547 unsigned long max_wm;
548 unsigned long default_wm;
549 unsigned long guard_size;
550 unsigned long cacheline_size;
553 struct cxsr_latency {
556 unsigned long fsb_freq;
557 unsigned long mem_freq;
558 unsigned long display_sr;
559 unsigned long display_hpll_disable;
560 unsigned long cursor_sr;
561 unsigned long cursor_hpll_disable;
564 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
565 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
566 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
567 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
568 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
569 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
570 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
571 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
576 uint32_t color_range;
577 bool color_range_auto;
580 enum hdmi_force_audio force_audio;
581 bool rgb_quant_range_selectable;
582 enum hdmi_picture_aspect aspect_ratio;
583 void (*write_infoframe)(struct drm_encoder *encoder,
584 enum hdmi_infoframe_type type,
585 const void *frame, ssize_t len);
586 void (*set_infoframes)(struct drm_encoder *encoder,
588 struct drm_display_mode *adjusted_mode);
589 bool (*infoframe_enabled)(struct drm_encoder *encoder);
592 struct intel_dp_mst_encoder;
593 #define DP_MAX_DOWNSTREAM_PORTS 0x10
597 * When platform provides two set of M_N registers for dp, we can
598 * program them and switch between them incase of DRRS.
599 * But When only one such register is provided, we have to program the
600 * required divider value on that registers itself based on the DRRS state.
602 * M1_N1 : Program dp_m_n on M1_N1 registers
603 * dp_m2_n2 on M2_N2 registers (If supported)
605 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
606 * M2_N2 registers are not supported
610 /* Sets the m1_n1 and m2_n2 */
617 uint32_t aux_ch_ctl_reg;
620 enum hdmi_force_audio force_audio;
621 uint32_t color_range;
622 bool color_range_auto;
626 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
627 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
628 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
629 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
630 uint8_t num_sink_rates;
631 int sink_rates[DP_MAX_SUPPORTED_RATES];
632 struct drm_dp_aux aux;
633 uint8_t train_set[4];
634 int panel_power_up_delay;
635 int panel_power_down_delay;
636 int panel_power_cycle_delay;
637 int backlight_on_delay;
638 int backlight_off_delay;
639 struct delayed_work panel_vdd_work;
641 unsigned long last_power_cycle;
642 unsigned long last_power_on;
643 unsigned long last_backlight_off;
645 struct notifier_block edp_notifier;
648 * Pipe whose power sequencer is currently locked into
649 * this port. Only relevant on VLV/CHV.
652 struct edp_power_seq pps_delays;
655 bool can_mst; /* this port supports mst */
657 int active_mst_links;
658 /* connector directly attached - won't be use for modeset in mst world */
659 struct intel_connector *attached_connector;
661 /* mst connector list */
662 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
663 struct drm_dp_mst_topology_mgr mst_mgr;
665 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
667 * This function returns the value we have to program the AUX_CTL
668 * register with to kick off an AUX transaction.
670 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
673 uint32_t aux_clock_divider);
676 struct intel_digital_port {
677 struct intel_encoder base;
681 struct intel_hdmi hdmi;
682 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
685 struct intel_dp_mst_encoder {
686 struct intel_encoder base;
688 struct intel_digital_port *primary;
689 void *port; /* store this opaque as its illegal to dereference it */
693 vlv_dport_to_channel(struct intel_digital_port *dport)
695 switch (dport->port) {
707 vlv_pipe_to_channel(enum pipe pipe)
720 static inline struct drm_crtc *
721 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
723 struct drm_i915_private *dev_priv = dev->dev_private;
724 return dev_priv->pipe_to_crtc_mapping[pipe];
727 static inline struct drm_crtc *
728 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 return dev_priv->plane_to_crtc_mapping[plane];
734 struct intel_unpin_work {
735 struct work_struct work;
736 struct drm_crtc *crtc;
737 struct drm_framebuffer *old_fb;
738 struct drm_i915_gem_object *pending_flip_obj;
739 struct drm_pending_vblank_event *event;
741 #define INTEL_FLIP_INACTIVE 0
742 #define INTEL_FLIP_PENDING 1
743 #define INTEL_FLIP_COMPLETE 2
746 struct drm_i915_gem_request *flip_queued_req;
747 int flip_queued_vblank;
748 int flip_ready_vblank;
749 bool enable_stall_check;
752 struct intel_set_config {
753 struct drm_encoder **save_connector_encoders;
754 struct drm_crtc **save_encoder_crtcs;
755 bool *save_crtc_enabled;
761 struct intel_load_detect_pipe {
762 struct drm_framebuffer *release_fb;
763 bool load_detect_temp;
767 static inline struct intel_encoder *
768 intel_attached_encoder(struct drm_connector *connector)
770 return to_intel_connector(connector)->encoder;
773 static inline struct intel_digital_port *
774 enc_to_dig_port(struct drm_encoder *encoder)
776 return container_of(encoder, struct intel_digital_port, base.base);
779 static inline struct intel_dp_mst_encoder *
780 enc_to_mst(struct drm_encoder *encoder)
782 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
785 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
787 return &enc_to_dig_port(encoder)->dp;
790 static inline struct intel_digital_port *
791 dp_to_dig_port(struct intel_dp *intel_dp)
793 return container_of(intel_dp, struct intel_digital_port, dp);
796 static inline struct intel_digital_port *
797 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
799 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
803 * Returns the number of planes for this pipe, ie the number of sprites + 1
804 * (primary plane). This doesn't count the cursor plane then.
806 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
808 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
811 /* intel_fifo_underrun.c */
812 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
813 enum pipe pipe, bool enable);
814 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
815 enum transcoder pch_transcoder,
817 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
819 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
820 enum transcoder pch_transcoder);
821 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
824 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
825 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
826 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
827 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
828 void gen6_reset_rps_interrupts(struct drm_device *dev);
829 void gen6_enable_rps_interrupts(struct drm_device *dev);
830 void gen6_disable_rps_interrupts(struct drm_device *dev);
831 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
832 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
833 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
834 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
837 * We only use drm_irq_uninstall() at unload and VT switch, so
838 * this is the only thing we need to check.
840 return dev_priv->pm.irqs_enabled;
843 int intel_get_crtc_scanline(struct intel_crtc *crtc);
844 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
845 unsigned int pipe_mask);
848 void intel_crt_init(struct drm_device *dev);
852 void intel_prepare_ddi(struct drm_device *dev);
853 void hsw_fdi_link_train(struct drm_crtc *crtc);
854 void intel_ddi_init(struct drm_device *dev, enum port port);
855 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
856 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
857 void intel_ddi_pll_init(struct drm_device *dev);
858 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
859 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
860 enum transcoder cpu_transcoder);
861 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
862 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
863 bool intel_ddi_pll_select(struct intel_crtc *crtc,
864 struct intel_crtc_state *crtc_state);
865 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
866 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
867 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
868 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
869 void intel_ddi_get_config(struct intel_encoder *encoder,
870 struct intel_crtc_state *pipe_config);
872 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
873 void intel_ddi_clock_get(struct intel_encoder *encoder,
874 struct intel_crtc_state *pipe_config);
875 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
877 /* intel_frontbuffer.c */
878 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
879 struct intel_engine_cs *ring,
880 enum fb_op_origin origin);
881 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
882 unsigned frontbuffer_bits);
883 void intel_frontbuffer_flip_complete(struct drm_device *dev,
884 unsigned frontbuffer_bits);
885 void intel_frontbuffer_flush(struct drm_device *dev,
886 unsigned frontbuffer_bits);
888 * intel_frontbuffer_flip - synchronous frontbuffer flip
890 * @frontbuffer_bits: frontbuffer plane tracking bits
892 * This function gets called after scheduling a flip on @obj. This is for
893 * synchronous plane updates which will happen on the next vblank and which will
894 * not get delayed by pending gpu rendering.
896 * Can be called without any locks held.
899 void intel_frontbuffer_flip(struct drm_device *dev,
900 unsigned frontbuffer_bits)
902 intel_frontbuffer_flush(dev, frontbuffer_bits);
905 unsigned int intel_fb_align_height(struct drm_device *dev,
907 uint32_t pixel_format,
908 uint64_t fb_format_modifier);
909 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
911 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
912 uint32_t pixel_format);
915 void intel_init_audio(struct drm_device *dev);
916 void intel_audio_codec_enable(struct intel_encoder *encoder);
917 void intel_audio_codec_disable(struct intel_encoder *encoder);
918 void i915_audio_component_init(struct drm_i915_private *dev_priv);
919 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
921 /* intel_display.c */
922 extern const struct drm_plane_funcs intel_plane_funcs;
923 bool intel_has_pending_fb_unpin(struct drm_device *dev);
924 int intel_pch_rawclk(struct drm_device *dev);
925 void intel_mark_busy(struct drm_device *dev);
926 void intel_mark_idle(struct drm_device *dev);
927 void intel_crtc_restore_mode(struct drm_crtc *crtc);
928 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
929 void intel_crtc_update_dpms(struct drm_crtc *crtc);
930 void intel_encoder_destroy(struct drm_encoder *encoder);
931 void intel_connector_dpms(struct drm_connector *, int mode);
932 bool intel_connector_get_hw_state(struct intel_connector *connector);
933 void intel_modeset_check_state(struct drm_device *dev);
934 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
935 struct intel_digital_port *port);
936 void intel_connector_attach_encoder(struct intel_connector *connector,
937 struct intel_encoder *encoder);
938 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
939 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
940 struct drm_crtc *crtc);
941 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
942 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
943 struct drm_file *file_priv);
944 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
946 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
948 intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 drm_wait_one_vblank(dev, pipe);
952 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
953 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
954 struct intel_digital_port *dport);
955 bool intel_get_load_detect_pipe(struct drm_connector *connector,
956 struct drm_display_mode *mode,
957 struct intel_load_detect_pipe *old,
958 struct drm_modeset_acquire_ctx *ctx);
959 void intel_release_load_detect_pipe(struct drm_connector *connector,
960 struct intel_load_detect_pipe *old,
961 struct drm_modeset_acquire_ctx *ctx);
962 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
963 struct drm_framebuffer *fb,
964 const struct drm_plane_state *plane_state,
965 struct intel_engine_cs *pipelined);
966 struct drm_framebuffer *
967 __intel_framebuffer_create(struct drm_device *dev,
968 struct drm_mode_fb_cmd2 *mode_cmd,
969 struct drm_i915_gem_object *obj);
970 void intel_prepare_page_flip(struct drm_device *dev, int plane);
971 void intel_finish_page_flip(struct drm_device *dev, int pipe);
972 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
973 void intel_check_page_flip(struct drm_device *dev, int pipe);
974 int intel_prepare_plane_fb(struct drm_plane *plane,
975 struct drm_framebuffer *fb,
976 const struct drm_plane_state *new_state);
977 void intel_cleanup_plane_fb(struct drm_plane *plane,
978 struct drm_framebuffer *fb,
979 const struct drm_plane_state *old_state);
980 int intel_plane_atomic_get_property(struct drm_plane *plane,
981 const struct drm_plane_state *state,
982 struct drm_property *property,
984 int intel_plane_atomic_set_property(struct drm_plane *plane,
985 struct drm_plane_state *state,
986 struct drm_property *property,
990 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
991 uint64_t fb_format_modifier);
994 intel_rotation_90_or_270(unsigned int rotation)
996 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
999 bool intel_wm_need_update(struct drm_plane *plane,
1000 struct drm_plane_state *state);
1002 /* shared dpll functions */
1003 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1004 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1005 struct intel_shared_dpll *pll,
1007 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1008 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1009 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1010 struct intel_crtc_state *state);
1011 void intel_put_shared_dpll(struct intel_crtc *crtc);
1013 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1014 const struct dpll *dpll);
1015 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1017 /* modesetting asserts */
1018 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state);
1022 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1023 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1024 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state);
1026 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1027 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1028 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1029 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1030 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1031 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1032 unsigned int tiling_mode,
1034 unsigned int pitch);
1035 void intel_prepare_reset(struct drm_device *dev);
1036 void intel_finish_reset(struct drm_device *dev);
1037 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1038 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1039 void intel_dp_get_m_n(struct intel_crtc *crtc,
1040 struct intel_crtc_state *pipe_config);
1041 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1042 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1044 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1046 bool intel_crtc_active(struct drm_crtc *crtc);
1047 void hsw_enable_ips(struct intel_crtc *crtc);
1048 void hsw_disable_ips(struct intel_crtc *crtc);
1049 enum intel_display_power_domain
1050 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1051 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1052 struct intel_crtc_state *pipe_config);
1053 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1054 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1056 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1057 struct drm_i915_gem_object *obj);
1060 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1061 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1062 struct intel_connector *intel_connector);
1063 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1064 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1065 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1066 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1067 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1068 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1069 bool intel_dp_compute_config(struct intel_encoder *encoder,
1070 struct intel_crtc_state *pipe_config);
1071 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1072 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1074 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1075 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1076 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1077 void intel_edp_panel_on(struct intel_dp *intel_dp);
1078 void intel_edp_panel_off(struct intel_dp *intel_dp);
1079 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1080 void intel_dp_mst_suspend(struct drm_device *dev);
1081 void intel_dp_mst_resume(struct drm_device *dev);
1082 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1083 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1084 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1085 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1086 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1087 void intel_plane_destroy(struct drm_plane *plane);
1088 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1089 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1090 void intel_edp_drrs_invalidate(struct drm_device *dev,
1091 unsigned frontbuffer_bits);
1092 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1094 /* intel_dp_mst.c */
1095 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1096 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1098 void intel_dsi_init(struct drm_device *dev);
1102 void intel_dvo_init(struct drm_device *dev);
1105 /* legacy fbdev emulation in intel_fbdev.c */
1106 #ifdef CONFIG_DRM_I915_FBDEV
1107 extern int intel_fbdev_init(struct drm_device *dev);
1108 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1109 extern void intel_fbdev_fini(struct drm_device *dev);
1110 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1111 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1112 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1114 static inline int intel_fbdev_init(struct drm_device *dev)
1119 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1123 static inline void intel_fbdev_fini(struct drm_device *dev)
1127 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1131 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1137 bool intel_fbc_enabled(struct drm_device *dev);
1138 void intel_fbc_update(struct drm_device *dev);
1139 void intel_fbc_init(struct drm_i915_private *dev_priv);
1140 void intel_fbc_disable(struct drm_device *dev);
1141 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1142 unsigned int frontbuffer_bits,
1143 enum fb_op_origin origin);
1144 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1145 unsigned int frontbuffer_bits);
1148 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1149 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1150 struct intel_connector *intel_connector);
1151 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1152 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1153 struct intel_crtc_state *pipe_config);
1157 void intel_lvds_init(struct drm_device *dev);
1158 bool intel_is_dual_link_lvds(struct drm_device *dev);
1162 int intel_connector_update_modes(struct drm_connector *connector,
1164 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1165 void intel_attach_force_audio_property(struct drm_connector *connector);
1166 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1169 /* intel_overlay.c */
1170 void intel_setup_overlay(struct drm_device *dev);
1171 void intel_cleanup_overlay(struct drm_device *dev);
1172 int intel_overlay_switch_off(struct intel_overlay *overlay);
1173 int intel_overlay_put_image(struct drm_device *dev, void *data,
1174 struct drm_file *file_priv);
1175 int intel_overlay_attrs(struct drm_device *dev, void *data,
1176 struct drm_file *file_priv);
1177 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1181 int intel_panel_init(struct intel_panel *panel,
1182 struct drm_display_mode *fixed_mode,
1183 struct drm_display_mode *downclock_mode);
1184 void intel_panel_fini(struct intel_panel *panel);
1185 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1186 struct drm_display_mode *adjusted_mode);
1187 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1188 struct intel_crtc_state *pipe_config,
1190 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1191 struct intel_crtc_state *pipe_config,
1193 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1194 u32 level, u32 max);
1195 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1196 void intel_panel_enable_backlight(struct intel_connector *connector);
1197 void intel_panel_disable_backlight(struct intel_connector *connector);
1198 void intel_panel_destroy_backlight(struct drm_connector *connector);
1199 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1200 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1201 extern struct drm_display_mode *intel_find_panel_downclock(
1202 struct drm_device *dev,
1203 struct drm_display_mode *fixed_mode,
1204 struct drm_connector *connector);
1205 void intel_backlight_register(struct drm_device *dev);
1206 void intel_backlight_unregister(struct drm_device *dev);
1210 void intel_psr_enable(struct intel_dp *intel_dp);
1211 void intel_psr_disable(struct intel_dp *intel_dp);
1212 void intel_psr_invalidate(struct drm_device *dev,
1213 unsigned frontbuffer_bits);
1214 void intel_psr_flush(struct drm_device *dev,
1215 unsigned frontbuffer_bits);
1216 void intel_psr_init(struct drm_device *dev);
1218 /* intel_runtime_pm.c */
1219 int intel_power_domains_init(struct drm_i915_private *);
1220 void intel_power_domains_fini(struct drm_i915_private *);
1221 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1222 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1224 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1225 enum intel_display_power_domain domain);
1226 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1227 enum intel_display_power_domain domain);
1228 void intel_display_power_get(struct drm_i915_private *dev_priv,
1229 enum intel_display_power_domain domain);
1230 void intel_display_power_put(struct drm_i915_private *dev_priv,
1231 enum intel_display_power_domain domain);
1232 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1233 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1234 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1235 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1236 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1238 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1241 void intel_init_clock_gating(struct drm_device *dev);
1242 void intel_suspend_hw(struct drm_device *dev);
1243 int ilk_wm_max_level(const struct drm_device *dev);
1244 void intel_update_watermarks(struct drm_crtc *crtc);
1245 void intel_update_sprite_watermarks(struct drm_plane *plane,
1246 struct drm_crtc *crtc,
1247 uint32_t sprite_width,
1248 uint32_t sprite_height,
1250 bool enabled, bool scaled);
1251 void intel_init_pm(struct drm_device *dev);
1252 void intel_pm_setup(struct drm_device *dev);
1253 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1254 void intel_gpu_ips_teardown(void);
1255 void intel_init_gt_powersave(struct drm_device *dev);
1256 void intel_cleanup_gt_powersave(struct drm_device *dev);
1257 void intel_enable_gt_powersave(struct drm_device *dev);
1258 void intel_disable_gt_powersave(struct drm_device *dev);
1259 void intel_suspend_gt_powersave(struct drm_device *dev);
1260 void intel_reset_gt_powersave(struct drm_device *dev);
1261 void gen6_update_ring_freq(struct drm_device *dev);
1262 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1263 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1264 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1265 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1266 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1267 struct drm_i915_gem_request *rq);
1268 void ilk_wm_get_hw_state(struct drm_device *dev);
1269 void skl_wm_get_hw_state(struct drm_device *dev);
1270 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1271 struct skl_ddb_allocation *ddb /* out */);
1275 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1278 /* intel_sprite.c */
1279 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1280 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1282 int intel_plane_restore(struct drm_plane *plane);
1283 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1284 struct drm_file *file_priv);
1285 bool intel_pipe_update_start(struct intel_crtc *crtc,
1286 uint32_t *start_vbl_count);
1287 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1288 void intel_post_enable_primary(struct drm_crtc *crtc);
1289 void intel_pre_disable_primary(struct drm_crtc *crtc);
1292 void intel_tv_init(struct drm_device *dev);
1294 /* intel_atomic.c */
1295 int intel_atomic_check(struct drm_device *dev,
1296 struct drm_atomic_state *state);
1297 int intel_atomic_commit(struct drm_device *dev,
1298 struct drm_atomic_state *state,
1300 int intel_connector_atomic_get_property(struct drm_connector *connector,
1301 const struct drm_connector_state *state,
1302 struct drm_property *property,
1304 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1305 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1306 struct drm_crtc_state *state);
1307 static inline struct intel_crtc_state *
1308 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1309 struct intel_crtc *crtc)
1311 struct drm_crtc_state *crtc_state;
1312 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1313 if (IS_ERR(crtc_state))
1314 return ERR_PTR(PTR_ERR(crtc_state));
1316 return to_intel_crtc_state(crtc_state);
1319 /* intel_atomic_plane.c */
1320 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1321 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1322 void intel_plane_destroy_state(struct drm_plane *plane,
1323 struct drm_plane_state *state);
1324 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1326 #endif /* __INTEL_DRV_H__ */