drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <linux/stackdepot.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include <drm/drm_rect.h>
  42 #include <drm/drm_vblank.h>
  43 #include <drm/drm_atomic.h>
  44 #include <media/cec-notifier.h>
  45
  46 struct drm_printer;
  47
  48 /**
  49  * __wait_for - magic wait macro
  50  *
  51  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  52  * important that we check the condition again after having timed out, since the
  53  * timeout could be due to preemption or similar and we've never had a chance to
  54  * check the condition before the timeout.
  55  */
  56 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  57         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  58         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  59         int ret__;                                                      \
  60         might_sleep();                                                  \
  61         for (;;) {                                                      \
  62                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  63                 OP;                                                     \
  64                 /* Guarantee COND check prior to timeout */             \
  65                 barrier();                                              \
  66                 if (COND) {                                             \
  67                         ret__ = 0;                                      \
  68                         break;                                          \
  69                 }                                                       \
  70                 if (expired__) {                                        \
  71                         ret__ = -ETIMEDOUT;                             \
  72                         break;                                          \
  73                 }                                                       \
  74                 usleep_range(wait__, wait__ * 2);                       \
  75                 if (wait__ < (Wmax))                                    \
  76                         wait__ <<= 1;                                   \
  77         }                                                               \
  78         ret__;                                                          \
  79 })
  80
  81 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  82                                                    (Wmax))
  83 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  84
  85 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  86 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  87 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  88 #else
  89 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  90 #endif
  91
  92 #define _wait_for_atomic(COND, US, ATOMIC) \
  93 ({ \
  94         int cpu, ret, timeout = (US) * 1000; \
  95         u64 base; \
  96         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  97         if (!(ATOMIC)) { \
  98                 preempt_disable(); \
  99                 cpu = smp_processor_id(); \
 100         } \
 101         base = local_clock(); \
 102         for (;;) { \
 103                 u64 now = local_clock(); \
 104                 if (!(ATOMIC)) \
 105                         preempt_enable(); \
 106                 /* Guarantee COND check prior to timeout */ \
 107                 barrier(); \
 108                 if (COND) { \
 109                         ret = 0; \
 110                         break; \
 111                 } \
 112                 if (now - base >= timeout) { \
 113                         ret = -ETIMEDOUT; \
 114                         break; \
 115                 } \
 116                 cpu_relax(); \
 117                 if (!(ATOMIC)) { \
 118                         preempt_disable(); \
 119                         if (unlikely(cpu != smp_processor_id())) { \
 120                                 timeout -= now - base; \
 121                                 cpu = smp_processor_id(); \
 122                                 base = local_clock(); \
 123                         } \
 124                 } \
 125         } \
 126         ret; \
 127 })
 128
 129 #define wait_for_us(COND, US) \
 130 ({ \
 131         int ret__; \
 132         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 133         if ((US) > 10) \
 134                 ret__ = _wait_for((COND), (US), 10, 10); \
 135         else \
 136                 ret__ = _wait_for_atomic((COND), (US), 0); \
 137         ret__; \
 138 })
 139
 140 #define wait_for_atomic_us(COND, US) \
 141 ({ \
 142         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 143         BUILD_BUG_ON((US) > 50000); \
 144         _wait_for_atomic((COND), (US), 1); \
 145 })
 146
 147 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 148
 149 #define KHz(x) (1000 * (x))
 150 #define MHz(x) KHz(1000 * (x))
 151
 152 #define KBps(x) (1000 * (x))
 153 #define MBps(x) KBps(1000 * (x))
 154 #define GBps(x) ((u64)1000 * MBps((x)))
 155
 156 /*
 157  * Display related stuff
 158  */
 159
 160 /* store information about an Ixxx DVO */
 161 /* The i830->i865 use multiple DVOs with multiple i2cs */
 162 /* the i915, i945 have a single sDVO i2c bus - which is different */
 163 #define MAX_OUTPUTS 6
 164 /* maximum connectors per crtcs in the mode set */
 165
 166 #define INTEL_I2C_BUS_DVO 1
 167 #define INTEL_I2C_BUS_SDVO 2
 168
 169 /* these are outputs from the chip - integrated only
 170    external chips are via DVO or SDVO output */
 171 enum intel_output_type {
 172         INTEL_OUTPUT_UNUSED = 0,
 173         INTEL_OUTPUT_ANALOG = 1,
 174         INTEL_OUTPUT_DVO = 2,
 175         INTEL_OUTPUT_SDVO = 3,
 176         INTEL_OUTPUT_LVDS = 4,
 177         INTEL_OUTPUT_TVOUT = 5,
 178         INTEL_OUTPUT_HDMI = 6,
 179         INTEL_OUTPUT_DP = 7,
 180         INTEL_OUTPUT_EDP = 8,
 181         INTEL_OUTPUT_DSI = 9,
 182         INTEL_OUTPUT_DDI = 10,
 183         INTEL_OUTPUT_DP_MST = 11,
 184 };
 185
 186 #define INTEL_DVO_CHIP_NONE 0
 187 #define INTEL_DVO_CHIP_LVDS 1
 188 #define INTEL_DVO_CHIP_TMDS 2
 189 #define INTEL_DVO_CHIP_TVOUT 4
 190
 191 #define INTEL_DSI_VIDEO_MODE    0
 192 #define INTEL_DSI_COMMAND_MODE  1
 193
 194 struct intel_framebuffer {
 195         struct drm_framebuffer base;
 196         struct intel_rotation_info rot_info;
 197
 198         /* for each plane in the normal GTT view */
 199         struct {
 200                 unsigned int x, y;
 201         } normal[2];
 202         /* for each plane in the rotated GTT view */
 203         struct {
 204                 unsigned int x, y;
 205                 unsigned int pitch; /* pixels */
 206         } rotated[2];
 207 };
 208
 209 struct intel_fbdev {
 210         struct drm_fb_helper helper;
 211         struct intel_framebuffer *fb;
 212         struct i915_vma *vma;
 213         unsigned long vma_flags;
 214         async_cookie_t cookie;
 215         int preferred_bpp;
 216
 217         /* Whether or not fbdev hpd processing is temporarily suspended */
 218         bool hpd_suspended : 1;
 219         /* Set when a hotplug was received while HPD processing was
 220          * suspended
 221          */
 222         bool hpd_waiting : 1;
 223
 224         /* Protects hpd_suspended */
 225         struct mutex hpd_lock;
 226 };
 227
 228 struct intel_encoder {
 229         struct drm_encoder base;
 230
 231         enum intel_output_type type;
 232         enum port port;
 233         unsigned int cloneable;
 234         bool (*hotplug)(struct intel_encoder *encoder,
 235                         struct intel_connector *connector);
 236         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 237                                                       struct intel_crtc_state *,
 238                                                       struct drm_connector_state *);
 239         int (*compute_config)(struct intel_encoder *,
 240                               struct intel_crtc_state *,
 241                               struct drm_connector_state *);
 242         void (*pre_pll_enable)(struct intel_encoder *,
 243                                const struct intel_crtc_state *,
 244                                const struct drm_connector_state *);
 245         void (*pre_enable)(struct intel_encoder *,
 246                            const struct intel_crtc_state *,
 247                            const struct drm_connector_state *);
 248         void (*enable)(struct intel_encoder *,
 249                        const struct intel_crtc_state *,
 250                        const struct drm_connector_state *);
 251         void (*disable)(struct intel_encoder *,
 252                         const struct intel_crtc_state *,
 253                         const struct drm_connector_state *);
 254         void (*post_disable)(struct intel_encoder *,
 255                              const struct intel_crtc_state *,
 256                              const struct drm_connector_state *);
 257         void (*post_pll_disable)(struct intel_encoder *,
 258                                  const struct intel_crtc_state *,
 259                                  const struct drm_connector_state *);
 260         void (*update_pipe)(struct intel_encoder *,
 261                             const struct intel_crtc_state *,
 262                             const struct drm_connector_state *);
 263         /* Read out the current hw state of this connector, returning true if
 264          * the encoder is active. If the encoder is enabled it also set the pipe
 265          * it is connected to in the pipe parameter. */
 266         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 267         /* Reconstructs the equivalent mode flags for the current hardware
 268          * state. This must be called _after_ display->get_pipe_config has
 269          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 270          * be set correctly before calling this function. */
 271         void (*get_config)(struct intel_encoder *,
 272                            struct intel_crtc_state *pipe_config);
 273         /*
 274          * Acquires the power domains needed for an active encoder during
 275          * hardware state readout.
 276          */
 277         void (*get_power_domains)(struct intel_encoder *encoder,
 278                                   struct intel_crtc_state *crtc_state);
 279         /*
 280          * Called during system suspend after all pending requests for the
 281          * encoder are flushed (for example for DP AUX transactions) and
 282          * device interrupts are disabled.
 283          */
 284         void (*suspend)(struct intel_encoder *);
 285         int crtc_mask;
 286         enum hpd_pin hpd_pin;
 287         enum intel_display_power_domain power_domain;
 288         /* for communication with audio component; protected by av_mutex */
 289         const struct drm_connector *audio_connector;
 290 };
 291
 292 struct intel_panel {
 293         struct drm_display_mode *fixed_mode;
 294         struct drm_display_mode *downclock_mode;
 295
 296         /* backlight */
 297         struct {
 298                 bool present;
 299                 u32 level;
 300                 u32 min;
 301                 u32 max;
 302                 bool enabled;
 303                 bool combination_mode;  /* gen 2/4 only */
 304                 bool active_low_pwm;
 305                 bool alternate_pwm_increment;   /* lpt+ */
 306
 307                 /* PWM chip */
 308                 bool util_pin_active_low;       /* bxt+ */
 309                 u8 controller;          /* bxt+ only */
 310                 struct pwm_device *pwm;
 311
 312                 struct backlight_device *device;
 313
 314                 /* Connector and platform specific backlight functions */
 315                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 316                 u32 (*get)(struct intel_connector *connector);
 317                 void (*set)(const struct drm_connector_state *conn_state, u32 level);
 318                 void (*disable)(const struct drm_connector_state *conn_state);
 319                 void (*enable)(const struct intel_crtc_state *crtc_state,
 320                                const struct drm_connector_state *conn_state);
 321                 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
 322                 void (*power)(struct intel_connector *, bool enable);
 323         } backlight;
 324 };
 325
 326 struct intel_digital_port;
 327
 328 /*
 329  * This structure serves as a translation layer between the generic HDCP code
 330  * and the bus-specific code. What that means is that HDCP over HDMI differs
 331  * from HDCP over DP, so to account for these differences, we need to
 332  * communicate with the receiver through this shim.
 333  *
 334  * For completeness, the 2 buses differ in the following ways:
 335  *      - DP AUX vs. DDC
 336  *              HDCP registers on the receiver are set via DP AUX for DP, and
 337  *              they are set via DDC for HDMI.
 338  *      - Receiver register offsets
 339  *              The offsets of the registers are different for DP vs. HDMI
 340  *      - Receiver register masks/offsets
 341  *              For instance, the ready bit for the KSV fifo is in a different
 342  *              place on DP vs HDMI
 343  *      - Receiver register names
 344  *              Seriously. In the DP spec, the 16-bit register containing
 345  *              downstream information is called BINFO, on HDMI it's called
 346  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 347  *              with a completely different definition.
 348  *      - KSV FIFO
 349  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 350  *              be read 3 keys at a time
 351  *      - Aksv output
 352  *              Since Aksv is hidden in hardware, there's different procedures
 353  *              to send it over DP AUX vs DDC
 354  */
 355 struct intel_hdcp_shim {
 356         /* Outputs the transmitter's An and Aksv values to the receiver. */
 357         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 358
 359         /* Reads the receiver's key selection vector */
 360         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 361
 362         /*
 363          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 364          * definitions are the same in the respective specs, but the names are
 365          * different. Call it BSTATUS since that's the name the HDMI spec
 366          * uses and it was there first.
 367          */
 368         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 369                             u8 *bstatus);
 370
 371         /* Determines whether a repeater is present downstream */
 372         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 373                                 bool *repeater_present);
 374
 375         /* Reads the receiver's Ri' value */
 376         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 377
 378         /* Determines if the receiver's KSV FIFO is ready for consumption */
 379         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 380                               bool *ksv_ready);
 381
 382         /* Reads the ksv fifo for num_downstream devices */
 383         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 384                              int num_downstream, u8 *ksv_fifo);
 385
 386         /* Reads a 32-bit part of V' from the receiver */
 387         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 388                                  int i, u32 *part);
 389
 390         /* Enables HDCP signalling on the port */
 391         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 392                                  bool enable);
 393
 394         /* Ensures the link is still protected */
 395         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 396
 397         /* Detects panel's hdcp capability. This is optional for HDMI. */
 398         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 399                             bool *hdcp_capable);
 400 };
 401
 402 struct intel_hdcp {
 403         const struct intel_hdcp_shim *shim;
 404         /* Mutex for hdcp state of the connector */
 405         struct mutex mutex;
 406         u64 value;
 407         struct delayed_work check_work;
 408         struct work_struct prop_work;
 409 };
 410
 411 struct intel_connector {
 412         struct drm_connector base;
 413         /*
 414          * The fixed encoder this connector is connected to.
 415          */
 416         struct intel_encoder *encoder;
 417
 418         /* ACPI device id for ACPI and driver cooperation */
 419         u32 acpi_device_id;
 420
 421         /* Reads out the current hw, returning true if the connector is enabled
 422          * and active (i.e. dpms ON state). */
 423         bool (*get_hw_state)(struct intel_connector *);
 424
 425         /* Panel info for eDP and LVDS */
 426         struct intel_panel panel;
 427
 428         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 429         struct edid *edid;
 430         struct edid *detect_edid;
 431
 432         /* since POLL and HPD connectors may use the same HPD line keep the native
 433            state of connector->polled in case hotplug storm detection changes it */
 434         u8 polled;
 435
 436         void *port; /* store this opaque as its illegal to dereference it */
 437
 438         struct intel_dp *mst_port;
 439
 440         /* Work struct to schedule a uevent on link train failure */
 441         struct work_struct modeset_retry_work;
 442
 443         struct intel_hdcp hdcp;
 444 };
 445
 446 struct intel_digital_connector_state {
 447         struct drm_connector_state base;
 448
 449         enum hdmi_force_audio force_audio;
 450         int broadcast_rgb;
 451 };
 452
 453 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 454
 455 struct dpll {
 456         /* given values */
 457         int n;
 458         int m1, m2;
 459         int p1, p2;
 460         /* derived values */
 461         int     dot;
 462         int     vco;
 463         int     m;
 464         int     p;
 465 };
 466
 467 struct intel_atomic_state {
 468         struct drm_atomic_state base;
 469
 470         struct {
 471                 /*
 472                  * Logical state of cdclk (used for all scaling, watermark,
 473                  * etc. calculations and checks). This is computed as if all
 474                  * enabled crtcs were active.
 475                  */
 476                 struct intel_cdclk_state logical;
 477
 478                 /*
 479                  * Actual state of cdclk, can be different from the logical
 480                  * state only when all crtc's are DPMS off.
 481                  */
 482                 struct intel_cdclk_state actual;
 483         } cdclk;
 484
 485         bool dpll_set, modeset;
 486
 487         /*
 488          * Does this transaction change the pipes that are active?  This mask
 489          * tracks which CRTC's have changed their active state at the end of
 490          * the transaction (not counting the temporary disable during modesets).
 491          * This mask should only be non-zero when intel_state->modeset is true,
 492          * but the converse is not necessarily true; simply changing a mode may
 493          * not flip the final active status of any CRTC's
 494          */
 495         unsigned int active_pipe_changes;
 496
 497         unsigned int active_crtcs;
 498         /* minimum acceptable cdclk for each pipe */
 499         int min_cdclk[I915_MAX_PIPES];
 500         /* minimum acceptable voltage level for each pipe */
 501         u8 min_voltage_level[I915_MAX_PIPES];
 502
 503         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 504
 505         /*
 506          * Current watermarks can't be trusted during hardware readout, so
 507          * don't bother calculating intermediate watermarks.
 508          */
 509         bool skip_intermediate_wm;
 510
 511         bool rps_interactive;
 512
 513         /* Gen9+ only */
 514         struct skl_ddb_values wm_results;
 515
 516         struct i915_sw_fence commit_ready;
 517
 518         struct llist_node freed;
 519 };
 520
 521 struct intel_plane_state {
 522         struct drm_plane_state base;
 523         struct i915_ggtt_view view;
 524         struct i915_vma *vma;
 525         unsigned long flags;
 526 #define PLANE_HAS_FENCE BIT(0)
 527
 528         struct {
 529                 u32 offset;
 530                 /*
 531                  * Plane stride in:
 532                  * bytes for 0/180 degree rotation
 533                  * pixels for 90/270 degree rotation
 534                  */
 535                 u32 stride;
 536                 int x, y;
 537         } color_plane[2];
 538
 539         /* plane control register */
 540         u32 ctl;
 541
 542         /* plane color control register */
 543         u32 color_ctl;
 544
 545         /*
 546          * scaler_id
 547          *    = -1 : not using a scaler
 548          *    >=  0 : using a scalers
 549          *
 550          * plane requiring a scaler:
 551          *   - During check_plane, its bit is set in
 552          *     crtc_state->scaler_state.scaler_users by calling helper function
 553          *     update_scaler_plane.
 554          *   - scaler_id indicates the scaler it got assigned.
 555          *
 556          * plane doesn't require a scaler:
 557          *   - this can happen when scaling is no more required or plane simply
 558          *     got disabled.
 559          *   - During check_plane, corresponding bit is reset in
 560          *     crtc_state->scaler_state.scaler_users by calling helper function
 561          *     update_scaler_plane.
 562          */
 563         int scaler_id;
 564
 565         /*
 566          * linked_plane:
 567          *
 568          * ICL planar formats require 2 planes that are updated as pairs.
 569          * This member is used to make sure the other plane is also updated
 570          * when required, and for update_slave() to find the correct
 571          * plane_state to pass as argument.
 572          */
 573         struct intel_plane *linked_plane;
 574
 575         /*
 576          * slave:
 577          * If set don't update use the linked plane's state for updating
 578          * this plane during atomic commit with the update_slave() callback.
 579          *
 580          * It's also used by the watermark code to ignore wm calculations on
 581          * this plane. They're calculated by the linked plane's wm code.
 582          */
 583         u32 slave;
 584
 585         struct drm_intel_sprite_colorkey ckey;
 586 };
 587
 588 struct intel_initial_plane_config {
 589         struct intel_framebuffer *fb;
 590         unsigned int tiling;
 591         int size;
 592         u32 base;
 593         u8 rotation;
 594 };
 595
 596 #define SKL_MIN_SRC_W 8
 597 #define SKL_MAX_SRC_W 4096
 598 #define SKL_MIN_SRC_H 8
 599 #define SKL_MAX_SRC_H 4096
 600 #define SKL_MIN_DST_W 8
 601 #define SKL_MAX_DST_W 4096
 602 #define SKL_MIN_DST_H 8
 603 #define SKL_MAX_DST_H 4096
 604 #define ICL_MAX_SRC_W 5120
 605 #define ICL_MAX_SRC_H 4096
 606 #define ICL_MAX_DST_W 5120
 607 #define ICL_MAX_DST_H 4096
 608 #define SKL_MIN_YUV_420_SRC_W 16
 609 #define SKL_MIN_YUV_420_SRC_H 16
 610
 611 struct intel_scaler {
 612         int in_use;
 613         u32 mode;
 614 };
 615
 616 struct intel_crtc_scaler_state {
 617 #define SKL_NUM_SCALERS 2
 618         struct intel_scaler scalers[SKL_NUM_SCALERS];
 619
 620         /*
 621          * scaler_users: keeps track of users requesting scalers on this crtc.
 622          *
 623          *     If a bit is set, a user is using a scaler.
 624          *     Here user can be a plane or crtc as defined below:
 625          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 626          *       bit 31    - crtc
 627          *
 628          * Instead of creating a new index to cover planes and crtc, using
 629          * existing drm_plane_index for planes which is well less than 31
 630          * planes and bit 31 for crtc. This should be fine to cover all
 631          * our platforms.
 632          *
 633          * intel_atomic_setup_scalers will setup available scalers to users
 634          * requesting scalers. It will gracefully fail if request exceeds
 635          * avilability.
 636          */
 637 #define SKL_CRTC_INDEX 31
 638         unsigned scaler_users;
 639
 640         /* scaler used by crtc for panel fitting purpose */
 641         int scaler_id;
 642 };
 643
 644 /* drm_mode->private_flags */
 645 #define I915_MODE_FLAG_INHERITED (1<<0)
 646 /* Flag to get scanline using frame time stamps */
 647 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 648 /* Flag to use the scanline counter instead of the pixel counter */
 649 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
 650
 651 struct intel_pipe_wm {
 652         struct intel_wm_level wm[5];
 653         u32 linetime;
 654         bool fbc_wm_enabled;
 655         bool pipe_enabled;
 656         bool sprites_enabled;
 657         bool sprites_scaled;
 658 };
 659
 660 struct skl_plane_wm {
 661         struct skl_wm_level wm[8];
 662         struct skl_wm_level uv_wm[8];
 663         struct skl_wm_level trans_wm;
 664         bool is_planar;
 665 };
 666
 667 struct skl_pipe_wm {
 668         struct skl_plane_wm planes[I915_MAX_PLANES];
 669         u32 linetime;
 670 };
 671
 672 enum vlv_wm_level {
 673         VLV_WM_LEVEL_PM2,
 674         VLV_WM_LEVEL_PM5,
 675         VLV_WM_LEVEL_DDR_DVFS,
 676         NUM_VLV_WM_LEVELS,
 677 };
 678
 679 struct vlv_wm_state {
 680         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 681         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 682         u8 num_levels;
 683         bool cxsr;
 684 };
 685
 686 struct vlv_fifo_state {
 687         u16 plane[I915_MAX_PLANES];
 688 };
 689
 690 enum g4x_wm_level {
 691         G4X_WM_LEVEL_NORMAL,
 692         G4X_WM_LEVEL_SR,
 693         G4X_WM_LEVEL_HPLL,
 694         NUM_G4X_WM_LEVELS,
 695 };
 696
 697 struct g4x_wm_state {
 698         struct g4x_pipe_wm wm;
 699         struct g4x_sr_wm sr;
 700         struct g4x_sr_wm hpll;
 701         bool cxsr;
 702         bool hpll_en;
 703         bool fbc_en;
 704 };
 705
 706 struct intel_crtc_wm_state {
 707         union {
 708                 struct {
 709                         /*
 710                          * Intermediate watermarks; these can be
 711                          * programmed immediately since they satisfy
 712                          * both the current configuration we're
 713                          * switching away from and the new
 714                          * configuration we're switching to.
 715                          */
 716                         struct intel_pipe_wm intermediate;
 717
 718                         /*
 719                          * Optimal watermarks, programmed post-vblank
 720                          * when this state is committed.
 721                          */
 722                         struct intel_pipe_wm optimal;
 723                 } ilk;
 724
 725                 struct {
 726                         /* gen9+ only needs 1-step wm programming */
 727                         struct skl_pipe_wm optimal;
 728                         struct skl_ddb_entry ddb;
 729                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 730                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 731                 } skl;
 732
 733                 struct {
 734                         /* "raw" watermarks (not inverted) */
 735                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 736                         /* intermediate watermarks (inverted) */
 737                         struct vlv_wm_state intermediate;
 738                         /* optimal watermarks (inverted) */
 739                         struct vlv_wm_state optimal;
 740                         /* display FIFO split */
 741                         struct vlv_fifo_state fifo_state;
 742                 } vlv;
 743
 744                 struct {
 745                         /* "raw" watermarks */
 746                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 747                         /* intermediate watermarks */
 748                         struct g4x_wm_state intermediate;
 749                         /* optimal watermarks */
 750                         struct g4x_wm_state optimal;
 751                 } g4x;
 752         };
 753
 754         /*
 755          * Platforms with two-step watermark programming will need to
 756          * update watermark programming post-vblank to switch from the
 757          * safe intermediate watermarks to the optimal final
 758          * watermarks.
 759          */
 760         bool need_postvbl_update;
 761 };
 762
 763 enum intel_output_format {
 764         INTEL_OUTPUT_FORMAT_INVALID,
 765         INTEL_OUTPUT_FORMAT_RGB,
 766         INTEL_OUTPUT_FORMAT_YCBCR420,
 767         INTEL_OUTPUT_FORMAT_YCBCR444,
 768 };
 769
 770 struct intel_crtc_state {
 771         struct drm_crtc_state base;
 772
 773         /**
 774          * quirks - bitfield with hw state readout quirks
 775          *
 776          * For various reasons the hw state readout code might not be able to
 777          * completely faithfully read out the current state. These cases are
 778          * tracked with quirk flags so that fastboot and state checker can act
 779          * accordingly.
 780          */
 781 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 782         unsigned long quirks;
 783
 784         unsigned fb_bits; /* framebuffers to flip */
 785         bool update_pipe; /* can a fast modeset be performed? */
 786         bool disable_cxsr;
 787         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 788         bool fb_changed; /* fb on any of the planes is changed */
 789         bool fifo_changed; /* FIFO split is changed */
 790
 791         /* Pipe source size (ie. panel fitter input size)
 792          * All planes will be positioned inside this space,
 793          * and get clipped at the edges. */
 794         int pipe_src_w, pipe_src_h;
 795
 796         /*
 797          * Pipe pixel rate, adjusted for
 798          * panel fitter/pipe scaler downscaling.
 799          */
 800         unsigned int pixel_rate;
 801
 802         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 803          * between pch encoders and cpu encoders. */
 804         bool has_pch_encoder;
 805
 806         /* Are we sending infoframes on the attached port */
 807         bool has_infoframe;
 808
 809         /* CPU Transcoder for the pipe. Currently this can only differ from the
 810          * pipe on Haswell and later (where we have a special eDP transcoder)
 811          * and Broxton (where we have special DSI transcoders). */
 812         enum transcoder cpu_transcoder;
 813
 814         /*
 815          * Use reduced/limited/broadcast rbg range, compressing from the full
 816          * range fed into the crtcs.
 817          */
 818         bool limited_color_range;
 819
 820         /* Bitmask of encoder types (enum intel_output_type)
 821          * driven by the pipe.
 822          */
 823         unsigned int output_types;
 824
 825         /* Whether we should send NULL infoframes. Required for audio. */
 826         bool has_hdmi_sink;
 827
 828         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 829          * has_dp_encoder is set. */
 830         bool has_audio;
 831
 832         /*
 833          * Enable dithering, used when the selected pipe bpp doesn't match the
 834          * plane bpp.
 835          */
 836         bool dither;
 837
 838         /*
 839          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 840          * compliance video pattern tests.
 841          * Disable dither only if it is a compliance test request for
 842          * 18bpp.
 843          */
 844         bool dither_force_disable;
 845
 846         /* Controls for the clock computation, to override various stages. */
 847         bool clock_set;
 848
 849         /* SDVO TV has a bunch of special case. To make multifunction encoders
 850          * work correctly, we need to track this at runtime.*/
 851         bool sdvo_tv_clock;
 852
 853         /*
 854          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 855          * required. This is set in the 2nd loop of calling encoder's
 856          * ->compute_config if the first pick doesn't work out.
 857          */
 858         bool bw_constrained;
 859
 860         /* Settings for the intel dpll used on pretty much everything but
 861          * haswell. */
 862         struct dpll dpll;
 863
 864         /* Selected dpll when shared or NULL. */
 865         struct intel_shared_dpll *shared_dpll;
 866
 867         /* Actual register state of the dpll, for shared dpll cross-checking. */
 868         struct intel_dpll_hw_state dpll_hw_state;
 869
 870         /* DSI PLL registers */
 871         struct {
 872                 u32 ctrl, div;
 873         } dsi_pll;
 874
 875         int pipe_bpp;
 876         struct intel_link_m_n dp_m_n;
 877
 878         /* m2_n2 for eDP downclock */
 879         struct intel_link_m_n dp_m2_n2;
 880         bool has_drrs;
 881
 882         bool has_psr;
 883         bool has_psr2;
 884
 885         /*
 886          * Frequence the dpll for the port should run at. Differs from the
 887          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 888          * already multiplied by pixel_multiplier.
 889          */
 890         int port_clock;
 891
 892         /* Used by SDVO (and if we ever fix it, HDMI). */
 893         unsigned pixel_multiplier;
 894
 895         u8 lane_count;
 896
 897         /*
 898          * Used by platforms having DP/HDMI PHY with programmable lane
 899          * latency optimization.
 900          */
 901         u8 lane_lat_optim_mask;
 902
 903         /* minimum acceptable voltage level */
 904         u8 min_voltage_level;
 905
 906         /* Panel fitter controls for gen2-gen4 + VLV */
 907         struct {
 908                 u32 control;
 909                 u32 pgm_ratios;
 910                 u32 lvds_border_bits;
 911         } gmch_pfit;
 912
 913         /* Panel fitter placement and size for Ironlake+ */
 914         struct {
 915                 u32 pos;
 916                 u32 size;
 917                 bool enabled;
 918                 bool force_thru;
 919         } pch_pfit;
 920
 921         /* FDI configuration, only valid if has_pch_encoder is set. */
 922         int fdi_lanes;
 923         struct intel_link_m_n fdi_m_n;
 924
 925         bool ips_enabled;
 926         bool ips_force_disable;
 927
 928         bool enable_fbc;
 929
 930         bool double_wide;
 931
 932         int pbn;
 933
 934         struct intel_crtc_scaler_state scaler_state;
 935
 936         /* w/a for waiting 2 vblanks during crtc enable */
 937         enum pipe hsw_workaround_pipe;
 938
 939         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 940         bool disable_lp_wm;
 941
 942         struct intel_crtc_wm_state wm;
 943
 944         /* Gamma mode programmed on the pipe */
 945         u32 gamma_mode;
 946
 947         /* bitmask of visible planes (enum plane_id) */
 948         u8 active_planes;
 949         u8 nv12_planes;
 950
 951         /* bitmask of planes that will be updated during the commit */
 952         u8 update_planes;
 953
 954         /* HDMI scrambling status */
 955         bool hdmi_scrambling;
 956
 957         /* HDMI High TMDS char rate ratio */
 958         bool hdmi_high_tmds_clock_ratio;
 959
 960         /* Output format RGB/YCBCR etc */
 961         enum intel_output_format output_format;
 962
 963         /* Output down scaling is done in LSPCON device */
 964         bool lspcon_downsampling;
 965
 966         /* Display Stream compression state */
 967         struct {
 968                 bool compression_enable;
 969                 bool dsc_split;
 970                 u16 compressed_bpp;
 971                 u8 slice_count;
 972         } dsc_params;
 973         struct drm_dsc_config dp_dsc_cfg;
 974
 975         /* Forward Error correction State */
 976         bool fec_enable;
 977 };
 978
 979 struct intel_crtc {
 980         struct drm_crtc base;
 981         enum pipe pipe;
 982         /*
 983          * Whether the crtc and the connected output pipeline is active. Implies
 984          * that crtc->enabled is set, i.e. the current mode configuration has
 985          * some outputs connected to this crtc.
 986          */
 987         bool active;
 988         u8 plane_ids_mask;
 989         unsigned long long enabled_power_domains;
 990         struct intel_overlay *overlay;
 991
 992         struct intel_crtc_state *config;
 993
 994         /* global reset count when the last flip was submitted */
 995         unsigned int reset_count;
 996
 997         /* Access to these should be protected by dev_priv->irq_lock. */
 998         bool cpu_fifo_underrun_disabled;
 999         bool pch_fifo_underrun_disabled;
1000
1001         /* per-pipe watermark state */
1002         struct {
1003                 /* watermarks currently being used  */
1004                 union {
1005                         struct intel_pipe_wm ilk;
1006                         struct vlv_wm_state vlv;
1007                         struct g4x_wm_state g4x;
1008                 } active;
1009         } wm;
1010
1011         int scanline_offset;
1012
1013         struct {
1014                 unsigned start_vbl_count;
1015                 ktime_t start_vbl_time;
1016                 int min_vbl, max_vbl;
1017                 int scanline_start;
1018         } debug;
1019
1020         /* scalers available on this crtc */
1021         int num_scalers;
1022 };
1023
1024 struct intel_plane {
1025         struct drm_plane base;
1026         enum i9xx_plane_id i9xx_plane;
1027         enum plane_id id;
1028         enum pipe pipe;
1029         bool has_fbc;
1030         bool has_ccs;
1031         u32 frontbuffer_bit;
1032
1033         struct {
1034                 u32 base, cntl, size;
1035         } cursor;
1036
1037         /*
1038          * NOTE: Do not place new plane state fields here (e.g., when adding
1039          * new plane properties).  New runtime state should now be placed in
1040          * the intel_plane_state structure and accessed via plane_state.
1041          */
1042
1043         unsigned int (*max_stride)(struct intel_plane *plane,
1044                                    u32 pixel_format, u64 modifier,
1045                                    unsigned int rotation);
1046         void (*update_plane)(struct intel_plane *plane,
1047                              const struct intel_crtc_state *crtc_state,
1048                              const struct intel_plane_state *plane_state);
1049         void (*update_slave)(struct intel_plane *plane,
1050                              const struct intel_crtc_state *crtc_state,
1051                              const struct intel_plane_state *plane_state);
1052         void (*disable_plane)(struct intel_plane *plane,
1053                               const struct intel_crtc_state *crtc_state);
1054         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1055         int (*check_plane)(struct intel_crtc_state *crtc_state,
1056                            struct intel_plane_state *plane_state);
1057 };
1058
1059 struct intel_watermark_params {
1060         u16 fifo_size;
1061         u16 max_wm;
1062         u8 default_wm;
1063         u8 guard_size;
1064         u8 cacheline_size;
1065 };
1066
1067 struct cxsr_latency {
1068         bool is_desktop : 1;
1069         bool is_ddr3 : 1;
1070         u16 fsb_freq;
1071         u16 mem_freq;
1072         u16 display_sr;
1073         u16 display_hpll_disable;
1074         u16 cursor_sr;
1075         u16 cursor_hpll_disable;
1076 };
1077
1078 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1079 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1080 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1081 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1082 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1083 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1084 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1085 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1086 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1087
1088 struct intel_hdmi {
1089         i915_reg_t hdmi_reg;
1090         int ddc_bus;
1091         struct {
1092                 enum drm_dp_dual_mode_type type;
1093                 int max_tmds_clock;
1094         } dp_dual_mode;
1095         bool has_hdmi_sink;
1096         bool has_audio;
1097         struct intel_connector *attached_connector;
1098         struct cec_notifier *cec_notifier;
1099 };
1100
1101 struct intel_dp_mst_encoder;
1102 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1103
1104 /*
1105  * enum link_m_n_set:
1106  *      When platform provides two set of M_N registers for dp, we can
1107  *      program them and switch between them incase of DRRS.
1108  *      But When only one such register is provided, we have to program the
1109  *      required divider value on that registers itself based on the DRRS state.
1110  *
1111  * M1_N1        : Program dp_m_n on M1_N1 registers
1112  *                        dp_m2_n2 on M2_N2 registers (If supported)
1113  *
1114  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1115  *                        M2_N2 registers are not supported
1116  */
1117
1118 enum link_m_n_set {
1119         /* Sets the m1_n1 and m2_n2 */
1120         M1_N1 = 0,
1121         M2_N2
1122 };
1123
1124 struct intel_dp_compliance_data {
1125         unsigned long edid;
1126         u8 video_pattern;
1127         u16 hdisplay, vdisplay;
1128         u8 bpc;
1129 };
1130
1131 struct intel_dp_compliance {
1132         unsigned long test_type;
1133         struct intel_dp_compliance_data test_data;
1134         bool test_active;
1135         int test_link_rate;
1136         u8 test_lane_count;
1137 };
1138
1139 struct intel_dp {
1140         i915_reg_t output_reg;
1141         u32 DP;
1142         int link_rate;
1143         u8 lane_count;
1144         u8 sink_count;
1145         bool link_mst;
1146         bool link_trained;
1147         bool has_audio;
1148         bool reset_link_params;
1149         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1150         u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1151         u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1152         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1153         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1154         u8 fec_capable;
1155         /* source rates */
1156         int num_source_rates;
1157         const int *source_rates;
1158         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1159         int num_sink_rates;
1160         int sink_rates[DP_MAX_SUPPORTED_RATES];
1161         bool use_rate_select;
1162         /* intersection of source and sink rates */
1163         int num_common_rates;
1164         int common_rates[DP_MAX_SUPPORTED_RATES];
1165         /* Max lane count for the current link */
1166         int max_link_lane_count;
1167         /* Max rate for the current link */
1168         int max_link_rate;
1169         /* sink or branch descriptor */
1170         struct drm_dp_desc desc;
1171         struct drm_dp_aux aux;
1172         u8 train_set[4];
1173         int panel_power_up_delay;
1174         int panel_power_down_delay;
1175         int panel_power_cycle_delay;
1176         int backlight_on_delay;
1177         int backlight_off_delay;
1178         struct delayed_work panel_vdd_work;
1179         bool want_panel_vdd;
1180         unsigned long last_power_on;
1181         unsigned long last_backlight_off;
1182         ktime_t panel_power_off_time;
1183
1184         struct notifier_block edp_notifier;
1185
1186         /*
1187          * Pipe whose power sequencer is currently locked into
1188          * this port. Only relevant on VLV/CHV.
1189          */
1190         enum pipe pps_pipe;
1191         /*
1192          * Pipe currently driving the port. Used for preventing
1193          * the use of the PPS for any pipe currentrly driving
1194          * external DP as that will mess things up on VLV.
1195          */
1196         enum pipe active_pipe;
1197         /*
1198          * Set if the sequencer may be reset due to a power transition,
1199          * requiring a reinitialization. Only relevant on BXT.
1200          */
1201         bool pps_reset;
1202         struct edp_power_seq pps_delays;
1203
1204         bool can_mst; /* this port supports mst */
1205         bool is_mst;
1206         int active_mst_links;
1207         /* connector directly attached - won't be use for modeset in mst world */
1208         struct intel_connector *attached_connector;
1209
1210         /* mst connector list */
1211         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1212         struct drm_dp_mst_topology_mgr mst_mgr;
1213
1214         u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1215         /*
1216          * This function returns the value we have to program the AUX_CTL
1217          * register with to kick off an AUX transaction.
1218          */
1219         u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1220                                 u32 aux_clock_divider);
1221
1222         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1223         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1224
1225         /* This is called before a link training is starterd */
1226         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1227
1228         /* Displayport compliance testing */
1229         struct intel_dp_compliance compliance;
1230
1231         /* Display stream compression testing */
1232         bool force_dsc_en;
1233 };
1234
1235 enum lspcon_vendor {
1236         LSPCON_VENDOR_MCA,
1237         LSPCON_VENDOR_PARADE
1238 };
1239
1240 struct intel_lspcon {
1241         bool active;
1242         enum drm_lspcon_mode mode;
1243         enum lspcon_vendor vendor;
1244 };
1245
1246 struct intel_digital_port {
1247         struct intel_encoder base;
1248         u32 saved_port_bits;
1249         struct intel_dp dp;
1250         struct intel_hdmi hdmi;
1251         struct intel_lspcon lspcon;
1252         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1253         bool release_cl2_override;
1254         u8 max_lanes;
1255         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1256         enum aux_ch aux_ch;
1257         enum intel_display_power_domain ddi_io_power_domain;
1258         bool tc_legacy_port:1;
1259         enum tc_port_type tc_type;
1260
1261         void (*write_infoframe)(struct intel_encoder *encoder,
1262                                 const struct intel_crtc_state *crtc_state,
1263                                 unsigned int type,
1264                                 const void *frame, ssize_t len);
1265         void (*set_infoframes)(struct intel_encoder *encoder,
1266                                bool enable,
1267                                const struct intel_crtc_state *crtc_state,
1268                                const struct drm_connector_state *conn_state);
1269         bool (*infoframe_enabled)(struct intel_encoder *encoder,
1270                                   const struct intel_crtc_state *pipe_config);
1271 };
1272
1273 struct intel_dp_mst_encoder {
1274         struct intel_encoder base;
1275         enum pipe pipe;
1276         struct intel_digital_port *primary;
1277         struct intel_connector *connector;
1278 };
1279
1280 static inline enum dpio_channel
1281 vlv_dport_to_channel(struct intel_digital_port *dport)
1282 {
1283         switch (dport->base.port) {
1284         case PORT_B:
1285         case PORT_D:
1286                 return DPIO_CH0;
1287         case PORT_C:
1288                 return DPIO_CH1;
1289         default:
1290                 BUG();
1291         }
1292 }
1293
1294 static inline enum dpio_phy
1295 vlv_dport_to_phy(struct intel_digital_port *dport)
1296 {
1297         switch (dport->base.port) {
1298         case PORT_B:
1299         case PORT_C:
1300                 return DPIO_PHY0;
1301         case PORT_D:
1302                 return DPIO_PHY1;
1303         default:
1304                 BUG();
1305         }
1306 }
1307
1308 static inline enum dpio_channel
1309 vlv_pipe_to_channel(enum pipe pipe)
1310 {
1311         switch (pipe) {
1312         case PIPE_A:
1313         case PIPE_C:
1314                 return DPIO_CH0;
1315         case PIPE_B:
1316                 return DPIO_CH1;
1317         default:
1318                 BUG();
1319         }
1320 }
1321
1322 static inline struct intel_crtc *
1323 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1324 {
1325         return dev_priv->pipe_to_crtc_mapping[pipe];
1326 }
1327
1328 static inline struct intel_crtc *
1329 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1330 {
1331         return dev_priv->plane_to_crtc_mapping[plane];
1332 }
1333
1334 struct intel_load_detect_pipe {
1335         struct drm_atomic_state *restore_state;
1336 };
1337
1338 static inline struct intel_encoder *
1339 intel_attached_encoder(struct drm_connector *connector)
1340 {
1341         return to_intel_connector(connector)->encoder;
1342 }
1343
1344 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1345 {
1346         switch (encoder->type) {
1347         case INTEL_OUTPUT_DDI:
1348         case INTEL_OUTPUT_DP:
1349         case INTEL_OUTPUT_EDP:
1350         case INTEL_OUTPUT_HDMI:
1351                 return true;
1352         default:
1353                 return false;
1354         }
1355 }
1356
1357 static inline struct intel_digital_port *
1358 enc_to_dig_port(struct drm_encoder *encoder)
1359 {
1360         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1361
1362         if (intel_encoder_is_dig_port(intel_encoder))
1363                 return container_of(encoder, struct intel_digital_port,
1364                                     base.base);
1365         else
1366                 return NULL;
1367 }
1368
1369 static inline struct intel_digital_port *
1370 conn_to_dig_port(struct intel_connector *connector)
1371 {
1372         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1373 }
1374
1375 static inline struct intel_dp_mst_encoder *
1376 enc_to_mst(struct drm_encoder *encoder)
1377 {
1378         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1379 }
1380
1381 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1382 {
1383         return &enc_to_dig_port(encoder)->dp;
1384 }
1385
1386 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1387 {
1388         switch (encoder->type) {
1389         case INTEL_OUTPUT_DP:
1390         case INTEL_OUTPUT_EDP:
1391                 return true;
1392         case INTEL_OUTPUT_DDI:
1393                 /* Skip pure HDMI/DVI DDI encoders */
1394                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1395         default:
1396                 return false;
1397         }
1398 }
1399
1400 static inline struct intel_lspcon *
1401 enc_to_intel_lspcon(struct drm_encoder *encoder)
1402 {
1403         return &enc_to_dig_port(encoder)->lspcon;
1404 }
1405
1406 static inline struct intel_digital_port *
1407 dp_to_dig_port(struct intel_dp *intel_dp)
1408 {
1409         return container_of(intel_dp, struct intel_digital_port, dp);
1410 }
1411
1412 static inline struct intel_lspcon *
1413 dp_to_lspcon(struct intel_dp *intel_dp)
1414 {
1415         return &dp_to_dig_port(intel_dp)->lspcon;
1416 }
1417
1418 static inline struct drm_i915_private *
1419 dp_to_i915(struct intel_dp *intel_dp)
1420 {
1421         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1422 }
1423
1424 static inline struct intel_digital_port *
1425 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1426 {
1427         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1428 }
1429
1430 static inline struct intel_plane_state *
1431 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1432                                  struct intel_plane *plane)
1433 {
1434         struct drm_plane_state *ret =
1435                 drm_atomic_get_plane_state(&state->base, &plane->base);
1436
1437         if (IS_ERR(ret))
1438                 return ERR_CAST(ret);
1439
1440         return to_intel_plane_state(ret);
1441 }
1442
1443 static inline struct intel_plane_state *
1444 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1445                                  struct intel_plane *plane)
1446 {
1447         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1448                                                                    &plane->base));
1449 }
1450
1451 static inline struct intel_plane_state *
1452 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1453                                  struct intel_plane *plane)
1454 {
1455         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1456                                                                    &plane->base));
1457 }
1458
1459 static inline struct intel_crtc_state *
1460 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1461                                 struct intel_crtc *crtc)
1462 {
1463         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1464                                                                  &crtc->base));
1465 }
1466
1467 static inline struct intel_crtc_state *
1468 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1469                                 struct intel_crtc *crtc)
1470 {
1471         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1472                                                                  &crtc->base));
1473 }
1474
1475 /* intel_fifo_underrun.c */
1476 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1477                                            enum pipe pipe, bool enable);
1478 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1479                                            enum pipe pch_transcoder,
1480                                            bool enable);
1481 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1482                                          enum pipe pipe);
1483 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1484                                          enum pipe pch_transcoder);
1485 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1486 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1487
1488 /* i915_irq.c */
1489 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1490 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1491 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1492 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1493 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1494 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1495 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1496 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1497
1498 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1499                                             u32 mask)
1500 {
1501         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1502 }
1503
1504 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1505 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1506 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1507 {
1508         /*
1509          * We only use drm_irq_uninstall() at unload and VT switch, so
1510          * this is the only thing we need to check.
1511          */
1512         return dev_priv->runtime_pm.irqs_enabled;
1513 }
1514
1515 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1516 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1517                                      u8 pipe_mask);
1518 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1519                                      u8 pipe_mask);
1520 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1521 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1522 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1523
1524 /* intel_crt.c */
1525 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1526                             i915_reg_t adpa_reg, enum pipe *pipe);
1527 void intel_crt_init(struct drm_i915_private *dev_priv);
1528 void intel_crt_reset(struct drm_encoder *encoder);
1529
1530 /* intel_ddi.c */
1531 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1532                                 const struct intel_crtc_state *old_crtc_state,
1533                                 const struct drm_connector_state *old_conn_state);
1534 void hsw_fdi_link_train(struct intel_crtc *crtc,
1535                         const struct intel_crtc_state *crtc_state);
1536 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1537 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1538 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1539 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1540 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1541 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1542 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1543 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1544 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1545 void intel_ddi_get_config(struct intel_encoder *encoder,
1546                           struct intel_crtc_state *pipe_config);
1547
1548 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1549                                     bool state);
1550 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1551                                          struct intel_crtc_state *crtc_state);
1552 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1553 u32 ddi_signal_levels(struct intel_dp *intel_dp);
1554 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1555 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1556                                  u8 voltage_swing);
1557 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1558                                      bool enable);
1559 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1560 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1561                         enum intel_dpll_id pll_id);
1562
1563 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1564                                    int color_plane, unsigned int height);
1565
1566 /* intel_audio.c */
1567 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1568 void intel_audio_codec_enable(struct intel_encoder *encoder,
1569                               const struct intel_crtc_state *crtc_state,
1570                               const struct drm_connector_state *conn_state);
1571 void intel_audio_codec_disable(struct intel_encoder *encoder,
1572                                const struct intel_crtc_state *old_crtc_state,
1573                                const struct drm_connector_state *old_conn_state);
1574 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1575 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1576 void intel_audio_init(struct drm_i915_private *dev_priv);
1577 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1578
1579 /* intel_cdclk.c */
1580 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1581 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1582 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1583 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1584 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1585 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1586 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1587 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1588 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1589 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1590 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1591 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1592 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1593 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1594                                const struct intel_cdclk_state *b);
1595 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1596                          const struct intel_cdclk_state *b);
1597 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1598                      const struct intel_cdclk_state *cdclk_state);
1599 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1600                             const char *context);
1601
1602 /* intel_display.c */
1603 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1604 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1605 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1606 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1607 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1608                       const char *name, u32 reg, int ref_freq);
1609 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1610                            const char *name, u32 reg);
1611 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1612 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1613 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1614 unsigned int intel_fb_xy_to_linear(int x, int y,
1615                                    const struct intel_plane_state *state,
1616                                    int plane);
1617 void intel_add_fb_offsets(int *x, int *y,
1618                           const struct intel_plane_state *state, int plane);
1619 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1620 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1621 void intel_mark_busy(struct drm_i915_private *dev_priv);
1622 void intel_mark_idle(struct drm_i915_private *dev_priv);
1623 int intel_display_suspend(struct drm_device *dev);
1624 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1625 void intel_encoder_destroy(struct drm_encoder *encoder);
1626 struct drm_display_mode *
1627 intel_encoder_current_mode(struct intel_encoder *encoder);
1628 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1629 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1630 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1631                               enum port port);
1632 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1633                                       struct drm_file *file_priv);
1634 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1635                                              enum pipe pipe);
1636 static inline bool
1637 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1638                     enum intel_output_type type)
1639 {
1640         return crtc_state->output_types & (1 << type);
1641 }
1642 static inline bool
1643 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1644 {
1645         return crtc_state->output_types &
1646                 ((1 << INTEL_OUTPUT_DP) |
1647                  (1 << INTEL_OUTPUT_DP_MST) |
1648                  (1 << INTEL_OUTPUT_EDP));
1649 }
1650 static inline void
1651 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1652 {
1653         drm_wait_one_vblank(&dev_priv->drm, pipe);
1654 }
1655 static inline void
1656 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1657 {
1658         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1659
1660         if (crtc->active)
1661                 intel_wait_for_vblank(dev_priv, pipe);
1662 }
1663
1664 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1665
1666 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1667 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1668                          struct intel_digital_port *dport,
1669                          unsigned int expected_mask);
1670 int intel_get_load_detect_pipe(struct drm_connector *connector,
1671                                const struct drm_display_mode *mode,
1672                                struct intel_load_detect_pipe *old,
1673                                struct drm_modeset_acquire_ctx *ctx);
1674 void intel_release_load_detect_pipe(struct drm_connector *connector,
1675                                     struct intel_load_detect_pipe *old,
1676                                     struct drm_modeset_acquire_ctx *ctx);
1677 struct i915_vma *
1678 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1679                            const struct i915_ggtt_view *view,
1680                            bool uses_fence,
1681                            unsigned long *out_flags);
1682 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1683 struct drm_framebuffer *
1684 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1685                          struct drm_mode_fb_cmd2 *mode_cmd);
1686 int intel_prepare_plane_fb(struct drm_plane *plane,
1687                            struct drm_plane_state *new_state);
1688 void intel_cleanup_plane_fb(struct drm_plane *plane,
1689                             struct drm_plane_state *old_state);
1690 int intel_plane_atomic_get_property(struct drm_plane *plane,
1691                                     const struct drm_plane_state *state,
1692                                     struct drm_property *property,
1693                                     u64 *val);
1694 int intel_plane_atomic_set_property(struct drm_plane *plane,
1695                                     struct drm_plane_state *state,
1696                                     struct drm_property *property,
1697                                     u64 val);
1698 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1699                                     struct drm_crtc_state *crtc_state,
1700                                     const struct intel_plane_state *old_plane_state,
1701                                     struct drm_plane_state *plane_state);
1702
1703 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1704                                     enum pipe pipe);
1705
1706 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1707                      const struct dpll *dpll);
1708 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1709 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1710
1711 /* modesetting asserts */
1712 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1713                            enum pipe pipe);
1714 void assert_pll(struct drm_i915_private *dev_priv,
1715                 enum pipe pipe, bool state);
1716 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1717 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1718 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1719 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1720 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1721 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1722                        enum pipe pipe, bool state);
1723 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1724 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1725 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1726 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1727 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1728 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1729 void intel_finish_reset(struct drm_i915_private *dev_priv);
1730 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1731 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1732 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1733 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1734 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1735 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1736 unsigned int skl_cdclk_get_vco(unsigned int freq);
1737 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1738 void intel_dp_get_m_n(struct intel_crtc *crtc,
1739                       struct intel_crtc_state *pipe_config);
1740 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1741                       enum link_m_n_set m_n);
1742 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1743 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1744                         struct dpll *best_clock);
1745 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1746
1747 bool intel_crtc_active(struct intel_crtc *crtc);
1748 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1749 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1750 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1751 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1752 enum intel_display_power_domain
1753 intel_aux_power_domain(struct intel_digital_port *dig_port);
1754 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1755                                  struct intel_crtc_state *pipe_config);
1756 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1757                                   struct intel_crtc_state *crtc_state);
1758
1759 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1760 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1761 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1762                   u32 pixel_format);
1763
1764 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1765 {
1766         return i915_ggtt_offset(state->vma);
1767 }
1768
1769 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1770                         const struct intel_plane_state *plane_state);
1771 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1772 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1773                   const struct intel_plane_state *plane_state);
1774 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1775 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1776                      int plane);
1777 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1778 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1779 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1780 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1781                                    u32 pixel_format, u64 modifier,
1782                                    unsigned int rotation);
1783
1784 /* intel_connector.c */
1785 int intel_connector_init(struct intel_connector *connector);
1786 struct intel_connector *intel_connector_alloc(void);
1787 void intel_connector_free(struct intel_connector *connector);
1788 void intel_connector_destroy(struct drm_connector *connector);
1789 int intel_connector_register(struct drm_connector *connector);
1790 void intel_connector_unregister(struct drm_connector *connector);
1791 void intel_connector_attach_encoder(struct intel_connector *connector,
1792                                     struct intel_encoder *encoder);
1793 bool intel_connector_get_hw_state(struct intel_connector *connector);
1794 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1795 int intel_connector_update_modes(struct drm_connector *connector,
1796                                  struct edid *edid);
1797 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1798 void intel_attach_force_audio_property(struct drm_connector *connector);
1799 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1800 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1801
1802 /* intel_csr.c */
1803 void intel_csr_ucode_init(struct drm_i915_private *);
1804 void intel_csr_load_program(struct drm_i915_private *);
1805 void intel_csr_ucode_fini(struct drm_i915_private *);
1806 void intel_csr_ucode_suspend(struct drm_i915_private *);
1807 void intel_csr_ucode_resume(struct drm_i915_private *);
1808
1809 /* intel_dp.c */
1810 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1811                            i915_reg_t dp_reg, enum port port,
1812                            enum pipe *pipe);
1813 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1814                    enum port port);
1815 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1816                              struct intel_connector *intel_connector);
1817 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1818                               int link_rate, u8 lane_count,
1819                               bool link_mst);
1820 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1821                                             int link_rate, u8 lane_count);
1822 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1823 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1824 int intel_dp_retrain_link(struct intel_encoder *encoder,
1825                           struct drm_modeset_acquire_ctx *ctx);
1826 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1827 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1828                                            const struct intel_crtc_state *crtc_state,
1829                                            bool enable);
1830 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1831 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1832 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1833 int intel_dp_compute_config(struct intel_encoder *encoder,
1834                             struct intel_crtc_state *pipe_config,
1835                             struct drm_connector_state *conn_state);
1836 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1837 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1838 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1839                                   bool long_hpd);
1840 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1841                             const struct drm_connector_state *conn_state);
1842 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1843 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1844 void intel_edp_panel_on(struct intel_dp *intel_dp);
1845 void intel_edp_panel_off(struct intel_dp *intel_dp);
1846 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1847 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1848 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1849 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1850 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1851 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1852 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1853 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
1854 void intel_plane_destroy(struct drm_plane *plane);
1855 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1856                            const struct intel_crtc_state *crtc_state);
1857 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1858                             const struct intel_crtc_state *crtc_state);
1859 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1860                                unsigned int frontbuffer_bits);
1861 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1862                           unsigned int frontbuffer_bits);
1863
1864 void
1865 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1866                                        u8 dp_train_pat);
1867 void
1868 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1869 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1870 u8
1871 intel_dp_voltage_max(struct intel_dp *intel_dp);
1872 u8
1873 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
1874 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1875                            u8 *link_bw, u8 *rate_select);
1876 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1877 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1878 bool
1879 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
1880 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
1881                                 int mode_clock, int mode_hdisplay);
1882 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1883                                 int mode_hdisplay);
1884
1885 /* intel_vdsc.c */
1886 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1887                                 struct intel_crtc_state *pipe_config);
1888 enum intel_display_power_domain
1889 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1890
1891 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1892 {
1893         return ~((1 << lane_count) - 1) & 0xf;
1894 }
1895
1896 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1897 int intel_dp_link_required(int pixel_clock, int bpp);
1898 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1899 bool intel_digital_port_connected(struct intel_encoder *encoder);
1900 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
1901                            struct intel_digital_port *dig_port);
1902
1903 /* intel_dp_aux_backlight.c */
1904 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1905
1906 /* intel_dp_mst.c */
1907 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1908 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1909 /* vlv_dsi.c */
1910 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1911
1912 /* icl_dsi.c */
1913 void icl_dsi_init(struct drm_i915_private *dev_priv);
1914
1915 /* intel_dsi_dcs_backlight.c */
1916 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1917
1918 /* intel_dvo.c */
1919 void intel_dvo_init(struct drm_i915_private *dev_priv);
1920 /* intel_hotplug.c */
1921 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1922 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1923                            struct intel_connector *connector);
1924
1925 /* legacy fbdev emulation in intel_fbdev.c */
1926 #ifdef CONFIG_DRM_FBDEV_EMULATION
1927 extern int intel_fbdev_init(struct drm_device *dev);
1928 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1929 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1930 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1931 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1932 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1933 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1934 #else
1935 static inline int intel_fbdev_init(struct drm_device *dev)
1936 {
1937         return 0;
1938 }
1939
1940 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1941 {
1942 }
1943
1944 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1945 {
1946 }
1947
1948 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1949 {
1950 }
1951
1952 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1953 {
1954 }
1955
1956 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1957 {
1958 }
1959
1960 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1961 {
1962 }
1963 #endif
1964
1965 /* intel_fbc.c */
1966 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1967                            struct intel_atomic_state *state);
1968 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1969 void intel_fbc_pre_update(struct intel_crtc *crtc,
1970                           struct intel_crtc_state *crtc_state,
1971                           struct intel_plane_state *plane_state);
1972 void intel_fbc_post_update(struct intel_crtc *crtc);
1973 void intel_fbc_init(struct drm_i915_private *dev_priv);
1974 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1975 void intel_fbc_enable(struct intel_crtc *crtc,
1976                       struct intel_crtc_state *crtc_state,
1977                       struct intel_plane_state *plane_state);
1978 void intel_fbc_disable(struct intel_crtc *crtc);
1979 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1980 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1981                           unsigned int frontbuffer_bits,
1982                           enum fb_op_origin origin);
1983 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1984                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1985 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1986 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1987 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1988
1989 /* intel_hdmi.c */
1990 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1991                      enum port port);
1992 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1993                                struct intel_connector *intel_connector);
1994 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1995 int intel_hdmi_compute_config(struct intel_encoder *encoder,
1996                               struct intel_crtc_state *pipe_config,
1997                               struct drm_connector_state *conn_state);
1998 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1999                                        struct drm_connector *connector,
2000                                        bool high_tmds_clock_ratio,
2001                                        bool scrambling);
2002 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
2003 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
2004
2005 /* intel_lvds.c */
2006 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
2007                              i915_reg_t lvds_reg, enum pipe *pipe);
2008 void intel_lvds_init(struct drm_i915_private *dev_priv);
2009 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
2010 bool intel_is_dual_link_lvds(struct drm_device *dev);
2011
2012 /* intel_overlay.c */
2013 void intel_overlay_setup(struct drm_i915_private *dev_priv);
2014 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2015 int intel_overlay_switch_off(struct intel_overlay *overlay);
2016 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2017                                   struct drm_file *file_priv);
2018 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2019                               struct drm_file *file_priv);
2020 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2021
2022
2023 /* intel_panel.c */
2024 int intel_panel_init(struct intel_panel *panel,
2025                      struct drm_display_mode *fixed_mode,
2026                      struct drm_display_mode *downclock_mode);
2027 void intel_panel_fini(struct intel_panel *panel);
2028 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2029                             struct drm_display_mode *adjusted_mode);
2030 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2031                              struct intel_crtc_state *pipe_config,
2032                              int fitting_mode);
2033 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2034                               struct intel_crtc_state *pipe_config,
2035                               int fitting_mode);
2036 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2037                                     u32 level, u32 max);
2038 int intel_panel_setup_backlight(struct drm_connector *connector,
2039                                 enum pipe pipe);
2040 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2041                                   const struct drm_connector_state *conn_state);
2042 void intel_panel_update_backlight(struct intel_encoder *encoder,
2043                                   const struct intel_crtc_state *crtc_state,
2044                                   const struct drm_connector_state *conn_state);
2045 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2046 extern struct drm_display_mode *intel_find_panel_downclock(
2047                                 struct drm_i915_private *dev_priv,
2048                                 struct drm_display_mode *fixed_mode,
2049                                 struct drm_connector *connector);
2050
2051 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2052 int intel_backlight_device_register(struct intel_connector *connector);
2053 void intel_backlight_device_unregister(struct intel_connector *connector);
2054 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2055 static inline int intel_backlight_device_register(struct intel_connector *connector)
2056 {
2057         return 0;
2058 }
2059 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2060 {
2061 }
2062 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2063
2064 /* intel_hdcp.c */
2065 void intel_hdcp_atomic_check(struct drm_connector *connector,
2066                              struct drm_connector_state *old_state,
2067                              struct drm_connector_state *new_state);
2068 int intel_hdcp_init(struct intel_connector *connector,
2069                     const struct intel_hdcp_shim *hdcp_shim);
2070 int intel_hdcp_enable(struct intel_connector *connector);
2071 int intel_hdcp_disable(struct intel_connector *connector);
2072 int intel_hdcp_check_link(struct intel_connector *connector);
2073 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2074 bool intel_hdcp_capable(struct intel_connector *connector);
2075
2076 /* intel_psr.c */
2077 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2078 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2079 void intel_psr_enable(struct intel_dp *intel_dp,
2080                       const struct intel_crtc_state *crtc_state);
2081 void intel_psr_disable(struct intel_dp *intel_dp,
2082                       const struct intel_crtc_state *old_crtc_state);
2083 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2084                                struct drm_modeset_acquire_ctx *ctx,
2085                                u64 value);
2086 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2087                           unsigned frontbuffer_bits,
2088                           enum fb_op_origin origin);
2089 void intel_psr_flush(struct drm_i915_private *dev_priv,
2090                      unsigned frontbuffer_bits,
2091                      enum fb_op_origin origin);
2092 void intel_psr_init(struct drm_i915_private *dev_priv);
2093 void intel_psr_compute_config(struct intel_dp *intel_dp,
2094                               struct intel_crtc_state *crtc_state);
2095 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2096 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2097 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2098 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2099                             u32 *out_value);
2100 bool intel_psr_enabled(struct intel_dp *intel_dp);
2101
2102 /* intel_quirks.c */
2103 void intel_init_quirks(struct drm_i915_private *dev_priv);
2104
2105 /* intel_runtime_pm.c */
2106 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
2107 int intel_power_domains_init(struct drm_i915_private *);
2108 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2109 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2110 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2111 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2112 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2113 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2114 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2115
2116 enum i915_drm_suspend_mode {
2117         I915_DRM_SUSPEND_IDLE,
2118         I915_DRM_SUSPEND_MEM,
2119         I915_DRM_SUSPEND_HIBERNATE,
2120 };
2121
2122 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2123                                  enum i915_drm_suspend_mode);
2124 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2125 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2126 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2127 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2128 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2129 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
2130 const char *
2131 intel_display_power_domain_str(enum intel_display_power_domain domain);
2132
2133 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2134                                     enum intel_display_power_domain domain);
2135 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2136                                       enum intel_display_power_domain domain);
2137 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2138                                         enum intel_display_power_domain domain);
2139 intel_wakeref_t
2140 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2141                                    enum intel_display_power_domain domain);
2142 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2143                                        enum intel_display_power_domain domain);
2144 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2145 void intel_display_power_put(struct drm_i915_private *dev_priv,
2146                              enum intel_display_power_domain domain,
2147                              intel_wakeref_t wakeref);
2148 #else
2149 #define intel_display_power_put(i915, domain, wakeref) \
2150         intel_display_power_put_unchecked(i915, domain)
2151 #endif
2152 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2153                             u8 req_slices);
2154
2155 static inline void
2156 assert_rpm_device_not_suspended(struct drm_i915_private *i915)
2157 {
2158         WARN_ONCE(i915->runtime_pm.suspended,
2159                   "Device suspended during HW access\n");
2160 }
2161
2162 static inline void
2163 assert_rpm_wakelock_held(struct drm_i915_private *i915)
2164 {
2165         assert_rpm_device_not_suspended(i915);
2166         WARN_ONCE(!atomic_read(&i915->runtime_pm.wakeref_count),
2167                   "RPM wakelock ref not held during HW access");
2168 }
2169
2170 /**
2171  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2172  * @i915: i915 device instance
2173  *
2174  * This function disable asserts that check if we hold an RPM wakelock
2175  * reference, while keeping the device-not-suspended checks still enabled.
2176  * It's meant to be used only in special circumstances where our rule about
2177  * the wakelock refcount wrt. the device power state doesn't hold. According
2178  * to this rule at any point where we access the HW or want to keep the HW in
2179  * an active state we must hold an RPM wakelock reference acquired via one of
2180  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2181  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2182  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2183  * users should avoid using this function.
2184  *
2185  * Any calls to this function must have a symmetric call to
2186  * enable_rpm_wakeref_asserts().
2187  */
2188 static inline void
2189 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2190 {
2191         atomic_inc(&i915->runtime_pm.wakeref_count);
2192 }
2193
2194 /**
2195  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2196  * @i915: i915 device instance
2197  *
2198  * This function re-enables the RPM assert checks after disabling them with
2199  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2200  * circumstances otherwise its use should be avoided.
2201  *
2202  * Any calls to this function must have a symmetric call to
2203  * disable_rpm_wakeref_asserts().
2204  */
2205 static inline void
2206 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2207 {
2208         atomic_dec(&i915->runtime_pm.wakeref_count);
2209 }
2210
2211 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
2212 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
2213 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
2214
2215 #define with_intel_runtime_pm(i915, wf) \
2216         for ((wf) = intel_runtime_pm_get(i915); (wf); \
2217              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2218
2219 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2220         for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2221              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2222
2223 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
2224 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2225 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
2226 #else
2227 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2228 #endif
2229
2230 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2231 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2232                                     struct drm_printer *p);
2233 #else
2234 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2235                                                   struct drm_printer *p)
2236 {
2237 }
2238 #endif
2239
2240 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2241                              bool override, unsigned int mask);
2242 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2243                           enum dpio_channel ch, bool override);
2244
2245
2246 /* intel_pm.c */
2247 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2248 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2249 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2250 void intel_update_watermarks(struct intel_crtc *crtc);
2251 void intel_init_pm(struct drm_i915_private *dev_priv);
2252 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2253 void intel_pm_setup(struct drm_i915_private *dev_priv);
2254 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2255 void intel_gpu_ips_teardown(void);
2256 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2257 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2258 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2259 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2260 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2261 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2262 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2263 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2264 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2265 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2266 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2267 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2268 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2269 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2270 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2271                                struct skl_ddb_entry *ddb_y,
2272                                struct skl_ddb_entry *ddb_uv);
2273 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2274                           struct skl_ddb_allocation *ddb /* out */);
2275 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2276                               struct skl_pipe_wm *out);
2277 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2278 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2279 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2280 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2281 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2282 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2283                          const struct skl_wm_level *l2);
2284 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2285                                  const struct skl_ddb_entry entries[],
2286                                  int num_entries, int ignore_idx);
2287 void skl_write_plane_wm(struct intel_plane *plane,
2288                         const struct intel_crtc_state *crtc_state);
2289 void skl_write_cursor_wm(struct intel_plane *plane,
2290                          const struct intel_crtc_state *crtc_state);
2291 bool ilk_disable_lp_wm(struct drm_device *dev);
2292 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2293                                   struct intel_crtc_state *cstate);
2294 void intel_init_ipc(struct drm_i915_private *dev_priv);
2295 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2296
2297 /* intel_sdvo.c */
2298 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2299                              i915_reg_t sdvo_reg, enum pipe *pipe);
2300 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2301                      i915_reg_t reg, enum port port);
2302
2303
2304 /* intel_sprite.c */
2305 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2306                              int usecs);
2307 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2308                                               enum pipe pipe, int plane);
2309 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2310                                     struct drm_file *file_priv);
2311 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2312 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2313 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2314 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2315 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2316 struct intel_plane *
2317 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2318                            enum pipe pipe, enum plane_id plane_id);
2319
2320 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2321 {
2322         /* Don't need to do a gen check, these planes are only available on gen11 */
2323         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2324                 return true;
2325
2326         return false;
2327 }
2328
2329 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2330 {
2331         if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2332                 return false;
2333
2334         return plane->id < PLANE_SPRITE2;
2335 }
2336
2337 /* intel_tv.c */
2338 void intel_tv_init(struct drm_i915_private *dev_priv);
2339
2340 /* intel_atomic.c */
2341 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2342                                                 const struct drm_connector_state *state,
2343                                                 struct drm_property *property,
2344                                                 u64 *val);
2345 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2346                                                 struct drm_connector_state *state,
2347                                                 struct drm_property *property,
2348                                                 u64 val);
2349 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2350                                          struct drm_connector_state *new_state);
2351 struct drm_connector_state *
2352 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2353
2354 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2355 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2356                                struct drm_crtc_state *state);
2357 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2358 void intel_atomic_state_clear(struct drm_atomic_state *);
2359
2360 static inline struct intel_crtc_state *
2361 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2362                             struct intel_crtc *crtc)
2363 {
2364         struct drm_crtc_state *crtc_state;
2365         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2366         if (IS_ERR(crtc_state))
2367                 return ERR_CAST(crtc_state);
2368
2369         return to_intel_crtc_state(crtc_state);
2370 }
2371
2372 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2373                                struct intel_crtc *intel_crtc,
2374                                struct intel_crtc_state *crtc_state);
2375
2376 /* intel_atomic_plane.c */
2377 struct intel_plane *intel_plane_alloc(void);
2378 void intel_plane_free(struct intel_plane *plane);
2379 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2380 void intel_plane_destroy_state(struct drm_plane *plane,
2381                                struct drm_plane_state *state);
2382 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2383 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2384                                struct intel_crtc *crtc);
2385 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2386                                 struct intel_crtc *crtc);
2387 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2388                                         struct intel_crtc_state *crtc_state,
2389                                         const struct intel_plane_state *old_plane_state,
2390                                         struct intel_plane_state *intel_state);
2391
2392 /* intel_color.c */
2393 void intel_color_init(struct intel_crtc *crtc);
2394 int intel_color_check(struct intel_crtc_state *crtc_state);
2395 void intel_color_commit(const struct intel_crtc_state *crtc_state);
2396 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
2397
2398 /* intel_lspcon.c */
2399 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2400 void lspcon_resume(struct intel_lspcon *lspcon);
2401 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2402 void lspcon_write_infoframe(struct intel_encoder *encoder,
2403                             const struct intel_crtc_state *crtc_state,
2404                             unsigned int type,
2405                             const void *buf, ssize_t len);
2406 void lspcon_set_infoframes(struct intel_encoder *encoder,
2407                            bool enable,
2408                            const struct intel_crtc_state *crtc_state,
2409                            const struct drm_connector_state *conn_state);
2410 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2411                               const struct intel_crtc_state *pipe_config);
2412 void lspcon_ycbcr420_config(struct drm_connector *connector,
2413                             struct intel_crtc_state *crtc_state);
2414
2415 /* intel_pipe_crc.c */
2416 #ifdef CONFIG_DEBUG_FS
2417 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2418 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2419                                  const char *source_name, size_t *values_cnt);
2420 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2421                                               size_t *count);
2422 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2423 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2424 #else
2425 #define intel_crtc_set_crc_source NULL
2426 #define intel_crtc_verify_crc_source NULL
2427 #define intel_crtc_get_crc_sources NULL
2428 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2429 {
2430 }
2431
2432 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2433 {
2434 }
2435 #endif
2436 #endif /* __INTEL_DRV_H__ */