2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
40 * _wait_for - magic (register) wait macro
42 * Does the right thing for modeset paths when run under kdgb or similar atomic
43 * contexts. Note that it's important that we check the condition again after
44 * having timed out, since the timeout could be due to preemption or similar and
45 * we've never had a chance to check the condition before the timeout.
47 #define _wait_for(COND, MS, W) ({ \
48 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
51 if (time_after(jiffies, timeout__)) { \
56 if (W && drm_can_sleep()) { \
65 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
66 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
67 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
68 DIV_ROUND_UP((US), 1000), 0)
70 #define KHz(x) (1000 * (x))
71 #define MHz(x) KHz(1000 * (x))
74 * Display related stuff
77 /* store information about an Ixxx DVO */
78 /* The i830->i865 use multiple DVOs with multiple i2cs */
79 /* the i915, i945 have a single sDVO i2c bus - which is different */
81 /* maximum connectors per crtcs in the mode set */
83 /* Maximum cursor sizes */
84 #define GEN2_CURSOR_WIDTH 64
85 #define GEN2_CURSOR_HEIGHT 64
86 #define MAX_CURSOR_WIDTH 256
87 #define MAX_CURSOR_HEIGHT 256
89 #define INTEL_I2C_BUS_DVO 1
90 #define INTEL_I2C_BUS_SDVO 2
92 /* these are outputs from the chip - integrated only
93 external chips are via DVO or SDVO output */
94 enum intel_output_type {
95 INTEL_OUTPUT_UNUSED = 0,
96 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_SDVO = 3,
99 INTEL_OUTPUT_LVDS = 4,
100 INTEL_OUTPUT_TVOUT = 5,
101 INTEL_OUTPUT_HDMI = 6,
102 INTEL_OUTPUT_DISPLAYPORT = 7,
103 INTEL_OUTPUT_EDP = 8,
104 INTEL_OUTPUT_DSI = 9,
105 INTEL_OUTPUT_UNKNOWN = 10,
106 INTEL_OUTPUT_DP_MST = 11,
109 #define INTEL_DVO_CHIP_NONE 0
110 #define INTEL_DVO_CHIP_LVDS 1
111 #define INTEL_DVO_CHIP_TMDS 2
112 #define INTEL_DVO_CHIP_TVOUT 4
114 #define INTEL_DSI_VIDEO_MODE 0
115 #define INTEL_DSI_COMMAND_MODE 1
117 struct intel_framebuffer {
118 struct drm_framebuffer base;
119 struct drm_i915_gem_object *obj;
123 struct drm_fb_helper helper;
124 struct intel_framebuffer *fb;
125 struct list_head fbdev_list;
126 struct drm_display_mode *our_mode;
130 struct intel_encoder {
131 struct drm_encoder base;
133 * The new crtc this encoder will be driven from. Only differs from
134 * base->crtc while a modeset is in progress.
136 struct intel_crtc *new_crtc;
138 enum intel_output_type type;
139 unsigned int cloneable;
140 bool connectors_active;
141 void (*hot_plug)(struct intel_encoder *);
142 bool (*compute_config)(struct intel_encoder *,
143 struct intel_crtc_state *);
144 void (*pre_pll_enable)(struct intel_encoder *);
145 void (*pre_enable)(struct intel_encoder *);
146 void (*enable)(struct intel_encoder *);
147 void (*mode_set)(struct intel_encoder *intel_encoder);
148 void (*disable)(struct intel_encoder *);
149 void (*post_disable)(struct intel_encoder *);
150 /* Read out the current hw state of this connector, returning true if
151 * the encoder is active. If the encoder is enabled it also set the pipe
152 * it is connected to in the pipe parameter. */
153 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
154 /* Reconstructs the equivalent mode flags for the current hardware
155 * state. This must be called _after_ display->get_pipe_config has
156 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
157 * be set correctly before calling this function. */
158 void (*get_config)(struct intel_encoder *,
159 struct intel_crtc_state *pipe_config);
161 * Called during system suspend after all pending requests for the
162 * encoder are flushed (for example for DP AUX transactions) and
163 * device interrupts are disabled.
165 void (*suspend)(struct intel_encoder *);
167 enum hpd_pin hpd_pin;
171 struct drm_display_mode *fixed_mode;
172 struct drm_display_mode *downclock_mode;
182 bool combination_mode; /* gen 2/4 only */
184 struct backlight_device *device;
187 void (*backlight_power)(struct intel_connector *, bool enable);
190 struct intel_connector {
191 struct drm_connector base;
193 * The fixed encoder this connector is connected to.
195 struct intel_encoder *encoder;
198 * The new encoder this connector will be driven. Only differs from
199 * encoder while a modeset is in progress.
201 struct intel_encoder *new_encoder;
203 /* Reads out the current hw, returning true if the connector is enabled
204 * and active (i.e. dpms ON state). */
205 bool (*get_hw_state)(struct intel_connector *);
208 * Removes all interfaces through which the connector is accessible
209 * - like sysfs, debugfs entries -, so that no new operations can be
210 * started on the connector. Also makes sure all currently pending
211 * operations finish before returing.
213 void (*unregister)(struct intel_connector *);
215 /* Panel info for eDP and LVDS */
216 struct intel_panel panel;
218 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
220 struct edid *detect_edid;
222 /* since POLL and HPD connectors may use the same HPD line keep the native
223 state of connector->polled in case hotplug storm detection changes it */
226 void *port; /* store this opaque as its illegal to dereference it */
228 struct intel_dp *mst_port;
231 typedef struct dpll {
243 struct intel_plane_state {
244 struct drm_plane_state base;
247 struct drm_rect clip;
251 * used only for sprite planes to determine when to implicitly
252 * enable/disable the primary plane
257 struct intel_initial_plane_config {
263 struct intel_crtc_state {
264 struct drm_crtc_state base;
267 * quirks - bitfield with hw state readout quirks
269 * For various reasons the hw state readout code might not be able to
270 * completely faithfully read out the current state. These cases are
271 * tracked with quirk flags so that fastboot and state checker can act
274 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
275 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
276 unsigned long quirks;
278 /* Pipe source size (ie. panel fitter input size)
279 * All planes will be positioned inside this space,
280 * and get clipped at the edges. */
281 int pipe_src_w, pipe_src_h;
283 /* Whether to set up the PCH/FDI. Note that we never allow sharing
284 * between pch encoders and cpu encoders. */
285 bool has_pch_encoder;
287 /* Are we sending infoframes on the attached port */
290 /* CPU Transcoder for the pipe. Currently this can only differ from the
291 * pipe on Haswell (where we have a special eDP transcoder). */
292 enum transcoder cpu_transcoder;
295 * Use reduced/limited/broadcast rbg range, compressing from the full
296 * range fed into the crtcs.
298 bool limited_color_range;
300 /* DP has a bunch of special case unfortunately, so mark the pipe
304 /* Whether we should send NULL infoframes. Required for audio. */
307 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
308 * has_dp_encoder is set. */
312 * Enable dithering, used when the selected pipe bpp doesn't match the
317 /* Controls for the clock computation, to override various stages. */
320 /* SDVO TV has a bunch of special case. To make multifunction encoders
321 * work correctly, we need to track this at runtime.*/
325 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
326 * required. This is set in the 2nd loop of calling encoder's
327 * ->compute_config if the first pick doesn't work out.
331 /* Settings for the intel dpll used on pretty much everything but
335 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
336 enum intel_dpll_id shared_dpll;
339 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
340 * - enum skl_dpll on SKL
342 uint32_t ddi_pll_sel;
344 /* Actual register state of the dpll, for shared dpll cross-checking. */
345 struct intel_dpll_hw_state dpll_hw_state;
348 struct intel_link_m_n dp_m_n;
350 /* m2_n2 for eDP downclock */
351 struct intel_link_m_n dp_m2_n2;
355 * Frequence the dpll for the port should run at. Differs from the
356 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
357 * already multiplied by pixel_multiplier.
361 /* Used by SDVO (and if we ever fix it, HDMI). */
362 unsigned pixel_multiplier;
364 /* Panel fitter controls for gen2-gen4 + VLV */
368 u32 lvds_border_bits;
371 /* Panel fitter placement and size for Ironlake+ */
379 /* FDI configuration, only valid if has_pch_encoder is set. */
381 struct intel_link_m_n fdi_m_n;
387 bool dp_encoder_is_mst;
391 struct intel_pipe_wm {
392 struct intel_wm_level wm[5];
396 bool sprites_enabled;
400 struct intel_mmio_flip {
401 struct drm_i915_gem_request *req;
402 struct work_struct work;
406 struct skl_wm_level wm[8];
407 struct skl_wm_level trans_wm;
412 * Tracking of operations that need to be performed at the beginning/end of an
413 * atomic commit, outside the atomic section where interrupts are disabled.
414 * These are generally operations that grab mutexes or might otherwise sleep
415 * and thus can't be run with interrupts disabled.
417 struct intel_crtc_atomic_commit {
420 unsigned start_vbl_count;
422 /* Sleepable operations to perform before commit */
425 bool pre_disable_primary;
427 unsigned disabled_planes;
429 /* Sleepable operations to perform after commit */
433 bool post_enable_primary;
434 unsigned update_sprite_watermarks;
438 struct drm_crtc base;
441 u8 lut_r[256], lut_g[256], lut_b[256];
443 * Whether the crtc and the connected output pipeline is active. Implies
444 * that crtc->enabled is set, i.e. the current mode configuration has
445 * some outputs connected to this crtc.
448 unsigned long enabled_power_domains;
449 bool primary_enabled; /* is the primary plane (partially) visible? */
451 struct intel_overlay *overlay;
452 struct intel_unpin_work *unpin_work;
454 atomic_t unpin_work_count;
456 /* Display surface base address adjustement for pageflips. Note that on
457 * gen4+ this only adjusts up to a tile, offsets within a tile are
458 * handled in the hw itself (with the TILEOFF register). */
459 unsigned long dspaddr_offset;
461 struct drm_i915_gem_object *cursor_bo;
462 uint32_t cursor_addr;
463 int16_t cursor_width, cursor_height;
464 uint32_t cursor_cntl;
465 uint32_t cursor_size;
466 uint32_t cursor_base;
468 struct intel_initial_plane_config plane_config;
469 struct intel_crtc_state *config;
470 struct intel_crtc_state *new_config;
473 /* reset counter value when the last flip was submitted */
474 unsigned int reset_counter;
476 /* Access to these should be protected by dev_priv->irq_lock. */
477 bool cpu_fifo_underrun_disabled;
478 bool pch_fifo_underrun_disabled;
480 /* per-pipe watermark state */
482 /* watermarks currently being used */
483 struct intel_pipe_wm active;
484 /* SKL wm values currently in use */
485 struct skl_pipe_wm skl_active;
489 struct intel_mmio_flip mmio_flip;
491 struct intel_crtc_atomic_commit atomic;
494 struct intel_plane_wm_parameters {
495 uint32_t horiz_pixels;
496 uint32_t vert_pixels;
497 uint8_t bytes_per_pixel;
503 struct drm_plane base;
506 struct drm_i915_gem_object *obj;
510 /* Since we need to change the watermarks before/after
511 * enabling/disabling the planes, we need to store the parameters here
512 * as the other pieces of the struct may not reflect the values we want
513 * for the watermark calculations. Currently only Haswell uses this.
515 struct intel_plane_wm_parameters wm;
518 * NOTE: Do not place new plane state fields here (e.g., when adding
519 * new plane properties). New runtime state should now be placed in
520 * the intel_plane_state structure and accessed via drm_plane->state.
523 void (*update_plane)(struct drm_plane *plane,
524 struct drm_crtc *crtc,
525 struct drm_framebuffer *fb,
526 struct drm_i915_gem_object *obj,
527 int crtc_x, int crtc_y,
528 unsigned int crtc_w, unsigned int crtc_h,
529 uint32_t x, uint32_t y,
530 uint32_t src_w, uint32_t src_h);
531 void (*disable_plane)(struct drm_plane *plane,
532 struct drm_crtc *crtc);
533 int (*check_plane)(struct drm_plane *plane,
534 struct intel_plane_state *state);
535 void (*commit_plane)(struct drm_plane *plane,
536 struct intel_plane_state *state);
537 int (*update_colorkey)(struct drm_plane *plane,
538 struct drm_intel_sprite_colorkey *key);
539 void (*get_colorkey)(struct drm_plane *plane,
540 struct drm_intel_sprite_colorkey *key);
543 struct intel_watermark_params {
544 unsigned long fifo_size;
545 unsigned long max_wm;
546 unsigned long default_wm;
547 unsigned long guard_size;
548 unsigned long cacheline_size;
551 struct cxsr_latency {
554 unsigned long fsb_freq;
555 unsigned long mem_freq;
556 unsigned long display_sr;
557 unsigned long display_hpll_disable;
558 unsigned long cursor_sr;
559 unsigned long cursor_hpll_disable;
562 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
563 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
564 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
565 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
566 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
567 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
568 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
573 uint32_t color_range;
574 bool color_range_auto;
577 enum hdmi_force_audio force_audio;
578 bool rgb_quant_range_selectable;
579 enum hdmi_picture_aspect aspect_ratio;
580 void (*write_infoframe)(struct drm_encoder *encoder,
581 enum hdmi_infoframe_type type,
582 const void *frame, ssize_t len);
583 void (*set_infoframes)(struct drm_encoder *encoder,
585 struct drm_display_mode *adjusted_mode);
586 bool (*infoframe_enabled)(struct drm_encoder *encoder);
589 struct intel_dp_mst_encoder;
590 #define DP_MAX_DOWNSTREAM_PORTS 0x10
594 uint32_t aux_ch_ctl_reg;
597 enum hdmi_force_audio force_audio;
598 uint32_t color_range;
599 bool color_range_auto;
602 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
603 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
604 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
605 struct drm_dp_aux aux;
606 uint8_t train_set[4];
607 int panel_power_up_delay;
608 int panel_power_down_delay;
609 int panel_power_cycle_delay;
610 int backlight_on_delay;
611 int backlight_off_delay;
612 struct delayed_work panel_vdd_work;
614 unsigned long last_power_cycle;
615 unsigned long last_power_on;
616 unsigned long last_backlight_off;
618 struct notifier_block edp_notifier;
621 * Pipe whose power sequencer is currently locked into
622 * this port. Only relevant on VLV/CHV.
625 struct edp_power_seq pps_delays;
628 bool can_mst; /* this port supports mst */
630 int active_mst_links;
631 /* connector directly attached - won't be use for modeset in mst world */
632 struct intel_connector *attached_connector;
634 /* mst connector list */
635 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
636 struct drm_dp_mst_topology_mgr mst_mgr;
638 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
640 * This function returns the value we have to program the AUX_CTL
641 * register with to kick off an AUX transaction.
643 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
646 uint32_t aux_clock_divider);
649 struct intel_digital_port {
650 struct intel_encoder base;
654 struct intel_hdmi hdmi;
655 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
658 struct intel_dp_mst_encoder {
659 struct intel_encoder base;
661 struct intel_digital_port *primary;
662 void *port; /* store this opaque as its illegal to dereference it */
666 vlv_dport_to_channel(struct intel_digital_port *dport)
668 switch (dport->port) {
680 vlv_pipe_to_channel(enum pipe pipe)
693 static inline struct drm_crtc *
694 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 return dev_priv->pipe_to_crtc_mapping[pipe];
700 static inline struct drm_crtc *
701 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
703 struct drm_i915_private *dev_priv = dev->dev_private;
704 return dev_priv->plane_to_crtc_mapping[plane];
707 struct intel_unpin_work {
708 struct work_struct work;
709 struct drm_crtc *crtc;
710 struct drm_i915_gem_object *old_fb_obj;
711 struct drm_i915_gem_object *pending_flip_obj;
712 struct drm_pending_vblank_event *event;
714 #define INTEL_FLIP_INACTIVE 0
715 #define INTEL_FLIP_PENDING 1
716 #define INTEL_FLIP_COMPLETE 2
719 struct drm_i915_gem_request *flip_queued_req;
720 int flip_queued_vblank;
721 int flip_ready_vblank;
722 bool enable_stall_check;
725 struct intel_set_config {
726 struct drm_encoder **save_connector_encoders;
727 struct drm_crtc **save_encoder_crtcs;
728 bool *save_crtc_enabled;
734 struct intel_load_detect_pipe {
735 struct drm_framebuffer *release_fb;
736 bool load_detect_temp;
740 static inline struct intel_encoder *
741 intel_attached_encoder(struct drm_connector *connector)
743 return to_intel_connector(connector)->encoder;
746 static inline struct intel_digital_port *
747 enc_to_dig_port(struct drm_encoder *encoder)
749 return container_of(encoder, struct intel_digital_port, base.base);
752 static inline struct intel_dp_mst_encoder *
753 enc_to_mst(struct drm_encoder *encoder)
755 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
758 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
760 return &enc_to_dig_port(encoder)->dp;
763 static inline struct intel_digital_port *
764 dp_to_dig_port(struct intel_dp *intel_dp)
766 return container_of(intel_dp, struct intel_digital_port, dp);
769 static inline struct intel_digital_port *
770 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
772 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
776 * Returns the number of planes for this pipe, ie the number of sprites + 1
777 * (primary plane). This doesn't count the cursor plane then.
779 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
781 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
784 /* intel_fifo_underrun.c */
785 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
786 enum pipe pipe, bool enable);
787 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
788 enum transcoder pch_transcoder,
790 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
792 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
793 enum transcoder pch_transcoder);
794 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
797 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
798 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
799 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
800 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
801 void gen6_reset_rps_interrupts(struct drm_device *dev);
802 void gen6_enable_rps_interrupts(struct drm_device *dev);
803 void gen6_disable_rps_interrupts(struct drm_device *dev);
804 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
805 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
806 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
807 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
810 * We only use drm_irq_uninstall() at unload and VT switch, so
811 * this is the only thing we need to check.
813 return dev_priv->pm.irqs_enabled;
816 int intel_get_crtc_scanline(struct intel_crtc *crtc);
817 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
820 void intel_crt_init(struct drm_device *dev);
824 void intel_prepare_ddi(struct drm_device *dev);
825 void hsw_fdi_link_train(struct drm_crtc *crtc);
826 void intel_ddi_init(struct drm_device *dev, enum port port);
827 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
828 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
829 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
830 void intel_ddi_pll_init(struct drm_device *dev);
831 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
832 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
833 enum transcoder cpu_transcoder);
834 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
835 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
836 bool intel_ddi_pll_select(struct intel_crtc *crtc,
837 struct intel_crtc_state *crtc_state);
838 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
839 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
840 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
841 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
842 void intel_ddi_get_config(struct intel_encoder *encoder,
843 struct intel_crtc_state *pipe_config);
845 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
846 void intel_ddi_clock_get(struct intel_encoder *encoder,
847 struct intel_crtc_state *pipe_config);
848 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
850 /* intel_frontbuffer.c */
851 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
852 struct intel_engine_cs *ring);
853 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
854 unsigned frontbuffer_bits);
855 void intel_frontbuffer_flip_complete(struct drm_device *dev,
856 unsigned frontbuffer_bits);
857 void intel_frontbuffer_flush(struct drm_device *dev,
858 unsigned frontbuffer_bits);
860 * intel_frontbuffer_flip - synchronous frontbuffer flip
862 * @frontbuffer_bits: frontbuffer plane tracking bits
864 * This function gets called after scheduling a flip on @obj. This is for
865 * synchronous plane updates which will happen on the next vblank and which will
866 * not get delayed by pending gpu rendering.
868 * Can be called without any locks held.
871 void intel_frontbuffer_flip(struct drm_device *dev,
872 unsigned frontbuffer_bits)
874 intel_frontbuffer_flush(dev, frontbuffer_bits);
877 int intel_fb_align_height(struct drm_device *dev, int height,
878 unsigned int tiling);
879 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
883 void intel_init_audio(struct drm_device *dev);
884 void intel_audio_codec_enable(struct intel_encoder *encoder);
885 void intel_audio_codec_disable(struct intel_encoder *encoder);
886 void i915_audio_component_init(struct drm_i915_private *dev_priv);
887 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
889 /* intel_display.c */
890 extern const struct drm_plane_funcs intel_plane_funcs;
891 bool intel_has_pending_fb_unpin(struct drm_device *dev);
892 int intel_pch_rawclk(struct drm_device *dev);
893 void intel_mark_busy(struct drm_device *dev);
894 void intel_mark_idle(struct drm_device *dev);
895 void intel_crtc_restore_mode(struct drm_crtc *crtc);
896 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
897 void intel_crtc_update_dpms(struct drm_crtc *crtc);
898 void intel_encoder_destroy(struct drm_encoder *encoder);
899 void intel_connector_dpms(struct drm_connector *, int mode);
900 bool intel_connector_get_hw_state(struct intel_connector *connector);
901 void intel_modeset_check_state(struct drm_device *dev);
902 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
903 struct intel_digital_port *port);
904 void intel_connector_attach_encoder(struct intel_connector *connector,
905 struct intel_encoder *encoder);
906 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
907 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
908 struct drm_crtc *crtc);
909 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
910 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
911 struct drm_file *file_priv);
912 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
914 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
916 intel_wait_for_vblank(struct drm_device *dev, int pipe)
918 drm_wait_one_vblank(dev, pipe);
920 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
921 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
922 struct intel_digital_port *dport);
923 bool intel_get_load_detect_pipe(struct drm_connector *connector,
924 struct drm_display_mode *mode,
925 struct intel_load_detect_pipe *old,
926 struct drm_modeset_acquire_ctx *ctx);
927 void intel_release_load_detect_pipe(struct drm_connector *connector,
928 struct intel_load_detect_pipe *old);
929 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
930 struct drm_framebuffer *fb,
931 struct intel_engine_cs *pipelined);
932 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
933 struct drm_framebuffer *
934 __intel_framebuffer_create(struct drm_device *dev,
935 struct drm_mode_fb_cmd2 *mode_cmd,
936 struct drm_i915_gem_object *obj);
937 void intel_prepare_page_flip(struct drm_device *dev, int plane);
938 void intel_finish_page_flip(struct drm_device *dev, int pipe);
939 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
940 void intel_check_page_flip(struct drm_device *dev, int pipe);
941 int intel_prepare_plane_fb(struct drm_plane *plane,
942 struct drm_framebuffer *fb);
943 void intel_cleanup_plane_fb(struct drm_plane *plane,
944 struct drm_framebuffer *fb);
945 int intel_plane_atomic_get_property(struct drm_plane *plane,
946 const struct drm_plane_state *state,
947 struct drm_property *property,
949 int intel_plane_atomic_set_property(struct drm_plane *plane,
950 struct drm_plane_state *state,
951 struct drm_property *property,
954 /* shared dpll functions */
955 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
956 void assert_shared_dpll(struct drm_i915_private *dev_priv,
957 struct intel_shared_dpll *pll,
959 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
960 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
961 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
962 struct intel_crtc_state *state);
963 void intel_put_shared_dpll(struct intel_crtc *crtc);
965 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
966 const struct dpll *dpll);
967 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
969 /* modesetting asserts */
970 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
972 void assert_pll(struct drm_i915_private *dev_priv,
973 enum pipe pipe, bool state);
974 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
975 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
976 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
977 enum pipe pipe, bool state);
978 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
979 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
980 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
981 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
982 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
983 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
984 unsigned int tiling_mode,
987 void intel_prepare_reset(struct drm_device *dev);
988 void intel_finish_reset(struct drm_device *dev);
989 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
990 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
991 void intel_dp_get_m_n(struct intel_crtc *crtc,
992 struct intel_crtc_state *pipe_config);
993 void intel_dp_set_m_n(struct intel_crtc *crtc);
994 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
996 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
998 bool intel_crtc_active(struct drm_crtc *crtc);
999 void hsw_enable_ips(struct intel_crtc *crtc);
1000 void hsw_disable_ips(struct intel_crtc *crtc);
1001 enum intel_display_power_domain
1002 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1003 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1004 struct intel_crtc_state *pipe_config);
1005 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1006 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1009 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1010 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1011 struct intel_connector *intel_connector);
1012 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1013 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1014 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1015 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1016 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1017 void intel_dp_check_link_status(struct intel_dp *intel_dp);
1018 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1019 bool intel_dp_compute_config(struct intel_encoder *encoder,
1020 struct intel_crtc_state *pipe_config);
1021 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1022 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1024 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1025 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1026 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1027 void intel_edp_panel_on(struct intel_dp *intel_dp);
1028 void intel_edp_panel_off(struct intel_dp *intel_dp);
1029 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1030 void intel_dp_mst_suspend(struct drm_device *dev);
1031 void intel_dp_mst_resume(struct drm_device *dev);
1032 int intel_dp_max_link_bw(struct intel_dp *intel_dp);
1033 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1034 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1035 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1036 void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
1037 int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1038 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
1039 unsigned int crtc_w, unsigned int crtc_h,
1040 uint32_t src_x, uint32_t src_y,
1041 uint32_t src_w, uint32_t src_h);
1042 int intel_disable_plane(struct drm_plane *plane);
1043 void intel_plane_destroy(struct drm_plane *plane);
1044 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1045 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1046 void intel_edp_drrs_invalidate(struct drm_device *dev,
1047 unsigned frontbuffer_bits);
1048 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1050 /* intel_dp_mst.c */
1051 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1052 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1054 void intel_dsi_init(struct drm_device *dev);
1058 void intel_dvo_init(struct drm_device *dev);
1061 /* legacy fbdev emulation in intel_fbdev.c */
1062 #ifdef CONFIG_DRM_I915_FBDEV
1063 extern int intel_fbdev_init(struct drm_device *dev);
1064 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1065 extern void intel_fbdev_fini(struct drm_device *dev);
1066 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1067 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1068 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1070 static inline int intel_fbdev_init(struct drm_device *dev)
1075 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1079 static inline void intel_fbdev_fini(struct drm_device *dev)
1083 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1087 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1093 bool intel_fbc_enabled(struct drm_device *dev);
1094 void intel_fbc_update(struct drm_device *dev);
1095 void intel_fbc_init(struct drm_i915_private *dev_priv);
1096 void intel_fbc_disable(struct drm_device *dev);
1097 void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
1100 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1101 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1102 struct intel_connector *intel_connector);
1103 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1104 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1105 struct intel_crtc_state *pipe_config);
1109 void intel_lvds_init(struct drm_device *dev);
1110 bool intel_is_dual_link_lvds(struct drm_device *dev);
1114 int intel_connector_update_modes(struct drm_connector *connector,
1116 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1117 void intel_attach_force_audio_property(struct drm_connector *connector);
1118 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1121 /* intel_overlay.c */
1122 void intel_setup_overlay(struct drm_device *dev);
1123 void intel_cleanup_overlay(struct drm_device *dev);
1124 int intel_overlay_switch_off(struct intel_overlay *overlay);
1125 int intel_overlay_put_image(struct drm_device *dev, void *data,
1126 struct drm_file *file_priv);
1127 int intel_overlay_attrs(struct drm_device *dev, void *data,
1128 struct drm_file *file_priv);
1129 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1133 int intel_panel_init(struct intel_panel *panel,
1134 struct drm_display_mode *fixed_mode,
1135 struct drm_display_mode *downclock_mode);
1136 void intel_panel_fini(struct intel_panel *panel);
1137 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1138 struct drm_display_mode *adjusted_mode);
1139 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1140 struct intel_crtc_state *pipe_config,
1142 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1143 struct intel_crtc_state *pipe_config,
1145 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1146 u32 level, u32 max);
1147 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1148 void intel_panel_enable_backlight(struct intel_connector *connector);
1149 void intel_panel_disable_backlight(struct intel_connector *connector);
1150 void intel_panel_destroy_backlight(struct drm_connector *connector);
1151 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1152 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1153 extern struct drm_display_mode *intel_find_panel_downclock(
1154 struct drm_device *dev,
1155 struct drm_display_mode *fixed_mode,
1156 struct drm_connector *connector);
1157 void intel_backlight_register(struct drm_device *dev);
1158 void intel_backlight_unregister(struct drm_device *dev);
1162 void intel_psr_enable(struct intel_dp *intel_dp);
1163 void intel_psr_disable(struct intel_dp *intel_dp);
1164 void intel_psr_invalidate(struct drm_device *dev,
1165 unsigned frontbuffer_bits);
1166 void intel_psr_flush(struct drm_device *dev,
1167 unsigned frontbuffer_bits);
1168 void intel_psr_init(struct drm_device *dev);
1170 /* intel_runtime_pm.c */
1171 int intel_power_domains_init(struct drm_i915_private *);
1172 void intel_power_domains_fini(struct drm_i915_private *);
1173 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1174 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1176 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1177 enum intel_display_power_domain domain);
1178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1179 enum intel_display_power_domain domain);
1180 void intel_display_power_get(struct drm_i915_private *dev_priv,
1181 enum intel_display_power_domain domain);
1182 void intel_display_power_put(struct drm_i915_private *dev_priv,
1183 enum intel_display_power_domain domain);
1184 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1185 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1186 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1187 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1188 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1190 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1193 void intel_init_clock_gating(struct drm_device *dev);
1194 void intel_suspend_hw(struct drm_device *dev);
1195 int ilk_wm_max_level(const struct drm_device *dev);
1196 void intel_update_watermarks(struct drm_crtc *crtc);
1197 void intel_update_sprite_watermarks(struct drm_plane *plane,
1198 struct drm_crtc *crtc,
1199 uint32_t sprite_width,
1200 uint32_t sprite_height,
1202 bool enabled, bool scaled);
1203 void intel_init_pm(struct drm_device *dev);
1204 void intel_pm_setup(struct drm_device *dev);
1205 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1206 void intel_gpu_ips_teardown(void);
1207 void intel_init_gt_powersave(struct drm_device *dev);
1208 void intel_cleanup_gt_powersave(struct drm_device *dev);
1209 void intel_enable_gt_powersave(struct drm_device *dev);
1210 void intel_disable_gt_powersave(struct drm_device *dev);
1211 void intel_suspend_gt_powersave(struct drm_device *dev);
1212 void intel_reset_gt_powersave(struct drm_device *dev);
1213 void ironlake_teardown_rc6(struct drm_device *dev);
1214 void gen6_update_ring_freq(struct drm_device *dev);
1215 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1216 void gen6_rps_boost(struct drm_i915_private *dev_priv);
1217 void ilk_wm_get_hw_state(struct drm_device *dev);
1218 void skl_wm_get_hw_state(struct drm_device *dev);
1219 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1220 struct skl_ddb_allocation *ddb /* out */);
1224 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1227 /* intel_sprite.c */
1228 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1229 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1231 int intel_plane_set_property(struct drm_plane *plane,
1232 struct drm_property *prop,
1234 int intel_plane_restore(struct drm_plane *plane);
1235 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1236 struct drm_file *file_priv);
1237 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1238 struct drm_file *file_priv);
1239 bool intel_pipe_update_start(struct intel_crtc *crtc,
1240 uint32_t *start_vbl_count);
1241 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1242 void intel_post_enable_primary(struct drm_crtc *crtc);
1243 void intel_pre_disable_primary(struct drm_crtc *crtc);
1246 void intel_tv_init(struct drm_device *dev);
1248 /* intel_atomic.c */
1249 int intel_atomic_check(struct drm_device *dev,
1250 struct drm_atomic_state *state);
1251 int intel_atomic_commit(struct drm_device *dev,
1252 struct drm_atomic_state *state,
1254 int intel_connector_atomic_get_property(struct drm_connector *connector,
1255 const struct drm_connector_state *state,
1256 struct drm_property *property,
1258 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1259 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1260 struct drm_crtc_state *state);
1262 /* intel_atomic_plane.c */
1263 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1264 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1265 void intel_plane_destroy_state(struct drm_plane *plane,
1266 struct drm_plane_state *state);
1267 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1269 #endif /* __INTEL_DRV_H__ */