2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
40 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
41 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
44 * _wait_for - magic (register) wait macro
46 * Does the right thing for modeset paths when run under kdgb or similar atomic
47 * contexts. Note that it's important that we check the condition again after
48 * having timed out, since the timeout could be due to preemption or similar and
49 * we've never had a chance to check the condition before the timeout.
51 #define _wait_for(COND, MS, W) ({ \
52 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
55 if (time_after(jiffies, timeout__)) { \
60 if ((W) && drm_can_sleep()) { \
61 usleep_range((W)*1000, (W)*2000); \
69 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
70 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
71 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
72 DIV_ROUND_UP((US), 1000), 0)
74 #define KHz(x) (1000 * (x))
75 #define MHz(x) KHz(1000 * (x))
78 * Display related stuff
81 /* store information about an Ixxx DVO */
82 /* The i830->i865 use multiple DVOs with multiple i2cs */
83 /* the i915, i945 have a single sDVO i2c bus - which is different */
85 /* maximum connectors per crtcs in the mode set */
87 /* Maximum cursor sizes */
88 #define GEN2_CURSOR_WIDTH 64
89 #define GEN2_CURSOR_HEIGHT 64
90 #define MAX_CURSOR_WIDTH 256
91 #define MAX_CURSOR_HEIGHT 256
93 #define INTEL_I2C_BUS_DVO 1
94 #define INTEL_I2C_BUS_SDVO 2
96 /* these are outputs from the chip - integrated only
97 external chips are via DVO or SDVO output */
98 enum intel_output_type {
99 INTEL_OUTPUT_UNUSED = 0,
100 INTEL_OUTPUT_ANALOG = 1,
101 INTEL_OUTPUT_DVO = 2,
102 INTEL_OUTPUT_SDVO = 3,
103 INTEL_OUTPUT_LVDS = 4,
104 INTEL_OUTPUT_TVOUT = 5,
105 INTEL_OUTPUT_HDMI = 6,
106 INTEL_OUTPUT_DISPLAYPORT = 7,
107 INTEL_OUTPUT_EDP = 8,
108 INTEL_OUTPUT_DSI = 9,
109 INTEL_OUTPUT_UNKNOWN = 10,
110 INTEL_OUTPUT_DP_MST = 11,
113 #define INTEL_DVO_CHIP_NONE 0
114 #define INTEL_DVO_CHIP_LVDS 1
115 #define INTEL_DVO_CHIP_TMDS 2
116 #define INTEL_DVO_CHIP_TVOUT 4
118 #define INTEL_DSI_VIDEO_MODE 0
119 #define INTEL_DSI_COMMAND_MODE 1
121 struct intel_framebuffer {
122 struct drm_framebuffer base;
123 struct drm_i915_gem_object *obj;
127 struct drm_fb_helper helper;
128 struct intel_framebuffer *fb;
129 struct list_head fbdev_list;
130 struct drm_display_mode *our_mode;
134 struct intel_encoder {
135 struct drm_encoder base;
137 * The new crtc this encoder will be driven from. Only differs from
138 * base->crtc while a modeset is in progress.
140 struct intel_crtc *new_crtc;
142 enum intel_output_type type;
143 unsigned int cloneable;
144 bool connectors_active;
145 void (*hot_plug)(struct intel_encoder *);
146 bool (*compute_config)(struct intel_encoder *,
147 struct intel_crtc_state *);
148 void (*pre_pll_enable)(struct intel_encoder *);
149 void (*pre_enable)(struct intel_encoder *);
150 void (*enable)(struct intel_encoder *);
151 void (*mode_set)(struct intel_encoder *intel_encoder);
152 void (*disable)(struct intel_encoder *);
153 void (*post_disable)(struct intel_encoder *);
154 /* Read out the current hw state of this connector, returning true if
155 * the encoder is active. If the encoder is enabled it also set the pipe
156 * it is connected to in the pipe parameter. */
157 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
158 /* Reconstructs the equivalent mode flags for the current hardware
159 * state. This must be called _after_ display->get_pipe_config has
160 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
161 * be set correctly before calling this function. */
162 void (*get_config)(struct intel_encoder *,
163 struct intel_crtc_state *pipe_config);
165 * Called during system suspend after all pending requests for the
166 * encoder are flushed (for example for DP AUX transactions) and
167 * device interrupts are disabled.
169 void (*suspend)(struct intel_encoder *);
171 enum hpd_pin hpd_pin;
175 struct drm_display_mode *fixed_mode;
176 struct drm_display_mode *downclock_mode;
186 bool combination_mode; /* gen 2/4 only */
188 struct backlight_device *device;
191 void (*backlight_power)(struct intel_connector *, bool enable);
194 struct intel_connector {
195 struct drm_connector base;
197 * The fixed encoder this connector is connected to.
199 struct intel_encoder *encoder;
202 * The new encoder this connector will be driven. Only differs from
203 * encoder while a modeset is in progress.
205 struct intel_encoder *new_encoder;
207 /* Reads out the current hw, returning true if the connector is enabled
208 * and active (i.e. dpms ON state). */
209 bool (*get_hw_state)(struct intel_connector *);
212 * Removes all interfaces through which the connector is accessible
213 * - like sysfs, debugfs entries -, so that no new operations can be
214 * started on the connector. Also makes sure all currently pending
215 * operations finish before returing.
217 void (*unregister)(struct intel_connector *);
219 /* Panel info for eDP and LVDS */
220 struct intel_panel panel;
222 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
224 struct edid *detect_edid;
226 /* since POLL and HPD connectors may use the same HPD line keep the native
227 state of connector->polled in case hotplug storm detection changes it */
230 void *port; /* store this opaque as its illegal to dereference it */
232 struct intel_dp *mst_port;
235 typedef struct dpll {
247 struct intel_plane_state {
248 struct drm_plane_state base;
251 struct drm_rect clip;
255 * used only for sprite planes to determine when to implicitly
256 * enable/disable the primary plane
262 * = -1 : not using a scaler
263 * >= 0 : using a scalers
265 * plane requiring a scaler:
266 * - During check_plane, its bit is set in
267 * crtc_state->scaler_state.scaler_users by calling helper function
268 * update_scaler_users.
269 * - scaler_id indicates the scaler it got assigned.
271 * plane doesn't require a scaler:
272 * - this can happen when scaling is no more required or plane simply
274 * - During check_plane, corresponding bit is reset in
275 * crtc_state->scaler_state.scaler_users by calling helper function
276 * update_scaler_users.
281 struct intel_initial_plane_config {
282 struct intel_framebuffer *fb;
288 #define SKL_MIN_SRC_W 8
289 #define SKL_MAX_SRC_W 4096
290 #define SKL_MIN_SRC_H 8
291 #define SKL_MAX_SRC_H 2304
292 #define SKL_MIN_DST_W 8
293 #define SKL_MAX_DST_W 4096
294 #define SKL_MIN_DST_H 8
295 #define SKL_MAX_DST_H 2304
297 struct intel_scaler {
303 struct intel_crtc_scaler_state {
304 #define SKL_NUM_SCALERS 2
305 struct intel_scaler scalers[SKL_NUM_SCALERS];
308 * scaler_users: keeps track of users requesting scalers on this crtc.
310 * If a bit is set, a user is using a scaler.
311 * Here user can be a plane or crtc as defined below:
312 * bits 0-30 - plane (bit position is index from drm_plane_index)
315 * Instead of creating a new index to cover planes and crtc, using
316 * existing drm_plane_index for planes which is well less than 31
317 * planes and bit 31 for crtc. This should be fine to cover all
320 * intel_atomic_setup_scalers will setup available scalers to users
321 * requesting scalers. It will gracefully fail if request exceeds
324 #define SKL_CRTC_INDEX 31
325 unsigned scaler_users;
327 /* scaler used by crtc for panel fitting purpose */
331 struct intel_crtc_state {
332 struct drm_crtc_state base;
335 * quirks - bitfield with hw state readout quirks
337 * For various reasons the hw state readout code might not be able to
338 * completely faithfully read out the current state. These cases are
339 * tracked with quirk flags so that fastboot and state checker can act
342 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
343 #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
344 unsigned long quirks;
346 /* Pipe source size (ie. panel fitter input size)
347 * All planes will be positioned inside this space,
348 * and get clipped at the edges. */
349 int pipe_src_w, pipe_src_h;
351 /* Whether to set up the PCH/FDI. Note that we never allow sharing
352 * between pch encoders and cpu encoders. */
353 bool has_pch_encoder;
355 /* Are we sending infoframes on the attached port */
358 /* CPU Transcoder for the pipe. Currently this can only differ from the
359 * pipe on Haswell (where we have a special eDP transcoder). */
360 enum transcoder cpu_transcoder;
363 * Use reduced/limited/broadcast rbg range, compressing from the full
364 * range fed into the crtcs.
366 bool limited_color_range;
368 /* DP has a bunch of special case unfortunately, so mark the pipe
372 /* Whether we should send NULL infoframes. Required for audio. */
375 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
376 * has_dp_encoder is set. */
380 * Enable dithering, used when the selected pipe bpp doesn't match the
385 /* Controls for the clock computation, to override various stages. */
388 /* SDVO TV has a bunch of special case. To make multifunction encoders
389 * work correctly, we need to track this at runtime.*/
393 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
394 * required. This is set in the 2nd loop of calling encoder's
395 * ->compute_config if the first pick doesn't work out.
399 /* Settings for the intel dpll used on pretty much everything but
403 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
404 enum intel_dpll_id shared_dpll;
407 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
408 * - enum skl_dpll on SKL
410 uint32_t ddi_pll_sel;
412 /* Actual register state of the dpll, for shared dpll cross-checking. */
413 struct intel_dpll_hw_state dpll_hw_state;
416 struct intel_link_m_n dp_m_n;
418 /* m2_n2 for eDP downclock */
419 struct intel_link_m_n dp_m2_n2;
423 * Frequence the dpll for the port should run at. Differs from the
424 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
425 * already multiplied by pixel_multiplier.
429 /* Used by SDVO (and if we ever fix it, HDMI). */
430 unsigned pixel_multiplier;
432 /* Panel fitter controls for gen2-gen4 + VLV */
436 u32 lvds_border_bits;
439 /* Panel fitter placement and size for Ironlake+ */
447 /* FDI configuration, only valid if has_pch_encoder is set. */
449 struct intel_link_m_n fdi_m_n;
455 bool dp_encoder_is_mst;
458 struct intel_crtc_scaler_state scaler_state;
461 struct intel_pipe_wm {
462 struct intel_wm_level wm[5];
466 bool sprites_enabled;
470 struct intel_mmio_flip {
471 struct drm_i915_gem_request *req;
472 struct work_struct work;
476 struct skl_wm_level wm[8];
477 struct skl_wm_level trans_wm;
482 * Tracking of operations that need to be performed at the beginning/end of an
483 * atomic commit, outside the atomic section where interrupts are disabled.
484 * These are generally operations that grab mutexes or might otherwise sleep
485 * and thus can't be run with interrupts disabled.
487 struct intel_crtc_atomic_commit {
490 unsigned start_vbl_count;
492 /* Sleepable operations to perform before commit */
495 bool pre_disable_primary;
497 unsigned disabled_planes;
499 /* Sleepable operations to perform after commit */
503 bool post_enable_primary;
504 unsigned update_sprite_watermarks;
508 struct drm_crtc base;
511 u8 lut_r[256], lut_g[256], lut_b[256];
513 * Whether the crtc and the connected output pipeline is active. Implies
514 * that crtc->enabled is set, i.e. the current mode configuration has
515 * some outputs connected to this crtc.
518 unsigned long enabled_power_domains;
519 bool primary_enabled; /* is the primary plane (partially) visible? */
521 struct intel_overlay *overlay;
522 struct intel_unpin_work *unpin_work;
524 atomic_t unpin_work_count;
526 /* Display surface base address adjustement for pageflips. Note that on
527 * gen4+ this only adjusts up to a tile, offsets within a tile are
528 * handled in the hw itself (with the TILEOFF register). */
529 unsigned long dspaddr_offset;
531 struct drm_i915_gem_object *cursor_bo;
532 uint32_t cursor_addr;
533 uint32_t cursor_cntl;
534 uint32_t cursor_size;
535 uint32_t cursor_base;
537 struct intel_initial_plane_config plane_config;
538 struct intel_crtc_state *config;
541 /* reset counter value when the last flip was submitted */
542 unsigned int reset_counter;
544 /* Access to these should be protected by dev_priv->irq_lock. */
545 bool cpu_fifo_underrun_disabled;
546 bool pch_fifo_underrun_disabled;
548 /* per-pipe watermark state */
550 /* watermarks currently being used */
551 struct intel_pipe_wm active;
552 /* SKL wm values currently in use */
553 struct skl_pipe_wm skl_active;
557 struct intel_mmio_flip mmio_flip;
559 struct intel_crtc_atomic_commit atomic;
561 /* scalers available on this crtc */
565 struct intel_plane_wm_parameters {
566 uint32_t horiz_pixels;
567 uint32_t vert_pixels;
568 uint8_t bytes_per_pixel;
572 unsigned int rotation;
576 struct drm_plane base;
582 /* FIXME convert to properties */
583 struct drm_intel_sprite_colorkey ckey;
585 /* Since we need to change the watermarks before/after
586 * enabling/disabling the planes, we need to store the parameters here
587 * as the other pieces of the struct may not reflect the values we want
588 * for the watermark calculations. Currently only Haswell uses this.
590 struct intel_plane_wm_parameters wm;
593 * NOTE: Do not place new plane state fields here (e.g., when adding
594 * new plane properties). New runtime state should now be placed in
595 * the intel_plane_state structure and accessed via drm_plane->state.
598 void (*update_plane)(struct drm_plane *plane,
599 struct drm_crtc *crtc,
600 struct drm_framebuffer *fb,
601 int crtc_x, int crtc_y,
602 unsigned int crtc_w, unsigned int crtc_h,
603 uint32_t x, uint32_t y,
604 uint32_t src_w, uint32_t src_h);
605 void (*disable_plane)(struct drm_plane *plane,
606 struct drm_crtc *crtc);
607 int (*check_plane)(struct drm_plane *plane,
608 struct intel_plane_state *state);
609 void (*commit_plane)(struct drm_plane *plane,
610 struct intel_plane_state *state);
613 struct intel_watermark_params {
614 unsigned long fifo_size;
615 unsigned long max_wm;
616 unsigned long default_wm;
617 unsigned long guard_size;
618 unsigned long cacheline_size;
621 struct cxsr_latency {
624 unsigned long fsb_freq;
625 unsigned long mem_freq;
626 unsigned long display_sr;
627 unsigned long display_hpll_disable;
628 unsigned long cursor_sr;
629 unsigned long cursor_hpll_disable;
632 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
633 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
634 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
635 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
636 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
637 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
638 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
639 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
644 uint32_t color_range;
645 bool color_range_auto;
648 enum hdmi_force_audio force_audio;
649 bool rgb_quant_range_selectable;
650 enum hdmi_picture_aspect aspect_ratio;
651 void (*write_infoframe)(struct drm_encoder *encoder,
652 enum hdmi_infoframe_type type,
653 const void *frame, ssize_t len);
654 void (*set_infoframes)(struct drm_encoder *encoder,
656 struct drm_display_mode *adjusted_mode);
657 bool (*infoframe_enabled)(struct drm_encoder *encoder);
660 struct intel_dp_mst_encoder;
661 #define DP_MAX_DOWNSTREAM_PORTS 0x10
665 * When platform provides two set of M_N registers for dp, we can
666 * program them and switch between them incase of DRRS.
667 * But When only one such register is provided, we have to program the
668 * required divider value on that registers itself based on the DRRS state.
670 * M1_N1 : Program dp_m_n on M1_N1 registers
671 * dp_m2_n2 on M2_N2 registers (If supported)
673 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
674 * M2_N2 registers are not supported
678 /* Sets the m1_n1 and m2_n2 */
685 uint32_t aux_ch_ctl_reg;
688 enum hdmi_force_audio force_audio;
689 uint32_t color_range;
690 bool color_range_auto;
694 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
695 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
696 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
697 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
698 uint8_t num_sink_rates;
699 int sink_rates[DP_MAX_SUPPORTED_RATES];
700 struct drm_dp_aux aux;
701 uint8_t train_set[4];
702 int panel_power_up_delay;
703 int panel_power_down_delay;
704 int panel_power_cycle_delay;
705 int backlight_on_delay;
706 int backlight_off_delay;
707 struct delayed_work panel_vdd_work;
709 unsigned long last_power_cycle;
710 unsigned long last_power_on;
711 unsigned long last_backlight_off;
713 struct notifier_block edp_notifier;
716 * Pipe whose power sequencer is currently locked into
717 * this port. Only relevant on VLV/CHV.
720 struct edp_power_seq pps_delays;
723 bool can_mst; /* this port supports mst */
725 int active_mst_links;
726 /* connector directly attached - won't be use for modeset in mst world */
727 struct intel_connector *attached_connector;
729 /* mst connector list */
730 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
731 struct drm_dp_mst_topology_mgr mst_mgr;
733 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
735 * This function returns the value we have to program the AUX_CTL
736 * register with to kick off an AUX transaction.
738 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
741 uint32_t aux_clock_divider);
744 struct intel_digital_port {
745 struct intel_encoder base;
749 struct intel_hdmi hdmi;
750 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
753 struct intel_dp_mst_encoder {
754 struct intel_encoder base;
756 struct intel_digital_port *primary;
757 void *port; /* store this opaque as its illegal to dereference it */
761 vlv_dport_to_channel(struct intel_digital_port *dport)
763 switch (dport->port) {
775 vlv_pipe_to_channel(enum pipe pipe)
788 static inline struct drm_crtc *
789 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 return dev_priv->pipe_to_crtc_mapping[pipe];
795 static inline struct drm_crtc *
796 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 return dev_priv->plane_to_crtc_mapping[plane];
802 struct intel_unpin_work {
803 struct work_struct work;
804 struct drm_crtc *crtc;
805 struct drm_framebuffer *old_fb;
806 struct drm_i915_gem_object *pending_flip_obj;
807 struct drm_pending_vblank_event *event;
809 #define INTEL_FLIP_INACTIVE 0
810 #define INTEL_FLIP_PENDING 1
811 #define INTEL_FLIP_COMPLETE 2
814 struct drm_i915_gem_request *flip_queued_req;
815 int flip_queued_vblank;
816 int flip_ready_vblank;
817 bool enable_stall_check;
820 struct intel_set_config {
821 struct drm_encoder **save_connector_encoders;
822 struct drm_crtc **save_encoder_crtcs;
823 bool *save_crtc_enabled;
829 struct intel_load_detect_pipe {
830 struct drm_framebuffer *release_fb;
831 bool load_detect_temp;
835 static inline struct intel_encoder *
836 intel_attached_encoder(struct drm_connector *connector)
838 return to_intel_connector(connector)->encoder;
841 static inline struct intel_digital_port *
842 enc_to_dig_port(struct drm_encoder *encoder)
844 return container_of(encoder, struct intel_digital_port, base.base);
847 static inline struct intel_dp_mst_encoder *
848 enc_to_mst(struct drm_encoder *encoder)
850 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
853 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
855 return &enc_to_dig_port(encoder)->dp;
858 static inline struct intel_digital_port *
859 dp_to_dig_port(struct intel_dp *intel_dp)
861 return container_of(intel_dp, struct intel_digital_port, dp);
864 static inline struct intel_digital_port *
865 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
867 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
871 * Returns the number of planes for this pipe, ie the number of sprites + 1
872 * (primary plane). This doesn't count the cursor plane then.
874 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
876 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
879 /* intel_fifo_underrun.c */
880 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
881 enum pipe pipe, bool enable);
882 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
883 enum transcoder pch_transcoder,
885 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
887 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
888 enum transcoder pch_transcoder);
889 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
892 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
893 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
894 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
895 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
896 void gen6_reset_rps_interrupts(struct drm_device *dev);
897 void gen6_enable_rps_interrupts(struct drm_device *dev);
898 void gen6_disable_rps_interrupts(struct drm_device *dev);
899 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
900 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
901 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
902 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
905 * We only use drm_irq_uninstall() at unload and VT switch, so
906 * this is the only thing we need to check.
908 return dev_priv->pm.irqs_enabled;
911 int intel_get_crtc_scanline(struct intel_crtc *crtc);
912 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
913 unsigned int pipe_mask);
916 void intel_crt_init(struct drm_device *dev);
920 void intel_prepare_ddi(struct drm_device *dev);
921 void hsw_fdi_link_train(struct drm_crtc *crtc);
922 void intel_ddi_init(struct drm_device *dev, enum port port);
923 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
924 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
925 void intel_ddi_pll_init(struct drm_device *dev);
926 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
927 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
928 enum transcoder cpu_transcoder);
929 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
930 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
931 bool intel_ddi_pll_select(struct intel_crtc *crtc,
932 struct intel_crtc_state *crtc_state);
933 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
934 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
935 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
936 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
937 void intel_ddi_get_config(struct intel_encoder *encoder,
938 struct intel_crtc_state *pipe_config);
939 struct intel_encoder *
940 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
942 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
943 void intel_ddi_clock_get(struct intel_encoder *encoder,
944 struct intel_crtc_state *pipe_config);
945 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
946 void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
947 enum port port, int type);
949 /* intel_frontbuffer.c */
950 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
951 struct intel_engine_cs *ring,
952 enum fb_op_origin origin);
953 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
954 unsigned frontbuffer_bits);
955 void intel_frontbuffer_flip_complete(struct drm_device *dev,
956 unsigned frontbuffer_bits);
957 void intel_frontbuffer_flush(struct drm_device *dev,
958 unsigned frontbuffer_bits);
960 * intel_frontbuffer_flip - synchronous frontbuffer flip
962 * @frontbuffer_bits: frontbuffer plane tracking bits
964 * This function gets called after scheduling a flip on @obj. This is for
965 * synchronous plane updates which will happen on the next vblank and which will
966 * not get delayed by pending gpu rendering.
968 * Can be called without any locks held.
971 void intel_frontbuffer_flip(struct drm_device *dev,
972 unsigned frontbuffer_bits)
974 intel_frontbuffer_flush(dev, frontbuffer_bits);
977 unsigned int intel_fb_align_height(struct drm_device *dev,
979 uint32_t pixel_format,
980 uint64_t fb_format_modifier);
981 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
983 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
984 uint32_t pixel_format);
987 void intel_init_audio(struct drm_device *dev);
988 void intel_audio_codec_enable(struct intel_encoder *encoder);
989 void intel_audio_codec_disable(struct intel_encoder *encoder);
990 void i915_audio_component_init(struct drm_i915_private *dev_priv);
991 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
993 /* intel_display.c */
994 extern const struct drm_plane_funcs intel_plane_funcs;
995 bool intel_has_pending_fb_unpin(struct drm_device *dev);
996 int intel_pch_rawclk(struct drm_device *dev);
997 void intel_mark_busy(struct drm_device *dev);
998 void intel_mark_idle(struct drm_device *dev);
999 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1000 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
1001 void intel_crtc_update_dpms(struct drm_crtc *crtc);
1002 void intel_encoder_destroy(struct drm_encoder *encoder);
1003 int intel_connector_init(struct intel_connector *);
1004 struct intel_connector *intel_connector_alloc(void);
1005 void intel_connector_dpms(struct drm_connector *, int mode);
1006 bool intel_connector_get_hw_state(struct intel_connector *connector);
1007 void intel_modeset_check_state(struct drm_device *dev);
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port);
1010 void intel_connector_attach_encoder(struct intel_connector *connector,
1011 struct intel_encoder *encoder);
1012 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1013 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1014 struct drm_crtc *crtc);
1015 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1016 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1017 struct drm_file *file_priv);
1018 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1020 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1022 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1024 drm_wait_one_vblank(dev, pipe);
1026 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1027 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1028 struct intel_digital_port *dport);
1029 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1030 struct drm_display_mode *mode,
1031 struct intel_load_detect_pipe *old,
1032 struct drm_modeset_acquire_ctx *ctx);
1033 void intel_release_load_detect_pipe(struct drm_connector *connector,
1034 struct intel_load_detect_pipe *old,
1035 struct drm_modeset_acquire_ctx *ctx);
1036 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1037 struct drm_framebuffer *fb,
1038 const struct drm_plane_state *plane_state,
1039 struct intel_engine_cs *pipelined);
1040 struct drm_framebuffer *
1041 __intel_framebuffer_create(struct drm_device *dev,
1042 struct drm_mode_fb_cmd2 *mode_cmd,
1043 struct drm_i915_gem_object *obj);
1044 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1045 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1046 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1047 void intel_check_page_flip(struct drm_device *dev, int pipe);
1048 int intel_prepare_plane_fb(struct drm_plane *plane,
1049 struct drm_framebuffer *fb,
1050 const struct drm_plane_state *new_state);
1051 void intel_cleanup_plane_fb(struct drm_plane *plane,
1052 struct drm_framebuffer *fb,
1053 const struct drm_plane_state *old_state);
1054 int intel_plane_atomic_get_property(struct drm_plane *plane,
1055 const struct drm_plane_state *state,
1056 struct drm_property *property,
1058 int intel_plane_atomic_set_property(struct drm_plane *plane,
1059 struct drm_plane_state *state,
1060 struct drm_property *property,
1064 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1065 uint64_t fb_format_modifier);
1068 intel_rotation_90_or_270(unsigned int rotation)
1070 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1074 intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel,
1075 uint64_t fb_modifier);
1076 void intel_create_rotation_property(struct drm_device *dev,
1077 struct intel_plane *plane);
1079 bool intel_wm_need_update(struct drm_plane *plane,
1080 struct drm_plane_state *state);
1082 /* shared dpll functions */
1083 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1084 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1085 struct intel_shared_dpll *pll,
1087 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1088 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1089 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1090 struct intel_crtc_state *state);
1091 void intel_put_shared_dpll(struct intel_crtc *crtc);
1093 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1094 const struct dpll *dpll);
1095 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1097 /* modesetting asserts */
1098 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1100 void assert_pll(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state);
1102 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1103 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1104 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1105 enum pipe pipe, bool state);
1106 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1107 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1108 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1109 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1110 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1111 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1112 unsigned int tiling_mode,
1114 unsigned int pitch);
1115 void intel_prepare_reset(struct drm_device *dev);
1116 void intel_finish_reset(struct drm_device *dev);
1117 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1118 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1119 void broxton_init_cdclk(struct drm_device *dev);
1120 void broxton_uninit_cdclk(struct drm_device *dev);
1121 void broxton_set_cdclk(struct drm_device *dev, int frequency);
1122 void broxton_ddi_phy_init(struct drm_device *dev);
1123 void broxton_ddi_phy_uninit(struct drm_device *dev);
1124 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1125 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1126 void intel_dp_get_m_n(struct intel_crtc *crtc,
1127 struct intel_crtc_state *pipe_config);
1128 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1129 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1131 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1133 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1134 intel_clock_t *best_clock);
1135 bool intel_crtc_active(struct drm_crtc *crtc);
1136 void hsw_enable_ips(struct intel_crtc *crtc);
1137 void hsw_disable_ips(struct intel_crtc *crtc);
1138 enum intel_display_power_domain
1139 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1140 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1141 struct intel_crtc_state *pipe_config);
1142 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1143 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1144 void skl_detach_scalers(struct intel_crtc *intel_crtc);
1145 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1146 struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1147 struct intel_plane_state *plane_state, int force_detach);
1149 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1150 struct drm_i915_gem_object *obj);
1153 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1154 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1155 struct intel_connector *intel_connector);
1156 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1157 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1158 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1159 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1160 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1161 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1162 bool intel_dp_compute_config(struct intel_encoder *encoder,
1163 struct intel_crtc_state *pipe_config);
1164 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1165 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1167 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1168 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1169 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1170 void intel_edp_panel_on(struct intel_dp *intel_dp);
1171 void intel_edp_panel_off(struct intel_dp *intel_dp);
1172 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1173 void intel_dp_mst_suspend(struct drm_device *dev);
1174 void intel_dp_mst_resume(struct drm_device *dev);
1175 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1176 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1177 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1178 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1179 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1180 void intel_plane_destroy(struct drm_plane *plane);
1181 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1182 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1183 void intel_edp_drrs_invalidate(struct drm_device *dev,
1184 unsigned frontbuffer_bits);
1185 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1187 /* intel_dp_mst.c */
1188 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1189 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1191 void intel_dsi_init(struct drm_device *dev);
1195 void intel_dvo_init(struct drm_device *dev);
1198 /* legacy fbdev emulation in intel_fbdev.c */
1199 #ifdef CONFIG_DRM_I915_FBDEV
1200 extern int intel_fbdev_init(struct drm_device *dev);
1201 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1202 extern void intel_fbdev_fini(struct drm_device *dev);
1203 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1204 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1205 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1207 static inline int intel_fbdev_init(struct drm_device *dev)
1212 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1216 static inline void intel_fbdev_fini(struct drm_device *dev)
1220 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1224 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1230 bool intel_fbc_enabled(struct drm_device *dev);
1231 void intel_fbc_update(struct drm_device *dev);
1232 void intel_fbc_init(struct drm_i915_private *dev_priv);
1233 void intel_fbc_disable(struct drm_device *dev);
1234 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1235 unsigned int frontbuffer_bits,
1236 enum fb_op_origin origin);
1237 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1238 unsigned int frontbuffer_bits);
1241 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1242 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1243 struct intel_connector *intel_connector);
1244 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1245 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1246 struct intel_crtc_state *pipe_config);
1250 void intel_lvds_init(struct drm_device *dev);
1251 bool intel_is_dual_link_lvds(struct drm_device *dev);
1255 int intel_connector_update_modes(struct drm_connector *connector,
1257 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1258 void intel_attach_force_audio_property(struct drm_connector *connector);
1259 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1262 /* intel_overlay.c */
1263 void intel_setup_overlay(struct drm_device *dev);
1264 void intel_cleanup_overlay(struct drm_device *dev);
1265 int intel_overlay_switch_off(struct intel_overlay *overlay);
1266 int intel_overlay_put_image(struct drm_device *dev, void *data,
1267 struct drm_file *file_priv);
1268 int intel_overlay_attrs(struct drm_device *dev, void *data,
1269 struct drm_file *file_priv);
1270 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1274 int intel_panel_init(struct intel_panel *panel,
1275 struct drm_display_mode *fixed_mode,
1276 struct drm_display_mode *downclock_mode);
1277 void intel_panel_fini(struct intel_panel *panel);
1278 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1279 struct drm_display_mode *adjusted_mode);
1280 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1281 struct intel_crtc_state *pipe_config,
1283 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1284 struct intel_crtc_state *pipe_config,
1286 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1287 u32 level, u32 max);
1288 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1289 void intel_panel_enable_backlight(struct intel_connector *connector);
1290 void intel_panel_disable_backlight(struct intel_connector *connector);
1291 void intel_panel_destroy_backlight(struct drm_connector *connector);
1292 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1293 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1294 extern struct drm_display_mode *intel_find_panel_downclock(
1295 struct drm_device *dev,
1296 struct drm_display_mode *fixed_mode,
1297 struct drm_connector *connector);
1298 void intel_backlight_register(struct drm_device *dev);
1299 void intel_backlight_unregister(struct drm_device *dev);
1303 void intel_psr_enable(struct intel_dp *intel_dp);
1304 void intel_psr_disable(struct intel_dp *intel_dp);
1305 void intel_psr_invalidate(struct drm_device *dev,
1306 unsigned frontbuffer_bits);
1307 void intel_psr_flush(struct drm_device *dev,
1308 unsigned frontbuffer_bits);
1309 void intel_psr_init(struct drm_device *dev);
1310 void intel_psr_single_frame_update(struct drm_device *dev);
1312 /* intel_runtime_pm.c */
1313 int intel_power_domains_init(struct drm_i915_private *);
1314 void intel_power_domains_fini(struct drm_i915_private *);
1315 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1316 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1318 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1319 enum intel_display_power_domain domain);
1320 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1321 enum intel_display_power_domain domain);
1322 void intel_display_power_get(struct drm_i915_private *dev_priv,
1323 enum intel_display_power_domain domain);
1324 void intel_display_power_put(struct drm_i915_private *dev_priv,
1325 enum intel_display_power_domain domain);
1326 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1327 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1328 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1329 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1330 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1332 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1335 void intel_init_clock_gating(struct drm_device *dev);
1336 void intel_suspend_hw(struct drm_device *dev);
1337 int ilk_wm_max_level(const struct drm_device *dev);
1338 void intel_update_watermarks(struct drm_crtc *crtc);
1339 void intel_update_sprite_watermarks(struct drm_plane *plane,
1340 struct drm_crtc *crtc,
1341 uint32_t sprite_width,
1342 uint32_t sprite_height,
1344 bool enabled, bool scaled);
1345 void intel_init_pm(struct drm_device *dev);
1346 void intel_pm_setup(struct drm_device *dev);
1347 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1348 void intel_gpu_ips_teardown(void);
1349 void intel_init_gt_powersave(struct drm_device *dev);
1350 void intel_cleanup_gt_powersave(struct drm_device *dev);
1351 void intel_enable_gt_powersave(struct drm_device *dev);
1352 void intel_disable_gt_powersave(struct drm_device *dev);
1353 void intel_suspend_gt_powersave(struct drm_device *dev);
1354 void intel_reset_gt_powersave(struct drm_device *dev);
1355 void gen6_update_ring_freq(struct drm_device *dev);
1356 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1357 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1358 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1359 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1360 struct drm_i915_file_private *file_priv);
1361 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1362 struct drm_i915_gem_request *rq);
1363 void ilk_wm_get_hw_state(struct drm_device *dev);
1364 void skl_wm_get_hw_state(struct drm_device *dev);
1365 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1366 struct skl_ddb_allocation *ddb /* out */);
1370 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1373 /* intel_sprite.c */
1374 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1375 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1377 int intel_plane_restore(struct drm_plane *plane);
1378 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1379 struct drm_file *file_priv);
1380 bool intel_pipe_update_start(struct intel_crtc *crtc,
1381 uint32_t *start_vbl_count);
1382 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1383 void intel_post_enable_primary(struct drm_crtc *crtc);
1384 void intel_pre_disable_primary(struct drm_crtc *crtc);
1387 void intel_tv_init(struct drm_device *dev);
1389 /* intel_atomic.c */
1390 int intel_atomic_check(struct drm_device *dev,
1391 struct drm_atomic_state *state);
1392 int intel_atomic_commit(struct drm_device *dev,
1393 struct drm_atomic_state *state,
1395 int intel_connector_atomic_get_property(struct drm_connector *connector,
1396 const struct drm_connector_state *state,
1397 struct drm_property *property,
1399 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1400 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1401 struct drm_crtc_state *state);
1402 static inline struct intel_crtc_state *
1403 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1404 struct intel_crtc *crtc)
1406 struct drm_crtc_state *crtc_state;
1407 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1408 if (IS_ERR(crtc_state))
1409 return ERR_PTR(PTR_ERR(crtc_state));
1411 return to_intel_crtc_state(crtc_state);
1413 int intel_atomic_setup_scalers(struct drm_device *dev,
1414 struct intel_crtc *intel_crtc,
1415 struct intel_crtc_state *crtc_state);
1417 /* intel_atomic_plane.c */
1418 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1419 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1420 void intel_plane_destroy_state(struct drm_plane *plane,
1421 struct drm_plane_state *state);
1422 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1424 #endif /* __INTEL_DRV_H__ */