drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <linux/slab.h>
  33 #include "i915_drv.h"
  34 #include "intel_drv.h"
  35 #include "intel_dsi.h"
  36 #include "intel_dsi_cmd.h"
  37
  38 static const struct {
  39         u16 panel_id;
  40         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  41 } intel_dsi_drivers[] = {
  42         {
  43                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  44                 .init = vbt_panel_init,
  45         },
  46 };
  47
  48 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  49 {
  50         struct drm_encoder *encoder = &intel_dsi->base.base;
  51         struct drm_device *dev = encoder->dev;
  52         struct drm_i915_private *dev_priv = dev->dev_private;
  53         u32 mask;
  54
  55         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  56                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  57
  58         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
  59                 DRM_ERROR("DPI FIFOs are not empty\n");
  60 }
  61
  62 static void band_gap_reset(struct drm_i915_private *dev_priv)
  63 {
  64         mutex_lock(&dev_priv->dpio_lock);
  65
  66         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
  67         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
  68         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
  69         udelay(150);
  70         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
  71         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
  72
  73         mutex_unlock(&dev_priv->dpio_lock);
  74 }
  75
  76 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  77 {
  78         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
  79 }
  80
  81 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  82 {
  83         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
  84 }
  85
  86 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  87 {
  88         DRM_DEBUG_KMS("\n");
  89 }
  90
  91 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  92                                      struct intel_crtc_state *config)
  93 {
  94         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  95                                                    base);
  96         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  97         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  98         struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
  99
 100         DRM_DEBUG_KMS("\n");
 101
 102         if (fixed_mode)
 103                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 104
 105         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 106         adjusted_mode->flags = 0;
 107
 108         return true;
 109 }
 110
 111 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 112 {
 113         struct drm_device *dev = encoder->base.dev;
 114         struct drm_i915_private *dev_priv = dev->dev_private;
 115         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 116         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 117         enum port port;
 118         u32 temp;
 119
 120         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 121                 temp = I915_READ(VLV_CHICKEN_3);
 122                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 123                                         intel_dsi->pixel_overlap <<
 124                                         PIXEL_OVERLAP_CNT_SHIFT;
 125                 I915_WRITE(VLV_CHICKEN_3, temp);
 126         }
 127
 128         for_each_dsi_port(port, intel_dsi->ports) {
 129                 temp = I915_READ(MIPI_PORT_CTRL(port));
 130                 temp &= ~LANE_CONFIGURATION_MASK;
 131                 temp &= ~DUAL_LINK_MODE_MASK;
 132
 133                 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 134                         temp |= (intel_dsi->dual_link - 1)
 135                                                 << DUAL_LINK_MODE_SHIFT;
 136                         temp |= intel_crtc->pipe ?
 137                                         LANE_CONFIGURATION_DUAL_LINK_B :
 138                                         LANE_CONFIGURATION_DUAL_LINK_A;
 139                 }
 140                 /* assert ip_tg_enable signal */
 141                 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
 142                 POSTING_READ(MIPI_PORT_CTRL(port));
 143         }
 144 }
 145
 146 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 147 {
 148         struct drm_device *dev = encoder->base.dev;
 149         struct drm_i915_private *dev_priv = dev->dev_private;
 150         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 151         enum port port;
 152         u32 temp;
 153
 154         for_each_dsi_port(port, intel_dsi->ports) {
 155                 /* de-assert ip_tg_enable signal */
 156                 temp = I915_READ(MIPI_PORT_CTRL(port));
 157                 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
 158                 POSTING_READ(MIPI_PORT_CTRL(port));
 159         }
 160 }
 161
 162 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 163 {
 164         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 165         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 166         enum port port;
 167         u32 val;
 168
 169         DRM_DEBUG_KMS("\n");
 170
 171         mutex_lock(&dev_priv->dpio_lock);
 172         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 173          * needed everytime after power gate */
 174         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 175         mutex_unlock(&dev_priv->dpio_lock);
 176
 177         /* bandgap reset is needed after everytime we do power gate */
 178         band_gap_reset(dev_priv);
 179
 180         for_each_dsi_port(port, intel_dsi->ports) {
 181
 182                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 183                 usleep_range(2500, 3000);
 184
 185                 val = I915_READ(MIPI_PORT_CTRL(port));
 186
 187                 /* Enable MIPI PHY transparent latch
 188                  * Common bit for both MIPI Port A & MIPI Port C
 189                  * No similar bit in MIPI Port C reg
 190                  */
 191                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 192                 usleep_range(1000, 1500);
 193
 194                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 195                 usleep_range(2500, 3000);
 196
 197                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 198                 usleep_range(2500, 3000);
 199         }
 200 }
 201
 202 static void intel_dsi_enable(struct intel_encoder *encoder)
 203 {
 204         struct drm_device *dev = encoder->base.dev;
 205         struct drm_i915_private *dev_priv = dev->dev_private;
 206         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 207         enum port port;
 208
 209         DRM_DEBUG_KMS("\n");
 210
 211         if (is_cmd_mode(intel_dsi)) {
 212                 for_each_dsi_port(port, intel_dsi->ports)
 213                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 214         } else {
 215                 msleep(20); /* XXX */
 216                 for_each_dsi_port(port, intel_dsi->ports)
 217                         dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port);
 218                 msleep(100);
 219
 220                 drm_panel_enable(intel_dsi->panel);
 221
 222                 for_each_dsi_port(port, intel_dsi->ports)
 223                         wait_for_dsi_fifo_empty(intel_dsi, port);
 224
 225                 intel_dsi_port_enable(encoder);
 226         }
 227 }
 228
 229 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 230 {
 231         struct drm_device *dev = encoder->base.dev;
 232         struct drm_i915_private *dev_priv = dev->dev_private;
 233         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 234         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 235         enum pipe pipe = intel_crtc->pipe;
 236         enum port port;
 237         u32 tmp;
 238
 239         DRM_DEBUG_KMS("\n");
 240
 241         /* Disable DPOunit clock gating, can stall pipe
 242          * and we need DPLL REFA always enabled */
 243         tmp = I915_READ(DPLL(pipe));
 244         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 245         I915_WRITE(DPLL(pipe), tmp);
 246
 247         /* update the hw state for DPLL */
 248         intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
 249                 DPLL_REFA_CLK_ENABLE_VLV;
 250
 251         tmp = I915_READ(DSPCLK_GATE_D);
 252         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 253         I915_WRITE(DSPCLK_GATE_D, tmp);
 254
 255         /* put device in ready state */
 256         intel_dsi_device_ready(encoder);
 257
 258         msleep(intel_dsi->panel_on_delay);
 259
 260         drm_panel_prepare(intel_dsi->panel);
 261
 262         for_each_dsi_port(port, intel_dsi->ports)
 263                 wait_for_dsi_fifo_empty(intel_dsi, port);
 264
 265         /* Enable port in pre-enable phase itself because as per hw team
 266          * recommendation, port should be enabled befor plane & pipe */
 267         intel_dsi_enable(encoder);
 268 }
 269
 270 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 271 {
 272         DRM_DEBUG_KMS("\n");
 273
 274         /* for DSI port enable has to be done before pipe
 275          * and plane enable, so port enable is done in
 276          * pre_enable phase itself unlike other encoders
 277          */
 278 }
 279
 280 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 281 {
 282         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 283         enum port port;
 284
 285         DRM_DEBUG_KMS("\n");
 286
 287         if (is_vid_mode(intel_dsi)) {
 288                 /* Send Shutdown command to the panel in LP mode */
 289                 for_each_dsi_port(port, intel_dsi->ports)
 290                         dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN, port);
 291                 msleep(10);
 292         }
 293 }
 294
 295 static void intel_dsi_disable(struct intel_encoder *encoder)
 296 {
 297         struct drm_device *dev = encoder->base.dev;
 298         struct drm_i915_private *dev_priv = dev->dev_private;
 299         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 300         enum port port;
 301         u32 temp;
 302
 303         DRM_DEBUG_KMS("\n");
 304
 305         if (is_vid_mode(intel_dsi)) {
 306                 for_each_dsi_port(port, intel_dsi->ports)
 307                         wait_for_dsi_fifo_empty(intel_dsi, port);
 308
 309                 intel_dsi_port_disable(encoder);
 310                 msleep(2);
 311         }
 312
 313         for_each_dsi_port(port, intel_dsi->ports) {
 314                 /* Panel commands can be sent when clock is in LP11 */
 315                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 316
 317                 temp = I915_READ(MIPI_CTRL(port));
 318                 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 319                 I915_WRITE(MIPI_CTRL(port), temp |
 320                            intel_dsi->escape_clk_div <<
 321                            ESCAPE_CLOCK_DIVIDER_SHIFT);
 322
 323                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 324
 325                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 326                 temp &= ~VID_MODE_FORMAT_MASK;
 327                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 328
 329                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 330         }
 331         /* if disable packets are sent before sending shutdown packet then in
 332          * some next enable sequence send turn on packet error is observed */
 333         drm_panel_disable(intel_dsi->panel);
 334
 335         for_each_dsi_port(port, intel_dsi->ports)
 336                 wait_for_dsi_fifo_empty(intel_dsi, port);
 337 }
 338
 339 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 340 {
 341         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 342         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 343         enum port port;
 344         u32 val;
 345
 346         DRM_DEBUG_KMS("\n");
 347         for_each_dsi_port(port, intel_dsi->ports) {
 348
 349                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 350                                                         ULPS_STATE_ENTER);
 351                 usleep_range(2000, 2500);
 352
 353                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 354                                                         ULPS_STATE_EXIT);
 355                 usleep_range(2000, 2500);
 356
 357                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 358                                                         ULPS_STATE_ENTER);
 359                 usleep_range(2000, 2500);
 360
 361                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 362                  * only. MIPI Port C has no similar bit for checking
 363                  */
 364                 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
 365                                                         == 0x00000), 30))
 366                         DRM_ERROR("DSI LP not going Low\n");
 367
 368                 val = I915_READ(MIPI_PORT_CTRL(port));
 369                 /* Disable MIPI PHY transparent latch
 370                  * Common bit for both MIPI Port A & MIPI Port C
 371                  */
 372                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
 373                 usleep_range(1000, 1500);
 374
 375                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 376                 usleep_range(2000, 2500);
 377         }
 378
 379         vlv_disable_dsi_pll(encoder);
 380 }
 381
 382 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 383 {
 384         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 385         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 386         u32 val;
 387
 388         DRM_DEBUG_KMS("\n");
 389
 390         intel_dsi_disable(encoder);
 391
 392         intel_dsi_clear_device_ready(encoder);
 393
 394         val = I915_READ(DSPCLK_GATE_D);
 395         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 396         I915_WRITE(DSPCLK_GATE_D, val);
 397
 398         drm_panel_unprepare(intel_dsi->panel);
 399
 400         msleep(intel_dsi->panel_off_delay);
 401         msleep(intel_dsi->panel_pwr_cycle_delay);
 402 }
 403
 404 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 405                                    enum pipe *pipe)
 406 {
 407         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 408         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 409         struct drm_device *dev = encoder->base.dev;
 410         enum intel_display_power_domain power_domain;
 411         u32 dpi_enabled, func;
 412         enum port port;
 413
 414         DRM_DEBUG_KMS("\n");
 415
 416         power_domain = intel_display_port_power_domain(encoder);
 417         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 418                 return false;
 419
 420         /* XXX: this only works for one DSI output */
 421         for_each_dsi_port(port, intel_dsi->ports) {
 422                 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 423                 dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
 424                                                         DPI_ENABLE;
 425
 426                 /* Due to some hardware limitations on BYT, MIPI Port C DPI
 427                  * Enable bit does not get set. To check whether DSI Port C
 428                  * was enabled in BIOS, check the Pipe B enable bit
 429                  */
 430                 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 431                     (port == PORT_C))
 432                         dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 433                                                         PIPECONF_ENABLE;
 434
 435                 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 436                         if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
 437                                 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 438                                 return true;
 439                         }
 440                 }
 441         }
 442
 443         return false;
 444 }
 445
 446 static void intel_dsi_get_config(struct intel_encoder *encoder,
 447                                  struct intel_crtc_state *pipe_config)
 448 {
 449         u32 pclk;
 450         DRM_DEBUG_KMS("\n");
 451
 452         /*
 453          * DPLL_MD is not used in case of DSI, reading will get some default value
 454          * set dpll_md = 0
 455          */
 456         pipe_config->dpll_hw_state.dpll_md = 0;
 457
 458         pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 459         if (!pclk)
 460                 return;
 461
 462         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 463         pipe_config->port_clock = pclk;
 464 }
 465
 466 static enum drm_mode_status
 467 intel_dsi_mode_valid(struct drm_connector *connector,
 468                      struct drm_display_mode *mode)
 469 {
 470         struct intel_connector *intel_connector = to_intel_connector(connector);
 471         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 472
 473         DRM_DEBUG_KMS("\n");
 474
 475         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 476                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 477                 return MODE_NO_DBLESCAN;
 478         }
 479
 480         if (fixed_mode) {
 481                 if (mode->hdisplay > fixed_mode->hdisplay)
 482                         return MODE_PANEL;
 483                 if (mode->vdisplay > fixed_mode->vdisplay)
 484                         return MODE_PANEL;
 485         }
 486
 487         return MODE_OK;
 488 }
 489
 490 /* return txclkesc cycles in terms of divider and duration in us */
 491 static u16 txclkesc(u32 divider, unsigned int us)
 492 {
 493         switch (divider) {
 494         case ESCAPE_CLOCK_DIVIDER_1:
 495         default:
 496                 return 20 * us;
 497         case ESCAPE_CLOCK_DIVIDER_2:
 498                 return 10 * us;
 499         case ESCAPE_CLOCK_DIVIDER_4:
 500                 return 5 * us;
 501         }
 502 }
 503
 504 /* return pixels in terms of txbyteclkhs */
 505 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 506                        u16 burst_mode_ratio)
 507 {
 508         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 509                                          8 * 100), lane_count);
 510 }
 511
 512 static void set_dsi_timings(struct drm_encoder *encoder,
 513                             const struct drm_display_mode *mode)
 514 {
 515         struct drm_device *dev = encoder->dev;
 516         struct drm_i915_private *dev_priv = dev->dev_private;
 517         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 518         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 519         enum port port;
 520         unsigned int bpp = intel_crtc->config->pipe_bpp;
 521         unsigned int lane_count = intel_dsi->lane_count;
 522
 523         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 524
 525         hactive = mode->hdisplay;
 526         hfp = mode->hsync_start - mode->hdisplay;
 527         hsync = mode->hsync_end - mode->hsync_start;
 528         hbp = mode->htotal - mode->hsync_end;
 529
 530         if (intel_dsi->dual_link) {
 531                 hactive /= 2;
 532                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 533                         hactive += intel_dsi->pixel_overlap;
 534                 hfp /= 2;
 535                 hsync /= 2;
 536                 hbp /= 2;
 537         }
 538
 539         vfp = mode->vsync_start - mode->vdisplay;
 540         vsync = mode->vsync_end - mode->vsync_start;
 541         vbp = mode->vtotal - mode->vsync_end;
 542
 543         /* horizontal values are in terms of high speed byte clock */
 544         hactive = txbyteclkhs(hactive, bpp, lane_count,
 545                               intel_dsi->burst_mode_ratio);
 546         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 547         hsync = txbyteclkhs(hsync, bpp, lane_count,
 548                             intel_dsi->burst_mode_ratio);
 549         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 550
 551         for_each_dsi_port(port, intel_dsi->ports) {
 552                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 553                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 554
 555                 /* meaningful for video mode non-burst sync pulse mode only,
 556                  * can be zero for non-burst sync events and burst modes */
 557                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
 558                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
 559
 560                 /* vertical values are in terms of lines */
 561                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
 562                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
 563                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
 564         }
 565 }
 566
 567 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 568 {
 569         struct drm_encoder *encoder = &intel_encoder->base;
 570         struct drm_device *dev = encoder->dev;
 571         struct drm_i915_private *dev_priv = dev->dev_private;
 572         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 573         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 574         struct drm_display_mode *adjusted_mode =
 575                 &intel_crtc->config->base.adjusted_mode;
 576         enum port port;
 577         unsigned int bpp = intel_crtc->config->pipe_bpp;
 578         u32 val, tmp;
 579         u16 mode_hdisplay;
 580
 581         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 582
 583         mode_hdisplay = adjusted_mode->hdisplay;
 584
 585         if (intel_dsi->dual_link) {
 586                 mode_hdisplay /= 2;
 587                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 588                         mode_hdisplay += intel_dsi->pixel_overlap;
 589         }
 590
 591         for_each_dsi_port(port, intel_dsi->ports) {
 592                 /* escape clock divider, 20MHz, shared for A and C.
 593                  * device ready must be off when doing this! txclkesc? */
 594                 tmp = I915_READ(MIPI_CTRL(PORT_A));
 595                 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 596                 I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
 597
 598                 /* read request priority is per pipe */
 599                 tmp = I915_READ(MIPI_CTRL(port));
 600                 tmp &= ~READ_REQUEST_PRIORITY_MASK;
 601                 I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
 602
 603                 /* XXX: why here, why like this? handling in irq handler?! */
 604                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
 605                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
 606
 607                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
 608
 609                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
 610                         adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 611                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 612         }
 613
 614         set_dsi_timings(encoder, adjusted_mode);
 615
 616         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 617         if (is_cmd_mode(intel_dsi)) {
 618                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 619                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 620         } else {
 621                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 622
 623                 /* XXX: cross-check bpp vs. pixel format? */
 624                 val |= intel_dsi->pixel_format;
 625         }
 626
 627         tmp = 0;
 628         if (intel_dsi->eotp_pkt == 0)
 629                 tmp |= EOT_DISABLE;
 630         if (intel_dsi->clock_stop)
 631                 tmp |= CLOCKSTOP;
 632
 633         for_each_dsi_port(port, intel_dsi->ports) {
 634                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 635
 636                 /* timeouts for recovery. one frame IIUC. if counter expires,
 637                  * EOT and stop state. */
 638
 639                 /*
 640                  * In burst mode, value greater than one DPI line Time in byte
 641                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
 642                  * said value is recommended.
 643                  *
 644                  * In non-burst mode, Value greater than one DPI frame time in
 645                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 646                  * said value is recommended.
 647                  *
 648                  * In DBI only mode, value greater than one DBI frame time in
 649                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 650                  * said value is recommended.
 651                  */
 652
 653                 if (is_vid_mode(intel_dsi) &&
 654                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 655                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 656                                 txbyteclkhs(adjusted_mode->htotal, bpp,
 657                                         intel_dsi->lane_count,
 658                                         intel_dsi->burst_mode_ratio) + 1);
 659                 } else {
 660                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 661                                 txbyteclkhs(adjusted_mode->vtotal *
 662                                         adjusted_mode->htotal,
 663                                         bpp, intel_dsi->lane_count,
 664                                         intel_dsi->burst_mode_ratio) + 1);
 665                 }
 666                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 667                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
 668                                                 intel_dsi->turn_arnd_val);
 669                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
 670                                                 intel_dsi->rst_timer_val);
 671
 672                 /* dphy stuff */
 673
 674                 /* in terms of low power clock */
 675                 I915_WRITE(MIPI_INIT_COUNT(port),
 676                                 txclkesc(intel_dsi->escape_clk_div, 100));
 677
 678
 679                 /* recovery disables */
 680                 I915_WRITE(MIPI_EOT_DISABLE(port), val);
 681
 682                 /* in terms of low power clock */
 683                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 684
 685                 /* in terms of txbyteclkhs. actual high to low switch +
 686                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 687                  *
 688                  * XXX: write MIPI_STOP_STATE_STALL?
 689                  */
 690                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
 691                                                 intel_dsi->hs_to_lp_count);
 692
 693                 /* XXX: low power clock equivalence in terms of byte clock.
 694                  * the number of byte clocks occupied in one low power clock.
 695                  * based on txbyteclkhs and txclkesc.
 696                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
 697                  * ) / 105.???
 698                  */
 699                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 700
 701                 /* the bw essential for transmitting 16 long packets containing
 702                  * 252 bytes meant for dcs write memory command is programmed in
 703                  * this register in terms of byte clocks. based on dsi transfer
 704                  * rate and the number of lanes configured the time taken to
 705                  * transmit 16 long packets in a dsi stream varies. */
 706                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
 707
 708                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
 709                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 710                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 711
 712                 if (is_vid_mode(intel_dsi))
 713                         /* Some panels might have resolution which is not a
 714                          * multiple of 64 like 1366 x 768. Enable RANDOM
 715                          * resolution support for such panels by default */
 716                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
 717                                 intel_dsi->video_frmt_cfg_bits |
 718                                 intel_dsi->video_mode_format |
 719                                 IP_TG_CONFIG |
 720                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 721         }
 722 }
 723
 724 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 725 {
 726         DRM_DEBUG_KMS("\n");
 727
 728         intel_dsi_prepare(encoder);
 729
 730         vlv_enable_dsi_pll(encoder);
 731 }
 732
 733 static enum drm_connector_status
 734 intel_dsi_detect(struct drm_connector *connector, bool force)
 735 {
 736         return connector_status_connected;
 737 }
 738
 739 static int intel_dsi_get_modes(struct drm_connector *connector)
 740 {
 741         struct intel_connector *intel_connector = to_intel_connector(connector);
 742         struct drm_display_mode *mode;
 743
 744         DRM_DEBUG_KMS("\n");
 745
 746         if (!intel_connector->panel.fixed_mode) {
 747                 DRM_DEBUG_KMS("no fixed mode\n");
 748                 return 0;
 749         }
 750
 751         mode = drm_mode_duplicate(connector->dev,
 752                                   intel_connector->panel.fixed_mode);
 753         if (!mode) {
 754                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 755                 return 0;
 756         }
 757
 758         drm_mode_probed_add(connector, mode);
 759         return 1;
 760 }
 761
 762 static void intel_dsi_connector_destroy(struct drm_connector *connector)
 763 {
 764         struct intel_connector *intel_connector = to_intel_connector(connector);
 765
 766         DRM_DEBUG_KMS("\n");
 767         intel_panel_fini(&intel_connector->panel);
 768         drm_connector_cleanup(connector);
 769         kfree(connector);
 770 }
 771
 772 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 773 {
 774         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 775
 776         if (intel_dsi->panel) {
 777                 drm_panel_detach(intel_dsi->panel);
 778                 /* XXX: Logically this call belongs in the panel driver. */
 779                 drm_panel_remove(intel_dsi->panel);
 780         }
 781         intel_encoder_destroy(encoder);
 782 }
 783
 784 static const struct drm_encoder_funcs intel_dsi_funcs = {
 785         .destroy = intel_dsi_encoder_destroy,
 786 };
 787
 788 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 789         .get_modes = intel_dsi_get_modes,
 790         .mode_valid = intel_dsi_mode_valid,
 791         .best_encoder = intel_best_encoder,
 792 };
 793
 794 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 795         .dpms = intel_connector_dpms,
 796         .detect = intel_dsi_detect,
 797         .destroy = intel_dsi_connector_destroy,
 798         .fill_modes = drm_helper_probe_single_connector_modes,
 799         .atomic_get_property = intel_connector_atomic_get_property,
 800         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 801 };
 802
 803 void intel_dsi_init(struct drm_device *dev)
 804 {
 805         struct intel_dsi *intel_dsi;
 806         struct intel_encoder *intel_encoder;
 807         struct drm_encoder *encoder;
 808         struct intel_connector *intel_connector;
 809         struct drm_connector *connector;
 810         struct drm_display_mode *scan, *fixed_mode = NULL;
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         unsigned int i;
 813
 814         DRM_DEBUG_KMS("\n");
 815
 816         /* There is no detection method for MIPI so rely on VBT */
 817         if (!dev_priv->vbt.has_mipi)
 818                 return;
 819
 820         if (IS_VALLEYVIEW(dev)) {
 821                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
 822         } else {
 823                 DRM_ERROR("Unsupported Mipi device to reg base");
 824                 return;
 825         }
 826
 827         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 828         if (!intel_dsi)
 829                 return;
 830
 831         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 832         if (!intel_connector) {
 833                 kfree(intel_dsi);
 834                 return;
 835         }
 836
 837         intel_encoder = &intel_dsi->base;
 838         encoder = &intel_encoder->base;
 839         intel_dsi->attached_connector = intel_connector;
 840
 841         connector = &intel_connector->base;
 842
 843         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 844
 845         /* XXX: very likely not all of these are needed */
 846         intel_encoder->hot_plug = intel_dsi_hot_plug;
 847         intel_encoder->compute_config = intel_dsi_compute_config;
 848         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 849         intel_encoder->pre_enable = intel_dsi_pre_enable;
 850         intel_encoder->enable = intel_dsi_enable_nop;
 851         intel_encoder->disable = intel_dsi_pre_disable;
 852         intel_encoder->post_disable = intel_dsi_post_disable;
 853         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 854         intel_encoder->get_config = intel_dsi_get_config;
 855
 856         intel_connector->get_hw_state = intel_connector_get_hw_state;
 857         intel_connector->unregister = intel_connector_unregister;
 858
 859         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
 860         if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
 861                 intel_encoder->crtc_mask = (1 << PIPE_A);
 862                 intel_dsi->ports = (1 << PORT_A);
 863         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
 864                 intel_encoder->crtc_mask = (1 << PIPE_B);
 865                 intel_dsi->ports = (1 << PORT_C);
 866         }
 867
 868         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
 869                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
 870                                                              intel_dsi_drivers[i].panel_id);
 871                 if (intel_dsi->panel)
 872                         break;
 873         }
 874
 875         if (!intel_dsi->panel) {
 876                 DRM_DEBUG_KMS("no device found\n");
 877                 goto err;
 878         }
 879
 880         intel_encoder->type = INTEL_OUTPUT_DSI;
 881         intel_encoder->cloneable = 0;
 882         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 883                            DRM_MODE_CONNECTOR_DSI);
 884
 885         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 886
 887         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 888         connector->interlace_allowed = false;
 889         connector->doublescan_allowed = false;
 890
 891         intel_connector_attach_encoder(intel_connector, intel_encoder);
 892
 893         drm_connector_register(connector);
 894
 895         drm_panel_attach(intel_dsi->panel, connector);
 896
 897         mutex_lock(&dev->mode_config.mutex);
 898         drm_panel_get_modes(intel_dsi->panel);
 899         list_for_each_entry(scan, &connector->probed_modes, head) {
 900                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
 901                         fixed_mode = drm_mode_duplicate(dev, scan);
 902                         break;
 903                 }
 904         }
 905         mutex_unlock(&dev->mode_config.mutex);
 906
 907         if (!fixed_mode) {
 908                 DRM_DEBUG_KMS("no fixed mode\n");
 909                 goto err;
 910         }
 911
 912         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 913
 914         return;
 915
 916 err:
 917         drm_encoder_cleanup(&intel_encoder->base);
 918         kfree(intel_dsi);
 919         kfree(intel_connector);
 920 }