2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52 struct drm_i915_private *dev_priv = to_i915(dev);
53 uint32_t enabled_bits;
55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58 "HDMI port enabled, expecting disabled\n");
61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
63 struct intel_digital_port *intel_dig_port =
64 container_of(encoder, struct intel_digital_port, base.base);
65 return &intel_dig_port->hdmi;
68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
70 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
73 static u32 g4x_infoframe_index(unsigned int type)
76 case HDMI_INFOFRAME_TYPE_AVI:
77 return VIDEO_DIP_SELECT_AVI;
78 case HDMI_INFOFRAME_TYPE_SPD:
79 return VIDEO_DIP_SELECT_SPD;
80 case HDMI_INFOFRAME_TYPE_VENDOR:
81 return VIDEO_DIP_SELECT_VENDOR;
88 static u32 g4x_infoframe_enable(unsigned int type)
91 case HDMI_INFOFRAME_TYPE_AVI:
92 return VIDEO_DIP_ENABLE_AVI;
93 case HDMI_INFOFRAME_TYPE_SPD:
94 return VIDEO_DIP_ENABLE_SPD;
95 case HDMI_INFOFRAME_TYPE_VENDOR:
96 return VIDEO_DIP_ENABLE_VENDOR;
103 static u32 hsw_infoframe_enable(unsigned int type)
107 return VIDEO_DIP_ENABLE_VSC_HSW;
108 case HDMI_INFOFRAME_TYPE_AVI:
109 return VIDEO_DIP_ENABLE_AVI_HSW;
110 case HDMI_INFOFRAME_TYPE_SPD:
111 return VIDEO_DIP_ENABLE_SPD_HSW;
112 case HDMI_INFOFRAME_TYPE_VENDOR:
113 return VIDEO_DIP_ENABLE_VS_HSW;
121 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
122 enum transcoder cpu_transcoder,
128 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
129 case HDMI_INFOFRAME_TYPE_AVI:
130 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
131 case HDMI_INFOFRAME_TYPE_SPD:
132 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
133 case HDMI_INFOFRAME_TYPE_VENDOR:
134 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
137 return INVALID_MMIO_REG;
141 static void g4x_write_infoframe(struct drm_encoder *encoder,
142 const struct intel_crtc_state *crtc_state,
144 const void *frame, ssize_t len)
146 const uint32_t *data = frame;
147 struct drm_device *dev = encoder->dev;
148 struct drm_i915_private *dev_priv = to_i915(dev);
149 u32 val = I915_READ(VIDEO_DIP_CTL);
152 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
154 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
155 val |= g4x_infoframe_index(type);
157 val &= ~g4x_infoframe_enable(type);
159 I915_WRITE(VIDEO_DIP_CTL, val);
162 for (i = 0; i < len; i += 4) {
163 I915_WRITE(VIDEO_DIP_DATA, *data);
166 /* Write every possible data byte to force correct ECC calculation. */
167 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
168 I915_WRITE(VIDEO_DIP_DATA, 0);
171 val |= g4x_infoframe_enable(type);
172 val &= ~VIDEO_DIP_FREQ_MASK;
173 val |= VIDEO_DIP_FREQ_VSYNC;
175 I915_WRITE(VIDEO_DIP_CTL, val);
176 POSTING_READ(VIDEO_DIP_CTL);
179 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
180 const struct intel_crtc_state *pipe_config)
182 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
183 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
184 u32 val = I915_READ(VIDEO_DIP_CTL);
186 if ((val & VIDEO_DIP_ENABLE) == 0)
189 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
192 return val & (VIDEO_DIP_ENABLE_AVI |
193 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
196 static void ibx_write_infoframe(struct drm_encoder *encoder,
197 const struct intel_crtc_state *crtc_state,
199 const void *frame, ssize_t len)
201 const uint32_t *data = frame;
202 struct drm_device *dev = encoder->dev;
203 struct drm_i915_private *dev_priv = to_i915(dev);
204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
205 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
206 u32 val = I915_READ(reg);
209 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
212 val |= g4x_infoframe_index(type);
214 val &= ~g4x_infoframe_enable(type);
216 I915_WRITE(reg, val);
219 for (i = 0; i < len; i += 4) {
220 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
223 /* Write every possible data byte to force correct ECC calculation. */
224 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
225 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
228 val |= g4x_infoframe_enable(type);
229 val &= ~VIDEO_DIP_FREQ_MASK;
230 val |= VIDEO_DIP_FREQ_VSYNC;
232 I915_WRITE(reg, val);
236 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
237 const struct intel_crtc_state *pipe_config)
239 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
240 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
241 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
242 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
243 u32 val = I915_READ(reg);
245 if ((val & VIDEO_DIP_ENABLE) == 0)
248 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
251 return val & (VIDEO_DIP_ENABLE_AVI |
252 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
253 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
256 static void cpt_write_infoframe(struct drm_encoder *encoder,
257 const struct intel_crtc_state *crtc_state,
259 const void *frame, ssize_t len)
261 const uint32_t *data = frame;
262 struct drm_device *dev = encoder->dev;
263 struct drm_i915_private *dev_priv = to_i915(dev);
264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
265 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
266 u32 val = I915_READ(reg);
269 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
271 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
272 val |= g4x_infoframe_index(type);
274 /* The DIP control register spec says that we need to update the AVI
275 * infoframe without clearing its enable bit */
276 if (type != HDMI_INFOFRAME_TYPE_AVI)
277 val &= ~g4x_infoframe_enable(type);
279 I915_WRITE(reg, val);
282 for (i = 0; i < len; i += 4) {
283 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
286 /* Write every possible data byte to force correct ECC calculation. */
287 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
288 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
291 val |= g4x_infoframe_enable(type);
292 val &= ~VIDEO_DIP_FREQ_MASK;
293 val |= VIDEO_DIP_FREQ_VSYNC;
295 I915_WRITE(reg, val);
299 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
300 const struct intel_crtc_state *pipe_config)
302 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
303 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
304 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
306 if ((val & VIDEO_DIP_ENABLE) == 0)
309 return val & (VIDEO_DIP_ENABLE_AVI |
310 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
311 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
314 static void vlv_write_infoframe(struct drm_encoder *encoder,
315 const struct intel_crtc_state *crtc_state,
317 const void *frame, ssize_t len)
319 const uint32_t *data = frame;
320 struct drm_device *dev = encoder->dev;
321 struct drm_i915_private *dev_priv = to_i915(dev);
322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
323 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
324 u32 val = I915_READ(reg);
327 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
329 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
330 val |= g4x_infoframe_index(type);
332 val &= ~g4x_infoframe_enable(type);
334 I915_WRITE(reg, val);
337 for (i = 0; i < len; i += 4) {
338 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
341 /* Write every possible data byte to force correct ECC calculation. */
342 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
343 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
346 val |= g4x_infoframe_enable(type);
347 val &= ~VIDEO_DIP_FREQ_MASK;
348 val |= VIDEO_DIP_FREQ_VSYNC;
350 I915_WRITE(reg, val);
354 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
355 const struct intel_crtc_state *pipe_config)
357 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
358 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
359 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
360 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
362 if ((val & VIDEO_DIP_ENABLE) == 0)
365 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
368 return val & (VIDEO_DIP_ENABLE_AVI |
369 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
370 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
373 static void hsw_write_infoframe(struct drm_encoder *encoder,
374 const struct intel_crtc_state *crtc_state,
376 const void *frame, ssize_t len)
378 const uint32_t *data = frame;
379 struct drm_device *dev = encoder->dev;
380 struct drm_i915_private *dev_priv = to_i915(dev);
381 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
382 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
384 int data_size = type == DP_SDP_VSC ?
385 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
387 u32 val = I915_READ(ctl_reg);
389 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
391 val &= ~hsw_infoframe_enable(type);
392 I915_WRITE(ctl_reg, val);
395 for (i = 0; i < len; i += 4) {
396 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
397 type, i >> 2), *data);
400 /* Write every possible data byte to force correct ECC calculation. */
401 for (; i < data_size; i += 4)
402 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
406 val |= hsw_infoframe_enable(type);
407 I915_WRITE(ctl_reg, val);
408 POSTING_READ(ctl_reg);
411 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
412 const struct intel_crtc_state *pipe_config)
414 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
415 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
417 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
418 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
419 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
423 * The data we write to the DIP data buffer registers is 1 byte bigger than the
424 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
425 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
426 * used for both technologies.
428 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
429 * DW1: DB3 | DB2 | DB1 | DB0
430 * DW2: DB7 | DB6 | DB5 | DB4
433 * (HB is Header Byte, DB is Data Byte)
435 * The hdmi pack() functions don't know about that hardware specific hole so we
436 * trick them by giving an offset into the buffer and moving back the header
439 static void intel_write_infoframe(struct drm_encoder *encoder,
440 const struct intel_crtc_state *crtc_state,
441 union hdmi_infoframe *frame)
443 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
444 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
447 /* see comment above for the reason for this offset */
448 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
452 /* Insert the 'hole' (see big comment above) at position 3 */
453 buffer[0] = buffer[1];
454 buffer[1] = buffer[2];
455 buffer[2] = buffer[3];
459 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
462 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
463 const struct intel_crtc_state *crtc_state)
465 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
466 const struct drm_display_mode *adjusted_mode =
467 &crtc_state->base.adjusted_mode;
468 struct drm_connector *connector = &intel_hdmi->attached_connector->base;
469 bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
470 union hdmi_infoframe frame;
473 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
477 DRM_ERROR("couldn't fill AVI infoframe\n");
481 if (crtc_state->ycbcr420)
482 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
484 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
486 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
487 crtc_state->limited_color_range ?
488 HDMI_QUANTIZATION_RANGE_LIMITED :
489 HDMI_QUANTIZATION_RANGE_FULL,
490 intel_hdmi->rgb_quant_range_selectable);
492 /* TODO: handle pixel repetition for YCBCR420 outputs */
493 intel_write_infoframe(encoder, crtc_state, &frame);
496 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
497 const struct intel_crtc_state *crtc_state)
499 union hdmi_infoframe frame;
502 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
504 DRM_ERROR("couldn't fill SPD infoframe\n");
508 frame.spd.sdi = HDMI_SPD_SDI_PC;
510 intel_write_infoframe(encoder, crtc_state, &frame);
514 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
515 const struct intel_crtc_state *crtc_state)
517 union hdmi_infoframe frame;
520 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
521 &crtc_state->base.adjusted_mode);
525 intel_write_infoframe(encoder, crtc_state, &frame);
528 static void g4x_set_infoframes(struct drm_encoder *encoder,
530 const struct intel_crtc_state *crtc_state,
531 const struct drm_connector_state *conn_state)
533 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
534 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
535 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
536 i915_reg_t reg = VIDEO_DIP_CTL;
537 u32 val = I915_READ(reg);
538 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
540 assert_hdmi_port_disabled(intel_hdmi);
542 /* If the registers were not initialized yet, they might be zeroes,
543 * which means we're selecting the AVI DIP and we're setting its
544 * frequency to once. This seems to really confuse the HW and make
545 * things stop working (the register spec says the AVI always needs to
546 * be sent every VSync). So here we avoid writing to the register more
547 * than we need and also explicitly select the AVI DIP and explicitly
548 * set its frequency to every VSync. Avoiding to write it twice seems to
549 * be enough to solve the problem, but being defensive shouldn't hurt us
551 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
554 if (!(val & VIDEO_DIP_ENABLE))
556 if (port != (val & VIDEO_DIP_PORT_MASK)) {
557 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
558 (val & VIDEO_DIP_PORT_MASK) >> 29);
561 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
562 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
563 I915_WRITE(reg, val);
568 if (port != (val & VIDEO_DIP_PORT_MASK)) {
569 if (val & VIDEO_DIP_ENABLE) {
570 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
571 (val & VIDEO_DIP_PORT_MASK) >> 29);
574 val &= ~VIDEO_DIP_PORT_MASK;
578 val |= VIDEO_DIP_ENABLE;
579 val &= ~(VIDEO_DIP_ENABLE_AVI |
580 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
582 I915_WRITE(reg, val);
585 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
586 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
587 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
590 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
592 struct drm_connector *connector = conn_state->connector;
595 * HDMI cloning is only supported on g4x which doesn't
596 * support deep color or GCP infoframes anyway so no
597 * need to worry about multiple HDMI sinks here.
600 return connector->display_info.bpc > 8;
604 * Determine if default_phase=1 can be indicated in the GCP infoframe.
606 * From HDMI specification 1.4a:
607 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
608 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
609 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
610 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
613 static bool gcp_default_phase_possible(int pipe_bpp,
614 const struct drm_display_mode *mode)
616 unsigned int pixels_per_group;
620 /* 4 pixels in 5 clocks */
621 pixels_per_group = 4;
624 /* 2 pixels in 3 clocks */
625 pixels_per_group = 2;
628 /* 1 pixel in 2 clocks */
629 pixels_per_group = 1;
632 /* phase information not relevant for 8bpc */
636 return mode->crtc_hdisplay % pixels_per_group == 0 &&
637 mode->crtc_htotal % pixels_per_group == 0 &&
638 mode->crtc_hblank_start % pixels_per_group == 0 &&
639 mode->crtc_hblank_end % pixels_per_group == 0 &&
640 mode->crtc_hsync_start % pixels_per_group == 0 &&
641 mode->crtc_hsync_end % pixels_per_group == 0 &&
642 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
643 mode->crtc_htotal/2 % pixels_per_group == 0);
646 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
647 const struct intel_crtc_state *crtc_state,
648 const struct drm_connector_state *conn_state)
650 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
651 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
655 if (HAS_DDI(dev_priv))
656 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
657 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
658 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
659 else if (HAS_PCH_SPLIT(dev_priv))
660 reg = TVIDEO_DIP_GCP(crtc->pipe);
664 /* Indicate color depth whenever the sink supports deep color */
665 if (hdmi_sink_is_deep_color(conn_state))
666 val |= GCP_COLOR_INDICATION;
668 /* Enable default_phase whenever the display mode is suitably aligned */
669 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
670 &crtc_state->base.adjusted_mode))
671 val |= GCP_DEFAULT_PHASE_ENABLE;
673 I915_WRITE(reg, val);
678 static void ibx_set_infoframes(struct drm_encoder *encoder,
680 const struct intel_crtc_state *crtc_state,
681 const struct drm_connector_state *conn_state)
683 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
685 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
686 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
687 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
688 u32 val = I915_READ(reg);
689 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
691 assert_hdmi_port_disabled(intel_hdmi);
693 /* See the big comment in g4x_set_infoframes() */
694 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
697 if (!(val & VIDEO_DIP_ENABLE))
699 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
700 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
701 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
702 I915_WRITE(reg, val);
707 if (port != (val & VIDEO_DIP_PORT_MASK)) {
708 WARN(val & VIDEO_DIP_ENABLE,
709 "DIP already enabled on port %c\n",
710 (val & VIDEO_DIP_PORT_MASK) >> 29);
711 val &= ~VIDEO_DIP_PORT_MASK;
715 val |= VIDEO_DIP_ENABLE;
716 val &= ~(VIDEO_DIP_ENABLE_AVI |
717 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
718 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
720 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
721 val |= VIDEO_DIP_ENABLE_GCP;
723 I915_WRITE(reg, val);
726 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
727 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
728 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
731 static void cpt_set_infoframes(struct drm_encoder *encoder,
733 const struct intel_crtc_state *crtc_state,
734 const struct drm_connector_state *conn_state)
736 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
738 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
739 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
740 u32 val = I915_READ(reg);
742 assert_hdmi_port_disabled(intel_hdmi);
744 /* See the big comment in g4x_set_infoframes() */
745 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
748 if (!(val & VIDEO_DIP_ENABLE))
750 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
751 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
752 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
753 I915_WRITE(reg, val);
758 /* Set both together, unset both together: see the spec. */
759 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
760 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
761 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
763 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
764 val |= VIDEO_DIP_ENABLE_GCP;
766 I915_WRITE(reg, val);
769 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
770 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
771 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
774 static void vlv_set_infoframes(struct drm_encoder *encoder,
776 const struct intel_crtc_state *crtc_state,
777 const struct drm_connector_state *conn_state)
779 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
780 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
782 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
783 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
784 u32 val = I915_READ(reg);
785 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
787 assert_hdmi_port_disabled(intel_hdmi);
789 /* See the big comment in g4x_set_infoframes() */
790 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
793 if (!(val & VIDEO_DIP_ENABLE))
795 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
796 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
797 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
798 I915_WRITE(reg, val);
803 if (port != (val & VIDEO_DIP_PORT_MASK)) {
804 WARN(val & VIDEO_DIP_ENABLE,
805 "DIP already enabled on port %c\n",
806 (val & VIDEO_DIP_PORT_MASK) >> 29);
807 val &= ~VIDEO_DIP_PORT_MASK;
811 val |= VIDEO_DIP_ENABLE;
812 val &= ~(VIDEO_DIP_ENABLE_AVI |
813 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
814 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
816 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
817 val |= VIDEO_DIP_ENABLE_GCP;
819 I915_WRITE(reg, val);
822 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
823 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
824 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
827 static void hsw_set_infoframes(struct drm_encoder *encoder,
829 const struct intel_crtc_state *crtc_state,
830 const struct drm_connector_state *conn_state)
832 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
833 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
834 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
835 u32 val = I915_READ(reg);
837 assert_hdmi_port_disabled(intel_hdmi);
839 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
840 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
841 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
844 I915_WRITE(reg, val);
849 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
850 val |= VIDEO_DIP_ENABLE_GCP_HSW;
852 I915_WRITE(reg, val);
855 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
856 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
857 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
860 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
862 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
863 struct i2c_adapter *adapter =
864 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
866 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
869 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
870 enable ? "Enabling" : "Disabling");
872 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
876 static void intel_hdmi_prepare(struct intel_encoder *encoder,
877 const struct intel_crtc_state *crtc_state)
879 struct drm_device *dev = encoder->base.dev;
880 struct drm_i915_private *dev_priv = to_i915(dev);
881 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
882 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
883 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
886 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
888 hdmi_val = SDVO_ENCODING_HDMI;
889 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
890 hdmi_val |= HDMI_COLOR_RANGE_16_235;
891 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
892 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
893 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
894 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
896 if (crtc_state->pipe_bpp > 24)
897 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
899 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
901 if (crtc_state->has_hdmi_sink)
902 hdmi_val |= HDMI_MODE_SELECT_HDMI;
904 if (HAS_PCH_CPT(dev_priv))
905 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
906 else if (IS_CHERRYVIEW(dev_priv))
907 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
909 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
911 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
912 POSTING_READ(intel_hdmi->hdmi_reg);
915 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
918 struct drm_device *dev = encoder->base.dev;
919 struct drm_i915_private *dev_priv = to_i915(dev);
920 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
924 if (!intel_display_power_get_if_enabled(dev_priv,
925 encoder->power_domain))
930 tmp = I915_READ(intel_hdmi->hdmi_reg);
932 if (!(tmp & SDVO_ENABLE))
935 if (HAS_PCH_CPT(dev_priv))
936 *pipe = PORT_TO_PIPE_CPT(tmp);
937 else if (IS_CHERRYVIEW(dev_priv))
938 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
940 *pipe = PORT_TO_PIPE(tmp);
945 intel_display_power_put(dev_priv, encoder->power_domain);
950 static void intel_hdmi_get_config(struct intel_encoder *encoder,
951 struct intel_crtc_state *pipe_config)
953 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
954 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
955 struct drm_device *dev = encoder->base.dev;
956 struct drm_i915_private *dev_priv = to_i915(dev);
960 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
962 tmp = I915_READ(intel_hdmi->hdmi_reg);
964 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
965 flags |= DRM_MODE_FLAG_PHSYNC;
967 flags |= DRM_MODE_FLAG_NHSYNC;
969 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
970 flags |= DRM_MODE_FLAG_PVSYNC;
972 flags |= DRM_MODE_FLAG_NVSYNC;
974 if (tmp & HDMI_MODE_SELECT_HDMI)
975 pipe_config->has_hdmi_sink = true;
977 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
978 pipe_config->has_infoframe = true;
980 if (tmp & SDVO_AUDIO_ENABLE)
981 pipe_config->has_audio = true;
983 if (!HAS_PCH_SPLIT(dev_priv) &&
984 tmp & HDMI_COLOR_RANGE_16_235)
985 pipe_config->limited_color_range = true;
987 pipe_config->base.adjusted_mode.flags |= flags;
989 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
990 dotclock = pipe_config->port_clock * 2 / 3;
992 dotclock = pipe_config->port_clock;
994 if (pipe_config->pixel_multiplier)
995 dotclock /= pipe_config->pixel_multiplier;
997 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
999 pipe_config->lane_count = 4;
1002 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1003 const struct intel_crtc_state *pipe_config,
1004 const struct drm_connector_state *conn_state)
1006 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1008 WARN_ON(!pipe_config->has_hdmi_sink);
1009 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1010 pipe_name(crtc->pipe));
1011 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1014 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1015 const struct intel_crtc_state *pipe_config,
1016 const struct drm_connector_state *conn_state)
1018 struct drm_device *dev = encoder->base.dev;
1019 struct drm_i915_private *dev_priv = to_i915(dev);
1020 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1023 temp = I915_READ(intel_hdmi->hdmi_reg);
1025 temp |= SDVO_ENABLE;
1026 if (pipe_config->has_audio)
1027 temp |= SDVO_AUDIO_ENABLE;
1029 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1030 POSTING_READ(intel_hdmi->hdmi_reg);
1032 if (pipe_config->has_audio)
1033 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1036 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1037 const struct intel_crtc_state *pipe_config,
1038 const struct drm_connector_state *conn_state)
1040 struct drm_device *dev = encoder->base.dev;
1041 struct drm_i915_private *dev_priv = to_i915(dev);
1042 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1045 temp = I915_READ(intel_hdmi->hdmi_reg);
1047 temp |= SDVO_ENABLE;
1048 if (pipe_config->has_audio)
1049 temp |= SDVO_AUDIO_ENABLE;
1052 * HW workaround, need to write this twice for issue
1053 * that may result in first write getting masked.
1055 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1056 POSTING_READ(intel_hdmi->hdmi_reg);
1057 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1058 POSTING_READ(intel_hdmi->hdmi_reg);
1061 * HW workaround, need to toggle enable bit off and on
1062 * for 12bpc with pixel repeat.
1064 * FIXME: BSpec says this should be done at the end of
1065 * of the modeset sequence, so not sure if this isn't too soon.
1067 if (pipe_config->pipe_bpp > 24 &&
1068 pipe_config->pixel_multiplier > 1) {
1069 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1070 POSTING_READ(intel_hdmi->hdmi_reg);
1073 * HW workaround, need to write this twice for issue
1074 * that may result in first write getting masked.
1076 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077 POSTING_READ(intel_hdmi->hdmi_reg);
1078 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1079 POSTING_READ(intel_hdmi->hdmi_reg);
1082 if (pipe_config->has_audio)
1083 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1086 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1087 const struct intel_crtc_state *pipe_config,
1088 const struct drm_connector_state *conn_state)
1090 struct drm_device *dev = encoder->base.dev;
1091 struct drm_i915_private *dev_priv = to_i915(dev);
1092 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1093 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1094 enum pipe pipe = crtc->pipe;
1097 temp = I915_READ(intel_hdmi->hdmi_reg);
1099 temp |= SDVO_ENABLE;
1100 if (pipe_config->has_audio)
1101 temp |= SDVO_AUDIO_ENABLE;
1104 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1106 * The procedure for 12bpc is as follows:
1107 * 1. disable HDMI clock gating
1108 * 2. enable HDMI with 8bpc
1109 * 3. enable HDMI with 12bpc
1110 * 4. enable HDMI clock gating
1113 if (pipe_config->pipe_bpp > 24) {
1114 I915_WRITE(TRANS_CHICKEN1(pipe),
1115 I915_READ(TRANS_CHICKEN1(pipe)) |
1116 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1118 temp &= ~SDVO_COLOR_FORMAT_MASK;
1119 temp |= SDVO_COLOR_FORMAT_8bpc;
1122 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1123 POSTING_READ(intel_hdmi->hdmi_reg);
1125 if (pipe_config->pipe_bpp > 24) {
1126 temp &= ~SDVO_COLOR_FORMAT_MASK;
1127 temp |= HDMI_COLOR_FORMAT_12bpc;
1129 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1130 POSTING_READ(intel_hdmi->hdmi_reg);
1132 I915_WRITE(TRANS_CHICKEN1(pipe),
1133 I915_READ(TRANS_CHICKEN1(pipe)) &
1134 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1137 if (pipe_config->has_audio)
1138 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1141 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1142 const struct intel_crtc_state *pipe_config,
1143 const struct drm_connector_state *conn_state)
1147 static void intel_disable_hdmi(struct intel_encoder *encoder,
1148 const struct intel_crtc_state *old_crtc_state,
1149 const struct drm_connector_state *old_conn_state)
1151 struct drm_device *dev = encoder->base.dev;
1152 struct drm_i915_private *dev_priv = to_i915(dev);
1153 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1154 struct intel_digital_port *intel_dig_port =
1155 hdmi_to_dig_port(intel_hdmi);
1156 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1159 temp = I915_READ(intel_hdmi->hdmi_reg);
1161 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1162 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1163 POSTING_READ(intel_hdmi->hdmi_reg);
1166 * HW workaround for IBX, we need to move the port
1167 * to transcoder A after disabling it to allow the
1168 * matching DP port to be enabled on transcoder A.
1170 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1172 * We get CPU/PCH FIFO underruns on the other pipe when
1173 * doing the workaround. Sweep them under the rug.
1175 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1176 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1178 temp &= ~SDVO_PIPE_B_SELECT;
1179 temp |= SDVO_ENABLE;
1181 * HW workaround, need to write this twice for issue
1182 * that may result in first write getting masked.
1184 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1185 POSTING_READ(intel_hdmi->hdmi_reg);
1186 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1187 POSTING_READ(intel_hdmi->hdmi_reg);
1189 temp &= ~SDVO_ENABLE;
1190 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1191 POSTING_READ(intel_hdmi->hdmi_reg);
1193 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1194 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1195 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1198 intel_dig_port->set_infoframes(&encoder->base, false,
1199 old_crtc_state, old_conn_state);
1201 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1204 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1205 const struct intel_crtc_state *old_crtc_state,
1206 const struct drm_connector_state *old_conn_state)
1208 if (old_crtc_state->has_audio)
1209 intel_audio_codec_disable(encoder,
1210 old_crtc_state, old_conn_state);
1212 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1215 static void pch_disable_hdmi(struct intel_encoder *encoder,
1216 const struct intel_crtc_state *old_crtc_state,
1217 const struct drm_connector_state *old_conn_state)
1219 if (old_crtc_state->has_audio)
1220 intel_audio_codec_disable(encoder,
1221 old_crtc_state, old_conn_state);
1224 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1225 const struct intel_crtc_state *old_crtc_state,
1226 const struct drm_connector_state *old_conn_state)
1228 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1231 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1234 const struct ddi_vbt_port_info *info =
1235 &dev_priv->vbt.ddi_port_info[encoder->port];
1238 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1239 max_tmds_clock = 594000;
1240 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1241 max_tmds_clock = 300000;
1242 else if (INTEL_GEN(dev_priv) >= 5)
1243 max_tmds_clock = 225000;
1245 max_tmds_clock = 165000;
1247 if (info->max_tmds_clock)
1248 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1250 return max_tmds_clock;
1253 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1254 bool respect_downstream_limits,
1257 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1258 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1260 if (respect_downstream_limits) {
1261 struct intel_connector *connector = hdmi->attached_connector;
1262 const struct drm_display_info *info = &connector->base.display_info;
1264 if (hdmi->dp_dual_mode.max_tmds_clock)
1265 max_tmds_clock = min(max_tmds_clock,
1266 hdmi->dp_dual_mode.max_tmds_clock);
1268 if (info->max_tmds_clock)
1269 max_tmds_clock = min(max_tmds_clock,
1270 info->max_tmds_clock);
1271 else if (!hdmi->has_hdmi_sink || force_dvi)
1272 max_tmds_clock = min(max_tmds_clock, 165000);
1275 return max_tmds_clock;
1278 static enum drm_mode_status
1279 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1280 int clock, bool respect_downstream_limits,
1283 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1286 return MODE_CLOCK_LOW;
1287 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1288 return MODE_CLOCK_HIGH;
1290 /* BXT DPLL can't generate 223-240 MHz */
1291 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1292 return MODE_CLOCK_RANGE;
1294 /* CHV DPLL can't generate 216-240 MHz */
1295 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1296 return MODE_CLOCK_RANGE;
1301 static enum drm_mode_status
1302 intel_hdmi_mode_valid(struct drm_connector *connector,
1303 struct drm_display_mode *mode)
1305 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1306 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1307 struct drm_i915_private *dev_priv = to_i915(dev);
1308 enum drm_mode_status status;
1310 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1312 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1314 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1315 return MODE_NO_DBLESCAN;
1317 clock = mode->clock;
1319 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1322 if (clock > max_dotclk)
1323 return MODE_CLOCK_HIGH;
1325 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1328 if (drm_mode_is_420_only(&connector->display_info, mode))
1331 /* check if we can do 8bpc */
1332 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1334 /* if we can't do 8bpc we may still be able to do 12bpc */
1335 if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1336 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1341 static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
1343 struct drm_i915_private *dev_priv =
1344 to_i915(crtc_state->base.crtc->dev);
1345 struct drm_atomic_state *state = crtc_state->base.state;
1346 struct drm_connector_state *connector_state;
1347 struct drm_connector *connector;
1350 if (HAS_GMCH_DISPLAY(dev_priv))
1353 if (crtc_state->pipe_bpp <= 8*3)
1356 if (!crtc_state->has_hdmi_sink)
1360 * HDMI 12bpc affects the clocks, so it's only possible
1361 * when not cloning with other encoder types.
1363 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1366 for_each_new_connector_in_state(state, connector, connector_state, i) {
1367 const struct drm_display_info *info = &connector->display_info;
1369 if (connector_state->crtc != crtc_state->base.crtc)
1372 if (crtc_state->ycbcr420) {
1373 const struct drm_hdmi_info *hdmi = &info->hdmi;
1375 if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1378 if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1383 /* Display WA #1139: glk */
1384 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1385 crtc_state->base.adjusted_mode.htotal > 5460)
1392 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1393 struct intel_crtc_state *config,
1394 int *clock_12bpc, int *clock_8bpc)
1396 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1398 if (!connector->ycbcr_420_allowed) {
1399 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1403 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1404 config->port_clock /= 2;
1407 config->ycbcr420 = true;
1409 /* YCBCR 420 output conversion needs a scaler */
1410 if (skl_update_scaler_crtc(config)) {
1411 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1415 intel_pch_panel_fitting(intel_crtc, config,
1416 DRM_MODE_SCALE_FULLSCREEN);
1421 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1422 struct intel_crtc_state *pipe_config,
1423 struct drm_connector_state *conn_state)
1425 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1426 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1427 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1428 struct drm_connector *connector = conn_state->connector;
1429 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1430 struct intel_digital_connector_state *intel_conn_state =
1431 to_intel_digital_connector_state(conn_state);
1432 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1433 int clock_12bpc = clock_8bpc * 3 / 2;
1435 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1437 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1439 if (pipe_config->has_hdmi_sink)
1440 pipe_config->has_infoframe = true;
1442 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1443 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1444 pipe_config->limited_color_range =
1445 pipe_config->has_hdmi_sink &&
1446 drm_default_rgb_quant_range(adjusted_mode) ==
1447 HDMI_QUANTIZATION_RANGE_LIMITED;
1449 pipe_config->limited_color_range =
1450 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1453 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1454 pipe_config->pixel_multiplier = 2;
1459 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1460 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1461 &clock_12bpc, &clock_8bpc)) {
1462 DRM_ERROR("Can't support YCBCR420 output\n");
1467 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1468 pipe_config->has_pch_encoder = true;
1470 if (pipe_config->has_hdmi_sink) {
1471 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1472 pipe_config->has_audio = intel_hdmi->has_audio;
1474 pipe_config->has_audio =
1475 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1479 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1480 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1481 * outputs. We also need to check that the higher clock still fits
1484 if (hdmi_12bpc_possible(pipe_config) &&
1485 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) {
1486 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1489 /* Need to adjust the port link by 1.5x for 12bpc. */
1490 pipe_config->port_clock = clock_12bpc;
1492 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1495 pipe_config->port_clock = clock_8bpc;
1498 if (!pipe_config->bw_constrained) {
1499 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1500 pipe_config->pipe_bpp = desired_bpp;
1503 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1504 false, force_dvi) != MODE_OK) {
1505 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1509 /* Set user selected PAR to incoming mode's member */
1510 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1512 pipe_config->lane_count = 4;
1514 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1515 IS_GEMINILAKE(dev_priv))) {
1516 if (scdc->scrambling.low_rates)
1517 pipe_config->hdmi_scrambling = true;
1519 if (pipe_config->port_clock > 340000) {
1520 pipe_config->hdmi_scrambling = true;
1521 pipe_config->hdmi_high_tmds_clock_ratio = true;
1529 intel_hdmi_unset_edid(struct drm_connector *connector)
1531 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1533 intel_hdmi->has_hdmi_sink = false;
1534 intel_hdmi->has_audio = false;
1535 intel_hdmi->rgb_quant_range_selectable = false;
1537 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1538 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1540 kfree(to_intel_connector(connector)->detect_edid);
1541 to_intel_connector(connector)->detect_edid = NULL;
1545 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1547 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1548 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1549 enum port port = hdmi_to_dig_port(hdmi)->base.port;
1550 struct i2c_adapter *adapter =
1551 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1552 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1555 * Type 1 DVI adaptors are not required to implement any
1556 * registers, so we can't always detect their presence.
1557 * Ideally we should be able to check the state of the
1558 * CONFIG1 pin, but no such luck on our hardware.
1560 * The only method left to us is to check the VBT to see
1561 * if the port is a dual mode capable DP port. But let's
1562 * only do that when we sucesfully read the EDID, to avoid
1563 * confusing log messages about DP dual mode adaptors when
1564 * there's nothing connected to the port.
1566 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1568 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1569 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1570 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1572 type = DRM_DP_DUAL_MODE_NONE;
1576 if (type == DRM_DP_DUAL_MODE_NONE)
1579 hdmi->dp_dual_mode.type = type;
1580 hdmi->dp_dual_mode.max_tmds_clock =
1581 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1583 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1584 drm_dp_get_dual_mode_type_name(type),
1585 hdmi->dp_dual_mode.max_tmds_clock);
1589 intel_hdmi_set_edid(struct drm_connector *connector)
1591 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1592 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1594 bool connected = false;
1596 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1598 edid = drm_get_edid(connector,
1599 intel_gmbus_get_adapter(dev_priv,
1600 intel_hdmi->ddc_bus));
1602 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1604 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1606 to_intel_connector(connector)->detect_edid = edid;
1607 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1608 intel_hdmi->rgb_quant_range_selectable =
1609 drm_rgb_quant_range_selectable(edid);
1611 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1612 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1620 static enum drm_connector_status
1621 intel_hdmi_detect(struct drm_connector *connector, bool force)
1623 enum drm_connector_status status;
1624 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1626 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1627 connector->base.id, connector->name);
1629 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1631 intel_hdmi_unset_edid(connector);
1633 if (intel_hdmi_set_edid(connector))
1634 status = connector_status_connected;
1636 status = connector_status_disconnected;
1638 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1644 intel_hdmi_force(struct drm_connector *connector)
1646 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1647 connector->base.id, connector->name);
1649 intel_hdmi_unset_edid(connector);
1651 if (connector->status != connector_status_connected)
1654 intel_hdmi_set_edid(connector);
1657 static int intel_hdmi_get_modes(struct drm_connector *connector)
1661 edid = to_intel_connector(connector)->detect_edid;
1665 return intel_connector_update_modes(connector, edid);
1668 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1669 const struct intel_crtc_state *pipe_config,
1670 const struct drm_connector_state *conn_state)
1672 struct intel_digital_port *intel_dig_port =
1673 enc_to_dig_port(&encoder->base);
1675 intel_hdmi_prepare(encoder, pipe_config);
1677 intel_dig_port->set_infoframes(&encoder->base,
1678 pipe_config->has_infoframe,
1679 pipe_config, conn_state);
1682 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1683 const struct intel_crtc_state *pipe_config,
1684 const struct drm_connector_state *conn_state)
1686 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1689 vlv_phy_pre_encoder_enable(encoder, pipe_config);
1692 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1695 dport->set_infoframes(&encoder->base,
1696 pipe_config->has_infoframe,
1697 pipe_config, conn_state);
1699 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1701 vlv_wait_port_ready(dev_priv, dport, 0x0);
1704 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1705 const struct intel_crtc_state *pipe_config,
1706 const struct drm_connector_state *conn_state)
1708 intel_hdmi_prepare(encoder, pipe_config);
1710 vlv_phy_pre_pll_enable(encoder, pipe_config);
1713 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1714 const struct intel_crtc_state *pipe_config,
1715 const struct drm_connector_state *conn_state)
1717 intel_hdmi_prepare(encoder, pipe_config);
1719 chv_phy_pre_pll_enable(encoder, pipe_config);
1722 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1723 const struct intel_crtc_state *old_crtc_state,
1724 const struct drm_connector_state *old_conn_state)
1726 chv_phy_post_pll_disable(encoder, old_crtc_state);
1729 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1730 const struct intel_crtc_state *old_crtc_state,
1731 const struct drm_connector_state *old_conn_state)
1733 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1734 vlv_phy_reset_lanes(encoder, old_crtc_state);
1737 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1738 const struct intel_crtc_state *old_crtc_state,
1739 const struct drm_connector_state *old_conn_state)
1741 struct drm_device *dev = encoder->base.dev;
1742 struct drm_i915_private *dev_priv = to_i915(dev);
1744 mutex_lock(&dev_priv->sb_lock);
1746 /* Assert data lane reset */
1747 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
1749 mutex_unlock(&dev_priv->sb_lock);
1752 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1753 const struct intel_crtc_state *pipe_config,
1754 const struct drm_connector_state *conn_state)
1756 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1757 struct drm_device *dev = encoder->base.dev;
1758 struct drm_i915_private *dev_priv = to_i915(dev);
1760 chv_phy_pre_encoder_enable(encoder, pipe_config);
1762 /* FIXME: Program the support xxx V-dB */
1764 chv_set_phy_signal_level(encoder, 128, 102, false);
1766 dport->set_infoframes(&encoder->base,
1767 pipe_config->has_infoframe,
1768 pipe_config, conn_state);
1770 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1772 vlv_wait_port_ready(dev_priv, dport, 0x0);
1774 /* Second common lane will stay alive on its own now */
1775 chv_phy_release_cl2_override(encoder);
1778 static void intel_hdmi_destroy(struct drm_connector *connector)
1780 kfree(to_intel_connector(connector)->detect_edid);
1781 drm_connector_cleanup(connector);
1785 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1786 .detect = intel_hdmi_detect,
1787 .force = intel_hdmi_force,
1788 .fill_modes = drm_helper_probe_single_connector_modes,
1789 .atomic_get_property = intel_digital_connector_atomic_get_property,
1790 .atomic_set_property = intel_digital_connector_atomic_set_property,
1791 .late_register = intel_connector_register,
1792 .early_unregister = intel_connector_unregister,
1793 .destroy = intel_hdmi_destroy,
1794 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1795 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1798 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1799 .get_modes = intel_hdmi_get_modes,
1800 .mode_valid = intel_hdmi_mode_valid,
1801 .atomic_check = intel_digital_connector_atomic_check,
1804 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1805 .destroy = intel_encoder_destroy,
1809 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1811 intel_attach_force_audio_property(connector);
1812 intel_attach_broadcast_rgb_property(connector);
1813 intel_attach_aspect_ratio_property(connector);
1814 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1818 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1819 * @encoder: intel_encoder
1820 * @connector: drm_connector
1821 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1822 * or reset the high tmds clock ratio for scrambling
1823 * @scrambling: bool to Indicate if the function needs to set or reset
1826 * This function handles scrambling on HDMI 2.0 capable sinks.
1827 * If required clock rate is > 340 Mhz && scrambling is supported by sink
1828 * it enables scrambling. This should be called before enabling the HDMI
1829 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1830 * detect a scrambled clock within 100 ms.
1832 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1833 struct drm_connector *connector,
1834 bool high_tmds_clock_ratio,
1837 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1838 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1839 struct drm_scrambling *sink_scrambling =
1840 &connector->display_info.hdmi.scdc.scrambling;
1841 struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1842 intel_hdmi->ddc_bus);
1845 if (!sink_scrambling->supported)
1848 DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1849 encoder->base.name, connector->name);
1851 /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1852 ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1854 DRM_ERROR("Set TMDS ratio failed\n");
1858 /* Enable/disable sink scrambling */
1859 ret = drm_scdc_set_scrambling(adptr, scrambling);
1861 DRM_ERROR("Set sink scrambling failed\n");
1865 DRM_DEBUG_KMS("sink scrambling handled\n");
1868 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1874 ddc_pin = GMBUS_PIN_DPB;
1877 ddc_pin = GMBUS_PIN_DPC;
1880 ddc_pin = GMBUS_PIN_DPD_CHV;
1884 ddc_pin = GMBUS_PIN_DPB;
1890 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1896 ddc_pin = GMBUS_PIN_1_BXT;
1899 ddc_pin = GMBUS_PIN_2_BXT;
1903 ddc_pin = GMBUS_PIN_1_BXT;
1909 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1916 ddc_pin = GMBUS_PIN_1_BXT;
1919 ddc_pin = GMBUS_PIN_2_BXT;
1922 ddc_pin = GMBUS_PIN_4_CNP;
1926 ddc_pin = GMBUS_PIN_1_BXT;
1932 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1939 ddc_pin = GMBUS_PIN_DPB;
1942 ddc_pin = GMBUS_PIN_DPC;
1945 ddc_pin = GMBUS_PIN_DPD;
1949 ddc_pin = GMBUS_PIN_DPB;
1955 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1958 const struct ddi_vbt_port_info *info =
1959 &dev_priv->vbt.ddi_port_info[port];
1962 if (info->alternate_ddc_pin) {
1963 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1964 info->alternate_ddc_pin, port_name(port));
1965 return info->alternate_ddc_pin;
1968 if (IS_CHERRYVIEW(dev_priv))
1969 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
1970 else if (IS_GEN9_LP(dev_priv))
1971 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
1972 else if (HAS_PCH_CNP(dev_priv))
1973 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
1975 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
1977 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1978 ddc_pin, port_name(port));
1983 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
1985 struct drm_i915_private *dev_priv =
1986 to_i915(intel_dig_port->base.base.dev);
1988 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1989 intel_dig_port->write_infoframe = vlv_write_infoframe;
1990 intel_dig_port->set_infoframes = vlv_set_infoframes;
1991 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
1992 } else if (IS_G4X(dev_priv)) {
1993 intel_dig_port->write_infoframe = g4x_write_infoframe;
1994 intel_dig_port->set_infoframes = g4x_set_infoframes;
1995 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
1996 } else if (HAS_DDI(dev_priv)) {
1997 intel_dig_port->write_infoframe = hsw_write_infoframe;
1998 intel_dig_port->set_infoframes = hsw_set_infoframes;
1999 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
2000 } else if (HAS_PCH_IBX(dev_priv)) {
2001 intel_dig_port->write_infoframe = ibx_write_infoframe;
2002 intel_dig_port->set_infoframes = ibx_set_infoframes;
2003 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2005 intel_dig_port->write_infoframe = cpt_write_infoframe;
2006 intel_dig_port->set_infoframes = cpt_set_infoframes;
2007 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2011 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2012 struct intel_connector *intel_connector)
2014 struct drm_connector *connector = &intel_connector->base;
2015 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2016 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2017 struct drm_device *dev = intel_encoder->base.dev;
2018 struct drm_i915_private *dev_priv = to_i915(dev);
2019 enum port port = intel_encoder->port;
2021 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2024 if (WARN(intel_dig_port->max_lanes < 4,
2025 "Not enough lanes (%d) for HDMI on port %c\n",
2026 intel_dig_port->max_lanes, port_name(port)))
2029 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2030 DRM_MODE_CONNECTOR_HDMIA);
2031 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2033 connector->interlace_allowed = 1;
2034 connector->doublescan_allowed = 0;
2035 connector->stereo_allowed = 1;
2037 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2038 connector->ycbcr_420_allowed = true;
2040 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2042 if (WARN_ON(port == PORT_A))
2044 intel_encoder->hpd_pin = intel_hpd_pin(port);
2046 if (HAS_DDI(dev_priv))
2047 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2049 intel_connector->get_hw_state = intel_connector_get_hw_state;
2051 intel_hdmi_add_properties(intel_hdmi, connector);
2053 intel_connector_attach_encoder(intel_connector, intel_encoder);
2054 intel_hdmi->attached_connector = intel_connector;
2056 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2057 * 0xd. Failure to do so will result in spurious interrupts being
2058 * generated on the port when a cable is not attached.
2060 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2061 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2062 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2066 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2067 i915_reg_t hdmi_reg, enum port port)
2069 struct intel_digital_port *intel_dig_port;
2070 struct intel_encoder *intel_encoder;
2071 struct intel_connector *intel_connector;
2073 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2074 if (!intel_dig_port)
2077 intel_connector = intel_connector_alloc();
2078 if (!intel_connector) {
2079 kfree(intel_dig_port);
2083 intel_encoder = &intel_dig_port->base;
2085 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2086 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2087 "HDMI %c", port_name(port));
2089 intel_encoder->compute_config = intel_hdmi_compute_config;
2090 if (HAS_PCH_SPLIT(dev_priv)) {
2091 intel_encoder->disable = pch_disable_hdmi;
2092 intel_encoder->post_disable = pch_post_disable_hdmi;
2094 intel_encoder->disable = g4x_disable_hdmi;
2096 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2097 intel_encoder->get_config = intel_hdmi_get_config;
2098 if (IS_CHERRYVIEW(dev_priv)) {
2099 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2100 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2101 intel_encoder->enable = vlv_enable_hdmi;
2102 intel_encoder->post_disable = chv_hdmi_post_disable;
2103 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2104 } else if (IS_VALLEYVIEW(dev_priv)) {
2105 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2106 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2107 intel_encoder->enable = vlv_enable_hdmi;
2108 intel_encoder->post_disable = vlv_hdmi_post_disable;
2110 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2111 if (HAS_PCH_CPT(dev_priv))
2112 intel_encoder->enable = cpt_enable_hdmi;
2113 else if (HAS_PCH_IBX(dev_priv))
2114 intel_encoder->enable = ibx_enable_hdmi;
2116 intel_encoder->enable = g4x_enable_hdmi;
2119 intel_encoder->type = INTEL_OUTPUT_HDMI;
2120 intel_encoder->power_domain = intel_port_to_power_domain(port);
2121 intel_encoder->port = port;
2122 if (IS_CHERRYVIEW(dev_priv)) {
2124 intel_encoder->crtc_mask = 1 << 2;
2126 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2128 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2130 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2132 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2133 * to work on real hardware. And since g4x can send infoframes to
2134 * only one port anyway, nothing is lost by allowing it.
2136 if (IS_G4X(dev_priv))
2137 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2139 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2140 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2141 intel_dig_port->max_lanes = 4;
2143 intel_infoframe_init(intel_dig_port);
2145 intel_hdmi_init_connector(intel_dig_port, intel_connector);