drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_scdc_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "i915_drv.h"
  42
  43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  44 {
  45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  46 }
  47
  48 static void
  49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  50 {
  51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  52         struct drm_i915_private *dev_priv = to_i915(dev);
  53         uint32_t enabled_bits;
  54
  55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  56
  57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  58              "HDMI port enabled, expecting disabled\n");
  59 }
  60
  61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  62 {
  63         struct intel_digital_port *intel_dig_port =
  64                 container_of(encoder, struct intel_digital_port, base.base);
  65         return &intel_dig_port->hdmi;
  66 }
  67
  68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  69 {
  70         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  71 }
  72
  73 static u32 g4x_infoframe_index(unsigned int type)
  74 {
  75         switch (type) {
  76         case HDMI_INFOFRAME_TYPE_AVI:
  77                 return VIDEO_DIP_SELECT_AVI;
  78         case HDMI_INFOFRAME_TYPE_SPD:
  79                 return VIDEO_DIP_SELECT_SPD;
  80         case HDMI_INFOFRAME_TYPE_VENDOR:
  81                 return VIDEO_DIP_SELECT_VENDOR;
  82         default:
  83                 MISSING_CASE(type);
  84                 return 0;
  85         }
  86 }
  87
  88 static u32 g4x_infoframe_enable(unsigned int type)
  89 {
  90         switch (type) {
  91         case HDMI_INFOFRAME_TYPE_AVI:
  92                 return VIDEO_DIP_ENABLE_AVI;
  93         case HDMI_INFOFRAME_TYPE_SPD:
  94                 return VIDEO_DIP_ENABLE_SPD;
  95         case HDMI_INFOFRAME_TYPE_VENDOR:
  96                 return VIDEO_DIP_ENABLE_VENDOR;
  97         default:
  98                 MISSING_CASE(type);
  99                 return 0;
 100         }
 101 }
 102
 103 static u32 hsw_infoframe_enable(unsigned int type)
 104 {
 105         switch (type) {
 106         case DP_SDP_VSC:
 107                 return VIDEO_DIP_ENABLE_VSC_HSW;
 108         case HDMI_INFOFRAME_TYPE_AVI:
 109                 return VIDEO_DIP_ENABLE_AVI_HSW;
 110         case HDMI_INFOFRAME_TYPE_SPD:
 111                 return VIDEO_DIP_ENABLE_SPD_HSW;
 112         case HDMI_INFOFRAME_TYPE_VENDOR:
 113                 return VIDEO_DIP_ENABLE_VS_HSW;
 114         default:
 115                 MISSING_CASE(type);
 116                 return 0;
 117         }
 118 }
 119
 120 static i915_reg_t
 121 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 122                  enum transcoder cpu_transcoder,
 123                  unsigned int type,
 124                  int i)
 125 {
 126         switch (type) {
 127         case DP_SDP_VSC:
 128                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 129         case HDMI_INFOFRAME_TYPE_AVI:
 130                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 131         case HDMI_INFOFRAME_TYPE_SPD:
 132                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 133         case HDMI_INFOFRAME_TYPE_VENDOR:
 134                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 135         default:
 136                 MISSING_CASE(type);
 137                 return INVALID_MMIO_REG;
 138         }
 139 }
 140
 141 static void g4x_write_infoframe(struct drm_encoder *encoder,
 142                                 const struct intel_crtc_state *crtc_state,
 143                                 unsigned int type,
 144                                 const void *frame, ssize_t len)
 145 {
 146         const uint32_t *data = frame;
 147         struct drm_device *dev = encoder->dev;
 148         struct drm_i915_private *dev_priv = to_i915(dev);
 149         u32 val = I915_READ(VIDEO_DIP_CTL);
 150         int i;
 151
 152         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 153
 154         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 155         val |= g4x_infoframe_index(type);
 156
 157         val &= ~g4x_infoframe_enable(type);
 158
 159         I915_WRITE(VIDEO_DIP_CTL, val);
 160
 161         mmiowb();
 162         for (i = 0; i < len; i += 4) {
 163                 I915_WRITE(VIDEO_DIP_DATA, *data);
 164                 data++;
 165         }
 166         /* Write every possible data byte to force correct ECC calculation. */
 167         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 168                 I915_WRITE(VIDEO_DIP_DATA, 0);
 169         mmiowb();
 170
 171         val |= g4x_infoframe_enable(type);
 172         val &= ~VIDEO_DIP_FREQ_MASK;
 173         val |= VIDEO_DIP_FREQ_VSYNC;
 174
 175         I915_WRITE(VIDEO_DIP_CTL, val);
 176         POSTING_READ(VIDEO_DIP_CTL);
 177 }
 178
 179 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 180                                   const struct intel_crtc_state *pipe_config)
 181 {
 182         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 183         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 184         u32 val = I915_READ(VIDEO_DIP_CTL);
 185
 186         if ((val & VIDEO_DIP_ENABLE) == 0)
 187                 return false;
 188
 189         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 190                 return false;
 191
 192         return val & (VIDEO_DIP_ENABLE_AVI |
 193                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 194 }
 195
 196 static void ibx_write_infoframe(struct drm_encoder *encoder,
 197                                 const struct intel_crtc_state *crtc_state,
 198                                 unsigned int type,
 199                                 const void *frame, ssize_t len)
 200 {
 201         const uint32_t *data = frame;
 202         struct drm_device *dev = encoder->dev;
 203         struct drm_i915_private *dev_priv = to_i915(dev);
 204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 205         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 206         u32 val = I915_READ(reg);
 207         int i;
 208
 209         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 210
 211         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 212         val |= g4x_infoframe_index(type);
 213
 214         val &= ~g4x_infoframe_enable(type);
 215
 216         I915_WRITE(reg, val);
 217
 218         mmiowb();
 219         for (i = 0; i < len; i += 4) {
 220                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 221                 data++;
 222         }
 223         /* Write every possible data byte to force correct ECC calculation. */
 224         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 225                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 226         mmiowb();
 227
 228         val |= g4x_infoframe_enable(type);
 229         val &= ~VIDEO_DIP_FREQ_MASK;
 230         val |= VIDEO_DIP_FREQ_VSYNC;
 231
 232         I915_WRITE(reg, val);
 233         POSTING_READ(reg);
 234 }
 235
 236 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 237                                   const struct intel_crtc_state *pipe_config)
 238 {
 239         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 240         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 241         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 242         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 243         u32 val = I915_READ(reg);
 244
 245         if ((val & VIDEO_DIP_ENABLE) == 0)
 246                 return false;
 247
 248         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 249                 return false;
 250
 251         return val & (VIDEO_DIP_ENABLE_AVI |
 252                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 253                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 254 }
 255
 256 static void cpt_write_infoframe(struct drm_encoder *encoder,
 257                                 const struct intel_crtc_state *crtc_state,
 258                                 unsigned int type,
 259                                 const void *frame, ssize_t len)
 260 {
 261         const uint32_t *data = frame;
 262         struct drm_device *dev = encoder->dev;
 263         struct drm_i915_private *dev_priv = to_i915(dev);
 264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 265         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 266         u32 val = I915_READ(reg);
 267         int i;
 268
 269         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 270
 271         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 272         val |= g4x_infoframe_index(type);
 273
 274         /* The DIP control register spec says that we need to update the AVI
 275          * infoframe without clearing its enable bit */
 276         if (type != HDMI_INFOFRAME_TYPE_AVI)
 277                 val &= ~g4x_infoframe_enable(type);
 278
 279         I915_WRITE(reg, val);
 280
 281         mmiowb();
 282         for (i = 0; i < len; i += 4) {
 283                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 284                 data++;
 285         }
 286         /* Write every possible data byte to force correct ECC calculation. */
 287         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 288                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 289         mmiowb();
 290
 291         val |= g4x_infoframe_enable(type);
 292         val &= ~VIDEO_DIP_FREQ_MASK;
 293         val |= VIDEO_DIP_FREQ_VSYNC;
 294
 295         I915_WRITE(reg, val);
 296         POSTING_READ(reg);
 297 }
 298
 299 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 300                                   const struct intel_crtc_state *pipe_config)
 301 {
 302         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 303         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 304         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 305
 306         if ((val & VIDEO_DIP_ENABLE) == 0)
 307                 return false;
 308
 309         return val & (VIDEO_DIP_ENABLE_AVI |
 310                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 311                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 312 }
 313
 314 static void vlv_write_infoframe(struct drm_encoder *encoder,
 315                                 const struct intel_crtc_state *crtc_state,
 316                                 unsigned int type,
 317                                 const void *frame, ssize_t len)
 318 {
 319         const uint32_t *data = frame;
 320         struct drm_device *dev = encoder->dev;
 321         struct drm_i915_private *dev_priv = to_i915(dev);
 322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 323         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 324         u32 val = I915_READ(reg);
 325         int i;
 326
 327         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 328
 329         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 330         val |= g4x_infoframe_index(type);
 331
 332         val &= ~g4x_infoframe_enable(type);
 333
 334         I915_WRITE(reg, val);
 335
 336         mmiowb();
 337         for (i = 0; i < len; i += 4) {
 338                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 339                 data++;
 340         }
 341         /* Write every possible data byte to force correct ECC calculation. */
 342         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 343                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 344         mmiowb();
 345
 346         val |= g4x_infoframe_enable(type);
 347         val &= ~VIDEO_DIP_FREQ_MASK;
 348         val |= VIDEO_DIP_FREQ_VSYNC;
 349
 350         I915_WRITE(reg, val);
 351         POSTING_READ(reg);
 352 }
 353
 354 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 355                                   const struct intel_crtc_state *pipe_config)
 356 {
 357         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 358         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 359         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 360         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 361
 362         if ((val & VIDEO_DIP_ENABLE) == 0)
 363                 return false;
 364
 365         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 366                 return false;
 367
 368         return val & (VIDEO_DIP_ENABLE_AVI |
 369                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 370                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 371 }
 372
 373 static void hsw_write_infoframe(struct drm_encoder *encoder,
 374                                 const struct intel_crtc_state *crtc_state,
 375                                 unsigned int type,
 376                                 const void *frame, ssize_t len)
 377 {
 378         const uint32_t *data = frame;
 379         struct drm_device *dev = encoder->dev;
 380         struct drm_i915_private *dev_priv = to_i915(dev);
 381         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 382         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 383         i915_reg_t data_reg;
 384         int data_size = type == DP_SDP_VSC ?
 385                 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
 386         int i;
 387         u32 val = I915_READ(ctl_reg);
 388
 389         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 390
 391         val &= ~hsw_infoframe_enable(type);
 392         I915_WRITE(ctl_reg, val);
 393
 394         mmiowb();
 395         for (i = 0; i < len; i += 4) {
 396                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 397                                             type, i >> 2), *data);
 398                 data++;
 399         }
 400         /* Write every possible data byte to force correct ECC calculation. */
 401         for (; i < data_size; i += 4)
 402                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 403                                             type, i >> 2), 0);
 404         mmiowb();
 405
 406         val |= hsw_infoframe_enable(type);
 407         I915_WRITE(ctl_reg, val);
 408         POSTING_READ(ctl_reg);
 409 }
 410
 411 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 412                                   const struct intel_crtc_state *pipe_config)
 413 {
 414         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 415         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 416
 417         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 418                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 419                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 420 }
 421
 422 /*
 423  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 424  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 425  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 426  * used for both technologies.
 427  *
 428  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 429  * DW1:       DB3       | DB2 | DB1 | DB0
 430  * DW2:       DB7       | DB6 | DB5 | DB4
 431  * DW3: ...
 432  *
 433  * (HB is Header Byte, DB is Data Byte)
 434  *
 435  * The hdmi pack() functions don't know about that hardware specific hole so we
 436  * trick them by giving an offset into the buffer and moving back the header
 437  * bytes by one.
 438  */
 439 static void intel_write_infoframe(struct drm_encoder *encoder,
 440                                   const struct intel_crtc_state *crtc_state,
 441                                   union hdmi_infoframe *frame)
 442 {
 443         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 444         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 445         ssize_t len;
 446
 447         /* see comment above for the reason for this offset */
 448         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 449         if (len < 0)
 450                 return;
 451
 452         /* Insert the 'hole' (see big comment above) at position 3 */
 453         buffer[0] = buffer[1];
 454         buffer[1] = buffer[2];
 455         buffer[2] = buffer[3];
 456         buffer[3] = 0;
 457         len++;
 458
 459         intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 460 }
 461
 462 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 463                                          const struct intel_crtc_state *crtc_state)
 464 {
 465         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 466         const struct drm_display_mode *adjusted_mode =
 467                 &crtc_state->base.adjusted_mode;
 468         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 469         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
 470         union hdmi_infoframe frame;
 471         int ret;
 472
 473         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 474                                                        adjusted_mode,
 475                                                        is_hdmi2_sink);
 476         if (ret < 0) {
 477                 DRM_ERROR("couldn't fill AVI infoframe\n");
 478                 return;
 479         }
 480
 481         if (crtc_state->ycbcr420)
 482                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 483         else
 484                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 485
 486         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 487                                            crtc_state->limited_color_range ?
 488                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 489                                            HDMI_QUANTIZATION_RANGE_FULL,
 490                                            intel_hdmi->rgb_quant_range_selectable);
 491
 492         /* TODO: handle pixel repetition for YCBCR420 outputs */
 493         intel_write_infoframe(encoder, crtc_state, &frame);
 494 }
 495
 496 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 497                                          const struct intel_crtc_state *crtc_state)
 498 {
 499         union hdmi_infoframe frame;
 500         int ret;
 501
 502         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 503         if (ret < 0) {
 504                 DRM_ERROR("couldn't fill SPD infoframe\n");
 505                 return;
 506         }
 507
 508         frame.spd.sdi = HDMI_SPD_SDI_PC;
 509
 510         intel_write_infoframe(encoder, crtc_state, &frame);
 511 }
 512
 513 static void
 514 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 515                               const struct intel_crtc_state *crtc_state,
 516                               const struct drm_connector_state *conn_state)
 517 {
 518         union hdmi_infoframe frame;
 519         int ret;
 520
 521         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 522                                                           conn_state->connector,
 523                                                           &crtc_state->base.adjusted_mode);
 524         if (ret < 0)
 525                 return;
 526
 527         intel_write_infoframe(encoder, crtc_state, &frame);
 528 }
 529
 530 static void g4x_set_infoframes(struct drm_encoder *encoder,
 531                                bool enable,
 532                                const struct intel_crtc_state *crtc_state,
 533                                const struct drm_connector_state *conn_state)
 534 {
 535         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 536         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 537         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 538         i915_reg_t reg = VIDEO_DIP_CTL;
 539         u32 val = I915_READ(reg);
 540         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 541
 542         assert_hdmi_port_disabled(intel_hdmi);
 543
 544         /* If the registers were not initialized yet, they might be zeroes,
 545          * which means we're selecting the AVI DIP and we're setting its
 546          * frequency to once. This seems to really confuse the HW and make
 547          * things stop working (the register spec says the AVI always needs to
 548          * be sent every VSync). So here we avoid writing to the register more
 549          * than we need and also explicitly select the AVI DIP and explicitly
 550          * set its frequency to every VSync. Avoiding to write it twice seems to
 551          * be enough to solve the problem, but being defensive shouldn't hurt us
 552          * either. */
 553         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 554
 555         if (!enable) {
 556                 if (!(val & VIDEO_DIP_ENABLE))
 557                         return;
 558                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 559                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 560                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 561                         return;
 562                 }
 563                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 564                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 565                 I915_WRITE(reg, val);
 566                 POSTING_READ(reg);
 567                 return;
 568         }
 569
 570         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 571                 if (val & VIDEO_DIP_ENABLE) {
 572                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 573                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 574                         return;
 575                 }
 576                 val &= ~VIDEO_DIP_PORT_MASK;
 577                 val |= port;
 578         }
 579
 580         val |= VIDEO_DIP_ENABLE;
 581         val &= ~(VIDEO_DIP_ENABLE_AVI |
 582                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 583
 584         I915_WRITE(reg, val);
 585         POSTING_READ(reg);
 586
 587         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 588         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 589         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 590 }
 591
 592 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 593 {
 594         struct drm_connector *connector = conn_state->connector;
 595
 596         /*
 597          * HDMI cloning is only supported on g4x which doesn't
 598          * support deep color or GCP infoframes anyway so no
 599          * need to worry about multiple HDMI sinks here.
 600          */
 601
 602         return connector->display_info.bpc > 8;
 603 }
 604
 605 /*
 606  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 607  *
 608  * From HDMI specification 1.4a:
 609  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 610  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 611  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 612  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 613  *   phase of 0
 614  */
 615 static bool gcp_default_phase_possible(int pipe_bpp,
 616                                        const struct drm_display_mode *mode)
 617 {
 618         unsigned int pixels_per_group;
 619
 620         switch (pipe_bpp) {
 621         case 30:
 622                 /* 4 pixels in 5 clocks */
 623                 pixels_per_group = 4;
 624                 break;
 625         case 36:
 626                 /* 2 pixels in 3 clocks */
 627                 pixels_per_group = 2;
 628                 break;
 629         case 48:
 630                 /* 1 pixel in 2 clocks */
 631                 pixels_per_group = 1;
 632                 break;
 633         default:
 634                 /* phase information not relevant for 8bpc */
 635                 return false;
 636         }
 637
 638         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 639                 mode->crtc_htotal % pixels_per_group == 0 &&
 640                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 641                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 642                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 643                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 644                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 645                  mode->crtc_htotal/2 % pixels_per_group == 0);
 646 }
 647
 648 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 649                                          const struct intel_crtc_state *crtc_state,
 650                                          const struct drm_connector_state *conn_state)
 651 {
 652         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 653         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 654         i915_reg_t reg;
 655         u32 val = 0;
 656
 657         if (HAS_DDI(dev_priv))
 658                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 659         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 660                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 661         else if (HAS_PCH_SPLIT(dev_priv))
 662                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 663         else
 664                 return false;
 665
 666         /* Indicate color depth whenever the sink supports deep color */
 667         if (hdmi_sink_is_deep_color(conn_state))
 668                 val |= GCP_COLOR_INDICATION;
 669
 670         /* Enable default_phase whenever the display mode is suitably aligned */
 671         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 672                                        &crtc_state->base.adjusted_mode))
 673                 val |= GCP_DEFAULT_PHASE_ENABLE;
 674
 675         I915_WRITE(reg, val);
 676
 677         return val != 0;
 678 }
 679
 680 static void ibx_set_infoframes(struct drm_encoder *encoder,
 681                                bool enable,
 682                                const struct intel_crtc_state *crtc_state,
 683                                const struct drm_connector_state *conn_state)
 684 {
 685         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 687         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 688         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 689         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 690         u32 val = I915_READ(reg);
 691         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 692
 693         assert_hdmi_port_disabled(intel_hdmi);
 694
 695         /* See the big comment in g4x_set_infoframes() */
 696         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 697
 698         if (!enable) {
 699                 if (!(val & VIDEO_DIP_ENABLE))
 700                         return;
 701                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 702                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 703                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 704                 I915_WRITE(reg, val);
 705                 POSTING_READ(reg);
 706                 return;
 707         }
 708
 709         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 710                 WARN(val & VIDEO_DIP_ENABLE,
 711                      "DIP already enabled on port %c\n",
 712                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 713                 val &= ~VIDEO_DIP_PORT_MASK;
 714                 val |= port;
 715         }
 716
 717         val |= VIDEO_DIP_ENABLE;
 718         val &= ~(VIDEO_DIP_ENABLE_AVI |
 719                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 720                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 721
 722         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 723                 val |= VIDEO_DIP_ENABLE_GCP;
 724
 725         I915_WRITE(reg, val);
 726         POSTING_READ(reg);
 727
 728         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 729         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 730         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 731 }
 732
 733 static void cpt_set_infoframes(struct drm_encoder *encoder,
 734                                bool enable,
 735                                const struct intel_crtc_state *crtc_state,
 736                                const struct drm_connector_state *conn_state)
 737 {
 738         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 740         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 741         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 742         u32 val = I915_READ(reg);
 743
 744         assert_hdmi_port_disabled(intel_hdmi);
 745
 746         /* See the big comment in g4x_set_infoframes() */
 747         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 748
 749         if (!enable) {
 750                 if (!(val & VIDEO_DIP_ENABLE))
 751                         return;
 752                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 753                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 754                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 755                 I915_WRITE(reg, val);
 756                 POSTING_READ(reg);
 757                 return;
 758         }
 759
 760         /* Set both together, unset both together: see the spec. */
 761         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 762         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 763                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 764
 765         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 766                 val |= VIDEO_DIP_ENABLE_GCP;
 767
 768         I915_WRITE(reg, val);
 769         POSTING_READ(reg);
 770
 771         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 772         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 773         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 774 }
 775
 776 static void vlv_set_infoframes(struct drm_encoder *encoder,
 777                                bool enable,
 778                                const struct intel_crtc_state *crtc_state,
 779                                const struct drm_connector_state *conn_state)
 780 {
 781         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 782         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 784         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 785         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 786         u32 val = I915_READ(reg);
 787         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 788
 789         assert_hdmi_port_disabled(intel_hdmi);
 790
 791         /* See the big comment in g4x_set_infoframes() */
 792         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 793
 794         if (!enable) {
 795                 if (!(val & VIDEO_DIP_ENABLE))
 796                         return;
 797                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 798                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 799                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 800                 I915_WRITE(reg, val);
 801                 POSTING_READ(reg);
 802                 return;
 803         }
 804
 805         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 806                 WARN(val & VIDEO_DIP_ENABLE,
 807                      "DIP already enabled on port %c\n",
 808                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 809                 val &= ~VIDEO_DIP_PORT_MASK;
 810                 val |= port;
 811         }
 812
 813         val |= VIDEO_DIP_ENABLE;
 814         val &= ~(VIDEO_DIP_ENABLE_AVI |
 815                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 816                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 817
 818         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 819                 val |= VIDEO_DIP_ENABLE_GCP;
 820
 821         I915_WRITE(reg, val);
 822         POSTING_READ(reg);
 823
 824         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 825         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 826         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 827 }
 828
 829 static void hsw_set_infoframes(struct drm_encoder *encoder,
 830                                bool enable,
 831                                const struct intel_crtc_state *crtc_state,
 832                                const struct drm_connector_state *conn_state)
 833 {
 834         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 835         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 836         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 837         u32 val = I915_READ(reg);
 838
 839         assert_hdmi_port_disabled(intel_hdmi);
 840
 841         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 842                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 843                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 844
 845         if (!enable) {
 846                 I915_WRITE(reg, val);
 847                 POSTING_READ(reg);
 848                 return;
 849         }
 850
 851         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 852                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 853
 854         I915_WRITE(reg, val);
 855         POSTING_READ(reg);
 856
 857         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 858         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 859         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 860 }
 861
 862 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 863 {
 864         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 865         struct i2c_adapter *adapter =
 866                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 867
 868         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 869                 return;
 870
 871         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 872                       enable ? "Enabling" : "Disabling");
 873
 874         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 875                                          adapter, enable);
 876 }
 877
 878 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 879                                const struct intel_crtc_state *crtc_state)
 880 {
 881         struct drm_device *dev = encoder->base.dev;
 882         struct drm_i915_private *dev_priv = to_i915(dev);
 883         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 884         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 885         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 886         u32 hdmi_val;
 887
 888         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 889
 890         hdmi_val = SDVO_ENCODING_HDMI;
 891         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 892                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 893         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 894                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 895         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 896                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 897
 898         if (crtc_state->pipe_bpp > 24)
 899                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 900         else
 901                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 902
 903         if (crtc_state->has_hdmi_sink)
 904                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 905
 906         if (HAS_PCH_CPT(dev_priv))
 907                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 908         else if (IS_CHERRYVIEW(dev_priv))
 909                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 910         else
 911                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 912
 913         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 914         POSTING_READ(intel_hdmi->hdmi_reg);
 915 }
 916
 917 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 918                                     enum pipe *pipe)
 919 {
 920         struct drm_device *dev = encoder->base.dev;
 921         struct drm_i915_private *dev_priv = to_i915(dev);
 922         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 923         u32 tmp;
 924         bool ret;
 925
 926         if (!intel_display_power_get_if_enabled(dev_priv,
 927                                                 encoder->power_domain))
 928                 return false;
 929
 930         ret = false;
 931
 932         tmp = I915_READ(intel_hdmi->hdmi_reg);
 933
 934         if (!(tmp & SDVO_ENABLE))
 935                 goto out;
 936
 937         if (HAS_PCH_CPT(dev_priv))
 938                 *pipe = PORT_TO_PIPE_CPT(tmp);
 939         else if (IS_CHERRYVIEW(dev_priv))
 940                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 941         else
 942                 *pipe = PORT_TO_PIPE(tmp);
 943
 944         ret = true;
 945
 946 out:
 947         intel_display_power_put(dev_priv, encoder->power_domain);
 948
 949         return ret;
 950 }
 951
 952 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 953                                   struct intel_crtc_state *pipe_config)
 954 {
 955         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 956         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
 957         struct drm_device *dev = encoder->base.dev;
 958         struct drm_i915_private *dev_priv = to_i915(dev);
 959         u32 tmp, flags = 0;
 960         int dotclock;
 961
 962         tmp = I915_READ(intel_hdmi->hdmi_reg);
 963
 964         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 965                 flags |= DRM_MODE_FLAG_PHSYNC;
 966         else
 967                 flags |= DRM_MODE_FLAG_NHSYNC;
 968
 969         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 970                 flags |= DRM_MODE_FLAG_PVSYNC;
 971         else
 972                 flags |= DRM_MODE_FLAG_NVSYNC;
 973
 974         if (tmp & HDMI_MODE_SELECT_HDMI)
 975                 pipe_config->has_hdmi_sink = true;
 976
 977         if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
 978                 pipe_config->has_infoframe = true;
 979
 980         if (tmp & SDVO_AUDIO_ENABLE)
 981                 pipe_config->has_audio = true;
 982
 983         if (!HAS_PCH_SPLIT(dev_priv) &&
 984             tmp & HDMI_COLOR_RANGE_16_235)
 985                 pipe_config->limited_color_range = true;
 986
 987         pipe_config->base.adjusted_mode.flags |= flags;
 988
 989         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 990                 dotclock = pipe_config->port_clock * 2 / 3;
 991         else
 992                 dotclock = pipe_config->port_clock;
 993
 994         if (pipe_config->pixel_multiplier)
 995                 dotclock /= pipe_config->pixel_multiplier;
 996
 997         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 998
 999         pipe_config->lane_count = 4;
1000 }
1001
1002 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1003                                     const struct intel_crtc_state *pipe_config,
1004                                     const struct drm_connector_state *conn_state)
1005 {
1006         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1007
1008         WARN_ON(!pipe_config->has_hdmi_sink);
1009         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1010                          pipe_name(crtc->pipe));
1011         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1012 }
1013
1014 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1015                             const struct intel_crtc_state *pipe_config,
1016                             const struct drm_connector_state *conn_state)
1017 {
1018         struct drm_device *dev = encoder->base.dev;
1019         struct drm_i915_private *dev_priv = to_i915(dev);
1020         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1021         u32 temp;
1022
1023         temp = I915_READ(intel_hdmi->hdmi_reg);
1024
1025         temp |= SDVO_ENABLE;
1026         if (pipe_config->has_audio)
1027                 temp |= SDVO_AUDIO_ENABLE;
1028
1029         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1030         POSTING_READ(intel_hdmi->hdmi_reg);
1031
1032         if (pipe_config->has_audio)
1033                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1034 }
1035
1036 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1037                             const struct intel_crtc_state *pipe_config,
1038                             const struct drm_connector_state *conn_state)
1039 {
1040         struct drm_device *dev = encoder->base.dev;
1041         struct drm_i915_private *dev_priv = to_i915(dev);
1042         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1043         u32 temp;
1044
1045         temp = I915_READ(intel_hdmi->hdmi_reg);
1046
1047         temp |= SDVO_ENABLE;
1048         if (pipe_config->has_audio)
1049                 temp |= SDVO_AUDIO_ENABLE;
1050
1051         /*
1052          * HW workaround, need to write this twice for issue
1053          * that may result in first write getting masked.
1054          */
1055         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1056         POSTING_READ(intel_hdmi->hdmi_reg);
1057         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1058         POSTING_READ(intel_hdmi->hdmi_reg);
1059
1060         /*
1061          * HW workaround, need to toggle enable bit off and on
1062          * for 12bpc with pixel repeat.
1063          *
1064          * FIXME: BSpec says this should be done at the end of
1065          * of the modeset sequence, so not sure if this isn't too soon.
1066          */
1067         if (pipe_config->pipe_bpp > 24 &&
1068             pipe_config->pixel_multiplier > 1) {
1069                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1070                 POSTING_READ(intel_hdmi->hdmi_reg);
1071
1072                 /*
1073                  * HW workaround, need to write this twice for issue
1074                  * that may result in first write getting masked.
1075                  */
1076                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077                 POSTING_READ(intel_hdmi->hdmi_reg);
1078                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1079                 POSTING_READ(intel_hdmi->hdmi_reg);
1080         }
1081
1082         if (pipe_config->has_audio)
1083                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1084 }
1085
1086 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1087                             const struct intel_crtc_state *pipe_config,
1088                             const struct drm_connector_state *conn_state)
1089 {
1090         struct drm_device *dev = encoder->base.dev;
1091         struct drm_i915_private *dev_priv = to_i915(dev);
1092         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1093         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1094         enum pipe pipe = crtc->pipe;
1095         u32 temp;
1096
1097         temp = I915_READ(intel_hdmi->hdmi_reg);
1098
1099         temp |= SDVO_ENABLE;
1100         if (pipe_config->has_audio)
1101                 temp |= SDVO_AUDIO_ENABLE;
1102
1103         /*
1104          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1105          *
1106          * The procedure for 12bpc is as follows:
1107          * 1. disable HDMI clock gating
1108          * 2. enable HDMI with 8bpc
1109          * 3. enable HDMI with 12bpc
1110          * 4. enable HDMI clock gating
1111          */
1112
1113         if (pipe_config->pipe_bpp > 24) {
1114                 I915_WRITE(TRANS_CHICKEN1(pipe),
1115                            I915_READ(TRANS_CHICKEN1(pipe)) |
1116                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1117
1118                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1119                 temp |= SDVO_COLOR_FORMAT_8bpc;
1120         }
1121
1122         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1123         POSTING_READ(intel_hdmi->hdmi_reg);
1124
1125         if (pipe_config->pipe_bpp > 24) {
1126                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1127                 temp |= HDMI_COLOR_FORMAT_12bpc;
1128
1129                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1130                 POSTING_READ(intel_hdmi->hdmi_reg);
1131
1132                 I915_WRITE(TRANS_CHICKEN1(pipe),
1133                            I915_READ(TRANS_CHICKEN1(pipe)) &
1134                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1135         }
1136
1137         if (pipe_config->has_audio)
1138                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1139 }
1140
1141 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1142                             const struct intel_crtc_state *pipe_config,
1143                             const struct drm_connector_state *conn_state)
1144 {
1145 }
1146
1147 static void intel_disable_hdmi(struct intel_encoder *encoder,
1148                                const struct intel_crtc_state *old_crtc_state,
1149                                const struct drm_connector_state *old_conn_state)
1150 {
1151         struct drm_device *dev = encoder->base.dev;
1152         struct drm_i915_private *dev_priv = to_i915(dev);
1153         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1154         struct intel_digital_port *intel_dig_port =
1155                 hdmi_to_dig_port(intel_hdmi);
1156         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1157         u32 temp;
1158
1159         temp = I915_READ(intel_hdmi->hdmi_reg);
1160
1161         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1162         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1163         POSTING_READ(intel_hdmi->hdmi_reg);
1164
1165         /*
1166          * HW workaround for IBX, we need to move the port
1167          * to transcoder A after disabling it to allow the
1168          * matching DP port to be enabled on transcoder A.
1169          */
1170         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1171                 /*
1172                  * We get CPU/PCH FIFO underruns on the other pipe when
1173                  * doing the workaround. Sweep them under the rug.
1174                  */
1175                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1176                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1177
1178                 temp &= ~SDVO_PIPE_B_SELECT;
1179                 temp |= SDVO_ENABLE;
1180                 /*
1181                  * HW workaround, need to write this twice for issue
1182                  * that may result in first write getting masked.
1183                  */
1184                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1185                 POSTING_READ(intel_hdmi->hdmi_reg);
1186                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1187                 POSTING_READ(intel_hdmi->hdmi_reg);
1188
1189                 temp &= ~SDVO_ENABLE;
1190                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1191                 POSTING_READ(intel_hdmi->hdmi_reg);
1192
1193                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1194                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1195                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1196         }
1197
1198         intel_dig_port->set_infoframes(&encoder->base, false,
1199                                        old_crtc_state, old_conn_state);
1200
1201         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1202 }
1203
1204 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1205                              const struct intel_crtc_state *old_crtc_state,
1206                              const struct drm_connector_state *old_conn_state)
1207 {
1208         if (old_crtc_state->has_audio)
1209                 intel_audio_codec_disable(encoder);
1210
1211         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1212 }
1213
1214 static void pch_disable_hdmi(struct intel_encoder *encoder,
1215                              const struct intel_crtc_state *old_crtc_state,
1216                              const struct drm_connector_state *old_conn_state)
1217 {
1218         if (old_crtc_state->has_audio)
1219                 intel_audio_codec_disable(encoder);
1220 }
1221
1222 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1223                                   const struct intel_crtc_state *old_crtc_state,
1224                                   const struct drm_connector_state *old_conn_state)
1225 {
1226         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1227 }
1228
1229 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1230 {
1231         if (IS_G4X(dev_priv))
1232                 return 165000;
1233         else if (IS_GEMINILAKE(dev_priv))
1234                 return 594000;
1235         else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1236                 return 300000;
1237         else
1238                 return 225000;
1239 }
1240
1241 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1242                                  bool respect_downstream_limits,
1243                                  bool force_dvi)
1244 {
1245         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1246         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1247
1248         if (respect_downstream_limits) {
1249                 struct intel_connector *connector = hdmi->attached_connector;
1250                 const struct drm_display_info *info = &connector->base.display_info;
1251
1252                 if (hdmi->dp_dual_mode.max_tmds_clock)
1253                         max_tmds_clock = min(max_tmds_clock,
1254                                              hdmi->dp_dual_mode.max_tmds_clock);
1255
1256                 if (info->max_tmds_clock)
1257                         max_tmds_clock = min(max_tmds_clock,
1258                                              info->max_tmds_clock);
1259                 else if (!hdmi->has_hdmi_sink || force_dvi)
1260                         max_tmds_clock = min(max_tmds_clock, 165000);
1261         }
1262
1263         return max_tmds_clock;
1264 }
1265
1266 static enum drm_mode_status
1267 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1268                       int clock, bool respect_downstream_limits,
1269                       bool force_dvi)
1270 {
1271         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1272
1273         if (clock < 25000)
1274                 return MODE_CLOCK_LOW;
1275         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1276                 return MODE_CLOCK_HIGH;
1277
1278         /* BXT DPLL can't generate 223-240 MHz */
1279         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1280                 return MODE_CLOCK_RANGE;
1281
1282         /* CHV DPLL can't generate 216-240 MHz */
1283         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1284                 return MODE_CLOCK_RANGE;
1285
1286         return MODE_OK;
1287 }
1288
1289 static enum drm_mode_status
1290 intel_hdmi_mode_valid(struct drm_connector *connector,
1291                       struct drm_display_mode *mode)
1292 {
1293         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1294         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1295         struct drm_i915_private *dev_priv = to_i915(dev);
1296         enum drm_mode_status status;
1297         int clock;
1298         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1299         bool force_dvi =
1300                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1301
1302         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1303                 return MODE_NO_DBLESCAN;
1304
1305         clock = mode->clock;
1306
1307         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1308                 clock *= 2;
1309
1310         if (clock > max_dotclk)
1311                 return MODE_CLOCK_HIGH;
1312
1313         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1314                 clock *= 2;
1315
1316         if (drm_mode_is_420_only(&connector->display_info, mode))
1317                 clock /= 2;
1318
1319         /* check if we can do 8bpc */
1320         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1321
1322         /* if we can't do 8bpc we may still be able to do 12bpc */
1323         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1324                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1325
1326         return status;
1327 }
1328
1329 static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
1330 {
1331         struct drm_i915_private *dev_priv =
1332                 to_i915(crtc_state->base.crtc->dev);
1333         struct drm_atomic_state *state = crtc_state->base.state;
1334         struct drm_connector_state *connector_state;
1335         struct drm_connector *connector;
1336         int i;
1337
1338         if (HAS_GMCH_DISPLAY(dev_priv))
1339                 return false;
1340
1341         /*
1342          * HDMI 12bpc affects the clocks, so it's only possible
1343          * when not cloning with other encoder types.
1344          */
1345         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1346                 return false;
1347
1348         for_each_new_connector_in_state(state, connector, connector_state, i) {
1349                 const struct drm_display_info *info = &connector->display_info;
1350
1351                 if (connector_state->crtc != crtc_state->base.crtc)
1352                         continue;
1353
1354                 if (crtc_state->ycbcr420) {
1355                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1356
1357                         if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1358                                 return false;
1359                 } else {
1360                         if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1361                                 return false;
1362                 }
1363         }
1364
1365         /* Display Wa #1139 */
1366         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1367             crtc_state->base.adjusted_mode.htotal > 5460)
1368                 return false;
1369
1370         return true;
1371 }
1372
1373 static bool
1374 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1375                            struct intel_crtc_state *config,
1376                            int *clock_12bpc, int *clock_8bpc)
1377 {
1378         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1379
1380         if (!connector->ycbcr_420_allowed) {
1381                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1382                 return false;
1383         }
1384
1385         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1386         config->port_clock /= 2;
1387         *clock_12bpc /= 2;
1388         *clock_8bpc /= 2;
1389         config->ycbcr420 = true;
1390
1391         /* YCBCR 420 output conversion needs a scaler */
1392         if (skl_update_scaler_crtc(config)) {
1393                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1394                 return false;
1395         }
1396
1397         intel_pch_panel_fitting(intel_crtc, config,
1398                                 DRM_MODE_SCALE_FULLSCREEN);
1399
1400         return true;
1401 }
1402
1403 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1404                                struct intel_crtc_state *pipe_config,
1405                                struct drm_connector_state *conn_state)
1406 {
1407         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1408         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1409         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1410         struct drm_connector *connector = conn_state->connector;
1411         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1412         struct intel_digital_connector_state *intel_conn_state =
1413                 to_intel_digital_connector_state(conn_state);
1414         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1415         int clock_12bpc = clock_8bpc * 3 / 2;
1416         int desired_bpp;
1417         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1418
1419         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1420
1421         if (pipe_config->has_hdmi_sink)
1422                 pipe_config->has_infoframe = true;
1423
1424         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1425                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1426                 pipe_config->limited_color_range =
1427                         pipe_config->has_hdmi_sink &&
1428                         drm_default_rgb_quant_range(adjusted_mode) ==
1429                         HDMI_QUANTIZATION_RANGE_LIMITED;
1430         } else {
1431                 pipe_config->limited_color_range =
1432                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1433         }
1434
1435         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1436                 pipe_config->pixel_multiplier = 2;
1437                 clock_8bpc *= 2;
1438                 clock_12bpc *= 2;
1439         }
1440
1441         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1442                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1443                                                 &clock_12bpc, &clock_8bpc)) {
1444                         DRM_ERROR("Can't support YCBCR420 output\n");
1445                         return false;
1446                 }
1447         }
1448
1449         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1450                 pipe_config->has_pch_encoder = true;
1451
1452         if (pipe_config->has_hdmi_sink) {
1453                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1454                         pipe_config->has_audio = intel_hdmi->has_audio;
1455                 else
1456                         pipe_config->has_audio =
1457                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1458         }
1459
1460         /*
1461          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1462          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1463          * outputs. We also need to check that the higher clock still fits
1464          * within limits.
1465          */
1466         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi &&
1467             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK &&
1468             hdmi_12bpc_possible(pipe_config)) {
1469                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1470                 desired_bpp = 12*3;
1471
1472                 /* Need to adjust the port link by 1.5x for 12bpc. */
1473                 pipe_config->port_clock = clock_12bpc;
1474         } else {
1475                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1476                 desired_bpp = 8*3;
1477
1478                 pipe_config->port_clock = clock_8bpc;
1479         }
1480
1481         if (!pipe_config->bw_constrained) {
1482                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1483                 pipe_config->pipe_bpp = desired_bpp;
1484         }
1485
1486         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1487                                   false, force_dvi) != MODE_OK) {
1488                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1489                 return false;
1490         }
1491
1492         /* Set user selected PAR to incoming mode's member */
1493         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1494
1495         pipe_config->lane_count = 4;
1496
1497         if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1498                 if (scdc->scrambling.low_rates)
1499                         pipe_config->hdmi_scrambling = true;
1500
1501                 if (pipe_config->port_clock > 340000) {
1502                         pipe_config->hdmi_scrambling = true;
1503                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1504                 }
1505         }
1506
1507         return true;
1508 }
1509
1510 static void
1511 intel_hdmi_unset_edid(struct drm_connector *connector)
1512 {
1513         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1514
1515         intel_hdmi->has_hdmi_sink = false;
1516         intel_hdmi->has_audio = false;
1517         intel_hdmi->rgb_quant_range_selectable = false;
1518
1519         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1520         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1521
1522         kfree(to_intel_connector(connector)->detect_edid);
1523         to_intel_connector(connector)->detect_edid = NULL;
1524 }
1525
1526 static void
1527 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1528 {
1529         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1530         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1531         enum port port = hdmi_to_dig_port(hdmi)->port;
1532         struct i2c_adapter *adapter =
1533                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1534         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1535
1536         /*
1537          * Type 1 DVI adaptors are not required to implement any
1538          * registers, so we can't always detect their presence.
1539          * Ideally we should be able to check the state of the
1540          * CONFIG1 pin, but no such luck on our hardware.
1541          *
1542          * The only method left to us is to check the VBT to see
1543          * if the port is a dual mode capable DP port. But let's
1544          * only do that when we sucesfully read the EDID, to avoid
1545          * confusing log messages about DP dual mode adaptors when
1546          * there's nothing connected to the port.
1547          */
1548         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1549                 if (has_edid &&
1550                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1551                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1552                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1553                 } else {
1554                         type = DRM_DP_DUAL_MODE_NONE;
1555                 }
1556         }
1557
1558         if (type == DRM_DP_DUAL_MODE_NONE)
1559                 return;
1560
1561         hdmi->dp_dual_mode.type = type;
1562         hdmi->dp_dual_mode.max_tmds_clock =
1563                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1564
1565         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1566                       drm_dp_get_dual_mode_type_name(type),
1567                       hdmi->dp_dual_mode.max_tmds_clock);
1568 }
1569
1570 static bool
1571 intel_hdmi_set_edid(struct drm_connector *connector)
1572 {
1573         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1574         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1575         struct edid *edid;
1576         bool connected = false;
1577
1578         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1579
1580         edid = drm_get_edid(connector,
1581                             intel_gmbus_get_adapter(dev_priv,
1582                             intel_hdmi->ddc_bus));
1583
1584         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1585
1586         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1587
1588         to_intel_connector(connector)->detect_edid = edid;
1589         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1590                 intel_hdmi->rgb_quant_range_selectable =
1591                         drm_rgb_quant_range_selectable(edid);
1592
1593                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1594                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1595
1596                 connected = true;
1597         }
1598
1599         return connected;
1600 }
1601
1602 static enum drm_connector_status
1603 intel_hdmi_detect(struct drm_connector *connector, bool force)
1604 {
1605         enum drm_connector_status status;
1606         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1607
1608         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1609                       connector->base.id, connector->name);
1610
1611         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1612
1613         intel_hdmi_unset_edid(connector);
1614
1615         if (intel_hdmi_set_edid(connector)) {
1616                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1617
1618                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1619                 status = connector_status_connected;
1620         } else
1621                 status = connector_status_disconnected;
1622
1623         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1624
1625         return status;
1626 }
1627
1628 static void
1629 intel_hdmi_force(struct drm_connector *connector)
1630 {
1631         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1632
1633         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1634                       connector->base.id, connector->name);
1635
1636         intel_hdmi_unset_edid(connector);
1637
1638         if (connector->status != connector_status_connected)
1639                 return;
1640
1641         intel_hdmi_set_edid(connector);
1642         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1643 }
1644
1645 static int intel_hdmi_get_modes(struct drm_connector *connector)
1646 {
1647         struct edid *edid;
1648
1649         edid = to_intel_connector(connector)->detect_edid;
1650         if (edid == NULL)
1651                 return 0;
1652
1653         return intel_connector_update_modes(connector, edid);
1654 }
1655
1656 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1657                                   const struct intel_crtc_state *pipe_config,
1658                                   const struct drm_connector_state *conn_state)
1659 {
1660         struct intel_digital_port *intel_dig_port =
1661                 enc_to_dig_port(&encoder->base);
1662
1663         intel_hdmi_prepare(encoder, pipe_config);
1664
1665         intel_dig_port->set_infoframes(&encoder->base,
1666                                        pipe_config->has_infoframe,
1667                                        pipe_config, conn_state);
1668 }
1669
1670 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1671                                 const struct intel_crtc_state *pipe_config,
1672                                 const struct drm_connector_state *conn_state)
1673 {
1674         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1675         struct drm_device *dev = encoder->base.dev;
1676         struct drm_i915_private *dev_priv = to_i915(dev);
1677
1678         vlv_phy_pre_encoder_enable(encoder);
1679
1680         /* HDMI 1.0V-2dB */
1681         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1682                                  0x2b247878);
1683
1684         dport->set_infoframes(&encoder->base,
1685                               pipe_config->has_infoframe,
1686                               pipe_config, conn_state);
1687
1688         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1689
1690         vlv_wait_port_ready(dev_priv, dport, 0x0);
1691 }
1692
1693 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1694                                     const struct intel_crtc_state *pipe_config,
1695                                     const struct drm_connector_state *conn_state)
1696 {
1697         intel_hdmi_prepare(encoder, pipe_config);
1698
1699         vlv_phy_pre_pll_enable(encoder);
1700 }
1701
1702 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1703                                     const struct intel_crtc_state *pipe_config,
1704                                     const struct drm_connector_state *conn_state)
1705 {
1706         intel_hdmi_prepare(encoder, pipe_config);
1707
1708         chv_phy_pre_pll_enable(encoder);
1709 }
1710
1711 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1712                                       const struct intel_crtc_state *old_crtc_state,
1713                                       const struct drm_connector_state *old_conn_state)
1714 {
1715         chv_phy_post_pll_disable(encoder);
1716 }
1717
1718 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1719                                   const struct intel_crtc_state *old_crtc_state,
1720                                   const struct drm_connector_state *old_conn_state)
1721 {
1722         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1723         vlv_phy_reset_lanes(encoder);
1724 }
1725
1726 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1727                                   const struct intel_crtc_state *old_crtc_state,
1728                                   const struct drm_connector_state *old_conn_state)
1729 {
1730         struct drm_device *dev = encoder->base.dev;
1731         struct drm_i915_private *dev_priv = to_i915(dev);
1732
1733         mutex_lock(&dev_priv->sb_lock);
1734
1735         /* Assert data lane reset */
1736         chv_data_lane_soft_reset(encoder, true);
1737
1738         mutex_unlock(&dev_priv->sb_lock);
1739 }
1740
1741 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1742                                 const struct intel_crtc_state *pipe_config,
1743                                 const struct drm_connector_state *conn_state)
1744 {
1745         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1746         struct drm_device *dev = encoder->base.dev;
1747         struct drm_i915_private *dev_priv = to_i915(dev);
1748
1749         chv_phy_pre_encoder_enable(encoder);
1750
1751         /* FIXME: Program the support xxx V-dB */
1752         /* Use 800mV-0dB */
1753         chv_set_phy_signal_level(encoder, 128, 102, false);
1754
1755         dport->set_infoframes(&encoder->base,
1756                               pipe_config->has_infoframe,
1757                               pipe_config, conn_state);
1758
1759         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1760
1761         vlv_wait_port_ready(dev_priv, dport, 0x0);
1762
1763         /* Second common lane will stay alive on its own now */
1764         chv_phy_release_cl2_override(encoder);
1765 }
1766
1767 static void intel_hdmi_destroy(struct drm_connector *connector)
1768 {
1769         kfree(to_intel_connector(connector)->detect_edid);
1770         drm_connector_cleanup(connector);
1771         kfree(connector);
1772 }
1773
1774 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1775         .detect = intel_hdmi_detect,
1776         .force = intel_hdmi_force,
1777         .fill_modes = drm_helper_probe_single_connector_modes,
1778         .atomic_get_property = intel_digital_connector_atomic_get_property,
1779         .atomic_set_property = intel_digital_connector_atomic_set_property,
1780         .late_register = intel_connector_register,
1781         .early_unregister = intel_connector_unregister,
1782         .destroy = intel_hdmi_destroy,
1783         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1784         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1785 };
1786
1787 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1788         .get_modes = intel_hdmi_get_modes,
1789         .mode_valid = intel_hdmi_mode_valid,
1790         .atomic_check = intel_digital_connector_atomic_check,
1791 };
1792
1793 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1794         .destroy = intel_encoder_destroy,
1795 };
1796
1797 static void
1798 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1799 {
1800         intel_attach_force_audio_property(connector);
1801         intel_attach_broadcast_rgb_property(connector);
1802         intel_attach_aspect_ratio_property(connector);
1803         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1804 }
1805
1806 /*
1807  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1808  * @encoder: intel_encoder
1809  * @connector: drm_connector
1810  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1811  *  or reset the high tmds clock ratio for scrambling
1812  * @scrambling: bool to Indicate if the function needs to set or reset
1813  *  sink scrambling
1814  *
1815  * This function handles scrambling on HDMI 2.0 capable sinks.
1816  * If required clock rate is > 340 Mhz && scrambling is supported by sink
1817  * it enables scrambling. This should be called before enabling the HDMI
1818  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1819  * detect a scrambled clock within 100 ms.
1820  */
1821 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1822                                        struct drm_connector *connector,
1823                                        bool high_tmds_clock_ratio,
1824                                        bool scrambling)
1825 {
1826         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1827         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1828         struct drm_scrambling *sink_scrambling =
1829                                 &connector->display_info.hdmi.scdc.scrambling;
1830         struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1831                                                            intel_hdmi->ddc_bus);
1832         bool ret;
1833
1834         if (!sink_scrambling->supported)
1835                 return;
1836
1837         DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1838                       encoder->base.name, connector->name);
1839
1840         /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1841         ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1842         if (!ret) {
1843                 DRM_ERROR("Set TMDS ratio failed\n");
1844                 return;
1845         }
1846
1847         /* Enable/disable sink scrambling */
1848         ret = drm_scdc_set_scrambling(adptr, scrambling);
1849         if (!ret) {
1850                 DRM_ERROR("Set sink scrambling failed\n");
1851                 return;
1852         }
1853
1854         DRM_DEBUG_KMS("sink scrambling handled\n");
1855 }
1856
1857 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1858 {
1859         u8 ddc_pin;
1860
1861         switch (port) {
1862         case PORT_B:
1863                 ddc_pin = GMBUS_PIN_DPB;
1864                 break;
1865         case PORT_C:
1866                 ddc_pin = GMBUS_PIN_DPC;
1867                 break;
1868         case PORT_D:
1869                 ddc_pin = GMBUS_PIN_DPD_CHV;
1870                 break;
1871         default:
1872                 MISSING_CASE(port);
1873                 ddc_pin = GMBUS_PIN_DPB;
1874                 break;
1875         }
1876         return ddc_pin;
1877 }
1878
1879 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1880 {
1881         u8 ddc_pin;
1882
1883         switch (port) {
1884         case PORT_B:
1885                 ddc_pin = GMBUS_PIN_1_BXT;
1886                 break;
1887         case PORT_C:
1888                 ddc_pin = GMBUS_PIN_2_BXT;
1889                 break;
1890         default:
1891                 MISSING_CASE(port);
1892                 ddc_pin = GMBUS_PIN_1_BXT;
1893                 break;
1894         }
1895         return ddc_pin;
1896 }
1897
1898 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1899                               enum port port)
1900 {
1901         u8 ddc_pin;
1902
1903         switch (port) {
1904         case PORT_B:
1905                 ddc_pin = GMBUS_PIN_1_BXT;
1906                 break;
1907         case PORT_C:
1908                 ddc_pin = GMBUS_PIN_2_BXT;
1909                 break;
1910         case PORT_D:
1911                 ddc_pin = GMBUS_PIN_4_CNP;
1912                 break;
1913         default:
1914                 MISSING_CASE(port);
1915                 ddc_pin = GMBUS_PIN_1_BXT;
1916                 break;
1917         }
1918         return ddc_pin;
1919 }
1920
1921 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1922                               enum port port)
1923 {
1924         u8 ddc_pin;
1925
1926         switch (port) {
1927         case PORT_B:
1928                 ddc_pin = GMBUS_PIN_DPB;
1929                 break;
1930         case PORT_C:
1931                 ddc_pin = GMBUS_PIN_DPC;
1932                 break;
1933         case PORT_D:
1934                 ddc_pin = GMBUS_PIN_DPD;
1935                 break;
1936         default:
1937                 MISSING_CASE(port);
1938                 ddc_pin = GMBUS_PIN_DPB;
1939                 break;
1940         }
1941         return ddc_pin;
1942 }
1943
1944 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1945                              enum port port)
1946 {
1947         const struct ddi_vbt_port_info *info =
1948                 &dev_priv->vbt.ddi_port_info[port];
1949         u8 ddc_pin;
1950
1951         if (info->alternate_ddc_pin) {
1952                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1953                               info->alternate_ddc_pin, port_name(port));
1954                 return info->alternate_ddc_pin;
1955         }
1956
1957         if (IS_CHERRYVIEW(dev_priv))
1958                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
1959         else if (IS_GEN9_LP(dev_priv))
1960                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
1961         else if (HAS_PCH_CNP(dev_priv))
1962                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
1963         else
1964                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
1965
1966         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1967                       ddc_pin, port_name(port));
1968
1969         return ddc_pin;
1970 }
1971
1972 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
1973 {
1974         struct drm_i915_private *dev_priv =
1975                 to_i915(intel_dig_port->base.base.dev);
1976
1977         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1978                 intel_dig_port->write_infoframe = vlv_write_infoframe;
1979                 intel_dig_port->set_infoframes = vlv_set_infoframes;
1980                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
1981         } else if (IS_G4X(dev_priv)) {
1982                 intel_dig_port->write_infoframe = g4x_write_infoframe;
1983                 intel_dig_port->set_infoframes = g4x_set_infoframes;
1984                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
1985         } else if (HAS_DDI(dev_priv)) {
1986                 intel_dig_port->write_infoframe = hsw_write_infoframe;
1987                 intel_dig_port->set_infoframes = hsw_set_infoframes;
1988                 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
1989         } else if (HAS_PCH_IBX(dev_priv)) {
1990                 intel_dig_port->write_infoframe = ibx_write_infoframe;
1991                 intel_dig_port->set_infoframes = ibx_set_infoframes;
1992                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
1993         } else {
1994                 intel_dig_port->write_infoframe = cpt_write_infoframe;
1995                 intel_dig_port->set_infoframes = cpt_set_infoframes;
1996                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
1997         }
1998 }
1999
2000 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2001                                struct intel_connector *intel_connector)
2002 {
2003         struct drm_connector *connector = &intel_connector->base;
2004         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2005         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2006         struct drm_device *dev = intel_encoder->base.dev;
2007         struct drm_i915_private *dev_priv = to_i915(dev);
2008         enum port port = intel_dig_port->port;
2009
2010         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2011                       port_name(port));
2012
2013         if (WARN(intel_dig_port->max_lanes < 4,
2014                  "Not enough lanes (%d) for HDMI on port %c\n",
2015                  intel_dig_port->max_lanes, port_name(port)))
2016                 return;
2017
2018         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2019                            DRM_MODE_CONNECTOR_HDMIA);
2020         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2021
2022         connector->interlace_allowed = 1;
2023         connector->doublescan_allowed = 0;
2024         connector->stereo_allowed = 1;
2025
2026         if (IS_GEMINILAKE(dev_priv))
2027                 connector->ycbcr_420_allowed = true;
2028
2029         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2030
2031         if (WARN_ON(port == PORT_A))
2032                 return;
2033         intel_encoder->hpd_pin = intel_hpd_pin(port);
2034
2035         if (HAS_DDI(dev_priv))
2036                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2037         else
2038                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2039
2040         intel_hdmi_add_properties(intel_hdmi, connector);
2041
2042         intel_connector_attach_encoder(intel_connector, intel_encoder);
2043         intel_hdmi->attached_connector = intel_connector;
2044
2045         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2046          * 0xd.  Failure to do so will result in spurious interrupts being
2047          * generated on the port when a cable is not attached.
2048          */
2049         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2050                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2051                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2052         }
2053 }
2054
2055 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2056                      i915_reg_t hdmi_reg, enum port port)
2057 {
2058         struct intel_digital_port *intel_dig_port;
2059         struct intel_encoder *intel_encoder;
2060         struct intel_connector *intel_connector;
2061
2062         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2063         if (!intel_dig_port)
2064                 return;
2065
2066         intel_connector = intel_connector_alloc();
2067         if (!intel_connector) {
2068                 kfree(intel_dig_port);
2069                 return;
2070         }
2071
2072         intel_encoder = &intel_dig_port->base;
2073
2074         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2075                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2076                          "HDMI %c", port_name(port));
2077
2078         intel_encoder->compute_config = intel_hdmi_compute_config;
2079         if (HAS_PCH_SPLIT(dev_priv)) {
2080                 intel_encoder->disable = pch_disable_hdmi;
2081                 intel_encoder->post_disable = pch_post_disable_hdmi;
2082         } else {
2083                 intel_encoder->disable = g4x_disable_hdmi;
2084         }
2085         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2086         intel_encoder->get_config = intel_hdmi_get_config;
2087         if (IS_CHERRYVIEW(dev_priv)) {
2088                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2089                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2090                 intel_encoder->enable = vlv_enable_hdmi;
2091                 intel_encoder->post_disable = chv_hdmi_post_disable;
2092                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2093         } else if (IS_VALLEYVIEW(dev_priv)) {
2094                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2095                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2096                 intel_encoder->enable = vlv_enable_hdmi;
2097                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2098         } else {
2099                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2100                 if (HAS_PCH_CPT(dev_priv))
2101                         intel_encoder->enable = cpt_enable_hdmi;
2102                 else if (HAS_PCH_IBX(dev_priv))
2103                         intel_encoder->enable = ibx_enable_hdmi;
2104                 else
2105                         intel_encoder->enable = g4x_enable_hdmi;
2106         }
2107
2108         intel_encoder->type = INTEL_OUTPUT_HDMI;
2109         intel_encoder->power_domain = intel_port_to_power_domain(port);
2110         intel_encoder->port = port;
2111         if (IS_CHERRYVIEW(dev_priv)) {
2112                 if (port == PORT_D)
2113                         intel_encoder->crtc_mask = 1 << 2;
2114                 else
2115                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2116         } else {
2117                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2118         }
2119         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2120         /*
2121          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2122          * to work on real hardware. And since g4x can send infoframes to
2123          * only one port anyway, nothing is lost by allowing it.
2124          */
2125         if (IS_G4X(dev_priv))
2126                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2127
2128         intel_dig_port->port = port;
2129         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2130         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2131         intel_dig_port->max_lanes = 4;
2132
2133         intel_infoframe_init(intel_dig_port);
2134
2135         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2136 }