drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191 enum {
 192         ADVANCED_CONTEXT = 0,
 193         LEGACY_CONTEXT,
 194         ADVANCED_AD_CONTEXT,
 195         LEGACY_64B_CONTEXT
 196 };
 197 #define GEN8_CTX_MODE_SHIFT 3
 198 enum {
 199         FAULT_AND_HANG = 0,
 200         FAULT_AND_HALT, /* Debug only */
 201         FAULT_AND_STREAM,
 202         FAULT_AND_CONTINUE /* Unsupported */
 203 };
 204 #define GEN8_CTX_ID_SHIFT 32
 205
 206 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 207                 struct intel_context *ctx);
 208
 209 /**
 210  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 211  * @dev: DRM device.
 212  * @enable_execlists: value of i915.enable_execlists module parameter.
 213  *
 214  * Only certain platforms support Execlists (the prerequisites being
 215  * support for Logical Ring Contexts and Aliasing PPGTT or better).
 216  *
 217  * Return: 1 if Execlists is supported and has to be enabled.
 218  */
 219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 220 {
 221         WARN_ON(i915.enable_ppgtt == -1);
 222
 223         if (INTEL_INFO(dev)->gen >= 9)
 224                 return 1;
 225
 226         if (enable_execlists == 0)
 227                 return 0;
 228
 229         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 230             i915.use_mmio_flip >= 0)
 231                 return 1;
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * intel_execlists_ctx_id() - get the Execlists Context ID
 238  * @ctx_obj: Logical Ring Context backing object.
 239  *
 240  * Do not confuse with ctx->id! Unfortunately we have a name overload
 241  * here: the old context ID we pass to userspace as a handler so that
 242  * they can refer to a context, and the new context ID we pass to the
 243  * ELSP so that the GPU can inform us of the context status via
 244  * interrupts.
 245  *
 246  * Return: 20-bits globally unique context ID.
 247  */
 248 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 249 {
 250         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 251
 252         /* LRCA is required to be 4K aligned so the more significant 20 bits
 253          * are globally unique */
 254         return lrca >> 12;
 255 }
 256
 257 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
 258                                          struct drm_i915_gem_object *ctx_obj)
 259 {
 260         struct drm_device *dev = ring->dev;
 261         uint64_t desc;
 262         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 263
 264         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 265
 266         desc = GEN8_CTX_VALID;
 267         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 268         desc |= GEN8_CTX_L3LLC_COHERENT;
 269         desc |= GEN8_CTX_PRIVILEGE;
 270         desc |= lrca;
 271         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 272
 273         /* TODO: WaDisableLiteRestore when we start using semaphore
 274          * signalling between Command Streamers */
 275         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 276
 277         /* WaEnableForceRestoreInCtxtDescForVCS:skl */
 278         if (IS_GEN9(dev) &&
 279             INTEL_REVID(dev) <= SKL_REVID_B0 &&
 280             (ring->id == BCS || ring->id == VCS ||
 281             ring->id == VECS || ring->id == VCS2))
 282                 desc |= GEN8_CTX_FORCE_RESTORE;
 283
 284         return desc;
 285 }
 286
 287 static void execlists_elsp_write(struct intel_engine_cs *ring,
 288                                  struct drm_i915_gem_object *ctx_obj0,
 289                                  struct drm_i915_gem_object *ctx_obj1)
 290 {
 291         struct drm_device *dev = ring->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         uint64_t temp = 0;
 294         uint32_t desc[4];
 295
 296         /* XXX: You must always write both descriptors in the order below. */
 297         if (ctx_obj1)
 298                 temp = execlists_ctx_descriptor(ring, ctx_obj1);
 299         else
 300                 temp = 0;
 301         desc[1] = (u32)(temp >> 32);
 302         desc[0] = (u32)temp;
 303
 304         temp = execlists_ctx_descriptor(ring, ctx_obj0);
 305         desc[3] = (u32)(temp >> 32);
 306         desc[2] = (u32)temp;
 307
 308         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 309         I915_WRITE(RING_ELSP(ring), desc[1]);
 310         I915_WRITE(RING_ELSP(ring), desc[0]);
 311         I915_WRITE(RING_ELSP(ring), desc[3]);
 312
 313         /* The context is automatically loaded after the following */
 314         I915_WRITE(RING_ELSP(ring), desc[2]);
 315
 316         /* ELSP is a wo register, so use another nearby reg for posting instead */
 317         POSTING_READ(RING_EXECLIST_STATUS(ring));
 318         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 319 }
 320
 321 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
 322                                     struct drm_i915_gem_object *ring_obj,
 323                                     u32 tail)
 324 {
 325         struct page *page;
 326         uint32_t *reg_state;
 327
 328         page = i915_gem_object_get_page(ctx_obj, 1);
 329         reg_state = kmap_atomic(page);
 330
 331         reg_state[CTX_RING_TAIL+1] = tail;
 332         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
 333
 334         kunmap_atomic(reg_state);
 335
 336         return 0;
 337 }
 338
 339 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 340                                       struct intel_context *to0, u32 tail0,
 341                                       struct intel_context *to1, u32 tail1)
 342 {
 343         struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
 344         struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
 345         struct drm_i915_gem_object *ctx_obj1 = NULL;
 346         struct intel_ringbuffer *ringbuf1 = NULL;
 347
 348         BUG_ON(!ctx_obj0);
 349         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 350         WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
 351
 352         execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
 353
 354         if (to1) {
 355                 ringbuf1 = to1->engine[ring->id].ringbuf;
 356                 ctx_obj1 = to1->engine[ring->id].state;
 357                 BUG_ON(!ctx_obj1);
 358                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 359                 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
 360
 361                 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
 362         }
 363
 364         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 365 }
 366
 367 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 368 {
 369         struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
 370         struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
 371
 372         assert_spin_locked(&ring->execlist_lock);
 373
 374         if (list_empty(&ring->execlist_queue))
 375                 return;
 376
 377         /* Try to read in pairs */
 378         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 379                                  execlist_link) {
 380                 if (!req0) {
 381                         req0 = cursor;
 382                 } else if (req0->ctx == cursor->ctx) {
 383                         /* Same ctx: ignore first request, as second request
 384                          * will update tail past first request's workload */
 385                         cursor->elsp_submitted = req0->elsp_submitted;
 386                         list_del(&req0->execlist_link);
 387                         list_add_tail(&req0->execlist_link,
 388                                 &ring->execlist_retired_req_list);
 389                         req0 = cursor;
 390                 } else {
 391                         req1 = cursor;
 392                         break;
 393                 }
 394         }
 395
 396         WARN_ON(req1 && req1->elsp_submitted);
 397
 398         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 399                                   req1 ? req1->ctx : NULL,
 400                                   req1 ? req1->tail : 0);
 401
 402         req0->elsp_submitted++;
 403         if (req1)
 404                 req1->elsp_submitted++;
 405 }
 406
 407 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 408                                            u32 request_id)
 409 {
 410         struct drm_i915_gem_request *head_req;
 411
 412         assert_spin_locked(&ring->execlist_lock);
 413
 414         head_req = list_first_entry_or_null(&ring->execlist_queue,
 415                                             struct drm_i915_gem_request,
 416                                             execlist_link);
 417
 418         if (head_req != NULL) {
 419                 struct drm_i915_gem_object *ctx_obj =
 420                                 head_req->ctx->engine[ring->id].state;
 421                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 422                         WARN(head_req->elsp_submitted == 0,
 423                              "Never submitted head request\n");
 424
 425                         if (--head_req->elsp_submitted <= 0) {
 426                                 list_del(&head_req->execlist_link);
 427                                 list_add_tail(&head_req->execlist_link,
 428                                         &ring->execlist_retired_req_list);
 429                                 return true;
 430                         }
 431                 }
 432         }
 433
 434         return false;
 435 }
 436
 437 /**
 438  * intel_lrc_irq_handler() - handle Context Switch interrupts
 439  * @ring: Engine Command Streamer to handle.
 440  *
 441  * Check the unread Context Status Buffers and manage the submission of new
 442  * contexts to the ELSP accordingly.
 443  */
 444 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 445 {
 446         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 447         u32 status_pointer;
 448         u8 read_pointer;
 449         u8 write_pointer;
 450         u32 status;
 451         u32 status_id;
 452         u32 submit_contexts = 0;
 453
 454         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 455
 456         read_pointer = ring->next_context_status_buffer;
 457         write_pointer = status_pointer & 0x07;
 458         if (read_pointer > write_pointer)
 459                 write_pointer += 6;
 460
 461         spin_lock(&ring->execlist_lock);
 462
 463         while (read_pointer < write_pointer) {
 464                 read_pointer++;
 465                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 466                                 (read_pointer % 6) * 8);
 467                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 468                                 (read_pointer % 6) * 8 + 4);
 469
 470                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 471                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 472                                 if (execlists_check_remove_request(ring, status_id))
 473                                         WARN(1, "Lite Restored request removed from queue\n");
 474                         } else
 475                                 WARN(1, "Preemption without Lite Restore\n");
 476                 }
 477
 478                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 479                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 480                         if (execlists_check_remove_request(ring, status_id))
 481                                 submit_contexts++;
 482                 }
 483         }
 484
 485         if (submit_contexts != 0)
 486                 execlists_context_unqueue(ring);
 487
 488         spin_unlock(&ring->execlist_lock);
 489
 490         WARN(submit_contexts > 2, "More than two context complete events?\n");
 491         ring->next_context_status_buffer = write_pointer % 6;
 492
 493         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 494                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 495 }
 496
 497 static int execlists_context_queue(struct intel_engine_cs *ring,
 498                                    struct intel_context *to,
 499                                    u32 tail,
 500                                    struct drm_i915_gem_request *request)
 501 {
 502         struct drm_i915_gem_request *cursor;
 503         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 504         unsigned long flags;
 505         int num_elements = 0;
 506
 507         if (to != ring->default_context)
 508                 intel_lr_context_pin(ring, to);
 509
 510         if (!request) {
 511                 /*
 512                  * If there isn't a request associated with this submission,
 513                  * create one as a temporary holder.
 514                  */
 515                 WARN(1, "execlist context submission without request");
 516                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 517                 if (request == NULL)
 518                         return -ENOMEM;
 519                 request->ring = ring;
 520                 request->ctx = to;
 521         } else {
 522                 WARN_ON(to != request->ctx);
 523         }
 524         request->tail = tail;
 525         i915_gem_request_reference(request);
 526         i915_gem_context_reference(request->ctx);
 527
 528         intel_runtime_pm_get(dev_priv);
 529
 530         spin_lock_irqsave(&ring->execlist_lock, flags);
 531
 532         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 533                 if (++num_elements > 2)
 534                         break;
 535
 536         if (num_elements > 2) {
 537                 struct drm_i915_gem_request *tail_req;
 538
 539                 tail_req = list_last_entry(&ring->execlist_queue,
 540                                            struct drm_i915_gem_request,
 541                                            execlist_link);
 542
 543                 if (to == tail_req->ctx) {
 544                         WARN(tail_req->elsp_submitted != 0,
 545                                 "More than 2 already-submitted reqs queued\n");
 546                         list_del(&tail_req->execlist_link);
 547                         list_add_tail(&tail_req->execlist_link,
 548                                 &ring->execlist_retired_req_list);
 549                 }
 550         }
 551
 552         list_add_tail(&request->execlist_link, &ring->execlist_queue);
 553         if (num_elements == 0)
 554                 execlists_context_unqueue(ring);
 555
 556         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 557
 558         return 0;
 559 }
 560
 561 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
 562                                               struct intel_context *ctx)
 563 {
 564         struct intel_engine_cs *ring = ringbuf->ring;
 565         uint32_t flush_domains;
 566         int ret;
 567
 568         flush_domains = 0;
 569         if (ring->gpu_caches_dirty)
 570                 flush_domains = I915_GEM_GPU_DOMAINS;
 571
 572         ret = ring->emit_flush(ringbuf, ctx,
 573                                I915_GEM_GPU_DOMAINS, flush_domains);
 574         if (ret)
 575                 return ret;
 576
 577         ring->gpu_caches_dirty = false;
 578         return 0;
 579 }
 580
 581 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 582                                  struct intel_context *ctx,
 583                                  struct list_head *vmas)
 584 {
 585         struct intel_engine_cs *ring = ringbuf->ring;
 586         struct i915_vma *vma;
 587         uint32_t flush_domains = 0;
 588         bool flush_chipset = false;
 589         int ret;
 590
 591         list_for_each_entry(vma, vmas, exec_list) {
 592                 struct drm_i915_gem_object *obj = vma->obj;
 593
 594                 ret = i915_gem_object_sync(obj, ring);
 595                 if (ret)
 596                         return ret;
 597
 598                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 599                         flush_chipset |= i915_gem_clflush_object(obj, false);
 600
 601                 flush_domains |= obj->base.write_domain;
 602         }
 603
 604         if (flush_domains & I915_GEM_DOMAIN_GTT)
 605                 wmb();
 606
 607         /* Unconditionally invalidate gpu caches and ensure that we do flush
 608          * any residual writes from the previous batch.
 609          */
 610         return logical_ring_invalidate_all_caches(ringbuf, ctx);
 611 }
 612
 613 /**
 614  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 615  * @dev: DRM device.
 616  * @file: DRM file.
 617  * @ring: Engine Command Streamer to submit to.
 618  * @ctx: Context to employ for this submission.
 619  * @args: execbuffer call arguments.
 620  * @vmas: list of vmas.
 621  * @batch_obj: the batchbuffer to submit.
 622  * @exec_start: batchbuffer start virtual address pointer.
 623  * @flags: translated execbuffer call flags.
 624  *
 625  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 626  * away the submission details of the execbuffer ioctl call.
 627  *
 628  * Return: non-zero if the submission fails.
 629  */
 630 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 631                                struct intel_engine_cs *ring,
 632                                struct intel_context *ctx,
 633                                struct drm_i915_gem_execbuffer2 *args,
 634                                struct list_head *vmas,
 635                                struct drm_i915_gem_object *batch_obj,
 636                                u64 exec_start, u32 flags)
 637 {
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 640         int instp_mode;
 641         u32 instp_mask;
 642         int ret;
 643
 644         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 645         instp_mask = I915_EXEC_CONSTANTS_MASK;
 646         switch (instp_mode) {
 647         case I915_EXEC_CONSTANTS_REL_GENERAL:
 648         case I915_EXEC_CONSTANTS_ABSOLUTE:
 649         case I915_EXEC_CONSTANTS_REL_SURFACE:
 650                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 651                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 652                         return -EINVAL;
 653                 }
 654
 655                 if (instp_mode != dev_priv->relative_constants_mode) {
 656                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 657                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 658                                 return -EINVAL;
 659                         }
 660
 661                         /* The HW changed the meaning on this bit on gen6 */
 662                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 663                 }
 664                 break;
 665         default:
 666                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 667                 return -EINVAL;
 668         }
 669
 670         if (args->num_cliprects != 0) {
 671                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 672                 return -EINVAL;
 673         } else {
 674                 if (args->DR4 == 0xffffffff) {
 675                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 676                         args->DR4 = 0;
 677                 }
 678
 679                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 680                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 681                         return -EINVAL;
 682                 }
 683         }
 684
 685         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 686                 DRM_DEBUG("sol reset is gen7 only\n");
 687                 return -EINVAL;
 688         }
 689
 690         ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
 691         if (ret)
 692                 return ret;
 693
 694         if (ring == &dev_priv->ring[RCS] &&
 695             instp_mode != dev_priv->relative_constants_mode) {
 696                 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
 697                 if (ret)
 698                         return ret;
 699
 700                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 701                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 702                 intel_logical_ring_emit(ringbuf, INSTPM);
 703                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 704                 intel_logical_ring_advance(ringbuf);
 705
 706                 dev_priv->relative_constants_mode = instp_mode;
 707         }
 708
 709         ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
 710         if (ret)
 711                 return ret;
 712
 713         i915_gem_execbuffer_move_to_active(vmas, ring);
 714         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 715
 716         return 0;
 717 }
 718
 719 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 720 {
 721         struct drm_i915_gem_request *req, *tmp;
 722         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 723         unsigned long flags;
 724         struct list_head retired_list;
 725
 726         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 727         if (list_empty(&ring->execlist_retired_req_list))
 728                 return;
 729
 730         INIT_LIST_HEAD(&retired_list);
 731         spin_lock_irqsave(&ring->execlist_lock, flags);
 732         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 733         spin_unlock_irqrestore(&ring->execlist_lock, flags);
 734
 735         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 736                 struct intel_context *ctx = req->ctx;
 737                 struct drm_i915_gem_object *ctx_obj =
 738                                 ctx->engine[ring->id].state;
 739
 740                 if (ctx_obj && (ctx != ring->default_context))
 741                         intel_lr_context_unpin(ring, ctx);
 742                 intel_runtime_pm_put(dev_priv);
 743                 i915_gem_context_unreference(ctx);
 744                 list_del(&req->execlist_link);
 745                 i915_gem_request_unreference(req);
 746         }
 747 }
 748
 749 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 750 {
 751         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 752         int ret;
 753
 754         if (!intel_ring_initialized(ring))
 755                 return;
 756
 757         ret = intel_ring_idle(ring);
 758         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 759                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 760                           ring->name, ret);
 761
 762         /* TODO: Is this correct with Execlists enabled? */
 763         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 764         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 765                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 766                 return;
 767         }
 768         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 769 }
 770
 771 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
 772                                   struct intel_context *ctx)
 773 {
 774         struct intel_engine_cs *ring = ringbuf->ring;
 775         int ret;
 776
 777         if (!ring->gpu_caches_dirty)
 778                 return 0;
 779
 780         ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
 781         if (ret)
 782                 return ret;
 783
 784         ring->gpu_caches_dirty = false;
 785         return 0;
 786 }
 787
 788 /**
 789  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 790  * @ringbuf: Logical Ringbuffer to advance.
 791  *
 792  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 793  * really happens during submission is that the context and current tail will be placed
 794  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 795  * point, the tail *inside* the context is updated and the ELSP written to.
 796  */
 797 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
 798                                            struct intel_context *ctx,
 799                                            struct drm_i915_gem_request *request)
 800 {
 801         struct intel_engine_cs *ring = ringbuf->ring;
 802
 803         intel_logical_ring_advance(ringbuf);
 804
 805         if (intel_ring_stopped(ring))
 806                 return;
 807
 808         execlists_context_queue(ring, ctx, ringbuf->tail, request);
 809 }
 810
 811 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 812                 struct intel_context *ctx)
 813 {
 814         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 815         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 816         int ret = 0;
 817
 818         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 819         if (ctx->engine[ring->id].pin_count++ == 0) {
 820                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
 821                                 GEN8_LR_CONTEXT_ALIGN, 0);
 822                 if (ret)
 823                         goto reset_pin_count;
 824
 825                 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
 826                 if (ret)
 827                         goto unpin_ctx_obj;
 828         }
 829
 830         return ret;
 831
 832 unpin_ctx_obj:
 833         i915_gem_object_ggtt_unpin(ctx_obj);
 834 reset_pin_count:
 835         ctx->engine[ring->id].pin_count = 0;
 836
 837         return ret;
 838 }
 839
 840 void intel_lr_context_unpin(struct intel_engine_cs *ring,
 841                 struct intel_context *ctx)
 842 {
 843         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 844         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 845
 846         if (ctx_obj) {
 847                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 848                 if (--ctx->engine[ring->id].pin_count == 0) {
 849                         intel_unpin_ringbuffer_obj(ringbuf);
 850                         i915_gem_object_ggtt_unpin(ctx_obj);
 851                 }
 852         }
 853 }
 854
 855 static int logical_ring_alloc_request(struct intel_engine_cs *ring,
 856                                       struct intel_context *ctx)
 857 {
 858         struct drm_i915_gem_request *request;
 859         struct drm_i915_private *dev_private = ring->dev->dev_private;
 860         int ret;
 861
 862         if (ring->outstanding_lazy_request)
 863                 return 0;
 864
 865         request = kzalloc(sizeof(*request), GFP_KERNEL);
 866         if (request == NULL)
 867                 return -ENOMEM;
 868
 869         if (ctx != ring->default_context) {
 870                 ret = intel_lr_context_pin(ring, ctx);
 871                 if (ret) {
 872                         kfree(request);
 873                         return ret;
 874                 }
 875         }
 876
 877         kref_init(&request->ref);
 878         request->ring = ring;
 879         request->uniq = dev_private->request_uniq++;
 880
 881         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
 882         if (ret) {
 883                 intel_lr_context_unpin(ring, ctx);
 884                 kfree(request);
 885                 return ret;
 886         }
 887
 888         /* Hold a reference to the context this request belongs to
 889          * (we will need it when the time comes to emit/retire the
 890          * request).
 891          */
 892         request->ctx = ctx;
 893         i915_gem_context_reference(request->ctx);
 894
 895         ring->outstanding_lazy_request = request;
 896         return 0;
 897 }
 898
 899 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
 900                                      int bytes)
 901 {
 902         struct intel_engine_cs *ring = ringbuf->ring;
 903         struct drm_i915_gem_request *request;
 904         int ret;
 905
 906         if (intel_ring_space(ringbuf) >= bytes)
 907                 return 0;
 908
 909         list_for_each_entry(request, &ring->request_list, list) {
 910                 /*
 911                  * The request queue is per-engine, so can contain requests
 912                  * from multiple ringbuffers. Here, we must ignore any that
 913                  * aren't from the ringbuffer we're considering.
 914                  */
 915                 struct intel_context *ctx = request->ctx;
 916                 if (ctx->engine[ring->id].ringbuf != ringbuf)
 917                         continue;
 918
 919                 /* Would completion of this request free enough space? */
 920                 if (__intel_ring_space(request->tail, ringbuf->tail,
 921                                        ringbuf->size) >= bytes) {
 922                         break;
 923                 }
 924         }
 925
 926         if (&request->list == &ring->request_list)
 927                 return -ENOSPC;
 928
 929         ret = i915_wait_request(request);
 930         if (ret)
 931                 return ret;
 932
 933         i915_gem_retire_requests_ring(ring);
 934
 935         return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
 936 }
 937
 938 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 939                                        struct intel_context *ctx,
 940                                        int bytes)
 941 {
 942         struct intel_engine_cs *ring = ringbuf->ring;
 943         struct drm_device *dev = ring->dev;
 944         struct drm_i915_private *dev_priv = dev->dev_private;
 945         unsigned long end;
 946         int ret;
 947
 948         ret = logical_ring_wait_request(ringbuf, bytes);
 949         if (ret != -ENOSPC)
 950                 return ret;
 951
 952         /* Force the context submission in case we have been skipping it */
 953         intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
 954
 955         /* With GEM the hangcheck timer should kick us out of the loop,
 956          * leaving it early runs the risk of corrupting GEM state (due
 957          * to running on almost untested codepaths). But on resume
 958          * timers don't work yet, so prevent a complete hang in that
 959          * case by choosing an insanely large timeout. */
 960         end = jiffies + 60 * HZ;
 961
 962         ret = 0;
 963         do {
 964                 if (intel_ring_space(ringbuf) >= bytes)
 965                         break;
 966
 967                 msleep(1);
 968
 969                 if (dev_priv->mm.interruptible && signal_pending(current)) {
 970                         ret = -ERESTARTSYS;
 971                         break;
 972                 }
 973
 974                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 975                                            dev_priv->mm.interruptible);
 976                 if (ret)
 977                         break;
 978
 979                 if (time_after(jiffies, end)) {
 980                         ret = -EBUSY;
 981                         break;
 982                 }
 983         } while (1);
 984
 985         return ret;
 986 }
 987
 988 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
 989                                     struct intel_context *ctx)
 990 {
 991         uint32_t __iomem *virt;
 992         int rem = ringbuf->size - ringbuf->tail;
 993
 994         if (ringbuf->space < rem) {
 995                 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
 996
 997                 if (ret)
 998                         return ret;
 999         }
1000
1001         virt = ringbuf->virtual_start + ringbuf->tail;
1002         rem /= 4;
1003         while (rem--)
1004                 iowrite32(MI_NOOP, virt++);
1005
1006         ringbuf->tail = 0;
1007         intel_ring_update_space(ringbuf);
1008
1009         return 0;
1010 }
1011
1012 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1013                                 struct intel_context *ctx, int bytes)
1014 {
1015         int ret;
1016
1017         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1018                 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1019                 if (unlikely(ret))
1020                         return ret;
1021         }
1022
1023         if (unlikely(ringbuf->space < bytes)) {
1024                 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1025                 if (unlikely(ret))
1026                         return ret;
1027         }
1028
1029         return 0;
1030 }
1031
1032 /**
1033  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1034  *
1035  * @ringbuf: Logical ringbuffer.
1036  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1037  *
1038  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1039  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1040  * and also preallocates a request (every workload submission is still mediated through
1041  * requests, same as it did with legacy ringbuffer submission).
1042  *
1043  * Return: non-zero if the ringbuffer is not ready to be written to.
1044  */
1045 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1046                              struct intel_context *ctx, int num_dwords)
1047 {
1048         struct intel_engine_cs *ring = ringbuf->ring;
1049         struct drm_device *dev = ring->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         int ret;
1052
1053         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1054                                    dev_priv->mm.interruptible);
1055         if (ret)
1056                 return ret;
1057
1058         ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1059         if (ret)
1060                 return ret;
1061
1062         /* Preallocate the olr before touching the ring */
1063         ret = logical_ring_alloc_request(ring, ctx);
1064         if (ret)
1065                 return ret;
1066
1067         ringbuf->space -= num_dwords * sizeof(uint32_t);
1068         return 0;
1069 }
1070
1071 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1072                                                struct intel_context *ctx)
1073 {
1074         int ret, i;
1075         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1076         struct drm_device *dev = ring->dev;
1077         struct drm_i915_private *dev_priv = dev->dev_private;
1078         struct i915_workarounds *w = &dev_priv->workarounds;
1079
1080         if (WARN_ON_ONCE(w->count == 0))
1081                 return 0;
1082
1083         ring->gpu_caches_dirty = true;
1084         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1085         if (ret)
1086                 return ret;
1087
1088         ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1089         if (ret)
1090                 return ret;
1091
1092         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1093         for (i = 0; i < w->count; i++) {
1094                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1095                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1096         }
1097         intel_logical_ring_emit(ringbuf, MI_NOOP);
1098
1099         intel_logical_ring_advance(ringbuf);
1100
1101         ring->gpu_caches_dirty = true;
1102         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1103         if (ret)
1104                 return ret;
1105
1106         return 0;
1107 }
1108
1109 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1110 {
1111         struct drm_device *dev = ring->dev;
1112         struct drm_i915_private *dev_priv = dev->dev_private;
1113
1114         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1115         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1116
1117         I915_WRITE(RING_MODE_GEN7(ring),
1118                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1119                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1120         POSTING_READ(RING_MODE_GEN7(ring));
1121         ring->next_context_status_buffer = 0;
1122         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1123
1124         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1125
1126         return 0;
1127 }
1128
1129 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1130 {
1131         struct drm_device *dev = ring->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         int ret;
1134
1135         ret = gen8_init_common_ring(ring);
1136         if (ret)
1137                 return ret;
1138
1139         /* We need to disable the AsyncFlip performance optimisations in order
1140          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1141          * programmed to '1' on all products.
1142          *
1143          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1144          */
1145         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1146
1147         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1148
1149         return init_workarounds_ring(ring);
1150 }
1151
1152 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1153                               struct intel_context *ctx,
1154                               u64 offset, unsigned flags)
1155 {
1156         bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1157         int ret;
1158
1159         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1160         if (ret)
1161                 return ret;
1162
1163         /* FIXME(BDW): Address space and security selectors. */
1164         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1165         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1166         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1167         intel_logical_ring_emit(ringbuf, MI_NOOP);
1168         intel_logical_ring_advance(ringbuf);
1169
1170         return 0;
1171 }
1172
1173 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1174 {
1175         struct drm_device *dev = ring->dev;
1176         struct drm_i915_private *dev_priv = dev->dev_private;
1177         unsigned long flags;
1178
1179         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1180                 return false;
1181
1182         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1183         if (ring->irq_refcount++ == 0) {
1184                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1185                 POSTING_READ(RING_IMR(ring->mmio_base));
1186         }
1187         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1188
1189         return true;
1190 }
1191
1192 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1193 {
1194         struct drm_device *dev = ring->dev;
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         unsigned long flags;
1197
1198         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1199         if (--ring->irq_refcount == 0) {
1200                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1201                 POSTING_READ(RING_IMR(ring->mmio_base));
1202         }
1203         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1204 }
1205
1206 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1207                            struct intel_context *ctx,
1208                            u32 invalidate_domains,
1209                            u32 unused)
1210 {
1211         struct intel_engine_cs *ring = ringbuf->ring;
1212         struct drm_device *dev = ring->dev;
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214         uint32_t cmd;
1215         int ret;
1216
1217         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1218         if (ret)
1219                 return ret;
1220
1221         cmd = MI_FLUSH_DW + 1;
1222
1223         if (ring == &dev_priv->ring[VCS]) {
1224                 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
1225                         cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1226                                 MI_FLUSH_DW_STORE_INDEX |
1227                                 MI_FLUSH_DW_OP_STOREDW;
1228         } else {
1229                 if (invalidate_domains & I915_GEM_DOMAIN_RENDER)
1230                         cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1231                                 MI_FLUSH_DW_OP_STOREDW;
1232         }
1233
1234         intel_logical_ring_emit(ringbuf, cmd);
1235         intel_logical_ring_emit(ringbuf,
1236                                 I915_GEM_HWS_SCRATCH_ADDR |
1237                                 MI_FLUSH_DW_USE_GTT);
1238         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1239         intel_logical_ring_emit(ringbuf, 0); /* value */
1240         intel_logical_ring_advance(ringbuf);
1241
1242         return 0;
1243 }
1244
1245 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1246                                   struct intel_context *ctx,
1247                                   u32 invalidate_domains,
1248                                   u32 flush_domains)
1249 {
1250         struct intel_engine_cs *ring = ringbuf->ring;
1251         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1252         u32 flags = 0;
1253         int ret;
1254
1255         flags |= PIPE_CONTROL_CS_STALL;
1256
1257         if (flush_domains) {
1258                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1259                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1260         }
1261
1262         if (invalidate_domains) {
1263                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1264                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1265                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1266                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1267                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1268                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1269                 flags |= PIPE_CONTROL_QW_WRITE;
1270                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1271         }
1272
1273         ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1274         if (ret)
1275                 return ret;
1276
1277         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1278         intel_logical_ring_emit(ringbuf, flags);
1279         intel_logical_ring_emit(ringbuf, scratch_addr);
1280         intel_logical_ring_emit(ringbuf, 0);
1281         intel_logical_ring_emit(ringbuf, 0);
1282         intel_logical_ring_emit(ringbuf, 0);
1283         intel_logical_ring_advance(ringbuf);
1284
1285         return 0;
1286 }
1287
1288 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1289 {
1290         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1291 }
1292
1293 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1294 {
1295         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1296 }
1297
1298 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1299                              struct drm_i915_gem_request *request)
1300 {
1301         struct intel_engine_cs *ring = ringbuf->ring;
1302         u32 cmd;
1303         int ret;
1304
1305         ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1306         if (ret)
1307                 return ret;
1308
1309         cmd = MI_STORE_DWORD_IMM_GEN4;
1310         cmd |= MI_GLOBAL_GTT;
1311
1312         intel_logical_ring_emit(ringbuf, cmd);
1313         intel_logical_ring_emit(ringbuf,
1314                                 (ring->status_page.gfx_addr +
1315                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1316         intel_logical_ring_emit(ringbuf, 0);
1317         intel_logical_ring_emit(ringbuf,
1318                 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1319         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1320         intel_logical_ring_emit(ringbuf, MI_NOOP);
1321         intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1322
1323         return 0;
1324 }
1325
1326 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1327                                               struct intel_context *ctx)
1328 {
1329         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1330         struct render_state so;
1331         struct drm_i915_file_private *file_priv = ctx->file_priv;
1332         struct drm_file *file = file_priv ? file_priv->file : NULL;
1333         int ret;
1334
1335         ret = i915_gem_render_state_prepare(ring, &so);
1336         if (ret)
1337                 return ret;
1338
1339         if (so.rodata == NULL)
1340                 return 0;
1341
1342         ret = ring->emit_bb_start(ringbuf,
1343                         ctx,
1344                         so.ggtt_offset,
1345                         I915_DISPATCH_SECURE);
1346         if (ret)
1347                 goto out;
1348
1349         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1350
1351         ret = __i915_add_request(ring, file, so.obj);
1352         /* intel_logical_ring_add_request moves object to inactive if it
1353          * fails */
1354 out:
1355         i915_gem_render_state_fini(&so);
1356         return ret;
1357 }
1358
1359 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1360                        struct intel_context *ctx)
1361 {
1362         int ret;
1363
1364         ret = intel_logical_ring_workarounds_emit(ring, ctx);
1365         if (ret)
1366                 return ret;
1367
1368         return intel_lr_context_render_state_init(ring, ctx);
1369 }
1370
1371 /**
1372  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1373  *
1374  * @ring: Engine Command Streamer.
1375  *
1376  */
1377 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1378 {
1379         struct drm_i915_private *dev_priv;
1380
1381         if (!intel_ring_initialized(ring))
1382                 return;
1383
1384         dev_priv = ring->dev->dev_private;
1385
1386         intel_logical_ring_stop(ring);
1387         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1388         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1389
1390         if (ring->cleanup)
1391                 ring->cleanup(ring);
1392
1393         i915_cmd_parser_fini_ring(ring);
1394
1395         if (ring->status_page.obj) {
1396                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1397                 ring->status_page.obj = NULL;
1398         }
1399 }
1400
1401 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1402 {
1403         int ret;
1404
1405         /* Intentionally left blank. */
1406         ring->buffer = NULL;
1407
1408         ring->dev = dev;
1409         INIT_LIST_HEAD(&ring->active_list);
1410         INIT_LIST_HEAD(&ring->request_list);
1411         init_waitqueue_head(&ring->irq_queue);
1412
1413         INIT_LIST_HEAD(&ring->execlist_queue);
1414         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1415         spin_lock_init(&ring->execlist_lock);
1416
1417         ret = i915_cmd_parser_init_ring(ring);
1418         if (ret)
1419                 return ret;
1420
1421         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1422
1423         return ret;
1424 }
1425
1426 static int logical_render_ring_init(struct drm_device *dev)
1427 {
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1430         int ret;
1431
1432         ring->name = "render ring";
1433         ring->id = RCS;
1434         ring->mmio_base = RENDER_RING_BASE;
1435         ring->irq_enable_mask =
1436                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1437         ring->irq_keep_mask =
1438                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1439         if (HAS_L3_DPF(dev))
1440                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1441
1442         ring->init_hw = gen8_init_render_ring;
1443         ring->init_context = gen8_init_rcs_context;
1444         ring->cleanup = intel_fini_pipe_control;
1445         ring->get_seqno = gen8_get_seqno;
1446         ring->set_seqno = gen8_set_seqno;
1447         ring->emit_request = gen8_emit_request;
1448         ring->emit_flush = gen8_emit_flush_render;
1449         ring->irq_get = gen8_logical_ring_get_irq;
1450         ring->irq_put = gen8_logical_ring_put_irq;
1451         ring->emit_bb_start = gen8_emit_bb_start;
1452
1453         ring->dev = dev;
1454         ret = logical_ring_init(dev, ring);
1455         if (ret)
1456                 return ret;
1457
1458         return intel_init_pipe_control(ring);
1459 }
1460
1461 static int logical_bsd_ring_init(struct drm_device *dev)
1462 {
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1465
1466         ring->name = "bsd ring";
1467         ring->id = VCS;
1468         ring->mmio_base = GEN6_BSD_RING_BASE;
1469         ring->irq_enable_mask =
1470                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1471         ring->irq_keep_mask =
1472                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1473
1474         ring->init_hw = gen8_init_common_ring;
1475         ring->get_seqno = gen8_get_seqno;
1476         ring->set_seqno = gen8_set_seqno;
1477         ring->emit_request = gen8_emit_request;
1478         ring->emit_flush = gen8_emit_flush;
1479         ring->irq_get = gen8_logical_ring_get_irq;
1480         ring->irq_put = gen8_logical_ring_put_irq;
1481         ring->emit_bb_start = gen8_emit_bb_start;
1482
1483         return logical_ring_init(dev, ring);
1484 }
1485
1486 static int logical_bsd2_ring_init(struct drm_device *dev)
1487 {
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1490
1491         ring->name = "bds2 ring";
1492         ring->id = VCS2;
1493         ring->mmio_base = GEN8_BSD2_RING_BASE;
1494         ring->irq_enable_mask =
1495                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1496         ring->irq_keep_mask =
1497                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1498
1499         ring->init_hw = gen8_init_common_ring;
1500         ring->get_seqno = gen8_get_seqno;
1501         ring->set_seqno = gen8_set_seqno;
1502         ring->emit_request = gen8_emit_request;
1503         ring->emit_flush = gen8_emit_flush;
1504         ring->irq_get = gen8_logical_ring_get_irq;
1505         ring->irq_put = gen8_logical_ring_put_irq;
1506         ring->emit_bb_start = gen8_emit_bb_start;
1507
1508         return logical_ring_init(dev, ring);
1509 }
1510
1511 static int logical_blt_ring_init(struct drm_device *dev)
1512 {
1513         struct drm_i915_private *dev_priv = dev->dev_private;
1514         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1515
1516         ring->name = "blitter ring";
1517         ring->id = BCS;
1518         ring->mmio_base = BLT_RING_BASE;
1519         ring->irq_enable_mask =
1520                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1521         ring->irq_keep_mask =
1522                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1523
1524         ring->init_hw = gen8_init_common_ring;
1525         ring->get_seqno = gen8_get_seqno;
1526         ring->set_seqno = gen8_set_seqno;
1527         ring->emit_request = gen8_emit_request;
1528         ring->emit_flush = gen8_emit_flush;
1529         ring->irq_get = gen8_logical_ring_get_irq;
1530         ring->irq_put = gen8_logical_ring_put_irq;
1531         ring->emit_bb_start = gen8_emit_bb_start;
1532
1533         return logical_ring_init(dev, ring);
1534 }
1535
1536 static int logical_vebox_ring_init(struct drm_device *dev)
1537 {
1538         struct drm_i915_private *dev_priv = dev->dev_private;
1539         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1540
1541         ring->name = "video enhancement ring";
1542         ring->id = VECS;
1543         ring->mmio_base = VEBOX_RING_BASE;
1544         ring->irq_enable_mask =
1545                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1546         ring->irq_keep_mask =
1547                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1548
1549         ring->init_hw = gen8_init_common_ring;
1550         ring->get_seqno = gen8_get_seqno;
1551         ring->set_seqno = gen8_set_seqno;
1552         ring->emit_request = gen8_emit_request;
1553         ring->emit_flush = gen8_emit_flush;
1554         ring->irq_get = gen8_logical_ring_get_irq;
1555         ring->irq_put = gen8_logical_ring_put_irq;
1556         ring->emit_bb_start = gen8_emit_bb_start;
1557
1558         return logical_ring_init(dev, ring);
1559 }
1560
1561 /**
1562  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1563  * @dev: DRM device.
1564  *
1565  * This function inits the engines for an Execlists submission style (the equivalent in the
1566  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1567  * those engines that are present in the hardware.
1568  *
1569  * Return: non-zero if the initialization failed.
1570  */
1571 int intel_logical_rings_init(struct drm_device *dev)
1572 {
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574         int ret;
1575
1576         ret = logical_render_ring_init(dev);
1577         if (ret)
1578                 return ret;
1579
1580         if (HAS_BSD(dev)) {
1581                 ret = logical_bsd_ring_init(dev);
1582                 if (ret)
1583                         goto cleanup_render_ring;
1584         }
1585
1586         if (HAS_BLT(dev)) {
1587                 ret = logical_blt_ring_init(dev);
1588                 if (ret)
1589                         goto cleanup_bsd_ring;
1590         }
1591
1592         if (HAS_VEBOX(dev)) {
1593                 ret = logical_vebox_ring_init(dev);
1594                 if (ret)
1595                         goto cleanup_blt_ring;
1596         }
1597
1598         if (HAS_BSD2(dev)) {
1599                 ret = logical_bsd2_ring_init(dev);
1600                 if (ret)
1601                         goto cleanup_vebox_ring;
1602         }
1603
1604         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1605         if (ret)
1606                 goto cleanup_bsd2_ring;
1607
1608         return 0;
1609
1610 cleanup_bsd2_ring:
1611         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1612 cleanup_vebox_ring:
1613         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1614 cleanup_blt_ring:
1615         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1616 cleanup_bsd_ring:
1617         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1618 cleanup_render_ring:
1619         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1620
1621         return ret;
1622 }
1623
1624 static int
1625 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1626                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1627 {
1628         struct drm_device *dev = ring->dev;
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1631         struct page *page;
1632         uint32_t *reg_state;
1633         int ret;
1634
1635         if (!ppgtt)
1636                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1637
1638         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1639         if (ret) {
1640                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1641                 return ret;
1642         }
1643
1644         ret = i915_gem_object_get_pages(ctx_obj);
1645         if (ret) {
1646                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1647                 return ret;
1648         }
1649
1650         i915_gem_object_pin_pages(ctx_obj);
1651
1652         /* The second page of the context object contains some fields which must
1653          * be set up prior to the first execution. */
1654         page = i915_gem_object_get_page(ctx_obj, 1);
1655         reg_state = kmap_atomic(page);
1656
1657         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1658          * commands followed by (reg, value) pairs. The values we are setting here are
1659          * only for the first context restore: on a subsequent save, the GPU will
1660          * recreate this batchbuffer with new values (including all the missing
1661          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1662         if (ring->id == RCS)
1663                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1664         else
1665                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1666         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1667         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1668         reg_state[CTX_CONTEXT_CONTROL+1] =
1669                 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1670                                 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1671         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1672         reg_state[CTX_RING_HEAD+1] = 0;
1673         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1674         reg_state[CTX_RING_TAIL+1] = 0;
1675         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1676         /* Ring buffer start address is not known until the buffer is pinned.
1677          * It is written to the context image in execlists_update_context()
1678          */
1679         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1680         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1681                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1682         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1683         reg_state[CTX_BB_HEAD_U+1] = 0;
1684         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1685         reg_state[CTX_BB_HEAD_L+1] = 0;
1686         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1687         reg_state[CTX_BB_STATE+1] = (1<<5);
1688         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1689         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1690         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1691         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1692         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1693         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1694         if (ring->id == RCS) {
1695                 /* TODO: according to BSpec, the register state context
1696                  * for CHV does not have these. OTOH, these registers do
1697                  * exist in CHV. I'm waiting for a clarification */
1698                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1699                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1700                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1701                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1702                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1703                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1704         }
1705         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1706         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1707         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1708         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1709         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1710         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1711         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1712         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1713         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1714         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1715         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1716         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1717         reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1718         reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1719         reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1720         reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1721         reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1722         reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1723         reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1724         reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1725         if (ring->id == RCS) {
1726                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1727                 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1728                 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1729         }
1730
1731         kunmap_atomic(reg_state);
1732
1733         ctx_obj->dirty = 1;
1734         set_page_dirty(page);
1735         i915_gem_object_unpin_pages(ctx_obj);
1736
1737         return 0;
1738 }
1739
1740 /**
1741  * intel_lr_context_free() - free the LRC specific bits of a context
1742  * @ctx: the LR context to free.
1743  *
1744  * The real context freeing is done in i915_gem_context_free: this only
1745  * takes care of the bits that are LRC related: the per-engine backing
1746  * objects and the logical ringbuffer.
1747  */
1748 void intel_lr_context_free(struct intel_context *ctx)
1749 {
1750         int i;
1751
1752         for (i = 0; i < I915_NUM_RINGS; i++) {
1753                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1754
1755                 if (ctx_obj) {
1756                         struct intel_ringbuffer *ringbuf =
1757                                         ctx->engine[i].ringbuf;
1758                         struct intel_engine_cs *ring = ringbuf->ring;
1759
1760                         if (ctx == ring->default_context) {
1761                                 intel_unpin_ringbuffer_obj(ringbuf);
1762                                 i915_gem_object_ggtt_unpin(ctx_obj);
1763                         }
1764                         WARN_ON(ctx->engine[ring->id].pin_count);
1765                         intel_destroy_ringbuffer_obj(ringbuf);
1766                         kfree(ringbuf);
1767                         drm_gem_object_unreference(&ctx_obj->base);
1768                 }
1769         }
1770 }
1771
1772 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1773 {
1774         int ret = 0;
1775
1776         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1777
1778         switch (ring->id) {
1779         case RCS:
1780                 if (INTEL_INFO(ring->dev)->gen >= 9)
1781                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1782                 else
1783                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1784                 break;
1785         case VCS:
1786         case BCS:
1787         case VECS:
1788         case VCS2:
1789                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1790                 break;
1791         }
1792
1793         return ret;
1794 }
1795
1796 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1797                 struct drm_i915_gem_object *default_ctx_obj)
1798 {
1799         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1800
1801         /* The status page is offset 0 from the default context object
1802          * in LRC mode. */
1803         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1804         ring->status_page.page_addr =
1805                         kmap(sg_page(default_ctx_obj->pages->sgl));
1806         ring->status_page.obj = default_ctx_obj;
1807
1808         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1809                         (u32)ring->status_page.gfx_addr);
1810         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1811 }
1812
1813 /**
1814  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1815  * @ctx: LR context to create.
1816  * @ring: engine to be used with the context.
1817  *
1818  * This function can be called more than once, with different engines, if we plan
1819  * to use the context with them. The context backing objects and the ringbuffers
1820  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1821  * the creation is a deferred call: it's better to make sure first that we need to use
1822  * a given ring with the context.
1823  *
1824  * Return: non-zero on error.
1825  */
1826 int intel_lr_context_deferred_create(struct intel_context *ctx,
1827                                      struct intel_engine_cs *ring)
1828 {
1829         const bool is_global_default_ctx = (ctx == ring->default_context);
1830         struct drm_device *dev = ring->dev;
1831         struct drm_i915_gem_object *ctx_obj;
1832         uint32_t context_size;
1833         struct intel_ringbuffer *ringbuf;
1834         int ret;
1835
1836         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1837         WARN_ON(ctx->engine[ring->id].state);
1838
1839         context_size = round_up(get_lr_context_size(ring), 4096);
1840
1841         ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1842         if (IS_ERR(ctx_obj)) {
1843                 ret = PTR_ERR(ctx_obj);
1844                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1845                 return ret;
1846         }
1847
1848         if (is_global_default_ctx) {
1849                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1850                 if (ret) {
1851                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1852                                         ret);
1853                         drm_gem_object_unreference(&ctx_obj->base);
1854                         return ret;
1855                 }
1856         }
1857
1858         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1859         if (!ringbuf) {
1860                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1861                                 ring->name);
1862                 ret = -ENOMEM;
1863                 goto error_unpin_ctx;
1864         }
1865
1866         ringbuf->ring = ring;
1867
1868         ringbuf->size = 32 * PAGE_SIZE;
1869         ringbuf->effective_size = ringbuf->size;
1870         ringbuf->head = 0;
1871         ringbuf->tail = 0;
1872         ringbuf->last_retired_head = -1;
1873         intel_ring_update_space(ringbuf);
1874
1875         if (ringbuf->obj == NULL) {
1876                 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1877                 if (ret) {
1878                         DRM_DEBUG_DRIVER(
1879                                 "Failed to allocate ringbuffer obj %s: %d\n",
1880                                 ring->name, ret);
1881                         goto error_free_rbuf;
1882                 }
1883
1884                 if (is_global_default_ctx) {
1885                         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1886                         if (ret) {
1887                                 DRM_ERROR(
1888                                         "Failed to pin and map ringbuffer %s: %d\n",
1889                                         ring->name, ret);
1890                                 goto error_destroy_rbuf;
1891                         }
1892                 }
1893
1894         }
1895
1896         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1897         if (ret) {
1898                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1899                 goto error;
1900         }
1901
1902         ctx->engine[ring->id].ringbuf = ringbuf;
1903         ctx->engine[ring->id].state = ctx_obj;
1904
1905         if (ctx == ring->default_context)
1906                 lrc_setup_hardware_status_page(ring, ctx_obj);
1907         else if (ring->id == RCS && !ctx->rcs_initialized) {
1908                 if (ring->init_context) {
1909                         ret = ring->init_context(ring, ctx);
1910                         if (ret) {
1911                                 DRM_ERROR("ring init context: %d\n", ret);
1912                                 ctx->engine[ring->id].ringbuf = NULL;
1913                                 ctx->engine[ring->id].state = NULL;
1914                                 goto error;
1915                         }
1916                 }
1917
1918                 ctx->rcs_initialized = true;
1919         }
1920
1921         return 0;
1922
1923 error:
1924         if (is_global_default_ctx)
1925                 intel_unpin_ringbuffer_obj(ringbuf);
1926 error_destroy_rbuf:
1927         intel_destroy_ringbuffer_obj(ringbuf);
1928 error_free_rbuf:
1929         kfree(ringbuf);
1930 error_unpin_ctx:
1931         if (is_global_default_ctx)
1932                 i915_gem_object_ggtt_unpin(ctx_obj);
1933         drm_gem_object_unreference(&ctx_obj->base);
1934         return ret;
1935 }