drivers/gpu/drm/i915/intel_lrc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *    Michel Thierry <michel.thierry@intel.com>
  26  *    Thomas Daniel <thomas.daniel@intel.com>
  27  *    Oscar Mateo <oscar.mateo@intel.com>
  28  *
  29  */
  30
  31 /**
  32  * DOC: Logical Rings, Logical Ring Contexts and Execlists
  33  *
  34  * Motivation:
  35  * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
  36  * These expanded contexts enable a number of new abilities, especially
  37  * "Execlists" (also implemented in this file).
  38  *
  39  * One of the main differences with the legacy HW contexts is that logical
  40  * ring contexts incorporate many more things to the context's state, like
  41  * PDPs or ringbuffer control registers:
  42  *
  43  * The reason why PDPs are included in the context is straightforward: as
  44  * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
  45  * contained there mean you don't need to do a ppgtt->switch_mm yourself,
  46  * instead, the GPU will do it for you on the context switch.
  47  *
  48  * But, what about the ringbuffer control registers (head, tail, etc..)?
  49  * shouldn't we just need a set of those per engine command streamer? This is
  50  * where the name "Logical Rings" starts to make sense: by virtualizing the
  51  * rings, the engine cs shifts to a new "ring buffer" with every context
  52  * switch. When you want to submit a workload to the GPU you: A) choose your
  53  * context, B) find its appropriate virtualized ring, C) write commands to it
  54  * and then, finally, D) tell the GPU to switch to that context.
  55  *
  56  * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
  57  * to a contexts is via a context execution list, ergo "Execlists".
  58  *
  59  * LRC implementation:
  60  * Regarding the creation of contexts, we have:
  61  *
  62  * - One global default context.
  63  * - One local default context for each opened fd.
  64  * - One local extra context for each context create ioctl call.
  65  *
  66  * Now that ringbuffers belong per-context (and not per-engine, like before)
  67  * and that contexts are uniquely tied to a given engine (and not reusable,
  68  * like before) we need:
  69  *
  70  * - One ringbuffer per-engine inside each context.
  71  * - One backing object per-engine inside each context.
  72  *
  73  * The global default context starts its life with these new objects fully
  74  * allocated and populated. The local default context for each opened fd is
  75  * more complex, because we don't know at creation time which engine is going
  76  * to use them. To handle this, we have implemented a deferred creation of LR
  77  * contexts:
  78  *
  79  * The local context starts its life as a hollow or blank holder, that only
  80  * gets populated for a given engine once we receive an execbuffer. If later
  81  * on we receive another execbuffer ioctl for the same context but a different
  82  * engine, we allocate/populate a new ringbuffer and context backing object and
  83  * so on.
  84  *
  85  * Finally, regarding local contexts created using the ioctl call: as they are
  86  * only allowed with the render ring, we can allocate & populate them right
  87  * away (no need to defer anything, at least for now).
  88  *
  89  * Execlists implementation:
  90  * Execlists are the new method by which, on gen8+ hardware, workloads are
  91  * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
  92  * This method works as follows:
  93  *
  94  * When a request is committed, its commands (the BB start and any leading or
  95  * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
  96  * for the appropriate context. The tail pointer in the hardware context is not
  97  * updated at this time, but instead, kept by the driver in the ringbuffer
  98  * structure. A structure representing this request is added to a request queue
  99  * for the appropriate engine: this structure contains a copy of the context's
 100  * tail after the request was written to the ring buffer and a pointer to the
 101  * context itself.
 102  *
 103  * If the engine's request queue was empty before the request was added, the
 104  * queue is processed immediately. Otherwise the queue will be processed during
 105  * a context switch interrupt. In any case, elements on the queue will get sent
 106  * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 107  * globally unique 20-bits submission ID.
 108  *
 109  * When execution of a request completes, the GPU updates the context status
 110  * buffer with a context complete event and generates a context switch interrupt.
 111  * During the interrupt handling, the driver examines the events in the buffer:
 112  * for each context complete event, if the announced ID matches that on the head
 113  * of the request queue, then that request is retired and removed from the queue.
 114  *
 115  * After processing, if any requests were retired and the queue is not empty
 116  * then a new execution list can be submitted. The two requests at the front of
 117  * the queue are next to be submitted but since a context may not occur twice in
 118  * an execution list, if subsequent requests have the same ID as the first then
 119  * the two requests must be combined. This is done simply by discarding requests
 120  * at the head of the queue until either only one requests is left (in which case
 121  * we use a NULL second context) or the first two requests have unique IDs.
 122  *
 123  * By always executing the first two requests in the queue the driver ensures
 124  * that the GPU is kept as busy as possible. In the case where a single context
 125  * completes but a second context is still executing, the request for this second
 126  * context will be at the head of the queue when we remove the first one. This
 127  * request will then be resubmitted along with a new request for a different context,
 128  * which will cause the hardware to continue executing the second request and queue
 129  * the new request (the GPU detects the condition of a context getting preempted
 130  * with the same context and optimizes the context switch flow by not doing
 131  * preemption, but just sampling the new tail pointer).
 132  *
 133  */
 134
 135 #include <drm/drmP.h>
 136 #include <drm/i915_drm.h>
 137 #include "i915_drv.h"
 138
 139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
 142
 143 #define RING_EXECLIST_QFULL             (1 << 0x2)
 144 #define RING_EXECLIST1_VALID            (1 << 0x3)
 145 #define RING_EXECLIST0_VALID            (1 << 0x4)
 146 #define RING_EXECLIST_ACTIVE_STATUS     (3 << 0xE)
 147 #define RING_EXECLIST1_ACTIVE           (1 << 0x11)
 148 #define RING_EXECLIST0_ACTIVE           (1 << 0x12)
 149
 150 #define GEN8_CTX_STATUS_IDLE_ACTIVE     (1 << 0)
 151 #define GEN8_CTX_STATUS_PREEMPTED       (1 << 1)
 152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH  (1 << 2)
 153 #define GEN8_CTX_STATUS_ACTIVE_IDLE     (1 << 3)
 154 #define GEN8_CTX_STATUS_COMPLETE        (1 << 4)
 155 #define GEN8_CTX_STATUS_LITE_RESTORE    (1 << 15)
 156
 157 #define CTX_LRI_HEADER_0                0x01
 158 #define CTX_CONTEXT_CONTROL             0x02
 159 #define CTX_RING_HEAD                   0x04
 160 #define CTX_RING_TAIL                   0x06
 161 #define CTX_RING_BUFFER_START           0x08
 162 #define CTX_RING_BUFFER_CONTROL         0x0a
 163 #define CTX_BB_HEAD_U                   0x0c
 164 #define CTX_BB_HEAD_L                   0x0e
 165 #define CTX_BB_STATE                    0x10
 166 #define CTX_SECOND_BB_HEAD_U            0x12
 167 #define CTX_SECOND_BB_HEAD_L            0x14
 168 #define CTX_SECOND_BB_STATE             0x16
 169 #define CTX_BB_PER_CTX_PTR              0x18
 170 #define CTX_RCS_INDIRECT_CTX            0x1a
 171 #define CTX_RCS_INDIRECT_CTX_OFFSET     0x1c
 172 #define CTX_LRI_HEADER_1                0x21
 173 #define CTX_CTX_TIMESTAMP               0x22
 174 #define CTX_PDP3_UDW                    0x24
 175 #define CTX_PDP3_LDW                    0x26
 176 #define CTX_PDP2_UDW                    0x28
 177 #define CTX_PDP2_LDW                    0x2a
 178 #define CTX_PDP1_UDW                    0x2c
 179 #define CTX_PDP1_LDW                    0x2e
 180 #define CTX_PDP0_UDW                    0x30
 181 #define CTX_PDP0_LDW                    0x32
 182 #define CTX_LRI_HEADER_2                0x41
 183 #define CTX_R_PWR_CLK_STATE             0x42
 184 #define CTX_GPGPU_CSR_BASE_ADDRESS      0x44
 185
 186 #define GEN8_CTX_VALID (1<<0)
 187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
 188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
 189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
 190 #define GEN8_CTX_PRIVILEGE (1<<8)
 191
 192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
 193         const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
 194                 ppgtt->pdp.page_directory[n]->daddr : \
 195                 ppgtt->scratch_pd->daddr; \
 196         reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
 197         reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
 198 }
 199
 200 enum {
 201         ADVANCED_CONTEXT = 0,
 202         LEGACY_CONTEXT,
 203         ADVANCED_AD_CONTEXT,
 204         LEGACY_64B_CONTEXT
 205 };
 206 #define GEN8_CTX_MODE_SHIFT 3
 207 enum {
 208         FAULT_AND_HANG = 0,
 209         FAULT_AND_HALT, /* Debug only */
 210         FAULT_AND_STREAM,
 211         FAULT_AND_CONTINUE /* Unsupported */
 212 };
 213 #define GEN8_CTX_ID_SHIFT 32
 214
 215 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 216                 struct intel_context *ctx);
 217
 218 /**
 219  * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
 220  * @dev: DRM device.
 221  * @enable_execlists: value of i915.enable_execlists module parameter.
 222  *
 223  * Only certain platforms support Execlists (the prerequisites being
 224  * support for Logical Ring Contexts and Aliasing PPGTT or better).
 225  *
 226  * Return: 1 if Execlists is supported and has to be enabled.
 227  */
 228 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
 229 {
 230         WARN_ON(i915.enable_ppgtt == -1);
 231
 232         if (INTEL_INFO(dev)->gen >= 9)
 233                 return 1;
 234
 235         if (enable_execlists == 0)
 236                 return 0;
 237
 238         if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
 239             i915.use_mmio_flip >= 0)
 240                 return 1;
 241
 242         return 0;
 243 }
 244
 245 /**
 246  * intel_execlists_ctx_id() - get the Execlists Context ID
 247  * @ctx_obj: Logical Ring Context backing object.
 248  *
 249  * Do not confuse with ctx->id! Unfortunately we have a name overload
 250  * here: the old context ID we pass to userspace as a handler so that
 251  * they can refer to a context, and the new context ID we pass to the
 252  * ELSP so that the GPU can inform us of the context status via
 253  * interrupts.
 254  *
 255  * Return: 20-bits globally unique context ID.
 256  */
 257 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
 258 {
 259         u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 260
 261         /* LRCA is required to be 4K aligned so the more significant 20 bits
 262          * are globally unique */
 263         return lrca >> 12;
 264 }
 265
 266 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
 267                                          struct drm_i915_gem_object *ctx_obj)
 268 {
 269         struct drm_device *dev = ring->dev;
 270         uint64_t desc;
 271         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 272
 273         WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
 274
 275         desc = GEN8_CTX_VALID;
 276         desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
 277         if (IS_GEN8(ctx_obj->base.dev))
 278                 desc |= GEN8_CTX_L3LLC_COHERENT;
 279         desc |= GEN8_CTX_PRIVILEGE;
 280         desc |= lrca;
 281         desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
 282
 283         /* TODO: WaDisableLiteRestore when we start using semaphore
 284          * signalling between Command Streamers */
 285         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 286
 287         /* WaEnableForceRestoreInCtxtDescForVCS:skl */
 288         if (IS_GEN9(dev) &&
 289             INTEL_REVID(dev) <= SKL_REVID_B0 &&
 290             (ring->id == BCS || ring->id == VCS ||
 291             ring->id == VECS || ring->id == VCS2))
 292                 desc |= GEN8_CTX_FORCE_RESTORE;
 293
 294         return desc;
 295 }
 296
 297 static void execlists_elsp_write(struct intel_engine_cs *ring,
 298                                  struct drm_i915_gem_object *ctx_obj0,
 299                                  struct drm_i915_gem_object *ctx_obj1)
 300 {
 301         struct drm_device *dev = ring->dev;
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303         uint64_t temp = 0;
 304         uint32_t desc[4];
 305
 306         /* XXX: You must always write both descriptors in the order below. */
 307         if (ctx_obj1)
 308                 temp = execlists_ctx_descriptor(ring, ctx_obj1);
 309         else
 310                 temp = 0;
 311         desc[1] = (u32)(temp >> 32);
 312         desc[0] = (u32)temp;
 313
 314         temp = execlists_ctx_descriptor(ring, ctx_obj0);
 315         desc[3] = (u32)(temp >> 32);
 316         desc[2] = (u32)temp;
 317
 318         spin_lock(&dev_priv->uncore.lock);
 319         intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
 320         I915_WRITE_FW(RING_ELSP(ring), desc[1]);
 321         I915_WRITE_FW(RING_ELSP(ring), desc[0]);
 322         I915_WRITE_FW(RING_ELSP(ring), desc[3]);
 323
 324         /* The context is automatically loaded after the following */
 325         I915_WRITE_FW(RING_ELSP(ring), desc[2]);
 326
 327         /* ELSP is a wo register, so use another nearby reg for posting instead */
 328         POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
 329         intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
 330         spin_unlock(&dev_priv->uncore.lock);
 331 }
 332
 333 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
 334                                     struct drm_i915_gem_object *ring_obj,
 335                                     struct i915_hw_ppgtt *ppgtt,
 336                                     u32 tail)
 337 {
 338         struct page *page;
 339         uint32_t *reg_state;
 340
 341         page = i915_gem_object_get_page(ctx_obj, 1);
 342         reg_state = kmap_atomic(page);
 343
 344         reg_state[CTX_RING_TAIL+1] = tail;
 345         reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
 346
 347         /* True PPGTT with dynamic page allocation: update PDP registers and
 348          * point the unallocated PDPs to the scratch page
 349          */
 350         if (ppgtt) {
 351                 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
 352                 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
 353                 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
 354                 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
 355         }
 356
 357         kunmap_atomic(reg_state);
 358
 359         return 0;
 360 }
 361
 362 static void execlists_submit_contexts(struct intel_engine_cs *ring,
 363                                       struct intel_context *to0, u32 tail0,
 364                                       struct intel_context *to1, u32 tail1)
 365 {
 366         struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
 367         struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
 368         struct drm_i915_gem_object *ctx_obj1 = NULL;
 369         struct intel_ringbuffer *ringbuf1 = NULL;
 370
 371         BUG_ON(!ctx_obj0);
 372         WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
 373         WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
 374
 375         execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0);
 376
 377         if (to1) {
 378                 ringbuf1 = to1->engine[ring->id].ringbuf;
 379                 ctx_obj1 = to1->engine[ring->id].state;
 380                 BUG_ON(!ctx_obj1);
 381                 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
 382                 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
 383
 384                 execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1);
 385         }
 386
 387         execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
 388 }
 389
 390 static void execlists_context_unqueue(struct intel_engine_cs *ring)
 391 {
 392         struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
 393         struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
 394
 395         assert_spin_locked(&ring->execlist_lock);
 396
 397         /*
 398          * If irqs are not active generate a warning as batches that finish
 399          * without the irqs may get lost and a GPU Hang may occur.
 400          */
 401         WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
 402
 403         if (list_empty(&ring->execlist_queue))
 404                 return;
 405
 406         /* Try to read in pairs */
 407         list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
 408                                  execlist_link) {
 409                 if (!req0) {
 410                         req0 = cursor;
 411                 } else if (req0->ctx == cursor->ctx) {
 412                         /* Same ctx: ignore first request, as second request
 413                          * will update tail past first request's workload */
 414                         cursor->elsp_submitted = req0->elsp_submitted;
 415                         list_del(&req0->execlist_link);
 416                         list_add_tail(&req0->execlist_link,
 417                                 &ring->execlist_retired_req_list);
 418                         req0 = cursor;
 419                 } else {
 420                         req1 = cursor;
 421                         break;
 422                 }
 423         }
 424
 425         if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
 426                 /*
 427                  * WaIdleLiteRestore: make sure we never cause a lite
 428                  * restore with HEAD==TAIL
 429                  */
 430                 if (req0 && req0->elsp_submitted) {
 431                         /*
 432                          * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
 433                          * as we resubmit the request. See gen8_emit_request()
 434                          * for where we prepare the padding after the end of the
 435                          * request.
 436                          */
 437                         struct intel_ringbuffer *ringbuf;
 438
 439                         ringbuf = req0->ctx->engine[ring->id].ringbuf;
 440                         req0->tail += 8;
 441                         req0->tail &= ringbuf->size - 1;
 442                 }
 443         }
 444
 445         WARN_ON(req1 && req1->elsp_submitted);
 446
 447         execlists_submit_contexts(ring, req0->ctx, req0->tail,
 448                                   req1 ? req1->ctx : NULL,
 449                                   req1 ? req1->tail : 0);
 450
 451         req0->elsp_submitted++;
 452         if (req1)
 453                 req1->elsp_submitted++;
 454 }
 455
 456 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
 457                                            u32 request_id)
 458 {
 459         struct drm_i915_gem_request *head_req;
 460
 461         assert_spin_locked(&ring->execlist_lock);
 462
 463         head_req = list_first_entry_or_null(&ring->execlist_queue,
 464                                             struct drm_i915_gem_request,
 465                                             execlist_link);
 466
 467         if (head_req != NULL) {
 468                 struct drm_i915_gem_object *ctx_obj =
 469                                 head_req->ctx->engine[ring->id].state;
 470                 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
 471                         WARN(head_req->elsp_submitted == 0,
 472                              "Never submitted head request\n");
 473
 474                         if (--head_req->elsp_submitted <= 0) {
 475                                 list_del(&head_req->execlist_link);
 476                                 list_add_tail(&head_req->execlist_link,
 477                                         &ring->execlist_retired_req_list);
 478                                 return true;
 479                         }
 480                 }
 481         }
 482
 483         return false;
 484 }
 485
 486 /**
 487  * intel_lrc_irq_handler() - handle Context Switch interrupts
 488  * @ring: Engine Command Streamer to handle.
 489  *
 490  * Check the unread Context Status Buffers and manage the submission of new
 491  * contexts to the ELSP accordingly.
 492  */
 493 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
 494 {
 495         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 496         u32 status_pointer;
 497         u8 read_pointer;
 498         u8 write_pointer;
 499         u32 status;
 500         u32 status_id;
 501         u32 submit_contexts = 0;
 502
 503         status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
 504
 505         read_pointer = ring->next_context_status_buffer;
 506         write_pointer = status_pointer & 0x07;
 507         if (read_pointer > write_pointer)
 508                 write_pointer += 6;
 509
 510         spin_lock(&ring->execlist_lock);
 511
 512         while (read_pointer < write_pointer) {
 513                 read_pointer++;
 514                 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 515                                 (read_pointer % 6) * 8);
 516                 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
 517                                 (read_pointer % 6) * 8 + 4);
 518
 519                 if (status & GEN8_CTX_STATUS_PREEMPTED) {
 520                         if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
 521                                 if (execlists_check_remove_request(ring, status_id))
 522                                         WARN(1, "Lite Restored request removed from queue\n");
 523                         } else
 524                                 WARN(1, "Preemption without Lite Restore\n");
 525                 }
 526
 527                  if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
 528                      (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
 529                         if (execlists_check_remove_request(ring, status_id))
 530                                 submit_contexts++;
 531                 }
 532         }
 533
 534         if (submit_contexts != 0)
 535                 execlists_context_unqueue(ring);
 536
 537         spin_unlock(&ring->execlist_lock);
 538
 539         WARN(submit_contexts > 2, "More than two context complete events?\n");
 540         ring->next_context_status_buffer = write_pointer % 6;
 541
 542         I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
 543                    ((u32)ring->next_context_status_buffer & 0x07) << 8);
 544 }
 545
 546 static int execlists_context_queue(struct intel_engine_cs *ring,
 547                                    struct intel_context *to,
 548                                    u32 tail,
 549                                    struct drm_i915_gem_request *request)
 550 {
 551         struct drm_i915_gem_request *cursor;
 552         int num_elements = 0;
 553
 554         if (to != ring->default_context)
 555                 intel_lr_context_pin(ring, to);
 556
 557         if (!request) {
 558                 /*
 559                  * If there isn't a request associated with this submission,
 560                  * create one as a temporary holder.
 561                  */
 562                 request = kzalloc(sizeof(*request), GFP_KERNEL);
 563                 if (request == NULL)
 564                         return -ENOMEM;
 565                 request->ring = ring;
 566                 request->ctx = to;
 567                 kref_init(&request->ref);
 568                 i915_gem_context_reference(request->ctx);
 569         } else {
 570                 i915_gem_request_reference(request);
 571                 WARN_ON(to != request->ctx);
 572         }
 573         request->tail = tail;
 574
 575         spin_lock_irq(&ring->execlist_lock);
 576
 577         list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
 578                 if (++num_elements > 2)
 579                         break;
 580
 581         if (num_elements > 2) {
 582                 struct drm_i915_gem_request *tail_req;
 583
 584                 tail_req = list_last_entry(&ring->execlist_queue,
 585                                            struct drm_i915_gem_request,
 586                                            execlist_link);
 587
 588                 if (to == tail_req->ctx) {
 589                         WARN(tail_req->elsp_submitted != 0,
 590                                 "More than 2 already-submitted reqs queued\n");
 591                         list_del(&tail_req->execlist_link);
 592                         list_add_tail(&tail_req->execlist_link,
 593                                 &ring->execlist_retired_req_list);
 594                 }
 595         }
 596
 597         list_add_tail(&request->execlist_link, &ring->execlist_queue);
 598         if (num_elements == 0)
 599                 execlists_context_unqueue(ring);
 600
 601         spin_unlock_irq(&ring->execlist_lock);
 602
 603         return 0;
 604 }
 605
 606 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
 607                                               struct intel_context *ctx)
 608 {
 609         struct intel_engine_cs *ring = ringbuf->ring;
 610         uint32_t flush_domains;
 611         int ret;
 612
 613         flush_domains = 0;
 614         if (ring->gpu_caches_dirty)
 615                 flush_domains = I915_GEM_GPU_DOMAINS;
 616
 617         ret = ring->emit_flush(ringbuf, ctx,
 618                                I915_GEM_GPU_DOMAINS, flush_domains);
 619         if (ret)
 620                 return ret;
 621
 622         ring->gpu_caches_dirty = false;
 623         return 0;
 624 }
 625
 626 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
 627                                  struct intel_context *ctx,
 628                                  struct list_head *vmas)
 629 {
 630         struct intel_engine_cs *ring = ringbuf->ring;
 631         struct i915_vma *vma;
 632         uint32_t flush_domains = 0;
 633         bool flush_chipset = false;
 634         int ret;
 635
 636         list_for_each_entry(vma, vmas, exec_list) {
 637                 struct drm_i915_gem_object *obj = vma->obj;
 638
 639                 ret = i915_gem_object_sync(obj, ring);
 640                 if (ret)
 641                         return ret;
 642
 643                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 644                         flush_chipset |= i915_gem_clflush_object(obj, false);
 645
 646                 flush_domains |= obj->base.write_domain;
 647         }
 648
 649         if (flush_domains & I915_GEM_DOMAIN_GTT)
 650                 wmb();
 651
 652         /* Unconditionally invalidate gpu caches and ensure that we do flush
 653          * any residual writes from the previous batch.
 654          */
 655         return logical_ring_invalidate_all_caches(ringbuf, ctx);
 656 }
 657
 658 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request,
 659                                             struct intel_context *ctx)
 660 {
 661         int ret;
 662
 663         if (ctx != request->ring->default_context) {
 664                 ret = intel_lr_context_pin(request->ring, ctx);
 665                 if (ret)
 666                         return ret;
 667         }
 668
 669         request->ringbuf = ctx->engine[request->ring->id].ringbuf;
 670         request->ctx     = ctx;
 671         i915_gem_context_reference(request->ctx);
 672
 673         return 0;
 674 }
 675
 676 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
 677                                        struct intel_context *ctx,
 678                                        int bytes)
 679 {
 680         struct intel_engine_cs *ring = ringbuf->ring;
 681         struct drm_i915_gem_request *request;
 682         unsigned space;
 683         int ret;
 684
 685         if (intel_ring_space(ringbuf) >= bytes)
 686                 return 0;
 687
 688         list_for_each_entry(request, &ring->request_list, list) {
 689                 /*
 690                  * The request queue is per-engine, so can contain requests
 691                  * from multiple ringbuffers. Here, we must ignore any that
 692                  * aren't from the ringbuffer we're considering.
 693                  */
 694                 if (request->ringbuf != ringbuf)
 695                         continue;
 696
 697                 /* Would completion of this request free enough space? */
 698                 space = __intel_ring_space(request->postfix, ringbuf->tail,
 699                                            ringbuf->size);
 700                 if (space >= bytes)
 701                         break;
 702         }
 703
 704         if (WARN_ON(&request->list == &ring->request_list))
 705                 return -ENOSPC;
 706
 707         ret = i915_wait_request(request);
 708         if (ret)
 709                 return ret;
 710
 711         ringbuf->space = space;
 712         return 0;
 713 }
 714
 715 /*
 716  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
 717  * @ringbuf: Logical Ringbuffer to advance.
 718  *
 719  * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 720  * really happens during submission is that the context and current tail will be placed
 721  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 722  * point, the tail *inside* the context is updated and the ELSP written to.
 723  */
 724 static void
 725 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
 726                                       struct intel_context *ctx,
 727                                       struct drm_i915_gem_request *request)
 728 {
 729         struct intel_engine_cs *ring = ringbuf->ring;
 730
 731         intel_logical_ring_advance(ringbuf);
 732
 733         if (intel_ring_stopped(ring))
 734                 return;
 735
 736         execlists_context_queue(ring, ctx, ringbuf->tail, request);
 737 }
 738
 739 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
 740                                     struct intel_context *ctx)
 741 {
 742         uint32_t __iomem *virt;
 743         int rem = ringbuf->size - ringbuf->tail;
 744
 745         if (ringbuf->space < rem) {
 746                 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
 747
 748                 if (ret)
 749                         return ret;
 750         }
 751
 752         virt = ringbuf->virtual_start + ringbuf->tail;
 753         rem /= 4;
 754         while (rem--)
 755                 iowrite32(MI_NOOP, virt++);
 756
 757         ringbuf->tail = 0;
 758         intel_ring_update_space(ringbuf);
 759
 760         return 0;
 761 }
 762
 763 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
 764                                 struct intel_context *ctx, int bytes)
 765 {
 766         int ret;
 767
 768         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
 769                 ret = logical_ring_wrap_buffer(ringbuf, ctx);
 770                 if (unlikely(ret))
 771                         return ret;
 772         }
 773
 774         if (unlikely(ringbuf->space < bytes)) {
 775                 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
 776                 if (unlikely(ret))
 777                         return ret;
 778         }
 779
 780         return 0;
 781 }
 782
 783 /**
 784  * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
 785  *
 786  * @ringbuf: Logical ringbuffer.
 787  * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
 788  *
 789  * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
 790  * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
 791  * and also preallocates a request (every workload submission is still mediated through
 792  * requests, same as it did with legacy ringbuffer submission).
 793  *
 794  * Return: non-zero if the ringbuffer is not ready to be written to.
 795  */
 796 static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
 797                                     struct intel_context *ctx, int num_dwords)
 798 {
 799         struct intel_engine_cs *ring = ringbuf->ring;
 800         struct drm_device *dev = ring->dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         int ret;
 803
 804         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
 805                                    dev_priv->mm.interruptible);
 806         if (ret)
 807                 return ret;
 808
 809         ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
 810         if (ret)
 811                 return ret;
 812
 813         /* Preallocate the olr before touching the ring */
 814         ret = i915_gem_request_alloc(ring, ctx);
 815         if (ret)
 816                 return ret;
 817
 818         ringbuf->space -= num_dwords * sizeof(uint32_t);
 819         return 0;
 820 }
 821
 822 /**
 823  * execlists_submission() - submit a batchbuffer for execution, Execlists style
 824  * @dev: DRM device.
 825  * @file: DRM file.
 826  * @ring: Engine Command Streamer to submit to.
 827  * @ctx: Context to employ for this submission.
 828  * @args: execbuffer call arguments.
 829  * @vmas: list of vmas.
 830  * @batch_obj: the batchbuffer to submit.
 831  * @exec_start: batchbuffer start virtual address pointer.
 832  * @dispatch_flags: translated execbuffer call flags.
 833  *
 834  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
 835  * away the submission details of the execbuffer ioctl call.
 836  *
 837  * Return: non-zero if the submission fails.
 838  */
 839 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
 840                                struct intel_engine_cs *ring,
 841                                struct intel_context *ctx,
 842                                struct drm_i915_gem_execbuffer2 *args,
 843                                struct list_head *vmas,
 844                                struct drm_i915_gem_object *batch_obj,
 845                                u64 exec_start, u32 dispatch_flags)
 846 {
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 849         int instp_mode;
 850         u32 instp_mask;
 851         int ret;
 852
 853         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
 854         instp_mask = I915_EXEC_CONSTANTS_MASK;
 855         switch (instp_mode) {
 856         case I915_EXEC_CONSTANTS_REL_GENERAL:
 857         case I915_EXEC_CONSTANTS_ABSOLUTE:
 858         case I915_EXEC_CONSTANTS_REL_SURFACE:
 859                 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
 860                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
 861                         return -EINVAL;
 862                 }
 863
 864                 if (instp_mode != dev_priv->relative_constants_mode) {
 865                         if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
 866                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
 867                                 return -EINVAL;
 868                         }
 869
 870                         /* The HW changed the meaning on this bit on gen6 */
 871                         instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
 872                 }
 873                 break;
 874         default:
 875                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
 876                 return -EINVAL;
 877         }
 878
 879         if (args->num_cliprects != 0) {
 880                 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
 881                 return -EINVAL;
 882         } else {
 883                 if (args->DR4 == 0xffffffff) {
 884                         DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 885                         args->DR4 = 0;
 886                 }
 887
 888                 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
 889                         DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
 890                         return -EINVAL;
 891                 }
 892         }
 893
 894         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
 895                 DRM_DEBUG("sol reset is gen7 only\n");
 896                 return -EINVAL;
 897         }
 898
 899         ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
 900         if (ret)
 901                 return ret;
 902
 903         if (ring == &dev_priv->ring[RCS] &&
 904             instp_mode != dev_priv->relative_constants_mode) {
 905                 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
 906                 if (ret)
 907                         return ret;
 908
 909                 intel_logical_ring_emit(ringbuf, MI_NOOP);
 910                 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
 911                 intel_logical_ring_emit(ringbuf, INSTPM);
 912                 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
 913                 intel_logical_ring_advance(ringbuf);
 914
 915                 dev_priv->relative_constants_mode = instp_mode;
 916         }
 917
 918         ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags);
 919         if (ret)
 920                 return ret;
 921
 922         trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
 923
 924         i915_gem_execbuffer_move_to_active(vmas, ring);
 925         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 926
 927         return 0;
 928 }
 929
 930 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
 931 {
 932         struct drm_i915_gem_request *req, *tmp;
 933         struct list_head retired_list;
 934
 935         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 936         if (list_empty(&ring->execlist_retired_req_list))
 937                 return;
 938
 939         INIT_LIST_HEAD(&retired_list);
 940         spin_lock_irq(&ring->execlist_lock);
 941         list_replace_init(&ring->execlist_retired_req_list, &retired_list);
 942         spin_unlock_irq(&ring->execlist_lock);
 943
 944         list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
 945                 struct intel_context *ctx = req->ctx;
 946                 struct drm_i915_gem_object *ctx_obj =
 947                                 ctx->engine[ring->id].state;
 948
 949                 if (ctx_obj && (ctx != ring->default_context))
 950                         intel_lr_context_unpin(ring, ctx);
 951                 list_del(&req->execlist_link);
 952                 i915_gem_request_unreference(req);
 953         }
 954 }
 955
 956 void intel_logical_ring_stop(struct intel_engine_cs *ring)
 957 {
 958         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 959         int ret;
 960
 961         if (!intel_ring_initialized(ring))
 962                 return;
 963
 964         ret = intel_ring_idle(ring);
 965         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
 966                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
 967                           ring->name, ret);
 968
 969         /* TODO: Is this correct with Execlists enabled? */
 970         I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 971         if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 972                 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
 973                 return;
 974         }
 975         I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 976 }
 977
 978 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
 979                                   struct intel_context *ctx)
 980 {
 981         struct intel_engine_cs *ring = ringbuf->ring;
 982         int ret;
 983
 984         if (!ring->gpu_caches_dirty)
 985                 return 0;
 986
 987         ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
 988         if (ret)
 989                 return ret;
 990
 991         ring->gpu_caches_dirty = false;
 992         return 0;
 993 }
 994
 995 static int intel_lr_context_pin(struct intel_engine_cs *ring,
 996                 struct intel_context *ctx)
 997 {
 998         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 999         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1000         int ret = 0;
1001
1002         WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1003         if (ctx->engine[ring->id].pin_count++ == 0) {
1004                 ret = i915_gem_obj_ggtt_pin(ctx_obj,
1005                                 GEN8_LR_CONTEXT_ALIGN, 0);
1006                 if (ret)
1007                         goto reset_pin_count;
1008
1009                 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1010                 if (ret)
1011                         goto unpin_ctx_obj;
1012         }
1013
1014         return ret;
1015
1016 unpin_ctx_obj:
1017         i915_gem_object_ggtt_unpin(ctx_obj);
1018 reset_pin_count:
1019         ctx->engine[ring->id].pin_count = 0;
1020
1021         return ret;
1022 }
1023
1024 void intel_lr_context_unpin(struct intel_engine_cs *ring,
1025                 struct intel_context *ctx)
1026 {
1027         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
1028         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1029
1030         if (ctx_obj) {
1031                 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1032                 if (--ctx->engine[ring->id].pin_count == 0) {
1033                         intel_unpin_ringbuffer_obj(ringbuf);
1034                         i915_gem_object_ggtt_unpin(ctx_obj);
1035                 }
1036         }
1037 }
1038
1039 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1040                                                struct intel_context *ctx)
1041 {
1042         int ret, i;
1043         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1044         struct drm_device *dev = ring->dev;
1045         struct drm_i915_private *dev_priv = dev->dev_private;
1046         struct i915_workarounds *w = &dev_priv->workarounds;
1047
1048         if (WARN_ON_ONCE(w->count == 0))
1049                 return 0;
1050
1051         ring->gpu_caches_dirty = true;
1052         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1053         if (ret)
1054                 return ret;
1055
1056         ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1057         if (ret)
1058                 return ret;
1059
1060         intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1061         for (i = 0; i < w->count; i++) {
1062                 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1063                 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1064         }
1065         intel_logical_ring_emit(ringbuf, MI_NOOP);
1066
1067         intel_logical_ring_advance(ringbuf);
1068
1069         ring->gpu_caches_dirty = true;
1070         ret = logical_ring_flush_all_caches(ringbuf, ctx);
1071         if (ret)
1072                 return ret;
1073
1074         return 0;
1075 }
1076
1077 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1078 {
1079         struct drm_device *dev = ring->dev;
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081
1082         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1083         I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1084
1085         I915_WRITE(RING_MODE_GEN7(ring),
1086                    _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1087                    _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1088         POSTING_READ(RING_MODE_GEN7(ring));
1089         ring->next_context_status_buffer = 0;
1090         DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1091
1092         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1093
1094         return 0;
1095 }
1096
1097 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1098 {
1099         struct drm_device *dev = ring->dev;
1100         struct drm_i915_private *dev_priv = dev->dev_private;
1101         int ret;
1102
1103         ret = gen8_init_common_ring(ring);
1104         if (ret)
1105                 return ret;
1106
1107         /* We need to disable the AsyncFlip performance optimisations in order
1108          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1109          * programmed to '1' on all products.
1110          *
1111          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1112          */
1113         I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1114
1115         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1116
1117         return init_workarounds_ring(ring);
1118 }
1119
1120 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1121 {
1122         int ret;
1123
1124         ret = gen8_init_common_ring(ring);
1125         if (ret)
1126                 return ret;
1127
1128         return init_workarounds_ring(ring);
1129 }
1130
1131 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1132                               struct intel_context *ctx,
1133                               u64 offset, unsigned dispatch_flags)
1134 {
1135         bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1136         int ret;
1137
1138         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1139         if (ret)
1140                 return ret;
1141
1142         /* FIXME(BDW): Address space and security selectors. */
1143         intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1144         intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1145         intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1146         intel_logical_ring_emit(ringbuf, MI_NOOP);
1147         intel_logical_ring_advance(ringbuf);
1148
1149         return 0;
1150 }
1151
1152 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1153 {
1154         struct drm_device *dev = ring->dev;
1155         struct drm_i915_private *dev_priv = dev->dev_private;
1156         unsigned long flags;
1157
1158         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1159                 return false;
1160
1161         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1162         if (ring->irq_refcount++ == 0) {
1163                 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1164                 POSTING_READ(RING_IMR(ring->mmio_base));
1165         }
1166         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1167
1168         return true;
1169 }
1170
1171 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1172 {
1173         struct drm_device *dev = ring->dev;
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         unsigned long flags;
1176
1177         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1178         if (--ring->irq_refcount == 0) {
1179                 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1180                 POSTING_READ(RING_IMR(ring->mmio_base));
1181         }
1182         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1183 }
1184
1185 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1186                            struct intel_context *ctx,
1187                            u32 invalidate_domains,
1188                            u32 unused)
1189 {
1190         struct intel_engine_cs *ring = ringbuf->ring;
1191         struct drm_device *dev = ring->dev;
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         uint32_t cmd;
1194         int ret;
1195
1196         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1197         if (ret)
1198                 return ret;
1199
1200         cmd = MI_FLUSH_DW + 1;
1201
1202         /* We always require a command barrier so that subsequent
1203          * commands, such as breadcrumb interrupts, are strictly ordered
1204          * wrt the contents of the write cache being flushed to memory
1205          * (and thus being coherent from the CPU).
1206          */
1207         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1208
1209         if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1210                 cmd |= MI_INVALIDATE_TLB;
1211                 if (ring == &dev_priv->ring[VCS])
1212                         cmd |= MI_INVALIDATE_BSD;
1213         }
1214
1215         intel_logical_ring_emit(ringbuf, cmd);
1216         intel_logical_ring_emit(ringbuf,
1217                                 I915_GEM_HWS_SCRATCH_ADDR |
1218                                 MI_FLUSH_DW_USE_GTT);
1219         intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1220         intel_logical_ring_emit(ringbuf, 0); /* value */
1221         intel_logical_ring_advance(ringbuf);
1222
1223         return 0;
1224 }
1225
1226 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1227                                   struct intel_context *ctx,
1228                                   u32 invalidate_domains,
1229                                   u32 flush_domains)
1230 {
1231         struct intel_engine_cs *ring = ringbuf->ring;
1232         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1233         bool vf_flush_wa;
1234         u32 flags = 0;
1235         int ret;
1236
1237         flags |= PIPE_CONTROL_CS_STALL;
1238
1239         if (flush_domains) {
1240                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1241                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1242         }
1243
1244         if (invalidate_domains) {
1245                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1246                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1247                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1248                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1249                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1250                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1251                 flags |= PIPE_CONTROL_QW_WRITE;
1252                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1253         }
1254
1255         /*
1256          * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1257          * control.
1258          */
1259         vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1260                       flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1261
1262         ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
1263         if (ret)
1264                 return ret;
1265
1266         if (vf_flush_wa) {
1267                 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1268                 intel_logical_ring_emit(ringbuf, 0);
1269                 intel_logical_ring_emit(ringbuf, 0);
1270                 intel_logical_ring_emit(ringbuf, 0);
1271                 intel_logical_ring_emit(ringbuf, 0);
1272                 intel_logical_ring_emit(ringbuf, 0);
1273         }
1274
1275         intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1276         intel_logical_ring_emit(ringbuf, flags);
1277         intel_logical_ring_emit(ringbuf, scratch_addr);
1278         intel_logical_ring_emit(ringbuf, 0);
1279         intel_logical_ring_emit(ringbuf, 0);
1280         intel_logical_ring_emit(ringbuf, 0);
1281         intel_logical_ring_advance(ringbuf);
1282
1283         return 0;
1284 }
1285
1286 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1287 {
1288         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1289 }
1290
1291 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1292 {
1293         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1294 }
1295
1296 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1297                              struct drm_i915_gem_request *request)
1298 {
1299         struct intel_engine_cs *ring = ringbuf->ring;
1300         u32 cmd;
1301         int ret;
1302
1303         /*
1304          * Reserve space for 2 NOOPs at the end of each request to be
1305          * used as a workaround for not being allowed to do lite
1306          * restore with HEAD==TAIL (WaIdleLiteRestore).
1307          */
1308         ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
1309         if (ret)
1310                 return ret;
1311
1312         cmd = MI_STORE_DWORD_IMM_GEN4;
1313         cmd |= MI_GLOBAL_GTT;
1314
1315         intel_logical_ring_emit(ringbuf, cmd);
1316         intel_logical_ring_emit(ringbuf,
1317                                 (ring->status_page.gfx_addr +
1318                                 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1319         intel_logical_ring_emit(ringbuf, 0);
1320         intel_logical_ring_emit(ringbuf,
1321                 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1322         intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1323         intel_logical_ring_emit(ringbuf, MI_NOOP);
1324         intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1325
1326         /*
1327          * Here we add two extra NOOPs as padding to avoid
1328          * lite restore of a context with HEAD==TAIL.
1329          */
1330         intel_logical_ring_emit(ringbuf, MI_NOOP);
1331         intel_logical_ring_emit(ringbuf, MI_NOOP);
1332         intel_logical_ring_advance(ringbuf);
1333
1334         return 0;
1335 }
1336
1337 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1338                                               struct intel_context *ctx)
1339 {
1340         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1341         struct render_state so;
1342         struct drm_i915_file_private *file_priv = ctx->file_priv;
1343         struct drm_file *file = file_priv ? file_priv->file : NULL;
1344         int ret;
1345
1346         ret = i915_gem_render_state_prepare(ring, &so);
1347         if (ret)
1348                 return ret;
1349
1350         if (so.rodata == NULL)
1351                 return 0;
1352
1353         ret = ring->emit_bb_start(ringbuf,
1354                         ctx,
1355                         so.ggtt_offset,
1356                         I915_DISPATCH_SECURE);
1357         if (ret)
1358                 goto out;
1359
1360         i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1361
1362         ret = __i915_add_request(ring, file, so.obj);
1363         /* intel_logical_ring_add_request moves object to inactive if it
1364          * fails */
1365 out:
1366         i915_gem_render_state_fini(&so);
1367         return ret;
1368 }
1369
1370 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1371                        struct intel_context *ctx)
1372 {
1373         int ret;
1374
1375         ret = intel_logical_ring_workarounds_emit(ring, ctx);
1376         if (ret)
1377                 return ret;
1378
1379         return intel_lr_context_render_state_init(ring, ctx);
1380 }
1381
1382 /**
1383  * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1384  *
1385  * @ring: Engine Command Streamer.
1386  *
1387  */
1388 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1389 {
1390         struct drm_i915_private *dev_priv;
1391
1392         if (!intel_ring_initialized(ring))
1393                 return;
1394
1395         dev_priv = ring->dev->dev_private;
1396
1397         intel_logical_ring_stop(ring);
1398         WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1399         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1400
1401         if (ring->cleanup)
1402                 ring->cleanup(ring);
1403
1404         i915_cmd_parser_fini_ring(ring);
1405         i915_gem_batch_pool_fini(&ring->batch_pool);
1406
1407         if (ring->status_page.obj) {
1408                 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1409                 ring->status_page.obj = NULL;
1410         }
1411 }
1412
1413 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1414 {
1415         int ret;
1416
1417         /* Intentionally left blank. */
1418         ring->buffer = NULL;
1419
1420         ring->dev = dev;
1421         INIT_LIST_HEAD(&ring->active_list);
1422         INIT_LIST_HEAD(&ring->request_list);
1423         i915_gem_batch_pool_init(dev, &ring->batch_pool);
1424         init_waitqueue_head(&ring->irq_queue);
1425
1426         INIT_LIST_HEAD(&ring->execlist_queue);
1427         INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1428         spin_lock_init(&ring->execlist_lock);
1429
1430         ret = i915_cmd_parser_init_ring(ring);
1431         if (ret)
1432                 return ret;
1433
1434         ret = intel_lr_context_deferred_create(ring->default_context, ring);
1435
1436         return ret;
1437 }
1438
1439 static int logical_render_ring_init(struct drm_device *dev)
1440 {
1441         struct drm_i915_private *dev_priv = dev->dev_private;
1442         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1443         int ret;
1444
1445         ring->name = "render ring";
1446         ring->id = RCS;
1447         ring->mmio_base = RENDER_RING_BASE;
1448         ring->irq_enable_mask =
1449                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1450         ring->irq_keep_mask =
1451                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1452         if (HAS_L3_DPF(dev))
1453                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1454
1455         if (INTEL_INFO(dev)->gen >= 9)
1456                 ring->init_hw = gen9_init_render_ring;
1457         else
1458                 ring->init_hw = gen8_init_render_ring;
1459         ring->init_context = gen8_init_rcs_context;
1460         ring->cleanup = intel_fini_pipe_control;
1461         ring->get_seqno = gen8_get_seqno;
1462         ring->set_seqno = gen8_set_seqno;
1463         ring->emit_request = gen8_emit_request;
1464         ring->emit_flush = gen8_emit_flush_render;
1465         ring->irq_get = gen8_logical_ring_get_irq;
1466         ring->irq_put = gen8_logical_ring_put_irq;
1467         ring->emit_bb_start = gen8_emit_bb_start;
1468
1469         ring->dev = dev;
1470         ret = logical_ring_init(dev, ring);
1471         if (ret)
1472                 return ret;
1473
1474         return intel_init_pipe_control(ring);
1475 }
1476
1477 static int logical_bsd_ring_init(struct drm_device *dev)
1478 {
1479         struct drm_i915_private *dev_priv = dev->dev_private;
1480         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1481
1482         ring->name = "bsd ring";
1483         ring->id = VCS;
1484         ring->mmio_base = GEN6_BSD_RING_BASE;
1485         ring->irq_enable_mask =
1486                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1487         ring->irq_keep_mask =
1488                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1489
1490         ring->init_hw = gen8_init_common_ring;
1491         ring->get_seqno = gen8_get_seqno;
1492         ring->set_seqno = gen8_set_seqno;
1493         ring->emit_request = gen8_emit_request;
1494         ring->emit_flush = gen8_emit_flush;
1495         ring->irq_get = gen8_logical_ring_get_irq;
1496         ring->irq_put = gen8_logical_ring_put_irq;
1497         ring->emit_bb_start = gen8_emit_bb_start;
1498
1499         return logical_ring_init(dev, ring);
1500 }
1501
1502 static int logical_bsd2_ring_init(struct drm_device *dev)
1503 {
1504         struct drm_i915_private *dev_priv = dev->dev_private;
1505         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1506
1507         ring->name = "bds2 ring";
1508         ring->id = VCS2;
1509         ring->mmio_base = GEN8_BSD2_RING_BASE;
1510         ring->irq_enable_mask =
1511                 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1512         ring->irq_keep_mask =
1513                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1514
1515         ring->init_hw = gen8_init_common_ring;
1516         ring->get_seqno = gen8_get_seqno;
1517         ring->set_seqno = gen8_set_seqno;
1518         ring->emit_request = gen8_emit_request;
1519         ring->emit_flush = gen8_emit_flush;
1520         ring->irq_get = gen8_logical_ring_get_irq;
1521         ring->irq_put = gen8_logical_ring_put_irq;
1522         ring->emit_bb_start = gen8_emit_bb_start;
1523
1524         return logical_ring_init(dev, ring);
1525 }
1526
1527 static int logical_blt_ring_init(struct drm_device *dev)
1528 {
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1531
1532         ring->name = "blitter ring";
1533         ring->id = BCS;
1534         ring->mmio_base = BLT_RING_BASE;
1535         ring->irq_enable_mask =
1536                 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1537         ring->irq_keep_mask =
1538                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1539
1540         ring->init_hw = gen8_init_common_ring;
1541         ring->get_seqno = gen8_get_seqno;
1542         ring->set_seqno = gen8_set_seqno;
1543         ring->emit_request = gen8_emit_request;
1544         ring->emit_flush = gen8_emit_flush;
1545         ring->irq_get = gen8_logical_ring_get_irq;
1546         ring->irq_put = gen8_logical_ring_put_irq;
1547         ring->emit_bb_start = gen8_emit_bb_start;
1548
1549         return logical_ring_init(dev, ring);
1550 }
1551
1552 static int logical_vebox_ring_init(struct drm_device *dev)
1553 {
1554         struct drm_i915_private *dev_priv = dev->dev_private;
1555         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1556
1557         ring->name = "video enhancement ring";
1558         ring->id = VECS;
1559         ring->mmio_base = VEBOX_RING_BASE;
1560         ring->irq_enable_mask =
1561                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1562         ring->irq_keep_mask =
1563                 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1564
1565         ring->init_hw = gen8_init_common_ring;
1566         ring->get_seqno = gen8_get_seqno;
1567         ring->set_seqno = gen8_set_seqno;
1568         ring->emit_request = gen8_emit_request;
1569         ring->emit_flush = gen8_emit_flush;
1570         ring->irq_get = gen8_logical_ring_get_irq;
1571         ring->irq_put = gen8_logical_ring_put_irq;
1572         ring->emit_bb_start = gen8_emit_bb_start;
1573
1574         return logical_ring_init(dev, ring);
1575 }
1576
1577 /**
1578  * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1579  * @dev: DRM device.
1580  *
1581  * This function inits the engines for an Execlists submission style (the equivalent in the
1582  * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1583  * those engines that are present in the hardware.
1584  *
1585  * Return: non-zero if the initialization failed.
1586  */
1587 int intel_logical_rings_init(struct drm_device *dev)
1588 {
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         int ret;
1591
1592         ret = logical_render_ring_init(dev);
1593         if (ret)
1594                 return ret;
1595
1596         if (HAS_BSD(dev)) {
1597                 ret = logical_bsd_ring_init(dev);
1598                 if (ret)
1599                         goto cleanup_render_ring;
1600         }
1601
1602         if (HAS_BLT(dev)) {
1603                 ret = logical_blt_ring_init(dev);
1604                 if (ret)
1605                         goto cleanup_bsd_ring;
1606         }
1607
1608         if (HAS_VEBOX(dev)) {
1609                 ret = logical_vebox_ring_init(dev);
1610                 if (ret)
1611                         goto cleanup_blt_ring;
1612         }
1613
1614         if (HAS_BSD2(dev)) {
1615                 ret = logical_bsd2_ring_init(dev);
1616                 if (ret)
1617                         goto cleanup_vebox_ring;
1618         }
1619
1620         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1621         if (ret)
1622                 goto cleanup_bsd2_ring;
1623
1624         return 0;
1625
1626 cleanup_bsd2_ring:
1627         intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1628 cleanup_vebox_ring:
1629         intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1630 cleanup_blt_ring:
1631         intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1632 cleanup_bsd_ring:
1633         intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1634 cleanup_render_ring:
1635         intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1636
1637         return ret;
1638 }
1639
1640 static u32
1641 make_rpcs(struct drm_device *dev)
1642 {
1643         u32 rpcs = 0;
1644
1645         /*
1646          * No explicit RPCS request is needed to ensure full
1647          * slice/subslice/EU enablement prior to Gen9.
1648         */
1649         if (INTEL_INFO(dev)->gen < 9)
1650                 return 0;
1651
1652         /*
1653          * Starting in Gen9, render power gating can leave
1654          * slice/subslice/EU in a partially enabled state. We
1655          * must make an explicit request through RPCS for full
1656          * enablement.
1657         */
1658         if (INTEL_INFO(dev)->has_slice_pg) {
1659                 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1660                 rpcs |= INTEL_INFO(dev)->slice_total <<
1661                         GEN8_RPCS_S_CNT_SHIFT;
1662                 rpcs |= GEN8_RPCS_ENABLE;
1663         }
1664
1665         if (INTEL_INFO(dev)->has_subslice_pg) {
1666                 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1667                 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1668                         GEN8_RPCS_SS_CNT_SHIFT;
1669                 rpcs |= GEN8_RPCS_ENABLE;
1670         }
1671
1672         if (INTEL_INFO(dev)->has_eu_pg) {
1673                 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1674                         GEN8_RPCS_EU_MIN_SHIFT;
1675                 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1676                         GEN8_RPCS_EU_MAX_SHIFT;
1677                 rpcs |= GEN8_RPCS_ENABLE;
1678         }
1679
1680         return rpcs;
1681 }
1682
1683 static int
1684 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1685                     struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1686 {
1687         struct drm_device *dev = ring->dev;
1688         struct drm_i915_private *dev_priv = dev->dev_private;
1689         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1690         struct page *page;
1691         uint32_t *reg_state;
1692         int ret;
1693
1694         if (!ppgtt)
1695                 ppgtt = dev_priv->mm.aliasing_ppgtt;
1696
1697         ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1698         if (ret) {
1699                 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1700                 return ret;
1701         }
1702
1703         ret = i915_gem_object_get_pages(ctx_obj);
1704         if (ret) {
1705                 DRM_DEBUG_DRIVER("Could not get object pages\n");
1706                 return ret;
1707         }
1708
1709         i915_gem_object_pin_pages(ctx_obj);
1710
1711         /* The second page of the context object contains some fields which must
1712          * be set up prior to the first execution. */
1713         page = i915_gem_object_get_page(ctx_obj, 1);
1714         reg_state = kmap_atomic(page);
1715
1716         /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1717          * commands followed by (reg, value) pairs. The values we are setting here are
1718          * only for the first context restore: on a subsequent save, the GPU will
1719          * recreate this batchbuffer with new values (including all the missing
1720          * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1721         if (ring->id == RCS)
1722                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1723         else
1724                 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1725         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1726         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1727         reg_state[CTX_CONTEXT_CONTROL+1] =
1728                 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1729                                 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1730         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1731         reg_state[CTX_RING_HEAD+1] = 0;
1732         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1733         reg_state[CTX_RING_TAIL+1] = 0;
1734         reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1735         /* Ring buffer start address is not known until the buffer is pinned.
1736          * It is written to the context image in execlists_update_context()
1737          */
1738         reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1739         reg_state[CTX_RING_BUFFER_CONTROL+1] =
1740                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1741         reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1742         reg_state[CTX_BB_HEAD_U+1] = 0;
1743         reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1744         reg_state[CTX_BB_HEAD_L+1] = 0;
1745         reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1746         reg_state[CTX_BB_STATE+1] = (1<<5);
1747         reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1748         reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1749         reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1750         reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1751         reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1752         reg_state[CTX_SECOND_BB_STATE+1] = 0;
1753         if (ring->id == RCS) {
1754                 /* TODO: according to BSpec, the register state context
1755                  * for CHV does not have these. OTOH, these registers do
1756                  * exist in CHV. I'm waiting for a clarification */
1757                 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1758                 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1759                 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1760                 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1761                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1762                 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1763         }
1764         reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1765         reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1766         reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1767         reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1768         reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1769         reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1770         reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1771         reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1772         reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1773         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1774         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1775         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1776
1777         /* With dynamic page allocation, PDPs may not be allocated at this point,
1778          * Point the unallocated PDPs to the scratch page
1779          */
1780         ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
1781         ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
1782         ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
1783         ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
1784         if (ring->id == RCS) {
1785                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1786                 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
1787                 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
1788         }
1789
1790         kunmap_atomic(reg_state);
1791
1792         ctx_obj->dirty = 1;
1793         set_page_dirty(page);
1794         i915_gem_object_unpin_pages(ctx_obj);
1795
1796         return 0;
1797 }
1798
1799 /**
1800  * intel_lr_context_free() - free the LRC specific bits of a context
1801  * @ctx: the LR context to free.
1802  *
1803  * The real context freeing is done in i915_gem_context_free: this only
1804  * takes care of the bits that are LRC related: the per-engine backing
1805  * objects and the logical ringbuffer.
1806  */
1807 void intel_lr_context_free(struct intel_context *ctx)
1808 {
1809         int i;
1810
1811         for (i = 0; i < I915_NUM_RINGS; i++) {
1812                 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1813
1814                 if (ctx_obj) {
1815                         struct intel_ringbuffer *ringbuf =
1816                                         ctx->engine[i].ringbuf;
1817                         struct intel_engine_cs *ring = ringbuf->ring;
1818
1819                         if (ctx == ring->default_context) {
1820                                 intel_unpin_ringbuffer_obj(ringbuf);
1821                                 i915_gem_object_ggtt_unpin(ctx_obj);
1822                         }
1823                         WARN_ON(ctx->engine[ring->id].pin_count);
1824                         intel_destroy_ringbuffer_obj(ringbuf);
1825                         kfree(ringbuf);
1826                         drm_gem_object_unreference(&ctx_obj->base);
1827                 }
1828         }
1829 }
1830
1831 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1832 {
1833         int ret = 0;
1834
1835         WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1836
1837         switch (ring->id) {
1838         case RCS:
1839                 if (INTEL_INFO(ring->dev)->gen >= 9)
1840                         ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1841                 else
1842                         ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1843                 break;
1844         case VCS:
1845         case BCS:
1846         case VECS:
1847         case VCS2:
1848                 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1849                 break;
1850         }
1851
1852         return ret;
1853 }
1854
1855 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1856                 struct drm_i915_gem_object *default_ctx_obj)
1857 {
1858         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1859
1860         /* The status page is offset 0 from the default context object
1861          * in LRC mode. */
1862         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1863         ring->status_page.page_addr =
1864                         kmap(sg_page(default_ctx_obj->pages->sgl));
1865         ring->status_page.obj = default_ctx_obj;
1866
1867         I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1868                         (u32)ring->status_page.gfx_addr);
1869         POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1870 }
1871
1872 /**
1873  * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1874  * @ctx: LR context to create.
1875  * @ring: engine to be used with the context.
1876  *
1877  * This function can be called more than once, with different engines, if we plan
1878  * to use the context with them. The context backing objects and the ringbuffers
1879  * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1880  * the creation is a deferred call: it's better to make sure first that we need to use
1881  * a given ring with the context.
1882  *
1883  * Return: non-zero on error.
1884  */
1885 int intel_lr_context_deferred_create(struct intel_context *ctx,
1886                                      struct intel_engine_cs *ring)
1887 {
1888         const bool is_global_default_ctx = (ctx == ring->default_context);
1889         struct drm_device *dev = ring->dev;
1890         struct drm_i915_gem_object *ctx_obj;
1891         uint32_t context_size;
1892         struct intel_ringbuffer *ringbuf;
1893         int ret;
1894
1895         WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1896         WARN_ON(ctx->engine[ring->id].state);
1897
1898         context_size = round_up(get_lr_context_size(ring), 4096);
1899
1900         ctx_obj = i915_gem_alloc_object(dev, context_size);
1901         if (!ctx_obj) {
1902                 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
1903                 return -ENOMEM;
1904         }
1905
1906         if (is_global_default_ctx) {
1907                 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1908                 if (ret) {
1909                         DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1910                                         ret);
1911                         drm_gem_object_unreference(&ctx_obj->base);
1912                         return ret;
1913                 }
1914         }
1915
1916         ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1917         if (!ringbuf) {
1918                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1919                                 ring->name);
1920                 ret = -ENOMEM;
1921                 goto error_unpin_ctx;
1922         }
1923
1924         ringbuf->ring = ring;
1925
1926         ringbuf->size = 32 * PAGE_SIZE;
1927         ringbuf->effective_size = ringbuf->size;
1928         ringbuf->head = 0;
1929         ringbuf->tail = 0;
1930         ringbuf->last_retired_head = -1;
1931         intel_ring_update_space(ringbuf);
1932
1933         if (ringbuf->obj == NULL) {
1934                 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1935                 if (ret) {
1936                         DRM_DEBUG_DRIVER(
1937                                 "Failed to allocate ringbuffer obj %s: %d\n",
1938                                 ring->name, ret);
1939                         goto error_free_rbuf;
1940                 }
1941
1942                 if (is_global_default_ctx) {
1943                         ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1944                         if (ret) {
1945                                 DRM_ERROR(
1946                                         "Failed to pin and map ringbuffer %s: %d\n",
1947                                         ring->name, ret);
1948                                 goto error_destroy_rbuf;
1949                         }
1950                 }
1951
1952         }
1953
1954         ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1955         if (ret) {
1956                 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1957                 goto error;
1958         }
1959
1960         ctx->engine[ring->id].ringbuf = ringbuf;
1961         ctx->engine[ring->id].state = ctx_obj;
1962
1963         if (ctx == ring->default_context)
1964                 lrc_setup_hardware_status_page(ring, ctx_obj);
1965         else if (ring->id == RCS && !ctx->rcs_initialized) {
1966                 if (ring->init_context) {
1967                         ret = ring->init_context(ring, ctx);
1968                         if (ret) {
1969                                 DRM_ERROR("ring init context: %d\n", ret);
1970                                 ctx->engine[ring->id].ringbuf = NULL;
1971                                 ctx->engine[ring->id].state = NULL;
1972                                 goto error;
1973                         }
1974                 }
1975
1976                 ctx->rcs_initialized = true;
1977         }
1978
1979         return 0;
1980
1981 error:
1982         if (is_global_default_ctx)
1983                 intel_unpin_ringbuffer_obj(ringbuf);
1984 error_destroy_rbuf:
1985         intel_destroy_ringbuffer_obj(ringbuf);
1986 error_free_rbuf:
1987         kfree(ringbuf);
1988 error_unpin_ctx:
1989         if (is_global_default_ctx)
1990                 i915_gem_object_ggtt_unpin(ctx_obj);
1991         drm_gem_object_unreference(&ctx_obj->base);
1992         return ret;
1993 }
1994
1995 void intel_lr_context_reset(struct drm_device *dev,
1996                         struct intel_context *ctx)
1997 {
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_engine_cs *ring;
2000         int i;
2001
2002         for_each_ring(ring, dev_priv, i) {
2003                 struct drm_i915_gem_object *ctx_obj =
2004                                 ctx->engine[ring->id].state;
2005                 struct intel_ringbuffer *ringbuf =
2006                                 ctx->engine[ring->id].ringbuf;
2007                 uint32_t *reg_state;
2008                 struct page *page;
2009
2010                 if (!ctx_obj)
2011                         continue;
2012
2013                 if (i915_gem_object_get_pages(ctx_obj)) {
2014                         WARN(1, "Failed get_pages for context obj\n");
2015                         continue;
2016                 }
2017                 page = i915_gem_object_get_page(ctx_obj, 1);
2018                 reg_state = kmap_atomic(page);
2019
2020                 reg_state[CTX_RING_HEAD+1] = 0;
2021                 reg_state[CTX_RING_TAIL+1] = 0;
2022
2023                 kunmap_atomic(reg_state);
2024
2025                 ringbuf->head = 0;
2026                 ringbuf->tail = 0;
2027         }
2028 }