drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 /*
   5  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
   6  * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
   7  * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
   8  *
   9  * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
  10  * cacheline, the Head Pointer must not be greater than the Tail
  11  * Pointer."
  12  */
  13 #define I915_RING_FREE_SPACE 64
  14
  15 struct  intel_hw_status_page {
  16         u32             *page_addr;
  17         unsigned int    gfx_addr;
  18         struct          drm_i915_gem_object *obj;
  19 };
  20
  21 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  22 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  23
  24 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  25 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  26
  27 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  28 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  29
  30 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  31 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  32
  33 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  34 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  35
  36 enum intel_ring_hangcheck_action {
  37         HANGCHECK_IDLE = 0,
  38         HANGCHECK_WAIT,
  39         HANGCHECK_ACTIVE,
  40         HANGCHECK_KICK,
  41         HANGCHECK_HUNG,
  42 };
  43
  44 #define HANGCHECK_SCORE_RING_HUNG 31
  45
  46 struct intel_ring_hangcheck {
  47         bool deadlock;
  48         u32 seqno;
  49         u32 acthd;
  50         int score;
  51         enum intel_ring_hangcheck_action action;
  52 };
  53
  54 struct  intel_ring_buffer {
  55         const char      *name;
  56         enum intel_ring_id {
  57                 RCS = 0x0,
  58                 VCS,
  59                 BCS,
  60                 VECS,
  61         } id;
  62 #define I915_NUM_RINGS 4
  63         u32             mmio_base;
  64         void            __iomem *virtual_start;
  65         struct          drm_device *dev;
  66         struct          drm_i915_gem_object *obj;
  67
  68         u32             head;
  69         u32             tail;
  70         int             space;
  71         int             size;
  72         int             effective_size;
  73         struct intel_hw_status_page status_page;
  74
  75         /** We track the position of the requests in the ring buffer, and
  76          * when each is retired we increment last_retired_head as the GPU
  77          * must have finished processing the request and so we know we
  78          * can advance the ringbuffer up to that position.
  79          *
  80          * last_retired_head is set to -1 after the value is consumed so
  81          * we can detect new retirements.
  82          */
  83         u32             last_retired_head;
  84
  85         unsigned irq_refcount; /* protected by dev_priv->irq_lock */
  86         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
  87         u32             trace_irq_seqno;
  88         u32             sync_seqno[I915_NUM_RINGS-1];
  89         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  90         void            (*irq_put)(struct intel_ring_buffer *ring);
  91
  92         int             (*init)(struct intel_ring_buffer *ring);
  93
  94         void            (*write_tail)(struct intel_ring_buffer *ring,
  95                                       u32 value);
  96         int __must_check (*flush)(struct intel_ring_buffer *ring,
  97                                   u32   invalidate_domains,
  98                                   u32   flush_domains);
  99         int             (*add_request)(struct intel_ring_buffer *ring);
 100         /* Some chipsets are not quite as coherent as advertised and need
 101          * an expensive kick to force a true read of the up-to-date seqno.
 102          * However, the up-to-date seqno is not always required and the last
 103          * seen value is good enough. Note that the seqno will always be
 104          * monotonic, even if not coherent.
 105          */
 106         u32             (*get_seqno)(struct intel_ring_buffer *ring,
 107                                      bool lazy_coherency);
 108         void            (*set_seqno)(struct intel_ring_buffer *ring,
 109                                      u32 seqno);
 110         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
 111                                                u32 offset, u32 length,
 112                                                unsigned flags);
 113 #define I915_DISPATCH_SECURE 0x1
 114 #define I915_DISPATCH_PINNED 0x2
 115         void            (*cleanup)(struct intel_ring_buffer *ring);
 116         int             (*sync_to)(struct intel_ring_buffer *ring,
 117                                    struct intel_ring_buffer *to,
 118                                    u32 seqno);
 119
 120         /* our mbox written by others */
 121         u32             semaphore_register[I915_NUM_RINGS];
 122         /* mboxes this ring signals to */
 123         u32             signal_mbox[I915_NUM_RINGS];
 124
 125         /**
 126          * List of objects currently involved in rendering from the
 127          * ringbuffer.
 128          *
 129          * Includes buffers having the contents of their GPU caches
 130          * flushed, not necessarily primitives.  last_rendering_seqno
 131          * represents when the rendering involved will be completed.
 132          *
 133          * A reference is held on the buffer while on this list.
 134          */
 135         struct list_head active_list;
 136
 137         /**
 138          * List of breadcrumbs associated with GPU requests currently
 139          * outstanding.
 140          */
 141         struct list_head request_list;
 142
 143         /**
 144          * Do we have some not yet emitted requests outstanding?
 145          */
 146         struct drm_i915_gem_request *preallocated_lazy_request;
 147         u32 outstanding_lazy_seqno;
 148         bool gpu_caches_dirty;
 149         bool fbc_dirty;
 150
 151         wait_queue_head_t irq_queue;
 152
 153         /**
 154          * Do an explicit TLB flush before MI_SET_CONTEXT
 155          */
 156         bool itlb_before_ctx_switch;
 157         struct i915_hw_context *default_context;
 158         struct i915_hw_context *last_context;
 159
 160         struct intel_ring_hangcheck hangcheck;
 161
 162         struct {
 163                 struct drm_i915_gem_object *obj;
 164                 u32 gtt_offset;
 165                 volatile u32 *cpu_page;
 166         } scratch;
 167 };
 168
 169 static inline bool
 170 intel_ring_initialized(struct intel_ring_buffer *ring)
 171 {
 172         return ring->obj != NULL;
 173 }
 174
 175 static inline unsigned
 176 intel_ring_flag(struct intel_ring_buffer *ring)
 177 {
 178         return 1 << ring->id;
 179 }
 180
 181 static inline u32
 182 intel_ring_sync_index(struct intel_ring_buffer *ring,
 183                       struct intel_ring_buffer *other)
 184 {
 185         int idx;
 186
 187         /*
 188          * cs -> 0 = vcs, 1 = bcs
 189          * vcs -> 0 = bcs, 1 = cs,
 190          * bcs -> 0 = cs, 1 = vcs.
 191          */
 192
 193         idx = (other - ring) - 1;
 194         if (idx < 0)
 195                 idx += I915_NUM_RINGS;
 196
 197         return idx;
 198 }
 199
 200 static inline u32
 201 intel_read_status_page(struct intel_ring_buffer *ring,
 202                        int reg)
 203 {
 204         /* Ensure that the compiler doesn't optimize away the load. */
 205         barrier();
 206         return ring->status_page.page_addr[reg];
 207 }
 208
 209 static inline void
 210 intel_write_status_page(struct intel_ring_buffer *ring,
 211                         int reg, u32 value)
 212 {
 213         ring->status_page.page_addr[reg] = value;
 214 }
 215
 216 /**
 217  * Reads a dword out of the status page, which is written to from the command
 218  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 219  * MI_STORE_DATA_IMM.
 220  *
 221  * The following dwords have a reserved meaning:
 222  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 223  * 0x04: ring 0 head pointer
 224  * 0x05: ring 1 head pointer (915-class)
 225  * 0x06: ring 2 head pointer (915-class)
 226  * 0x10-0x1b: Context status DWords (GM45)
 227  * 0x1f: Last written status offset. (GM45)
 228  *
 229  * The area from dword 0x20 to 0x3ff is available for driver usage.
 230  */
 231 #define I915_GEM_HWS_INDEX              0x20
 232 #define I915_GEM_HWS_SCRATCH_INDEX      0x30
 233 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 234
 235 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 236
 237 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 238 int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
 239 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 240                                    u32 data)
 241 {
 242         iowrite32(data, ring->virtual_start + ring->tail);
 243         ring->tail += 4;
 244 }
 245 static inline void intel_ring_advance(struct intel_ring_buffer *ring)
 246 {
 247         ring->tail &= ring->size - 1;
 248 }
 249 void __intel_ring_advance(struct intel_ring_buffer *ring);
 250
 251 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 252 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
 253 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
 254 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 255
 256 int intel_init_render_ring_buffer(struct drm_device *dev);
 257 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 258 int intel_init_blt_ring_buffer(struct drm_device *dev);
 259 int intel_init_vebox_ring_buffer(struct drm_device *dev);
 260
 261 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 262 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 263
 264 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
 265 {
 266         return ring->tail;
 267 }
 268
 269 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
 270 {
 271         BUG_ON(ring->outstanding_lazy_seqno == 0);
 272         return ring->outstanding_lazy_seqno;
 273 }
 274
 275 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 276 {
 277         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 278                 ring->trace_irq_seqno = seqno;
 279 }
 280
 281 /* DRI warts */
 282 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 283
 284 #endif /* _INTEL_RINGBUFFER_H_ */