drivers/gpu/drm/i915/intel_uncore.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/pm_runtime.h>
  25 #include <asm/iosf_mbi.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "i915_vgpu.h"
  30 #include "intel_pm.h"
  31
  32 #define FORCEWAKE_ACK_TIMEOUT_MS 50
  33 #define GT_FIFO_TIMEOUT_MS       10
  34
  35 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
  36
  37 void
  38 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
  39 {
  40         spin_lock_init(&mmio_debug->lock);
  41         mmio_debug->unclaimed_mmio_check = 1;
  42 }
  43
  44 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug)
  45 {
  46         lockdep_assert_held(&mmio_debug->lock);
  47
  48         /* Save and disable mmio debugging for the user bypass */
  49         if (!mmio_debug->suspend_count++) {
  50                 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check;
  51                 mmio_debug->unclaimed_mmio_check = 0;
  52         }
  53 }
  54
  55 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug)
  56 {
  57         lockdep_assert_held(&mmio_debug->lock);
  58
  59         if (!--mmio_debug->suspend_count)
  60                 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check;
  61 }
  62
  63 static const char * const forcewake_domain_names[] = {
  64         "render",
  65         "blitter",
  66         "media",
  67         "vdbox0",
  68         "vdbox1",
  69         "vdbox2",
  70         "vdbox3",
  71         "vebox0",
  72         "vebox1",
  73 };
  74
  75 const char *
  76 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
  77 {
  78         BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
  79
  80         if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
  81                 return forcewake_domain_names[id];
  82
  83         WARN_ON(id);
  84
  85         return "unknown";
  86 }
  87
  88 #define fw_ack(d) readl((d)->reg_ack)
  89 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
  90 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
  91
  92 static inline void
  93 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  94 {
  95         /*
  96          * We don't really know if the powerwell for the forcewake domain we are
  97          * trying to reset here does exist at this point (engines could be fused
  98          * off in ICL+), so no waiting for acks
  99          */
 100         /* WaRsClearFWBitsAtReset:bdw,skl */
 101         fw_clear(d, 0xffff);
 102 }
 103
 104 static inline void
 105 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
 106 {
 107         GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
 108         d->uncore->fw_domains_timer |= d->mask;
 109         d->wake_count++;
 110         hrtimer_start_range_ns(&d->timer,
 111                                NSEC_PER_MSEC,
 112                                NSEC_PER_MSEC,
 113                                HRTIMER_MODE_REL);
 114 }
 115
 116 static inline int
 117 __wait_for_ack(const struct intel_uncore_forcewake_domain *d,
 118                const u32 ack,
 119                const u32 value)
 120 {
 121         return wait_for_atomic((fw_ack(d) & ack) == value,
 122                                FORCEWAKE_ACK_TIMEOUT_MS);
 123 }
 124
 125 static inline int
 126 wait_ack_clear(const struct intel_uncore_forcewake_domain *d,
 127                const u32 ack)
 128 {
 129         return __wait_for_ack(d, ack, 0);
 130 }
 131
 132 static inline int
 133 wait_ack_set(const struct intel_uncore_forcewake_domain *d,
 134              const u32 ack)
 135 {
 136         return __wait_for_ack(d, ack, ack);
 137 }
 138
 139 static inline void
 140 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
 141 {
 142         if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
 143                 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
 144                           intel_uncore_forcewake_domain_to_str(d->id));
 145                 add_taint_for_CI(TAINT_WARN); /* CI now unreliable */
 146         }
 147 }
 148
 149 enum ack_type {
 150         ACK_CLEAR = 0,
 151         ACK_SET
 152 };
 153
 154 static int
 155 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 156                                  const enum ack_type type)
 157 {
 158         const u32 ack_bit = FORCEWAKE_KERNEL;
 159         const u32 value = type == ACK_SET ? ack_bit : 0;
 160         unsigned int pass;
 161         bool ack_detected;
 162
 163         /*
 164          * There is a possibility of driver's wake request colliding
 165          * with hardware's own wake requests and that can cause
 166          * hardware to not deliver the driver's ack message.
 167          *
 168          * Use a fallback bit toggle to kick the gpu state machine
 169          * in the hope that the original ack will be delivered along with
 170          * the fallback ack.
 171          *
 172          * This workaround is described in HSDES #1604254524 and it's known as:
 173          * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
 174          * although the name is a bit misleading.
 175          */
 176
 177         pass = 1;
 178         do {
 179                 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 180
 181                 fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
 182                 /* Give gt some time to relax before the polling frenzy */
 183                 udelay(10 * pass);
 184                 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
 185
 186                 ack_detected = (fw_ack(d) & ack_bit) == value;
 187
 188                 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
 189         } while (!ack_detected && pass++ < 10);
 190
 191         DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
 192                          intel_uncore_forcewake_domain_to_str(d->id),
 193                          type == ACK_SET ? "set" : "clear",
 194                          fw_ack(d),
 195                          pass);
 196
 197         return ack_detected ? 0 : -ETIMEDOUT;
 198 }
 199
 200 static inline void
 201 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d)
 202 {
 203         if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))
 204                 return;
 205
 206         if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))
 207                 fw_domain_wait_ack_clear(d);
 208 }
 209
 210 static inline void
 211 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
 212 {
 213         fw_set(d, FORCEWAKE_KERNEL);
 214 }
 215
 216 static inline void
 217 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d)
 218 {
 219         if (wait_ack_set(d, FORCEWAKE_KERNEL)) {
 220                 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
 221                           intel_uncore_forcewake_domain_to_str(d->id));
 222                 add_taint_for_CI(TAINT_WARN); /* CI now unreliable */
 223         }
 224 }
 225
 226 static inline void
 227 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d)
 228 {
 229         if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))
 230                 return;
 231
 232         if (fw_domain_wait_ack_with_fallback(d, ACK_SET))
 233                 fw_domain_wait_ack_set(d);
 234 }
 235
 236 static inline void
 237 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
 238 {
 239         fw_clear(d, FORCEWAKE_KERNEL);
 240 }
 241
 242 static void
 243 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 244 {
 245         struct intel_uncore_forcewake_domain *d;
 246         unsigned int tmp;
 247
 248         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 249
 250         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 251                 fw_domain_wait_ack_clear(d);
 252                 fw_domain_get(d);
 253         }
 254
 255         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 256                 fw_domain_wait_ack_set(d);
 257
 258         uncore->fw_domains_active |= fw_domains;
 259 }
 260
 261 static void
 262 fw_domains_get_with_fallback(struct intel_uncore *uncore,
 263                              enum forcewake_domains fw_domains)
 264 {
 265         struct intel_uncore_forcewake_domain *d;
 266         unsigned int tmp;
 267
 268         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 269
 270         for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
 271                 fw_domain_wait_ack_clear_fallback(d);
 272                 fw_domain_get(d);
 273         }
 274
 275         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 276                 fw_domain_wait_ack_set_fallback(d);
 277
 278         uncore->fw_domains_active |= fw_domains;
 279 }
 280
 281 static void
 282 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
 283 {
 284         struct intel_uncore_forcewake_domain *d;
 285         unsigned int tmp;
 286
 287         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 288
 289         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 290                 fw_domain_put(d);
 291
 292         uncore->fw_domains_active &= ~fw_domains;
 293 }
 294
 295 static void
 296 fw_domains_reset(struct intel_uncore *uncore,
 297                  enum forcewake_domains fw_domains)
 298 {
 299         struct intel_uncore_forcewake_domain *d;
 300         unsigned int tmp;
 301
 302         if (!fw_domains)
 303                 return;
 304
 305         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
 306
 307         for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
 308                 fw_domain_reset(d);
 309 }
 310
 311 static inline u32 gt_thread_status(struct intel_uncore *uncore)
 312 {
 313         u32 val;
 314
 315         val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
 316         val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
 317
 318         return val;
 319 }
 320
 321 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
 322 {
 323         /*
 324          * w/a for a sporadic read returning 0 by waiting for the GT
 325          * thread to wake up.
 326          */
 327         drm_WARN_ONCE(&uncore->i915->drm,
 328                       wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000),
 329                       "GT thread status wait timed out\n");
 330 }
 331
 332 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
 333                                               enum forcewake_domains fw_domains)
 334 {
 335         fw_domains_get(uncore, fw_domains);
 336
 337         /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
 338         __gen6_gt_wait_for_thread_c0(uncore);
 339 }
 340
 341 static inline u32 fifo_free_entries(struct intel_uncore *uncore)
 342 {
 343         u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
 344
 345         return count & GT_FIFO_FREE_ENTRIES_MASK;
 346 }
 347
 348 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)
 349 {
 350         u32 n;
 351
 352         /* On VLV, FIFO will be shared by both SW and HW.
 353          * So, we need to read the FREE_ENTRIES everytime */
 354         if (IS_VALLEYVIEW(uncore->i915))
 355                 n = fifo_free_entries(uncore);
 356         else
 357                 n = uncore->fifo_count;
 358
 359         if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
 360                 if (wait_for_atomic((n = fifo_free_entries(uncore)) >
 361                                     GT_FIFO_NUM_RESERVED_ENTRIES,
 362                                     GT_FIFO_TIMEOUT_MS)) {
 363                         drm_dbg(&uncore->i915->drm,
 364                                 "GT_FIFO timeout, entries: %u\n", n);
 365                         return;
 366                 }
 367         }
 368
 369         uncore->fifo_count = n - 1;
 370 }
 371
 372 static enum hrtimer_restart
 373 intel_uncore_fw_release_timer(struct hrtimer *timer)
 374 {
 375         struct intel_uncore_forcewake_domain *domain =
 376                container_of(timer, struct intel_uncore_forcewake_domain, timer);
 377         struct intel_uncore *uncore = domain->uncore;
 378         unsigned long irqflags;
 379
 380         assert_rpm_device_not_suspended(uncore->rpm);
 381
 382         if (xchg(&domain->active, false))
 383                 return HRTIMER_RESTART;
 384
 385         spin_lock_irqsave(&uncore->lock, irqflags);
 386
 387         uncore->fw_domains_timer &= ~domain->mask;
 388
 389         GEM_BUG_ON(!domain->wake_count);
 390         if (--domain->wake_count == 0)
 391                 uncore->funcs.force_wake_put(uncore, domain->mask);
 392
 393         spin_unlock_irqrestore(&uncore->lock, irqflags);
 394
 395         return HRTIMER_NORESTART;
 396 }
 397
 398 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
 399 static unsigned int
 400 intel_uncore_forcewake_reset(struct intel_uncore *uncore)
 401 {
 402         unsigned long irqflags;
 403         struct intel_uncore_forcewake_domain *domain;
 404         int retry_count = 100;
 405         enum forcewake_domains fw, active_domains;
 406
 407         iosf_mbi_assert_punit_acquired();
 408
 409         /* Hold uncore.lock across reset to prevent any register access
 410          * with forcewake not set correctly. Wait until all pending
 411          * timers are run before holding.
 412          */
 413         while (1) {
 414                 unsigned int tmp;
 415
 416                 active_domains = 0;
 417
 418                 for_each_fw_domain(domain, uncore, tmp) {
 419                         smp_store_mb(domain->active, false);
 420                         if (hrtimer_cancel(&domain->timer) == 0)
 421                                 continue;
 422
 423                         intel_uncore_fw_release_timer(&domain->timer);
 424                 }
 425
 426                 spin_lock_irqsave(&uncore->lock, irqflags);
 427
 428                 for_each_fw_domain(domain, uncore, tmp) {
 429                         if (hrtimer_active(&domain->timer))
 430                                 active_domains |= domain->mask;
 431                 }
 432
 433                 if (active_domains == 0)
 434                         break;
 435
 436                 if (--retry_count == 0) {
 437                         drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n");
 438                         break;
 439                 }
 440
 441                 spin_unlock_irqrestore(&uncore->lock, irqflags);
 442                 cond_resched();
 443         }
 444
 445         drm_WARN_ON(&uncore->i915->drm, active_domains);
 446
 447         fw = uncore->fw_domains_active;
 448         if (fw)
 449                 uncore->funcs.force_wake_put(uncore, fw);
 450
 451         fw_domains_reset(uncore, uncore->fw_domains);
 452         assert_forcewakes_inactive(uncore);
 453
 454         spin_unlock_irqrestore(&uncore->lock, irqflags);
 455
 456         return fw; /* track the lost user forcewake domains */
 457 }
 458
 459 static bool
 460 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 461 {
 462         u32 dbg;
 463
 464         dbg = __raw_uncore_read32(uncore, FPGA_DBG);
 465         if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
 466                 return false;
 467
 468         __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 469
 470         return true;
 471 }
 472
 473 static bool
 474 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
 475 {
 476         u32 cer;
 477
 478         cer = __raw_uncore_read32(uncore, CLAIM_ER);
 479         if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
 480                 return false;
 481
 482         __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
 483
 484         return true;
 485 }
 486
 487 static bool
 488 gen6_check_for_fifo_debug(struct intel_uncore *uncore)
 489 {
 490         u32 fifodbg;
 491
 492         fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
 493
 494         if (unlikely(fifodbg)) {
 495                 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg);
 496                 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
 497         }
 498
 499         return fifodbg;
 500 }
 501
 502 static bool
 503 check_for_unclaimed_mmio(struct intel_uncore *uncore)
 504 {
 505         bool ret = false;
 506
 507         lockdep_assert_held(&uncore->debug->lock);
 508
 509         if (uncore->debug->suspend_count)
 510                 return false;
 511
 512         if (intel_uncore_has_fpga_dbg_unclaimed(uncore))
 513                 ret |= fpga_check_for_unclaimed_mmio(uncore);
 514
 515         if (intel_uncore_has_dbg_unclaimed(uncore))
 516                 ret |= vlv_check_for_unclaimed_mmio(uncore);
 517
 518         if (intel_uncore_has_fifo(uncore))
 519                 ret |= gen6_check_for_fifo_debug(uncore);
 520
 521         return ret;
 522 }
 523
 524 static void forcewake_early_sanitize(struct intel_uncore *uncore,
 525                                      unsigned int restore_forcewake)
 526 {
 527         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
 528
 529         /* WaDisableShadowRegForCpd:chv */
 530         if (IS_CHERRYVIEW(uncore->i915)) {
 531                 __raw_uncore_write32(uncore, GTFIFOCTL,
 532                                      __raw_uncore_read32(uncore, GTFIFOCTL) |
 533                                      GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
 534                                      GT_FIFO_CTL_RC6_POLICY_STALL);
 535         }
 536
 537         iosf_mbi_punit_acquire();
 538         intel_uncore_forcewake_reset(uncore);
 539         if (restore_forcewake) {
 540                 spin_lock_irq(&uncore->lock);
 541                 uncore->funcs.force_wake_get(uncore, restore_forcewake);
 542
 543                 if (intel_uncore_has_fifo(uncore))
 544                         uncore->fifo_count = fifo_free_entries(uncore);
 545                 spin_unlock_irq(&uncore->lock);
 546         }
 547         iosf_mbi_punit_release();
 548 }
 549
 550 void intel_uncore_suspend(struct intel_uncore *uncore)
 551 {
 552         if (!intel_uncore_has_forcewake(uncore))
 553                 return;
 554
 555         iosf_mbi_punit_acquire();
 556         iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
 557                 &uncore->pmic_bus_access_nb);
 558         uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore);
 559         iosf_mbi_punit_release();
 560 }
 561
 562 void intel_uncore_resume_early(struct intel_uncore *uncore)
 563 {
 564         unsigned int restore_forcewake;
 565
 566         if (intel_uncore_unclaimed_mmio(uncore))
 567                 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n");
 568
 569         if (!intel_uncore_has_forcewake(uncore))
 570                 return;
 571
 572         restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
 573         forcewake_early_sanitize(uncore, restore_forcewake);
 574
 575         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 576 }
 577
 578 void intel_uncore_runtime_resume(struct intel_uncore *uncore)
 579 {
 580         if (!intel_uncore_has_forcewake(uncore))
 581                 return;
 582
 583         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
 584 }
 585
 586 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
 587                                          enum forcewake_domains fw_domains)
 588 {
 589         struct intel_uncore_forcewake_domain *domain;
 590         unsigned int tmp;
 591
 592         fw_domains &= uncore->fw_domains;
 593
 594         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 595                 if (domain->wake_count++) {
 596                         fw_domains &= ~domain->mask;
 597                         domain->active = true;
 598                 }
 599         }
 600
 601         if (fw_domains)
 602                 uncore->funcs.force_wake_get(uncore, fw_domains);
 603 }
 604
 605 /**
 606  * intel_uncore_forcewake_get - grab forcewake domain references
 607  * @uncore: the intel_uncore structure
 608  * @fw_domains: forcewake domains to get reference on
 609  *
 610  * This function can be used get GT's forcewake domain references.
 611  * Normal register access will handle the forcewake domains automatically.
 612  * However if some sequence requires the GT to not power down a particular
 613  * forcewake domains this function should be called at the beginning of the
 614  * sequence. And subsequently the reference should be dropped by symmetric
 615  * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 616  * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
 617  */
 618 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
 619                                 enum forcewake_domains fw_domains)
 620 {
 621         unsigned long irqflags;
 622
 623         if (!uncore->funcs.force_wake_get)
 624                 return;
 625
 626         assert_rpm_wakelock_held(uncore->rpm);
 627
 628         spin_lock_irqsave(&uncore->lock, irqflags);
 629         __intel_uncore_forcewake_get(uncore, fw_domains);
 630         spin_unlock_irqrestore(&uncore->lock, irqflags);
 631 }
 632
 633 /**
 634  * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 635  * @uncore: the intel_uncore structure
 636  *
 637  * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 638  * the GT powerwell and in the process disable our debugging for the
 639  * duration of userspace's bypass.
 640  */
 641 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
 642 {
 643         spin_lock_irq(&uncore->lock);
 644         if (!uncore->user_forcewake_count++) {
 645                 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL);
 646                 spin_lock(&uncore->debug->lock);
 647                 mmio_debug_suspend(uncore->debug);
 648                 spin_unlock(&uncore->debug->lock);
 649         }
 650         spin_unlock_irq(&uncore->lock);
 651 }
 652
 653 /**
 654  * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 655  * @uncore: the intel_uncore structure
 656  *
 657  * This function complements intel_uncore_forcewake_user_get() and releases
 658  * the GT powerwell taken on behalf of the userspace bypass.
 659  */
 660 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
 661 {
 662         spin_lock_irq(&uncore->lock);
 663         if (!--uncore->user_forcewake_count) {
 664                 spin_lock(&uncore->debug->lock);
 665                 mmio_debug_resume(uncore->debug);
 666
 667                 if (check_for_unclaimed_mmio(uncore))
 668                         dev_info(uncore->i915->drm.dev,
 669                                  "Invalid mmio detected during user access\n");
 670                 spin_unlock(&uncore->debug->lock);
 671
 672                 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL);
 673         }
 674         spin_unlock_irq(&uncore->lock);
 675 }
 676
 677 /**
 678  * intel_uncore_forcewake_get__locked - grab forcewake domain references
 679  * @uncore: the intel_uncore structure
 680  * @fw_domains: forcewake domains to get reference on
 681  *
 682  * See intel_uncore_forcewake_get(). This variant places the onus
 683  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 684  */
 685 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
 686                                         enum forcewake_domains fw_domains)
 687 {
 688         lockdep_assert_held(&uncore->lock);
 689
 690         if (!uncore->funcs.force_wake_get)
 691                 return;
 692
 693         __intel_uncore_forcewake_get(uncore, fw_domains);
 694 }
 695
 696 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,
 697                                          enum forcewake_domains fw_domains)
 698 {
 699         struct intel_uncore_forcewake_domain *domain;
 700         unsigned int tmp;
 701
 702         fw_domains &= uncore->fw_domains;
 703
 704         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 705                 GEM_BUG_ON(!domain->wake_count);
 706
 707                 if (--domain->wake_count) {
 708                         domain->active = true;
 709                         continue;
 710                 }
 711
 712                 fw_domain_arm_timer(domain);
 713         }
 714 }
 715
 716 /**
 717  * intel_uncore_forcewake_put - release a forcewake domain reference
 718  * @uncore: the intel_uncore structure
 719  * @fw_domains: forcewake domains to put references
 720  *
 721  * This function drops the device-level forcewakes for specified
 722  * domains obtained by intel_uncore_forcewake_get().
 723  */
 724 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
 725                                 enum forcewake_domains fw_domains)
 726 {
 727         unsigned long irqflags;
 728
 729         if (!uncore->funcs.force_wake_put)
 730                 return;
 731
 732         spin_lock_irqsave(&uncore->lock, irqflags);
 733         __intel_uncore_forcewake_put(uncore, fw_domains);
 734         spin_unlock_irqrestore(&uncore->lock, irqflags);
 735 }
 736
 737 /**
 738  * intel_uncore_forcewake_put__locked - grab forcewake domain references
 739  * @uncore: the intel_uncore structure
 740  * @fw_domains: forcewake domains to get reference on
 741  *
 742  * See intel_uncore_forcewake_put(). This variant places the onus
 743  * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 744  */
 745 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
 746                                         enum forcewake_domains fw_domains)
 747 {
 748         lockdep_assert_held(&uncore->lock);
 749
 750         if (!uncore->funcs.force_wake_put)
 751                 return;
 752
 753         __intel_uncore_forcewake_put(uncore, fw_domains);
 754 }
 755
 756 void assert_forcewakes_inactive(struct intel_uncore *uncore)
 757 {
 758         if (!uncore->funcs.force_wake_get)
 759                 return;
 760
 761         drm_WARN(&uncore->i915->drm, uncore->fw_domains_active,
 762                  "Expected all fw_domains to be inactive, but %08x are still on\n",
 763                  uncore->fw_domains_active);
 764 }
 765
 766 void assert_forcewakes_active(struct intel_uncore *uncore,
 767                               enum forcewake_domains fw_domains)
 768 {
 769         struct intel_uncore_forcewake_domain *domain;
 770         unsigned int tmp;
 771
 772         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 773                 return;
 774
 775         if (!uncore->funcs.force_wake_get)
 776                 return;
 777
 778         spin_lock_irq(&uncore->lock);
 779
 780         assert_rpm_wakelock_held(uncore->rpm);
 781
 782         fw_domains &= uncore->fw_domains;
 783         drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active,
 784                  "Expected %08x fw_domains to be active, but %08x are off\n",
 785                  fw_domains, fw_domains & ~uncore->fw_domains_active);
 786
 787         /*
 788          * Check that the caller has an explicit wakeref and we don't mistake
 789          * it for the auto wakeref.
 790          */
 791         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 792                 unsigned int actual = READ_ONCE(domain->wake_count);
 793                 unsigned int expect = 1;
 794
 795                 if (uncore->fw_domains_timer & domain->mask)
 796                         expect++; /* pending automatic release */
 797
 798                 if (drm_WARN(&uncore->i915->drm, actual < expect,
 799                              "Expected domain %d to be held awake by caller, count=%d\n",
 800                              domain->id, actual))
 801                         break;
 802         }
 803
 804         spin_unlock_irq(&uncore->lock);
 805 }
 806
 807 /* We give fast paths for the really cool registers */
 808 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 809
 810 #define __gen6_reg_read_fw_domains(uncore, offset) \
 811 ({ \
 812         enum forcewake_domains __fwd; \
 813         if (NEEDS_FORCE_WAKE(offset)) \
 814                 __fwd = FORCEWAKE_RENDER; \
 815         else \
 816                 __fwd = 0; \
 817         __fwd; \
 818 })
 819
 820 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 821 {
 822         if (offset < entry->start)
 823                 return -1;
 824         else if (offset > entry->end)
 825                 return 1;
 826         else
 827                 return 0;
 828 }
 829
 830 /* Copied and "macroized" from lib/bsearch.c */
 831 #define BSEARCH(key, base, num, cmp) ({                                 \
 832         unsigned int start__ = 0, end__ = (num);                        \
 833         typeof(base) result__ = NULL;                                   \
 834         while (start__ < end__) {                                       \
 835                 unsigned int mid__ = start__ + (end__ - start__) / 2;   \
 836                 int ret__ = (cmp)((key), (base) + mid__);               \
 837                 if (ret__ < 0) {                                        \
 838                         end__ = mid__;                                  \
 839                 } else if (ret__ > 0) {                                 \
 840                         start__ = mid__ + 1;                            \
 841                 } else {                                                \
 842                         result__ = (base) + mid__;                      \
 843                         break;                                          \
 844                 }                                                       \
 845         }                                                               \
 846         result__;                                                       \
 847 })
 848
 849 static enum forcewake_domains
 850 find_fw_domain(struct intel_uncore *uncore, u32 offset)
 851 {
 852         const struct intel_forcewake_range *entry;
 853
 854         entry = BSEARCH(offset,
 855                         uncore->fw_domains_table,
 856                         uncore->fw_domains_table_entries,
 857                         fw_range_cmp);
 858
 859         if (!entry)
 860                 return 0;
 861
 862         /*
 863          * The list of FW domains depends on the SKU in gen11+ so we
 864          * can't determine it statically. We use FORCEWAKE_ALL and
 865          * translate it here to the list of available domains.
 866          */
 867         if (entry->domains == FORCEWAKE_ALL)
 868                 return uncore->fw_domains;
 869
 870         drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains,
 871                  "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 872                  entry->domains & ~uncore->fw_domains, offset);
 873
 874         return entry->domains;
 875 }
 876
 877 #define GEN_FW_RANGE(s, e, d) \
 878         { .start = (s), .end = (e), .domains = (d) }
 879
 880 #define HAS_FWTABLE(dev_priv) \
 881         (INTEL_GEN(dev_priv) >= 9 || \
 882          IS_CHERRYVIEW(dev_priv) || \
 883          IS_VALLEYVIEW(dev_priv))
 884
 885 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 886 static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 887         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 888         GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
 889         GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
 890         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
 891         GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
 892         GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
 893         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 894 };
 895
 896 #define __fwtable_reg_read_fw_domains(uncore, offset) \
 897 ({ \
 898         enum forcewake_domains __fwd = 0; \
 899         if (NEEDS_FORCE_WAKE((offset))) \
 900                 __fwd = find_fw_domain(uncore, offset); \
 901         __fwd; \
 902 })
 903
 904 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
 905         find_fw_domain(uncore, offset)
 906
 907 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \
 908         find_fw_domain(uncore, offset)
 909
 910 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 911 static const i915_reg_t gen8_shadowed_regs[] = {
 912         RING_TAIL(RENDER_RING_BASE),    /* 0x2000 (base) */
 913         GEN6_RPNSWREQ,                  /* 0xA008 */
 914         GEN6_RC_VIDEO_FREQ,             /* 0xA00C */
 915         RING_TAIL(GEN6_BSD_RING_BASE),  /* 0x12000 (base) */
 916         RING_TAIL(VEBOX_RING_BASE),     /* 0x1a000 (base) */
 917         RING_TAIL(BLT_RING_BASE),       /* 0x22000 (base) */
 918         /* TODO: Other registers are not yet used */
 919 };
 920
 921 static const i915_reg_t gen11_shadowed_regs[] = {
 922         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 923         GEN6_RPNSWREQ,                          /* 0xA008 */
 924         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 925         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 926         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 927         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 928         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 929         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 930         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 931         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 932         /* TODO: Other registers are not yet used */
 933 };
 934
 935 static const i915_reg_t gen12_shadowed_regs[] = {
 936         RING_TAIL(RENDER_RING_BASE),            /* 0x2000 (base) */
 937         GEN6_RPNSWREQ,                          /* 0xA008 */
 938         GEN6_RC_VIDEO_FREQ,                     /* 0xA00C */
 939         RING_TAIL(BLT_RING_BASE),               /* 0x22000 (base) */
 940         RING_TAIL(GEN11_BSD_RING_BASE),         /* 0x1C0000 (base) */
 941         RING_TAIL(GEN11_BSD2_RING_BASE),        /* 0x1C4000 (base) */
 942         RING_TAIL(GEN11_VEBOX_RING_BASE),       /* 0x1C8000 (base) */
 943         RING_TAIL(GEN11_BSD3_RING_BASE),        /* 0x1D0000 (base) */
 944         RING_TAIL(GEN11_BSD4_RING_BASE),        /* 0x1D4000 (base) */
 945         RING_TAIL(GEN11_VEBOX2_RING_BASE),      /* 0x1D8000 (base) */
 946         /* TODO: Other registers are not yet used */
 947 };
 948
 949 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 950 {
 951         u32 offset = i915_mmio_reg_offset(*reg);
 952
 953         if (key < offset)
 954                 return -1;
 955         else if (key > offset)
 956                 return 1;
 957         else
 958                 return 0;
 959 }
 960
 961 #define __is_genX_shadowed(x) \
 962 static bool is_gen##x##_shadowed(u32 offset) \
 963 { \
 964         const i915_reg_t *regs = gen##x##_shadowed_regs; \
 965         return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
 966                        mmio_reg_cmp); \
 967 }
 968
 969 __is_genX_shadowed(8)
 970 __is_genX_shadowed(11)
 971 __is_genX_shadowed(12)
 972
 973 static enum forcewake_domains
 974 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
 975 {
 976         return FORCEWAKE_RENDER;
 977 }
 978
 979 #define __gen8_reg_write_fw_domains(uncore, offset) \
 980 ({ \
 981         enum forcewake_domains __fwd; \
 982         if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
 983                 __fwd = FORCEWAKE_RENDER; \
 984         else \
 985                 __fwd = 0; \
 986         __fwd; \
 987 })
 988
 989 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 990 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 991         GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
 992         GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 993         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
 994         GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 995         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
 996         GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 997         GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
 998         GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
 999         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1000         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1001         GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
1002         GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1003         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1004         GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
1005         GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
1006         GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
1007 };
1008
1009 #define __fwtable_reg_write_fw_domains(uncore, offset) \
1010 ({ \
1011         enum forcewake_domains __fwd = 0; \
1012         if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
1013                 __fwd = find_fw_domain(uncore, offset); \
1014         __fwd; \
1015 })
1016
1017 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
1018 ({ \
1019         enum forcewake_domains __fwd = 0; \
1020         const u32 __offset = (offset); \
1021         if (!is_gen11_shadowed(__offset)) \
1022                 __fwd = find_fw_domain(uncore, __offset); \
1023         __fwd; \
1024 })
1025
1026 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \
1027 ({ \
1028         enum forcewake_domains __fwd = 0; \
1029         const u32 __offset = (offset); \
1030         if (!is_gen12_shadowed(__offset)) \
1031                 __fwd = find_fw_domain(uncore, __offset); \
1032         __fwd; \
1033 })
1034
1035 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1036 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
1037         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1038         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1039         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1040         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1041         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1042         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1043         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1044         GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
1045         GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
1046         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1047         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1048         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1049         GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
1050         GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
1051         GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
1052         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1053         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1054         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1055         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1056         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1057         GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1058         GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1059         GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1060         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1061         GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1062         GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1063         GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1064         GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1065         GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1066         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1067         GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1068         GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
1069 };
1070
1071 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1072 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
1073         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1074         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1075         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1076         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1077         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1078         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1079         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1080         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1081         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1082         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1083         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1084         GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1085         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1086         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1087         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1088         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1089         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1090         GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
1091         GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
1092         GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
1093         GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
1094         GEN_FW_RANGE(0x1a000, 0x243ff, FORCEWAKE_BLITTER),
1095         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1096         GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1097         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1098         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1099         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1100         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1101         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1102         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1103         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1104         GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1105 };
1106
1107 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
1108 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
1109         GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
1110         GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
1111         GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
1112         GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
1113         GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
1114         GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
1115         GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
1116         GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
1117         GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
1118         GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
1119         GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
1120         GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
1121         GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1122         GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1123         GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
1124         GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1125         GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1126         GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
1127         GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1128         GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
1129         GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
1130         GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
1131         GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
1132         GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
1133         GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
1134         GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
1135         GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1136         GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
1137         GEN_FW_RANGE(0x40000, 0x1bffff, 0),
1138         GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
1139         GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
1140         GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
1141         GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
1142         GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
1143         GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
1144         GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
1145 };
1146
1147 static void
1148 ilk_dummy_write(struct intel_uncore *uncore)
1149 {
1150         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1151          * the chip from rc6 before touching it for real. MI_MODE is masked,
1152          * hence harmless to write 0 into. */
1153         __raw_uncore_write32(uncore, MI_MODE, 0);
1154 }
1155
1156 static void
1157 __unclaimed_reg_debug(struct intel_uncore *uncore,
1158                       const i915_reg_t reg,
1159                       const bool read,
1160                       const bool before)
1161 {
1162         if (drm_WARN(&uncore->i915->drm,
1163                      check_for_unclaimed_mmio(uncore) && !before,
1164                      "Unclaimed %s register 0x%x\n",
1165                      read ? "read from" : "write to",
1166                      i915_mmio_reg_offset(reg)))
1167                 /* Only report the first N failures */
1168                 i915_modparams.mmio_debug--;
1169 }
1170
1171 static inline void
1172 unclaimed_reg_debug(struct intel_uncore *uncore,
1173                     const i915_reg_t reg,
1174                     const bool read,
1175                     const bool before)
1176 {
1177         if (likely(!i915_modparams.mmio_debug))
1178                 return;
1179
1180         /* interrupts are disabled and re-enabled around uncore->lock usage */
1181         lockdep_assert_held(&uncore->lock);
1182
1183         if (before)
1184                 spin_lock(&uncore->debug->lock);
1185
1186         __unclaimed_reg_debug(uncore, reg, read, before);
1187
1188         if (!before)
1189                 spin_unlock(&uncore->debug->lock);
1190 }
1191
1192 #define GEN2_READ_HEADER(x) \
1193         u##x val = 0; \
1194         assert_rpm_wakelock_held(uncore->rpm);
1195
1196 #define GEN2_READ_FOOTER \
1197         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1198         return val
1199
1200 #define __gen2_read(x) \
1201 static u##x \
1202 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1203         GEN2_READ_HEADER(x); \
1204         val = __raw_uncore_read##x(uncore, reg); \
1205         GEN2_READ_FOOTER; \
1206 }
1207
1208 #define __gen5_read(x) \
1209 static u##x \
1210 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1211         GEN2_READ_HEADER(x); \
1212         ilk_dummy_write(uncore); \
1213         val = __raw_uncore_read##x(uncore, reg); \
1214         GEN2_READ_FOOTER; \
1215 }
1216
1217 __gen5_read(8)
1218 __gen5_read(16)
1219 __gen5_read(32)
1220 __gen5_read(64)
1221 __gen2_read(8)
1222 __gen2_read(16)
1223 __gen2_read(32)
1224 __gen2_read(64)
1225
1226 #undef __gen5_read
1227 #undef __gen2_read
1228
1229 #undef GEN2_READ_FOOTER
1230 #undef GEN2_READ_HEADER
1231
1232 #define GEN6_READ_HEADER(x) \
1233         u32 offset = i915_mmio_reg_offset(reg); \
1234         unsigned long irqflags; \
1235         u##x val = 0; \
1236         assert_rpm_wakelock_held(uncore->rpm); \
1237         spin_lock_irqsave(&uncore->lock, irqflags); \
1238         unclaimed_reg_debug(uncore, reg, true, true)
1239
1240 #define GEN6_READ_FOOTER \
1241         unclaimed_reg_debug(uncore, reg, true, false); \
1242         spin_unlock_irqrestore(&uncore->lock, irqflags); \
1243         trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
1244         return val
1245
1246 static noinline void ___force_wake_auto(struct intel_uncore *uncore,
1247                                         enum forcewake_domains fw_domains)
1248 {
1249         struct intel_uncore_forcewake_domain *domain;
1250         unsigned int tmp;
1251
1252         GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
1253
1254         for_each_fw_domain_masked(domain, fw_domains, uncore, tmp)
1255                 fw_domain_arm_timer(domain);
1256
1257         uncore->funcs.force_wake_get(uncore, fw_domains);
1258 }
1259
1260 static inline void __force_wake_auto(struct intel_uncore *uncore,
1261                                      enum forcewake_domains fw_domains)
1262 {
1263         GEM_BUG_ON(!fw_domains);
1264
1265         /* Turn on all requested but inactive supported forcewake domains. */
1266         fw_domains &= uncore->fw_domains;
1267         fw_domains &= ~uncore->fw_domains_active;
1268
1269         if (fw_domains)
1270                 ___force_wake_auto(uncore, fw_domains);
1271 }
1272
1273 #define __gen_read(func, x) \
1274 static u##x \
1275 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1276         enum forcewake_domains fw_engine; \
1277         GEN6_READ_HEADER(x); \
1278         fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
1279         if (fw_engine) \
1280                 __force_wake_auto(uncore, fw_engine); \
1281         val = __raw_uncore_read##x(uncore, reg); \
1282         GEN6_READ_FOOTER; \
1283 }
1284
1285 #define __gen_reg_read_funcs(func) \
1286 static enum forcewake_domains \
1287 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1288         return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1289 } \
1290 \
1291 __gen_read(func, 8) \
1292 __gen_read(func, 16) \
1293 __gen_read(func, 32) \
1294 __gen_read(func, 64)
1295
1296 __gen_reg_read_funcs(gen12_fwtable);
1297 __gen_reg_read_funcs(gen11_fwtable);
1298 __gen_reg_read_funcs(fwtable);
1299 __gen_reg_read_funcs(gen6);
1300
1301 #undef __gen_reg_read_funcs
1302 #undef GEN6_READ_FOOTER
1303 #undef GEN6_READ_HEADER
1304
1305 #define GEN2_WRITE_HEADER \
1306         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1307         assert_rpm_wakelock_held(uncore->rpm); \
1308
1309 #define GEN2_WRITE_FOOTER
1310
1311 #define __gen2_write(x) \
1312 static void \
1313 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1314         GEN2_WRITE_HEADER; \
1315         __raw_uncore_write##x(uncore, reg, val); \
1316         GEN2_WRITE_FOOTER; \
1317 }
1318
1319 #define __gen5_write(x) \
1320 static void \
1321 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1322         GEN2_WRITE_HEADER; \
1323         ilk_dummy_write(uncore); \
1324         __raw_uncore_write##x(uncore, reg, val); \
1325         GEN2_WRITE_FOOTER; \
1326 }
1327
1328 __gen5_write(8)
1329 __gen5_write(16)
1330 __gen5_write(32)
1331 __gen2_write(8)
1332 __gen2_write(16)
1333 __gen2_write(32)
1334
1335 #undef __gen5_write
1336 #undef __gen2_write
1337
1338 #undef GEN2_WRITE_FOOTER
1339 #undef GEN2_WRITE_HEADER
1340
1341 #define GEN6_WRITE_HEADER \
1342         u32 offset = i915_mmio_reg_offset(reg); \
1343         unsigned long irqflags; \
1344         trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1345         assert_rpm_wakelock_held(uncore->rpm); \
1346         spin_lock_irqsave(&uncore->lock, irqflags); \
1347         unclaimed_reg_debug(uncore, reg, false, true)
1348
1349 #define GEN6_WRITE_FOOTER \
1350         unclaimed_reg_debug(uncore, reg, false, false); \
1351         spin_unlock_irqrestore(&uncore->lock, irqflags)
1352
1353 #define __gen6_write(x) \
1354 static void \
1355 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1356         GEN6_WRITE_HEADER; \
1357         if (NEEDS_FORCE_WAKE(offset)) \
1358                 __gen6_gt_wait_for_fifo(uncore); \
1359         __raw_uncore_write##x(uncore, reg, val); \
1360         GEN6_WRITE_FOOTER; \
1361 }
1362 __gen6_write(8)
1363 __gen6_write(16)
1364 __gen6_write(32)
1365
1366 #define __gen_write(func, x) \
1367 static void \
1368 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
1369         enum forcewake_domains fw_engine; \
1370         GEN6_WRITE_HEADER; \
1371         fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
1372         if (fw_engine) \
1373                 __force_wake_auto(uncore, fw_engine); \
1374         __raw_uncore_write##x(uncore, reg, val); \
1375         GEN6_WRITE_FOOTER; \
1376 }
1377
1378 #define __gen_reg_write_funcs(func) \
1379 static enum forcewake_domains \
1380 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
1381         return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
1382 } \
1383 \
1384 __gen_write(func, 8) \
1385 __gen_write(func, 16) \
1386 __gen_write(func, 32)
1387
1388 __gen_reg_write_funcs(gen12_fwtable);
1389 __gen_reg_write_funcs(gen11_fwtable);
1390 __gen_reg_write_funcs(fwtable);
1391 __gen_reg_write_funcs(gen8);
1392
1393 #undef __gen_reg_write_funcs
1394 #undef GEN6_WRITE_FOOTER
1395 #undef GEN6_WRITE_HEADER
1396
1397 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
1398 do { \
1399         (uncore)->funcs.mmio_writeb = x##_write8; \
1400         (uncore)->funcs.mmio_writew = x##_write16; \
1401         (uncore)->funcs.mmio_writel = x##_write32; \
1402 } while (0)
1403
1404 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
1405 do { \
1406         (uncore)->funcs.mmio_readb = x##_read8; \
1407         (uncore)->funcs.mmio_readw = x##_read16; \
1408         (uncore)->funcs.mmio_readl = x##_read32; \
1409         (uncore)->funcs.mmio_readq = x##_read64; \
1410 } while (0)
1411
1412 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
1413 do { \
1414         ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
1415         (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
1416 } while (0)
1417
1418 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
1419 do { \
1420         ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
1421         (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
1422 } while (0)
1423
1424 static int __fw_domain_init(struct intel_uncore *uncore,
1425                             enum forcewake_domain_id domain_id,
1426                             i915_reg_t reg_set,
1427                             i915_reg_t reg_ack)
1428 {
1429         struct intel_uncore_forcewake_domain *d;
1430
1431         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1432         GEM_BUG_ON(uncore->fw_domain[domain_id]);
1433
1434         if (i915_inject_probe_failure(uncore->i915))
1435                 return -ENOMEM;
1436
1437         d = kzalloc(sizeof(*d), GFP_KERNEL);
1438         if (!d)
1439                 return -ENOMEM;
1440
1441         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set));
1442         drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack));
1443
1444         d->uncore = uncore;
1445         d->wake_count = 0;
1446         d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
1447         d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
1448
1449         d->id = domain_id;
1450
1451         BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
1452         BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
1453         BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1454         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
1455         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
1456         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
1457         BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
1458         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
1459         BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
1460
1461         d->mask = BIT(domain_id);
1462
1463         hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1464         d->timer.function = intel_uncore_fw_release_timer;
1465
1466         uncore->fw_domains |= BIT(domain_id);
1467
1468         fw_domain_reset(d);
1469
1470         uncore->fw_domain[domain_id] = d;
1471
1472         return 0;
1473 }
1474
1475 static void fw_domain_fini(struct intel_uncore *uncore,
1476                            enum forcewake_domain_id domain_id)
1477 {
1478         struct intel_uncore_forcewake_domain *d;
1479
1480         GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
1481
1482         d = fetch_and_zero(&uncore->fw_domain[domain_id]);
1483         if (!d)
1484                 return;
1485
1486         uncore->fw_domains &= ~BIT(domain_id);
1487         drm_WARN_ON(&uncore->i915->drm, d->wake_count);
1488         drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer));
1489         kfree(d);
1490 }
1491
1492 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
1493 {
1494         struct intel_uncore_forcewake_domain *d;
1495         int tmp;
1496
1497         for_each_fw_domain(d, uncore, tmp)
1498                 fw_domain_fini(uncore, d->id);
1499 }
1500
1501 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
1502 {
1503         struct drm_i915_private *i915 = uncore->i915;
1504         int ret = 0;
1505
1506         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1507
1508 #define fw_domain_init(uncore__, id__, set__, ack__) \
1509         (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
1510
1511         if (INTEL_GEN(i915) >= 11) {
1512                 int i;
1513
1514                 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1515                 uncore->funcs.force_wake_put = fw_domains_put;
1516                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1517                                FORCEWAKE_RENDER_GEN9,
1518                                FORCEWAKE_ACK_RENDER_GEN9);
1519                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1520                                FORCEWAKE_BLITTER_GEN9,
1521                                FORCEWAKE_ACK_BLITTER_GEN9);
1522
1523                 for (i = 0; i < I915_MAX_VCS; i++) {
1524                         if (!HAS_ENGINE(i915, _VCS(i)))
1525                                 continue;
1526
1527                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
1528                                        FORCEWAKE_MEDIA_VDBOX_GEN11(i),
1529                                        FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
1530                 }
1531                 for (i = 0; i < I915_MAX_VECS; i++) {
1532                         if (!HAS_ENGINE(i915, _VECS(i)))
1533                                 continue;
1534
1535                         fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
1536                                        FORCEWAKE_MEDIA_VEBOX_GEN11(i),
1537                                        FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
1538                 }
1539         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1540                 uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
1541                 uncore->funcs.force_wake_put = fw_domains_put;
1542                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1543                                FORCEWAKE_RENDER_GEN9,
1544                                FORCEWAKE_ACK_RENDER_GEN9);
1545                 fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
1546                                FORCEWAKE_BLITTER_GEN9,
1547                                FORCEWAKE_ACK_BLITTER_GEN9);
1548                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1549                                FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1550         } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1551                 uncore->funcs.force_wake_get = fw_domains_get;
1552                 uncore->funcs.force_wake_put = fw_domains_put;
1553                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1554                                FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1555                 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
1556                                FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1557         } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1558                 uncore->funcs.force_wake_get =
1559                         fw_domains_get_with_thread_status;
1560                 uncore->funcs.force_wake_put = fw_domains_put;
1561                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1562                                FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1563         } else if (IS_IVYBRIDGE(i915)) {
1564                 u32 ecobus;
1565
1566                 /* IVB configs may use multi-threaded forcewake */
1567
1568                 /* A small trick here - if the bios hasn't configured
1569                  * MT forcewake, and if the device is in RC6, then
1570                  * force_wake_mt_get will not wake the device and the
1571                  * ECOBUS read will return zero. Which will be
1572                  * (correctly) interpreted by the test below as MT
1573                  * forcewake being disabled.
1574                  */
1575                 uncore->funcs.force_wake_get =
1576                         fw_domains_get_with_thread_status;
1577                 uncore->funcs.force_wake_put = fw_domains_put;
1578
1579                 /* We need to init first for ECOBUS access and then
1580                  * determine later if we want to reinit, in case of MT access is
1581                  * not working. In this stage we don't know which flavour this
1582                  * ivb is, so it is better to reset also the gen6 fw registers
1583                  * before the ecobus check.
1584                  */
1585
1586                 __raw_uncore_write32(uncore, FORCEWAKE, 0);
1587                 __raw_posting_read(uncore, ECOBUS);
1588
1589                 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1590                                        FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1591                 if (ret)
1592                         goto out;
1593
1594                 spin_lock_irq(&uncore->lock);
1595                 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
1596                 ecobus = __raw_uncore_read32(uncore, ECOBUS);
1597                 fw_domains_put(uncore, FORCEWAKE_RENDER);
1598                 spin_unlock_irq(&uncore->lock);
1599
1600                 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1601                         drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n");
1602                         drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n");
1603                         fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
1604                         fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1605                                        FORCEWAKE, FORCEWAKE_ACK);
1606                 }
1607         } else if (IS_GEN(i915, 6)) {
1608                 uncore->funcs.force_wake_get =
1609                         fw_domains_get_with_thread_status;
1610                 uncore->funcs.force_wake_put = fw_domains_put;
1611                 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
1612                                FORCEWAKE, FORCEWAKE_ACK);
1613         }
1614
1615 #undef fw_domain_init
1616
1617         /* All future platforms are expected to require complex power gating */
1618         drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0);
1619
1620 out:
1621         if (ret)
1622                 intel_uncore_fw_domains_fini(uncore);
1623
1624         return ret;
1625 }
1626
1627 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
1628 { \
1629         (uncore)->fw_domains_table = \
1630                         (struct intel_forcewake_range *)(d); \
1631         (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \
1632 }
1633
1634 static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
1635                                          unsigned long action, void *data)
1636 {
1637         struct intel_uncore *uncore = container_of(nb,
1638                         struct intel_uncore, pmic_bus_access_nb);
1639
1640         switch (action) {
1641         case MBI_PMIC_BUS_ACCESS_BEGIN:
1642                 /*
1643                  * forcewake all now to make sure that we don't need to do a
1644                  * forcewake later which on systems where this notifier gets
1645                  * called requires the punit to access to the shared pmic i2c
1646                  * bus, which will be busy after this notification, leading to:
1647                  * "render: timed out waiting for forcewake ack request."
1648                  * errors.
1649                  *
1650                  * The notifier is unregistered during intel_runtime_suspend(),
1651                  * so it's ok to access the HW here without holding a RPM
1652                  * wake reference -> disable wakeref asserts for the time of
1653                  * the access.
1654                  */
1655                 disable_rpm_wakeref_asserts(uncore->rpm);
1656                 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1657                 enable_rpm_wakeref_asserts(uncore->rpm);
1658                 break;
1659         case MBI_PMIC_BUS_ACCESS_END:
1660                 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1661                 break;
1662         }
1663
1664         return NOTIFY_OK;
1665 }
1666
1667 static int uncore_mmio_setup(struct intel_uncore *uncore)
1668 {
1669         struct drm_i915_private *i915 = uncore->i915;
1670         struct pci_dev *pdev = i915->drm.pdev;
1671         int mmio_bar;
1672         int mmio_size;
1673
1674         mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
1675         /*
1676          * Before gen4, the registers and the GTT are behind different BARs.
1677          * However, from gen4 onwards, the registers and the GTT are shared
1678          * in the same BAR, so we want to restrict this ioremap from
1679          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1680          * the register BAR remains the same size for all the earlier
1681          * generations up to Ironlake.
1682          */
1683         if (INTEL_GEN(i915) < 5)
1684                 mmio_size = 512 * 1024;
1685         else
1686                 mmio_size = 2 * 1024 * 1024;
1687         uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
1688         if (uncore->regs == NULL) {
1689                 drm_err(&i915->drm, "failed to map registers\n");
1690                 return -EIO;
1691         }
1692
1693         return 0;
1694 }
1695
1696 static void uncore_mmio_cleanup(struct intel_uncore *uncore)
1697 {
1698         struct pci_dev *pdev = uncore->i915->drm.pdev;
1699
1700         pci_iounmap(pdev, uncore->regs);
1701 }
1702
1703 void intel_uncore_init_early(struct intel_uncore *uncore,
1704                              struct drm_i915_private *i915)
1705 {
1706         spin_lock_init(&uncore->lock);
1707         uncore->i915 = i915;
1708         uncore->rpm = &i915->runtime_pm;
1709         uncore->debug = &i915->mmio_debug;
1710 }
1711
1712 static void uncore_raw_init(struct intel_uncore *uncore)
1713 {
1714         GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
1715
1716         if (IS_GEN(uncore->i915, 5)) {
1717                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
1718                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
1719         } else {
1720                 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
1721                 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
1722         }
1723 }
1724
1725 static int uncore_forcewake_init(struct intel_uncore *uncore)
1726 {
1727         struct drm_i915_private *i915 = uncore->i915;
1728         int ret;
1729
1730         GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
1731
1732         ret = intel_uncore_fw_domains_init(uncore);
1733         if (ret)
1734                 return ret;
1735         forcewake_early_sanitize(uncore, 0);
1736
1737         if (IS_GEN_RANGE(i915, 6, 7)) {
1738                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
1739
1740                 if (IS_VALLEYVIEW(i915)) {
1741                         ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
1742                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1743                 } else {
1744                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1745                 }
1746         } else if (IS_GEN(i915, 8)) {
1747                 if (IS_CHERRYVIEW(i915)) {
1748                         ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
1749                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1750                         ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1751                 } else {
1752                         ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
1753                         ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
1754                 }
1755         } else if (IS_GEN_RANGE(i915, 9, 10)) {
1756                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
1757                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
1758                 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
1759         } else if (IS_GEN(i915, 11)) {
1760                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
1761                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
1762                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
1763         } else {
1764                 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges);
1765                 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
1766                 ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable);
1767         }
1768
1769         uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
1770         iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
1771
1772         return 0;
1773 }
1774
1775 int intel_uncore_init_mmio(struct intel_uncore *uncore)
1776 {
1777         struct drm_i915_private *i915 = uncore->i915;
1778         int ret;
1779
1780         ret = uncore_mmio_setup(uncore);
1781         if (ret)
1782                 return ret;
1783
1784         if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
1785                 uncore->flags |= UNCORE_HAS_FORCEWAKE;
1786
1787         if (!intel_uncore_has_forcewake(uncore)) {
1788                 uncore_raw_init(uncore);
1789         } else {
1790                 ret = uncore_forcewake_init(uncore);
1791                 if (ret)
1792                         goto out_mmio_cleanup;
1793         }
1794
1795         /* make sure fw funcs are set if and only if we have fw*/
1796         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
1797         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
1798         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
1799         GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
1800
1801         if (HAS_FPGA_DBG_UNCLAIMED(i915))
1802                 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
1803
1804         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1805                 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
1806
1807         if (IS_GEN_RANGE(i915, 6, 7))
1808                 uncore->flags |= UNCORE_HAS_FIFO;
1809
1810         /* clear out unclaimed reg detection bit */
1811         if (intel_uncore_unclaimed_mmio(uncore))
1812                 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n");
1813
1814         return 0;
1815
1816 out_mmio_cleanup:
1817         uncore_mmio_cleanup(uncore);
1818
1819         return ret;
1820 }
1821
1822 /*
1823  * We might have detected that some engines are fused off after we initialized
1824  * the forcewake domains. Prune them, to make sure they only reference existing
1825  * engines.
1826  */
1827 void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
1828 {
1829         struct drm_i915_private *i915 = uncore->i915;
1830         enum forcewake_domains fw_domains = uncore->fw_domains;
1831         enum forcewake_domain_id domain_id;
1832         int i;
1833
1834         if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11)
1835                 return;
1836
1837         for (i = 0; i < I915_MAX_VCS; i++) {
1838                 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
1839
1840                 if (HAS_ENGINE(i915, _VCS(i)))
1841                         continue;
1842
1843                 if (fw_domains & BIT(domain_id))
1844                         fw_domain_fini(uncore, domain_id);
1845         }
1846
1847         for (i = 0; i < I915_MAX_VECS; i++) {
1848                 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
1849
1850                 if (HAS_ENGINE(i915, _VECS(i)))
1851                         continue;
1852
1853                 if (fw_domains & BIT(domain_id))
1854                         fw_domain_fini(uncore, domain_id);
1855         }
1856 }
1857
1858 void intel_uncore_fini_mmio(struct intel_uncore *uncore)
1859 {
1860         if (intel_uncore_has_forcewake(uncore)) {
1861                 iosf_mbi_punit_acquire();
1862                 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
1863                         &uncore->pmic_bus_access_nb);
1864                 intel_uncore_forcewake_reset(uncore);
1865                 intel_uncore_fw_domains_fini(uncore);
1866                 iosf_mbi_punit_release();
1867         }
1868
1869         uncore_mmio_cleanup(uncore);
1870 }
1871
1872 static const struct reg_whitelist {
1873         i915_reg_t offset_ldw;
1874         i915_reg_t offset_udw;
1875         u16 gen_mask;
1876         u8 size;
1877 } reg_read_whitelist[] = { {
1878         .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1879         .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1880         .gen_mask = INTEL_GEN_MASK(4, 12),
1881         .size = 8
1882 } };
1883
1884 int i915_reg_read_ioctl(struct drm_device *dev,
1885                         void *data, struct drm_file *file)
1886 {
1887         struct drm_i915_private *i915 = to_i915(dev);
1888         struct intel_uncore *uncore = &i915->uncore;
1889         struct drm_i915_reg_read *reg = data;
1890         struct reg_whitelist const *entry;
1891         intel_wakeref_t wakeref;
1892         unsigned int flags;
1893         int remain;
1894         int ret = 0;
1895
1896         entry = reg_read_whitelist;
1897         remain = ARRAY_SIZE(reg_read_whitelist);
1898         while (remain) {
1899                 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
1900
1901                 GEM_BUG_ON(!is_power_of_2(entry->size));
1902                 GEM_BUG_ON(entry->size > 8);
1903                 GEM_BUG_ON(entry_offset & (entry->size - 1));
1904
1905                 if (INTEL_INFO(i915)->gen_mask & entry->gen_mask &&
1906                     entry_offset == (reg->offset & -entry->size))
1907                         break;
1908                 entry++;
1909                 remain--;
1910         }
1911
1912         if (!remain)
1913                 return -EINVAL;
1914
1915         flags = reg->offset & (entry->size - 1);
1916
1917         with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
1918                 if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
1919                         reg->val = intel_uncore_read64_2x32(uncore,
1920                                                             entry->offset_ldw,
1921                                                             entry->offset_udw);
1922                 else if (entry->size == 8 && flags == 0)
1923                         reg->val = intel_uncore_read64(uncore,
1924                                                        entry->offset_ldw);
1925                 else if (entry->size == 4 && flags == 0)
1926                         reg->val = intel_uncore_read(uncore, entry->offset_ldw);
1927                 else if (entry->size == 2 && flags == 0)
1928                         reg->val = intel_uncore_read16(uncore,
1929                                                        entry->offset_ldw);
1930                 else if (entry->size == 1 && flags == 0)
1931                         reg->val = intel_uncore_read8(uncore,
1932                                                       entry->offset_ldw);
1933                 else
1934                         ret = -EINVAL;
1935         }
1936
1937         return ret;
1938 }
1939
1940 /**
1941  * __intel_wait_for_register_fw - wait until register matches expected state
1942  * @uncore: the struct intel_uncore
1943  * @reg: the register to read
1944  * @mask: mask to apply to register value
1945  * @value: expected value
1946  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1947  * @slow_timeout_ms: slow timeout in millisecond
1948  * @out_value: optional placeholder to hold registry value
1949  *
1950  * This routine waits until the target register @reg contains the expected
1951  * @value after applying the @mask, i.e. it waits until ::
1952  *
1953  *     (I915_READ_FW(reg) & mask) == value
1954  *
1955  * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1956  * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1957  * must be not larger than 20,0000 microseconds.
1958  *
1959  * Note that this routine assumes the caller holds forcewake asserted, it is
1960  * not suitable for very long waits. See intel_wait_for_register() if you
1961  * wish to wait without holding forcewake for the duration (i.e. you expect
1962  * the wait to be slow).
1963  *
1964  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
1965  */
1966 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
1967                                  i915_reg_t reg,
1968                                  u32 mask,
1969                                  u32 value,
1970                                  unsigned int fast_timeout_us,
1971                                  unsigned int slow_timeout_ms,
1972                                  u32 *out_value)
1973 {
1974         u32 uninitialized_var(reg_value);
1975 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
1976         int ret;
1977
1978         /* Catch any overuse of this function */
1979         might_sleep_if(slow_timeout_ms);
1980         GEM_BUG_ON(fast_timeout_us > 20000);
1981
1982         ret = -ETIMEDOUT;
1983         if (fast_timeout_us && fast_timeout_us <= 20000)
1984                 ret = _wait_for_atomic(done, fast_timeout_us, 0);
1985         if (ret && slow_timeout_ms)
1986                 ret = wait_for(done, slow_timeout_ms);
1987
1988         if (out_value)
1989                 *out_value = reg_value;
1990
1991         return ret;
1992 #undef done
1993 }
1994
1995 /**
1996  * __intel_wait_for_register - wait until register matches expected state
1997  * @uncore: the struct intel_uncore
1998  * @reg: the register to read
1999  * @mask: mask to apply to register value
2000  * @value: expected value
2001  * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
2002  * @slow_timeout_ms: slow timeout in millisecond
2003  * @out_value: optional placeholder to hold registry value
2004  *
2005  * This routine waits until the target register @reg contains the expected
2006  * @value after applying the @mask, i.e. it waits until ::
2007  *
2008  *     (I915_READ(reg) & mask) == value
2009  *
2010  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
2011  *
2012  * Return: 0 if the register matches the desired condition, or -ETIMEDOUT.
2013  */
2014 int __intel_wait_for_register(struct intel_uncore *uncore,
2015                               i915_reg_t reg,
2016                               u32 mask,
2017                               u32 value,
2018                               unsigned int fast_timeout_us,
2019                               unsigned int slow_timeout_ms,
2020                               u32 *out_value)
2021 {
2022         unsigned fw =
2023                 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
2024         u32 reg_value;
2025         int ret;
2026
2027         might_sleep_if(slow_timeout_ms);
2028
2029         spin_lock_irq(&uncore->lock);
2030         intel_uncore_forcewake_get__locked(uncore, fw);
2031
2032         ret = __intel_wait_for_register_fw(uncore,
2033                                            reg, mask, value,
2034                                            fast_timeout_us, 0, &reg_value);
2035
2036         intel_uncore_forcewake_put__locked(uncore, fw);
2037         spin_unlock_irq(&uncore->lock);
2038
2039         if (ret && slow_timeout_ms)
2040                 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2041                                                                        reg),
2042                                  (reg_value & mask) == value,
2043                                  slow_timeout_ms * 1000, 10, 1000);
2044
2045         /* just trace the final value */
2046         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2047
2048         if (out_value)
2049                 *out_value = reg_value;
2050
2051         return ret;
2052 }
2053
2054 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
2055 {
2056         bool ret;
2057
2058         spin_lock_irq(&uncore->debug->lock);
2059         ret = check_for_unclaimed_mmio(uncore);
2060         spin_unlock_irq(&uncore->debug->lock);
2061
2062         return ret;
2063 }
2064
2065 bool
2066 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
2067 {
2068         bool ret = false;
2069
2070         spin_lock_irq(&uncore->debug->lock);
2071
2072         if (unlikely(uncore->debug->unclaimed_mmio_check <= 0))
2073                 goto out;
2074
2075         if (unlikely(check_for_unclaimed_mmio(uncore))) {
2076                 if (!i915_modparams.mmio_debug) {
2077                         drm_dbg(&uncore->i915->drm,
2078                                 "Unclaimed register detected, "
2079                                 "enabling oneshot unclaimed register reporting. "
2080                                 "Please use i915.mmio_debug=N for more information.\n");
2081                         i915_modparams.mmio_debug++;
2082                 }
2083                 uncore->debug->unclaimed_mmio_check--;
2084                 ret = true;
2085         }
2086
2087 out:
2088         spin_unlock_irq(&uncore->debug->lock);
2089
2090         return ret;
2091 }
2092
2093 /**
2094  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
2095  *                                  a register
2096  * @uncore: pointer to struct intel_uncore
2097  * @reg: register in question
2098  * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
2099  *
2100  * Returns a set of forcewake domains required to be taken with for example
2101  * intel_uncore_forcewake_get for the specified register to be accessible in the
2102  * specified mode (read, write or read/write) with raw mmio accessors.
2103  *
2104  * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
2105  * callers to do FIFO management on their own or risk losing writes.
2106  */
2107 enum forcewake_domains
2108 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
2109                                i915_reg_t reg, unsigned int op)
2110 {
2111         enum forcewake_domains fw_domains = 0;
2112
2113         drm_WARN_ON(&uncore->i915->drm, !op);
2114
2115         if (!intel_uncore_has_forcewake(uncore))
2116                 return 0;
2117
2118         if (op & FW_REG_READ)
2119                 fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
2120
2121         if (op & FW_REG_WRITE)
2122                 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
2123
2124         drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains);
2125
2126         return fw_domains;
2127 }
2128
2129 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2130 #include "selftests/mock_uncore.c"
2131 #include "selftests/intel_uncore.c"
2132 #endif