2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_edid.h>
19 #include <linux/arm-smccc.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/hdmi.h>
23 #include <linux/i2c.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/of_platform.h>
29 #include <linux/of_gpio.h>
30 #include <linux/of_graph.h>
31 #include <linux/phy/phy.h>
32 #include <linux/platform_device.h>
33 #include <linux/regmap.h>
34 #include <sound/hdmi-codec.h>
37 #include "mtk_hdmi_regs.h"
41 enum mtk_hdmi_clk_id {
42 MTK_HDMI_CLK_HDMI_PIXEL,
43 MTK_HDMI_CLK_HDMI_PLL,
44 MTK_HDMI_CLK_AUD_BCLK,
45 MTK_HDMI_CLK_AUD_SPDIF,
49 enum hdmi_aud_input_type {
50 HDMI_AUD_INPUT_I2S = 0,
54 enum hdmi_aud_i2s_fmt {
55 HDMI_I2S_MODE_RJT_24BIT = 0,
56 HDMI_I2S_MODE_RJT_16BIT,
57 HDMI_I2S_MODE_LJT_24BIT,
58 HDMI_I2S_MODE_LJT_16BIT,
59 HDMI_I2S_MODE_I2S_24BIT,
60 HDMI_I2S_MODE_I2S_16BIT
73 enum hdmi_aud_channel_type {
74 HDMI_AUD_CHAN_TYPE_1_0 = 0,
75 HDMI_AUD_CHAN_TYPE_1_1,
76 HDMI_AUD_CHAN_TYPE_2_0,
77 HDMI_AUD_CHAN_TYPE_2_1,
78 HDMI_AUD_CHAN_TYPE_3_0,
79 HDMI_AUD_CHAN_TYPE_3_1,
80 HDMI_AUD_CHAN_TYPE_4_0,
81 HDMI_AUD_CHAN_TYPE_4_1,
82 HDMI_AUD_CHAN_TYPE_5_0,
83 HDMI_AUD_CHAN_TYPE_5_1,
84 HDMI_AUD_CHAN_TYPE_6_0,
85 HDMI_AUD_CHAN_TYPE_6_1,
86 HDMI_AUD_CHAN_TYPE_7_0,
87 HDMI_AUD_CHAN_TYPE_7_1,
88 HDMI_AUD_CHAN_TYPE_3_0_LRS,
89 HDMI_AUD_CHAN_TYPE_3_1_LRS,
90 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
91 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
92 HDMI_AUD_CHAN_TYPE_6_1_CS,
93 HDMI_AUD_CHAN_TYPE_6_1_CH,
94 HDMI_AUD_CHAN_TYPE_6_1_OH,
95 HDMI_AUD_CHAN_TYPE_6_1_CHR,
96 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
97 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
98 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
99 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
100 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
102 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
104 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
105 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
106 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
107 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
108 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
109 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
110 HDMI_AUD_CHAN_TYPE_6_0_CS,
111 HDMI_AUD_CHAN_TYPE_6_0_CH,
112 HDMI_AUD_CHAN_TYPE_6_0_OH,
113 HDMI_AUD_CHAN_TYPE_6_0_CHR,
114 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
115 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
116 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
117 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
118 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
120 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
122 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
123 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
124 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
125 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
126 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
127 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
128 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
129 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
132 enum hdmi_aud_channel_swap_type {
134 HDMI_AUD_SWAP_LFE_CC,
136 HDMI_AUD_SWAP_RLS_RRS,
137 HDMI_AUD_SWAP_LR_STATUS,
140 struct hdmi_audio_param {
141 enum hdmi_audio_coding_type aud_codec;
142 enum hdmi_audio_sample_size aud_sampe_size;
143 enum hdmi_aud_input_type aud_input_type;
144 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
145 enum hdmi_aud_mclk aud_mclk;
146 enum hdmi_aud_channel_type aud_input_chan_type;
147 struct hdmi_codec_params codec_params;
151 struct drm_bridge bridge;
152 struct drm_bridge *next_bridge;
153 struct drm_connector conn;
156 struct device *cec_dev;
157 struct i2c_adapter *ddc_adpt;
158 struct clk *clk[MTK_HDMI_CLK_COUNT];
159 struct drm_display_mode mode;
167 struct regmap *sys_regmap;
168 unsigned int sys_offset;
170 enum hdmi_colorspace csp;
171 struct hdmi_audio_param aud_param;
177 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
179 return container_of(b, struct mtk_hdmi, bridge);
182 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
184 return container_of(c, struct mtk_hdmi, conn);
187 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
189 return readl(hdmi->regs + offset);
192 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
194 writel(val, hdmi->regs + offset);
197 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
199 void __iomem *reg = hdmi->regs + offset;
207 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
209 void __iomem *reg = hdmi->regs + offset;
217 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
219 void __iomem *reg = hdmi->regs + offset;
223 tmp = (tmp & ~mask) | (val & mask);
227 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
229 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
233 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
235 struct arm_smccc_res res;
238 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
239 * output. This bit can only be controlled in ARM supervisor mode.
240 * The ARM trusted firmware provides an API for the HDMI driver to set
241 * this control bit to enable HDMI output in supervisor mode.
243 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
244 0, 0, 0, 0, 0, &res);
246 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
247 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
248 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
249 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
252 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
254 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
255 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
258 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
260 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
263 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
265 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
268 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
270 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
272 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
274 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
275 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
279 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
281 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
285 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
287 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
290 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
292 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
295 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
298 u32 ctrl_reg = GRL_CTRL;
301 enum hdmi_infoframe_type frame_type;
305 int ctrl_frame_en = 0;
307 frame_type = *buffer;
318 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
319 frame_type, frame_ver, frame_len, checksum);
321 switch (frame_type) {
322 case HDMI_INFOFRAME_TYPE_AVI:
323 ctrl_frame_en = CTRL_AVI_EN;
326 case HDMI_INFOFRAME_TYPE_SPD:
327 ctrl_frame_en = CTRL_SPD_EN;
330 case HDMI_INFOFRAME_TYPE_AUDIO:
331 ctrl_frame_en = CTRL_AUDIO_EN;
334 case HDMI_INFOFRAME_TYPE_VENDOR:
335 ctrl_frame_en = VS_EN;
336 ctrl_reg = GRL_ACP_ISRC_CTRL;
339 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
340 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
341 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
342 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
344 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
345 for (i = 0; i < frame_len; i++)
346 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
348 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
351 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
353 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
357 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
359 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
360 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
361 usleep_range(2000, 4000);
362 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
363 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
366 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
368 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
369 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
373 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
375 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
376 usleep_range(2000, 4000);
377 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
380 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
382 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
383 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
384 usleep_range(2000, 4000);
385 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
386 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
389 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
391 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
395 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
398 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
402 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
403 struct drm_display_mode *mode)
405 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
407 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
408 mode->clock == 74250 &&
409 mode->vdisplay == 1080)
410 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
412 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
415 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
416 enum hdmi_aud_channel_swap_type swap)
421 case HDMI_AUD_SWAP_LR:
424 case HDMI_AUD_SWAP_LFE_CC:
425 swap_bit = LFE_CC_SWAP;
427 case HDMI_AUD_SWAP_LSRS:
428 swap_bit = LSRS_SWAP;
430 case HDMI_AUD_SWAP_RLS_RRS:
431 swap_bit = RLS_RRS_SWAP;
433 case HDMI_AUD_SWAP_LR_STATUS:
434 swap_bit = LR_STATUS_SWAP;
437 swap_bit = LFE_CC_SWAP;
440 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
443 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
444 enum hdmi_audio_sample_size bit_num)
449 case HDMI_AUDIO_SAMPLE_SIZE_16:
452 case HDMI_AUDIO_SAMPLE_SIZE_20:
455 case HDMI_AUDIO_SAMPLE_SIZE_24:
456 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
461 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
464 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
465 enum hdmi_aud_i2s_fmt i2s_fmt)
469 val = mtk_hdmi_read(hdmi, GRL_CFG0);
470 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
473 case HDMI_I2S_MODE_RJT_24BIT:
474 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
476 case HDMI_I2S_MODE_RJT_16BIT:
477 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
479 case HDMI_I2S_MODE_LJT_24BIT:
481 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
483 case HDMI_I2S_MODE_LJT_16BIT:
484 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
486 case HDMI_I2S_MODE_I2S_24BIT:
487 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
489 case HDMI_I2S_MODE_I2S_16BIT:
490 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
493 mtk_hdmi_write(hdmi, GRL_CFG0, val);
496 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
498 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
501 /* Disable high bitrate, set DST packet normal/double */
502 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
505 val = DST_NORMAL_DOUBLE | SACD_DST;
509 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
512 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
513 enum hdmi_aud_channel_type channel_type,
516 unsigned int ch_switch;
519 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
520 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
521 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
522 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
524 if (channel_count == 2) {
525 i2s_uv = I2S_UV_CH_EN(0);
526 } else if (channel_count == 3 || channel_count == 4) {
527 if (channel_count == 4 &&
528 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
529 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
530 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
532 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
533 } else if (channel_count == 6 || channel_count == 5) {
534 if (channel_count == 6 &&
535 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
536 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
537 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
538 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
540 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
543 } else if (channel_count == 8 || channel_count == 7) {
544 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
545 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
547 i2s_uv = I2S_UV_CH_EN(0);
550 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
551 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
552 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
553 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
556 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
557 enum hdmi_aud_input_type input_type)
561 val = mtk_hdmi_read(hdmi, GRL_CFG1);
562 if (input_type == HDMI_AUD_INPUT_I2S &&
563 (val & CFG1_SPDIF) == CFG1_SPDIF) {
565 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
566 (val & CFG1_SPDIF) == 0) {
569 mtk_hdmi_write(hdmi, GRL_CFG1, val);
572 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
577 for (i = 0; i < 5; i++) {
578 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
579 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
580 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
582 for (; i < 24; i++) {
583 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
584 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
588 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
592 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
593 if (val & MIX_CTRL_SRC_EN) {
594 val &= ~MIX_CTRL_SRC_EN;
595 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
596 usleep_range(255, 512);
597 val |= MIX_CTRL_SRC_EN;
598 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
602 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
606 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
607 val &= ~MIX_CTRL_SRC_EN;
608 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
609 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
612 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
613 enum hdmi_aud_mclk mclk)
617 val = mtk_hdmi_read(hdmi, GRL_CFG5);
618 val &= CFG5_CD_RATIO_MASK;
621 case HDMI_AUD_MCLK_128FS:
624 case HDMI_AUD_MCLK_256FS:
627 case HDMI_AUD_MCLK_384FS:
630 case HDMI_AUD_MCLK_512FS:
633 case HDMI_AUD_MCLK_768FS:
640 mtk_hdmi_write(hdmi, GRL_CFG5, val);
648 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
649 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
650 /* Clock, N: 32kHz 44.1kHz 48kHz */
651 { 25175, { 4576, 7007, 6864 } },
652 { 74176, { 11648, 17836, 11648 } },
653 { 148352, { 11648, 8918, 5824 } },
654 { 296703, { 5824, 4459, 5824 } },
655 { 297000, { 3072, 4704, 5120 } },
656 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
660 * hdmi_recommended_n() - Return N value recommended by HDMI specification
661 * @freq: audio sample rate in Hz
662 * @clock: rounded TMDS clock in kHz
664 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
666 const struct hdmi_acr_n *recommended;
669 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
670 if (clock == hdmi_rec_n_table[i].clock)
673 recommended = hdmi_rec_n_table + i;
677 return recommended->n[0];
679 return recommended->n[1];
681 return recommended->n[2];
683 return recommended->n[1] * 2;
685 return recommended->n[2] * 2;
687 return recommended->n[1] * 4;
689 return recommended->n[2] * 4;
691 return (128 * freq) / 1000;
695 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
699 return 25174825; /* 25.2/1.001 MHz */
701 return 74175824; /* 74.25/1.001 MHz */
703 return 148351648; /* 148.5/1.001 MHz */
705 return 296703297; /* 297/1.001 MHz */
711 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
712 unsigned int tmds_clock, unsigned int n)
714 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
715 128 * audio_sample_rate);
718 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
721 unsigned char val[NCTS_BYTES];
724 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
725 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
726 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
727 memset(val, 0, sizeof(val));
729 val[0] = (cts >> 24) & 0xff;
730 val[1] = (cts >> 16) & 0xff;
731 val[2] = (cts >> 8) & 0xff;
734 val[4] = (n >> 16) & 0xff;
735 val[5] = (n >> 8) & 0xff;
738 for (i = 0; i < NCTS_BYTES; i++)
739 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
742 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
743 unsigned int sample_rate,
748 n = hdmi_recommended_n(sample_rate, clock);
749 cts = hdmi_expected_cts(sample_rate, clock, n);
751 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
752 __func__, sample_rate, clock, n, cts);
754 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
756 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
759 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
761 switch (channel_type) {
762 case HDMI_AUD_CHAN_TYPE_1_0:
763 case HDMI_AUD_CHAN_TYPE_1_1:
764 case HDMI_AUD_CHAN_TYPE_2_0:
766 case HDMI_AUD_CHAN_TYPE_2_1:
767 case HDMI_AUD_CHAN_TYPE_3_0:
769 case HDMI_AUD_CHAN_TYPE_3_1:
770 case HDMI_AUD_CHAN_TYPE_4_0:
771 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
773 case HDMI_AUD_CHAN_TYPE_4_1:
774 case HDMI_AUD_CHAN_TYPE_5_0:
775 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
776 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
778 case HDMI_AUD_CHAN_TYPE_5_1:
779 case HDMI_AUD_CHAN_TYPE_6_0:
780 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
781 case HDMI_AUD_CHAN_TYPE_6_0_CS:
782 case HDMI_AUD_CHAN_TYPE_6_0_CH:
783 case HDMI_AUD_CHAN_TYPE_6_0_OH:
784 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
786 case HDMI_AUD_CHAN_TYPE_6_1:
787 case HDMI_AUD_CHAN_TYPE_6_1_CS:
788 case HDMI_AUD_CHAN_TYPE_6_1_CH:
789 case HDMI_AUD_CHAN_TYPE_6_1_OH:
790 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
791 case HDMI_AUD_CHAN_TYPE_7_0:
792 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
793 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
794 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
795 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
796 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
797 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
798 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
799 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
800 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
801 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
802 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
803 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
804 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
805 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
806 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
808 case HDMI_AUD_CHAN_TYPE_7_1:
809 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
810 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
811 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
812 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
813 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
814 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
815 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
816 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
817 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
818 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
819 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
820 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
821 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
822 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
829 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
834 /* The DPI driver already should have set TVDPLL to the correct rate */
835 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
837 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
842 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
844 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
845 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
848 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
850 mtk_hdmi_hw_config_sys(hdmi);
851 mtk_hdmi_hw_set_deep_color_mode(hdmi);
855 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
856 struct drm_display_mode *mode)
858 mtk_hdmi_hw_reset(hdmi);
859 mtk_hdmi_hw_enable_notice(hdmi, true);
860 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
861 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
862 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
864 mtk_hdmi_hw_msic_setting(hdmi, mode);
867 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
869 mtk_hdmi_hw_send_aud_packet(hdmi, enable);
873 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
875 mtk_hdmi_hw_ncts_enable(hdmi, on);
879 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
881 enum hdmi_aud_channel_type chan_type;
885 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
886 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
888 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
889 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
890 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
891 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
892 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
895 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
896 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
898 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
899 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
900 mtk_hdmi_hw_audio_config(hdmi, dst);
902 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
903 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
905 chan_type = hdmi->aud_param.aud_input_chan_type;
906 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
907 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
908 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
913 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
914 struct drm_display_mode *display_mode)
916 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
918 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
919 mtk_hdmi_hw_aud_src_disable(hdmi);
920 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
922 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
923 switch (sample_rate) {
933 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
935 switch (sample_rate) {
943 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
946 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
948 mtk_hdmi_hw_aud_src_reenable(hdmi);
952 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
953 struct drm_display_mode *display_mode)
955 mtk_hdmi_hw_aud_mute(hdmi);
956 mtk_hdmi_aud_enable_packet(hdmi, false);
958 mtk_hdmi_aud_set_input(hdmi);
959 mtk_hdmi_aud_set_src(hdmi, display_mode);
960 mtk_hdmi_hw_aud_set_channel_status(hdmi,
961 hdmi->aud_param.codec_params.iec.status);
963 usleep_range(50, 100);
965 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
966 mtk_hdmi_aud_enable_packet(hdmi, true);
967 mtk_hdmi_hw_aud_unmute(hdmi);
971 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
972 struct drm_display_mode *mode)
974 struct hdmi_avi_infoframe frame;
978 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
981 "Failed to get AVI infoframe from mode: %zd\n", err);
985 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
987 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
991 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
995 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
999 struct hdmi_spd_infoframe frame;
1003 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1005 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1010 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1012 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1016 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1020 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1022 struct hdmi_audio_infoframe frame;
1026 err = hdmi_audio_infoframe_init(&frame);
1028 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1033 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1034 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1035 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1036 frame.channels = mtk_hdmi_aud_get_chnl_count(
1037 hdmi->aud_param.aud_input_chan_type);
1039 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1041 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1046 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1050 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1051 struct drm_display_mode *mode)
1053 struct hdmi_vendor_infoframe frame;
1057 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1061 "Failed to get vendor infoframe from mode: %zd\n", err);
1065 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1067 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1072 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1076 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1078 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1080 hdmi->csp = HDMI_COLORSPACE_RGB;
1081 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1082 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1083 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1084 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1085 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1086 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1091 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1093 mtk_hdmi_aud_enable_packet(hdmi, true);
1094 hdmi->audio_enable = true;
1097 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1099 mtk_hdmi_aud_enable_packet(hdmi, false);
1100 hdmi->audio_enable = false;
1103 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1104 struct hdmi_audio_param *param)
1106 if (!hdmi->audio_enable) {
1107 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1110 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1111 param->aud_codec, param->aud_input_type,
1112 param->aud_input_chan_type, param->codec_params.sample_rate);
1113 memcpy(&hdmi->aud_param, param, sizeof(*param));
1114 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1117 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1118 struct drm_display_mode *mode)
1122 mtk_hdmi_hw_vid_black(hdmi, true);
1123 mtk_hdmi_hw_aud_mute(hdmi);
1124 mtk_hdmi_hw_send_av_mute(hdmi);
1125 phy_power_off(hdmi->phy);
1127 ret = mtk_hdmi_video_change_vpll(hdmi,
1128 mode->clock * 1000);
1130 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1133 mtk_hdmi_video_set_display_mode(hdmi, mode);
1135 phy_power_on(hdmi->phy);
1136 mtk_hdmi_aud_output_config(hdmi, mode);
1138 mtk_hdmi_hw_vid_black(hdmi, false);
1139 mtk_hdmi_hw_aud_unmute(hdmi);
1140 mtk_hdmi_hw_send_av_unmute(hdmi);
1145 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1146 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1147 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1148 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1149 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1152 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1153 struct device_node *np)
1157 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1158 hdmi->clk[i] = of_clk_get_by_name(np,
1159 mtk_hdmi_clk_names[i]);
1160 if (IS_ERR(hdmi->clk[i]))
1161 return PTR_ERR(hdmi->clk[i]);
1166 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1170 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1174 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1180 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1184 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1186 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1187 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1190 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1193 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1195 return mtk_cec_hpd_high(hdmi->cec_dev) ?
1196 connector_status_connected : connector_status_disconnected;
1199 static void hdmi_conn_destroy(struct drm_connector *conn)
1201 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1203 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1205 drm_connector_cleanup(conn);
1208 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1210 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1214 if (!hdmi->ddc_adpt)
1217 edid = drm_get_edid(conn, hdmi->ddc_adpt);
1221 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1223 drm_mode_connector_update_edid_property(conn, edid);
1225 ret = drm_add_edid_modes(conn, edid);
1230 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1231 struct drm_display_mode *mode)
1233 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1235 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1236 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1237 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1239 if (hdmi->bridge.next) {
1240 struct drm_display_mode adjusted_mode;
1242 drm_mode_copy(&adjusted_mode, mode);
1243 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1248 if (mode->clock < 27000)
1249 return MODE_CLOCK_LOW;
1250 if (mode->clock > 297000)
1251 return MODE_CLOCK_HIGH;
1253 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1256 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1258 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1260 return hdmi->bridge.encoder;
1263 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1264 .detect = hdmi_conn_detect,
1265 .fill_modes = drm_helper_probe_single_connector_modes,
1266 .destroy = hdmi_conn_destroy,
1267 .reset = drm_atomic_helper_connector_reset,
1268 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1269 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1272 static const struct drm_connector_helper_funcs
1273 mtk_hdmi_connector_helper_funcs = {
1274 .get_modes = mtk_hdmi_conn_get_modes,
1275 .mode_valid = mtk_hdmi_conn_mode_valid,
1276 .best_encoder = mtk_hdmi_conn_best_enc,
1279 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1281 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1283 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1284 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1291 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1293 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1296 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1297 &mtk_hdmi_connector_funcs,
1298 DRM_MODE_CONNECTOR_HDMIA);
1300 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1303 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1305 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1306 hdmi->conn.interlace_allowed = true;
1307 hdmi->conn.doublescan_allowed = false;
1309 ret = drm_mode_connector_attach_encoder(&hdmi->conn,
1313 "Failed to attach connector to encoder: %d\n", ret);
1317 if (hdmi->next_bridge) {
1318 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1322 "Failed to attach external bridge: %d\n", ret);
1327 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1332 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1333 const struct drm_display_mode *mode,
1334 struct drm_display_mode *adjusted_mode)
1339 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1341 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1346 phy_power_off(hdmi->phy);
1347 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1348 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1350 hdmi->enabled = false;
1353 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1355 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1360 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1361 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1363 hdmi->powered = false;
1366 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1367 struct drm_display_mode *mode,
1368 struct drm_display_mode *adjusted_mode)
1370 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1372 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1373 adjusted_mode->name, adjusted_mode->hdisplay);
1374 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1375 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1376 adjusted_mode->htotal);
1377 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1378 adjusted_mode->hskew, adjusted_mode->vdisplay);
1379 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1380 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1381 adjusted_mode->vtotal);
1382 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1383 adjusted_mode->vscan, adjusted_mode->flags);
1385 drm_mode_copy(&hdmi->mode, adjusted_mode);
1388 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1390 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1392 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1393 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1395 hdmi->powered = true;
1398 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1399 struct drm_display_mode *mode)
1401 mtk_hdmi_setup_audio_infoframe(hdmi);
1402 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1403 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1404 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1405 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1408 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1410 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1412 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1413 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1414 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1415 phy_power_on(hdmi->phy);
1416 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1418 hdmi->enabled = true;
1421 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1422 .attach = mtk_hdmi_bridge_attach,
1423 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1424 .disable = mtk_hdmi_bridge_disable,
1425 .post_disable = mtk_hdmi_bridge_post_disable,
1426 .mode_set = mtk_hdmi_bridge_mode_set,
1427 .pre_enable = mtk_hdmi_bridge_pre_enable,
1428 .enable = mtk_hdmi_bridge_enable,
1431 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1432 struct platform_device *pdev)
1434 struct device *dev = &pdev->dev;
1435 struct device_node *np = dev->of_node;
1436 struct device_node *cec_np, *remote, *i2c_np;
1437 struct platform_device *cec_pdev;
1438 struct regmap *regmap;
1439 struct resource *mem;
1442 ret = mtk_hdmi_get_all_clk(hdmi, np);
1444 dev_err(dev, "Failed to get clocks: %d\n", ret);
1448 /* The CEC module handles HDMI hotplug detection */
1449 cec_np = of_find_compatible_node(np->parent, NULL,
1450 "mediatek,mt8173-cec");
1452 dev_err(dev, "Failed to find CEC node\n");
1456 cec_pdev = of_find_device_by_node(cec_np);
1458 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1460 return -EPROBE_DEFER;
1462 hdmi->cec_dev = &cec_pdev->dev;
1465 * The mediatek,syscon-hdmi property contains a phandle link to the
1466 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1467 * registers it contains.
1469 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1470 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1473 ret = PTR_ERR(regmap);
1475 ret = PTR_ERR(regmap);
1477 "Failed to get system configuration registers: %d\n",
1481 hdmi->sys_regmap = regmap;
1483 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484 hdmi->regs = devm_ioremap_resource(dev, mem);
1485 if (IS_ERR(hdmi->regs))
1486 return PTR_ERR(hdmi->regs);
1488 remote = of_graph_get_remote_node(np, 1, 0);
1492 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1493 hdmi->next_bridge = of_drm_find_bridge(remote);
1494 if (!hdmi->next_bridge) {
1495 dev_err(dev, "Waiting for external bridge\n");
1496 of_node_put(remote);
1497 return -EPROBE_DEFER;
1501 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1503 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1505 of_node_put(remote);
1508 of_node_put(remote);
1510 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1511 if (!hdmi->ddc_adpt) {
1512 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1520 * HDMI audio codec callbacks
1523 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1524 struct hdmi_codec_daifmt *daifmt,
1525 struct hdmi_codec_params *params)
1527 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1528 struct hdmi_audio_param hdmi_params;
1529 unsigned int chan = params->cea.channels;
1531 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1532 params->sample_rate, params->sample_width, chan);
1534 if (!hdmi->bridge.encoder)
1539 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1542 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1545 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1548 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1551 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1555 switch (params->sample_rate) {
1565 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1566 params->sample_rate);
1570 switch (daifmt->fmt) {
1572 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1573 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1574 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1575 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1576 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1579 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1584 memcpy(&hdmi_params.codec_params, params,
1585 sizeof(hdmi_params.codec_params));
1587 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1592 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1594 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1596 dev_dbg(dev, "%s\n", __func__);
1598 mtk_hdmi_audio_enable(hdmi);
1603 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1605 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1607 dev_dbg(dev, "%s\n", __func__);
1609 mtk_hdmi_audio_disable(hdmi);
1613 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1615 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1617 dev_dbg(dev, "%s(%d)\n", __func__, enable);
1620 mtk_hdmi_hw_aud_mute(hdmi);
1622 mtk_hdmi_hw_aud_unmute(hdmi);
1627 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1629 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1631 dev_dbg(dev, "%s\n", __func__);
1633 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1638 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1639 .hw_params = mtk_hdmi_audio_hw_params,
1640 .audio_startup = mtk_hdmi_audio_startup,
1641 .audio_shutdown = mtk_hdmi_audio_shutdown,
1642 .digital_mute = mtk_hdmi_audio_digital_mute,
1643 .get_eld = mtk_hdmi_audio_get_eld,
1646 static void mtk_hdmi_register_audio_driver(struct device *dev)
1648 struct hdmi_codec_pdata codec_data = {
1649 .ops = &mtk_hdmi_audio_codec_ops,
1650 .max_i2s_channels = 2,
1653 struct platform_device *pdev;
1655 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1656 PLATFORM_DEVID_AUTO, &codec_data,
1657 sizeof(codec_data));
1661 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1664 static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1666 struct mtk_hdmi *hdmi;
1667 struct device *dev = &pdev->dev;
1670 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1676 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1680 hdmi->phy = devm_phy_get(dev, "hdmi");
1681 if (IS_ERR(hdmi->phy)) {
1682 ret = PTR_ERR(hdmi->phy);
1683 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1687 platform_set_drvdata(pdev, hdmi);
1689 ret = mtk_hdmi_output_init(hdmi);
1691 dev_err(dev, "Failed to initialize hdmi output\n");
1695 mtk_hdmi_register_audio_driver(dev);
1697 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1698 hdmi->bridge.of_node = pdev->dev.of_node;
1699 drm_bridge_add(&hdmi->bridge);
1701 ret = mtk_hdmi_clk_enable_audio(hdmi);
1703 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1704 goto err_bridge_remove;
1707 dev_dbg(dev, "mediatek hdmi probe success\n");
1711 drm_bridge_remove(&hdmi->bridge);
1715 static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1717 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1719 drm_bridge_remove(&hdmi->bridge);
1720 mtk_hdmi_clk_disable_audio(hdmi);
1724 #ifdef CONFIG_PM_SLEEP
1725 static int mtk_hdmi_suspend(struct device *dev)
1727 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1729 mtk_hdmi_clk_disable_audio(hdmi);
1730 dev_dbg(dev, "hdmi suspend success!\n");
1734 static int mtk_hdmi_resume(struct device *dev)
1736 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1739 ret = mtk_hdmi_clk_enable_audio(hdmi);
1741 dev_err(dev, "hdmi resume failed!\n");
1745 dev_dbg(dev, "hdmi resume success!\n");
1749 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1750 mtk_hdmi_suspend, mtk_hdmi_resume);
1752 static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1753 { .compatible = "mediatek,mt8173-hdmi", },
1757 static struct platform_driver mtk_hdmi_driver = {
1758 .probe = mtk_drm_hdmi_probe,
1759 .remove = mtk_drm_hdmi_remove,
1761 .name = "mediatek-drm-hdmi",
1762 .of_match_table = mtk_drm_hdmi_of_ids,
1763 .pm = &mtk_hdmi_pm_ops,
1767 static struct platform_driver * const mtk_hdmi_drivers[] = {
1768 &mtk_hdmi_phy_driver,
1769 &mtk_hdmi_ddc_driver,
1774 static int __init mtk_hdmitx_init(void)
1776 return platform_register_drivers(mtk_hdmi_drivers,
1777 ARRAY_SIZE(mtk_hdmi_drivers));
1780 static void __exit mtk_hdmitx_exit(void)
1782 platform_unregister_drivers(mtk_hdmi_drivers,
1783 ARRAY_SIZE(mtk_hdmi_drivers));
1786 module_init(mtk_hdmitx_init);
1787 module_exit(mtk_hdmitx_exit);
1789 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1790 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1791 MODULE_LICENSE("GPL v2");