drivers/gpu/drm/msm/adreno/a6xx_gmu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
   3
   4 #include <linux/clk.h>
   5 #include <linux/interconnect.h>
   6 #include <linux/of_platform.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/pm_domain.h>
   9 #include <linux/pm_opp.h>
  10 #include <soc/qcom/cmd-db.h>
  11 #include <drm/drm_gem.h>
  12
  13 #include "a6xx_gpu.h"
  14 #include "a6xx_gmu.xml.h"
  15 #include "msm_gem.h"
  16 #include "msm_gpu_trace.h"
  17 #include "msm_mmu.h"
  18
  19 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
  20 {
  21         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
  22         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
  23         struct msm_gpu *gpu = &adreno_gpu->base;
  24
  25         /* FIXME: add a banner here */
  26         gmu->hung = true;
  27
  28         /* Turn off the hangcheck timer while we are resetting */
  29         del_timer(&gpu->hangcheck_timer);
  30
  31         /* Queue the GPU handler because we need to treat this as a recovery */
  32         kthread_queue_work(gpu->worker, &gpu->recover_work);
  33 }
  34
  35 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
  36 {
  37         struct a6xx_gmu *gmu = data;
  38         u32 status;
  39
  40         status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
  41         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
  42
  43         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
  44                 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
  45
  46                 a6xx_gmu_fault(gmu);
  47         }
  48
  49         if (status &  A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
  50                 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
  51
  52         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
  53                 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
  54                         gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
  55
  56         return IRQ_HANDLED;
  57 }
  58
  59 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
  60 {
  61         struct a6xx_gmu *gmu = data;
  62         u32 status;
  63
  64         status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
  65         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
  66
  67         if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
  68                 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
  69
  70                 a6xx_gmu_fault(gmu);
  71         }
  72
  73         return IRQ_HANDLED;
  74 }
  75
  76 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
  77 {
  78         u32 val;
  79
  80         /* This can be called from gpu state code so make sure GMU is valid */
  81         if (!gmu->initialized)
  82                 return false;
  83
  84         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
  85
  86         return !(val &
  87                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
  88                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
  89 }
  90
  91 /* Check to see if the GX rail is still powered */
  92 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
  93 {
  94         u32 val;
  95
  96         /* This can be called from gpu state code so make sure GMU is valid */
  97         if (!gmu->initialized)
  98                 return false;
  99
 100         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
 101
 102         return !(val &
 103                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
 104                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
 105 }
 106
 107 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
 108                        bool suspended)
 109 {
 110         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 111         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 112         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 113         u32 perf_index;
 114         unsigned long gpu_freq;
 115         int ret = 0;
 116
 117         gpu_freq = dev_pm_opp_get_freq(opp);
 118
 119         if (gpu_freq == gmu->freq)
 120                 return;
 121
 122         for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
 123                 if (gpu_freq == gmu->gpu_freqs[perf_index])
 124                         break;
 125
 126         gmu->current_perf_index = perf_index;
 127         gmu->freq = gmu->gpu_freqs[perf_index];
 128
 129         trace_msm_gmu_freq_change(gmu->freq, perf_index);
 130
 131         /*
 132          * This can get called from devfreq while the hardware is idle. Don't
 133          * bring up the power if it isn't already active. All we're doing here
 134          * is updating the frequency so that when we come back online we're at
 135          * the right rate.
 136          */
 137         if (suspended)
 138                 return;
 139
 140         if (!gmu->legacy) {
 141                 a6xx_hfi_set_freq(gmu, perf_index);
 142                 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
 143                 return;
 144         }
 145
 146         gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
 147
 148         gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
 149                         ((3 & 0xf) << 28) | perf_index);
 150
 151         /*
 152          * Send an invalid index as a vote for the bus bandwidth and let the
 153          * firmware decide on the right vote
 154          */
 155         gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
 156
 157         /* Set and clear the OOB for DCVS to trigger the GMU */
 158         a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
 159         a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
 160
 161         ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
 162         if (ret)
 163                 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
 164
 165         dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
 166 }
 167
 168 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
 169 {
 170         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 171         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 172         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 173
 174         return  gmu->freq;
 175 }
 176
 177 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
 178 {
 179         u32 val;
 180         int local = gmu->idle_level;
 181
 182         /* SPTP and IFPC both report as IFPC */
 183         if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
 184                 local = GMU_IDLE_STATE_IFPC;
 185
 186         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
 187
 188         if (val == local) {
 189                 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
 190                         !a6xx_gmu_gx_is_on(gmu))
 191                         return true;
 192         }
 193
 194         return false;
 195 }
 196
 197 /* Wait for the GMU to get to its most idle state */
 198 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
 199 {
 200         return spin_until(a6xx_gmu_check_idle_level(gmu));
 201 }
 202
 203 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
 204 {
 205         int ret;
 206         u32 val;
 207         u32 mask, reset_val;
 208
 209         val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
 210         if (val <= 0x20010004) {
 211                 mask = 0xffffffff;
 212                 reset_val = 0xbabeface;
 213         } else {
 214                 mask = 0x1ff;
 215                 reset_val = 0x100;
 216         }
 217
 218         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
 219
 220         /* Set the log wptr index
 221          * note: downstream saves the value in poweroff and restores it here
 222          */
 223         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
 224
 225         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
 226
 227         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
 228                 (val & mask) == reset_val, 100, 10000);
 229
 230         if (ret)
 231                 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
 232
 233         return ret;
 234 }
 235
 236 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
 237 {
 238         u32 val;
 239         int ret;
 240
 241         gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
 242
 243         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
 244                 val & 1, 100, 10000);
 245         if (ret)
 246                 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
 247
 248         return ret;
 249 }
 250
 251 struct a6xx_gmu_oob_bits {
 252         int set, ack, set_new, ack_new, clear, clear_new;
 253         const char *name;
 254 };
 255
 256 /* These are the interrupt / ack bits for each OOB request that are set
 257  * in a6xx_gmu_set_oob and a6xx_clear_oob
 258  */
 259 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
 260         [GMU_OOB_GPU_SET] = {
 261                 .name = "GPU_SET",
 262                 .set = 16,
 263                 .ack = 24,
 264                 .set_new = 30,
 265                 .ack_new = 31,
 266                 .clear = 24,
 267                 .clear_new = 31,
 268         },
 269
 270         [GMU_OOB_PERFCOUNTER_SET] = {
 271                 .name = "PERFCOUNTER",
 272                 .set = 17,
 273                 .ack = 25,
 274                 .set_new = 28,
 275                 .ack_new = 30,
 276                 .clear = 25,
 277                 .clear_new = 29,
 278         },
 279
 280         [GMU_OOB_BOOT_SLUMBER] = {
 281                 .name = "BOOT_SLUMBER",
 282                 .set = 22,
 283                 .ack = 30,
 284                 .clear = 30,
 285         },
 286
 287         [GMU_OOB_DCVS_SET] = {
 288                 .name = "GPU_DCVS",
 289                 .set = 23,
 290                 .ack = 31,
 291                 .clear = 31,
 292         },
 293 };
 294
 295 /* Trigger a OOB (out of band) request to the GMU */
 296 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
 297 {
 298         int ret;
 299         u32 val;
 300         int request, ack;
 301
 302         WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
 303
 304         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
 305                 return -EINVAL;
 306
 307         if (gmu->legacy) {
 308                 request = a6xx_gmu_oob_bits[state].set;
 309                 ack = a6xx_gmu_oob_bits[state].ack;
 310         } else {
 311                 request = a6xx_gmu_oob_bits[state].set_new;
 312                 ack = a6xx_gmu_oob_bits[state].ack_new;
 313                 if (!request || !ack) {
 314                         DRM_DEV_ERROR(gmu->dev,
 315                                       "Invalid non-legacy GMU request %s\n",
 316                                       a6xx_gmu_oob_bits[state].name);
 317                         return -EINVAL;
 318                 }
 319         }
 320
 321         /* Trigger the equested OOB operation */
 322         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
 323
 324         /* Wait for the acknowledge interrupt */
 325         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
 326                 val & (1 << ack), 100, 10000);
 327
 328         if (ret)
 329                 DRM_DEV_ERROR(gmu->dev,
 330                         "Timeout waiting for GMU OOB set %s: 0x%x\n",
 331                                 a6xx_gmu_oob_bits[state].name,
 332                                 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
 333
 334         /* Clear the acknowledge interrupt */
 335         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
 336
 337         return ret;
 338 }
 339
 340 /* Clear a pending OOB state in the GMU */
 341 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
 342 {
 343         int bit;
 344
 345         WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
 346
 347         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
 348                 return;
 349
 350         if (gmu->legacy)
 351                 bit = a6xx_gmu_oob_bits[state].clear;
 352         else
 353                 bit = a6xx_gmu_oob_bits[state].clear_new;
 354
 355         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
 356 }
 357
 358 /* Enable CPU control of SPTP power power collapse */
 359 int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
 360 {
 361         int ret;
 362         u32 val;
 363
 364         if (!gmu->legacy)
 365                 return 0;
 366
 367         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
 368
 369         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
 370                 (val & 0x38) == 0x28, 1, 100);
 371
 372         if (ret) {
 373                 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
 374                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
 375         }
 376
 377         return 0;
 378 }
 379
 380 /* Disable CPU control of SPTP power power collapse */
 381 void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
 382 {
 383         u32 val;
 384         int ret;
 385
 386         if (!gmu->legacy)
 387                 return;
 388
 389         /* Make sure retention is on */
 390         gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
 391
 392         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
 393
 394         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
 395                 (val & 0x04), 100, 10000);
 396
 397         if (ret)
 398                 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
 399                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
 400 }
 401
 402 /* Let the GMU know we are starting a boot sequence */
 403 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
 404 {
 405         u32 vote;
 406
 407         /* Let the GMU know we are getting ready for boot */
 408         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
 409
 410         /* Choose the "default" power level as the highest available */
 411         vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
 412
 413         gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
 414         gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
 415
 416         /* Let the GMU know the boot sequence has started */
 417         return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 418 }
 419
 420 /* Let the GMU know that we are about to go into slumber */
 421 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
 422 {
 423         int ret;
 424
 425         /* Disable the power counter so the GMU isn't busy */
 426         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
 427
 428         /* Disable SPTP_PC if the CPU is responsible for it */
 429         if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
 430                 a6xx_sptprac_disable(gmu);
 431
 432         if (!gmu->legacy) {
 433                 ret = a6xx_hfi_send_prep_slumber(gmu);
 434                 goto out;
 435         }
 436
 437         /* Tell the GMU to get ready to slumber */
 438         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
 439
 440         ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 441         a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 442
 443         if (!ret) {
 444                 /* Check to see if the GMU really did slumber */
 445                 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
 446                         != 0x0f) {
 447                         DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
 448                         ret = -ETIMEDOUT;
 449                 }
 450         }
 451
 452 out:
 453         /* Put fence into allow mode */
 454         gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
 455         return ret;
 456 }
 457
 458 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
 459 {
 460         int ret;
 461         u32 val;
 462
 463         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
 464         /* Wait for the register to finish posting */
 465         wmb();
 466
 467         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
 468                 val & (1 << 1), 100, 10000);
 469         if (ret) {
 470                 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
 471                 return ret;
 472         }
 473
 474         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
 475                 !val, 100, 10000);
 476
 477         if (ret) {
 478                 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
 479                 return ret;
 480         }
 481
 482         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 483
 484         return 0;
 485 }
 486
 487 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
 488 {
 489         int ret;
 490         u32 val;
 491
 492         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
 493
 494         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
 495                 val, val & (1 << 16), 100, 10000);
 496         if (ret)
 497                 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
 498
 499         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
 500 }
 501
 502 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
 503 {
 504         msm_writel(value, ptr + (offset << 2));
 505 }
 506
 507 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
 508                 const char *name);
 509
 510 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
 511 {
 512         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 513         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 514         struct platform_device *pdev = to_platform_device(gmu->dev);
 515         void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
 516         void __iomem *seqptr = NULL;
 517         uint32_t pdc_address_offset;
 518         bool pdc_in_aop = false;
 519
 520         if (IS_ERR(pdcptr))
 521                 goto err;
 522
 523         if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
 524                 pdc_in_aop = true;
 525         else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
 526                 pdc_address_offset = 0x30090;
 527         else if (adreno_is_a619(adreno_gpu))
 528                 pdc_address_offset = 0x300a0;
 529         else
 530                 pdc_address_offset = 0x30080;
 531
 532         if (!pdc_in_aop) {
 533                 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
 534                 if (IS_ERR(seqptr))
 535                         goto err;
 536         }
 537
 538         /* Disable SDE clock gating */
 539         gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
 540
 541         /* Setup RSC PDC handshake for sleep and wakeup */
 542         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
 543         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
 544         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
 545         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
 546         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
 547         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
 548         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
 549         gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
 550         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
 551         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
 552         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
 553
 554         /* Load RSC sequencer uCode for sleep and wakeup */
 555         if (adreno_is_a650_family(adreno_gpu)) {
 556                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
 557                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
 558                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
 559                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
 560                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
 561         } else {
 562                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
 563                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
 564                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
 565                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
 566                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
 567         }
 568
 569         if (pdc_in_aop)
 570                 goto setup_pdc;
 571
 572         /* Load PDC sequencer uCode for power up and power down sequence */
 573         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
 574         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
 575         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
 576         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
 577         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
 578
 579         /* Set TCS commands used by PDC sequence for low power modes */
 580         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
 581         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
 582         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
 583         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
 584         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
 585         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
 586         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
 587         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
 588         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
 589
 590         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
 591         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
 592         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
 593
 594         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
 595         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
 596         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
 597         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
 598         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
 599         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
 600
 601         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
 602         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
 603         if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) ||
 604                         adreno_is_a650_family(adreno_gpu))
 605                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
 606         else
 607                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
 608         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
 609         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
 610         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
 611
 612         /* Setup GPU PDC */
 613 setup_pdc:
 614         pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
 615         pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
 616
 617         /* ensure no writes happen before the uCode is fully written */
 618         wmb();
 619
 620         a6xx_rpmh_stop(gmu);
 621
 622 err:
 623         if (!IS_ERR_OR_NULL(pdcptr))
 624                 iounmap(pdcptr);
 625         if (!IS_ERR_OR_NULL(seqptr))
 626                 iounmap(seqptr);
 627 }
 628
 629 /*
 630  * The lowest 16 bits of this value are the number of XO clock cycles for main
 631  * hysteresis which is set at 0x1680 cycles (300 us).  The higher 16 bits are
 632  * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
 633  */
 634
 635 #define GMU_PWR_COL_HYST 0x000a1680
 636
 637 /* Set up the idle state for the GMU */
 638 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
 639 {
 640         /* Disable GMU WB/RB buffer */
 641         gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
 642         gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
 643         gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
 644
 645         gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
 646
 647         switch (gmu->idle_level) {
 648         case GMU_IDLE_STATE_IFPC:
 649                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
 650                         GMU_PWR_COL_HYST);
 651                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
 652                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
 653                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
 654                 fallthrough;
 655         case GMU_IDLE_STATE_SPTP:
 656                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
 657                         GMU_PWR_COL_HYST);
 658                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
 659                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
 660                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
 661         }
 662
 663         /* Enable RPMh GPU client */
 664         gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
 665                 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
 666                 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
 667                 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
 668                 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
 669                 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
 670                 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
 671 }
 672
 673 struct block_header {
 674         u32 addr;
 675         u32 size;
 676         u32 type;
 677         u32 value;
 678         u32 data[];
 679 };
 680
 681 /* this should be a general kernel helper */
 682 static int in_range(u32 addr, u32 start, u32 size)
 683 {
 684         return addr >= start && addr < start + size;
 685 }
 686
 687 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
 688 {
 689         if (!in_range(blk->addr, bo->iova, bo->size))
 690                 return false;
 691
 692         memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
 693         return true;
 694 }
 695
 696 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
 697 {
 698         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 699         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 700         const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
 701         const struct block_header *blk;
 702         u32 reg_offset;
 703
 704         u32 itcm_base = 0x00000000;
 705         u32 dtcm_base = 0x00040000;
 706
 707         if (adreno_is_a650_family(adreno_gpu))
 708                 dtcm_base = 0x10004000;
 709
 710         if (gmu->legacy) {
 711                 /* Sanity check the size of the firmware that was loaded */
 712                 if (fw_image->size > 0x8000) {
 713                         DRM_DEV_ERROR(gmu->dev,
 714                                 "GMU firmware is bigger than the available region\n");
 715                         return -EINVAL;
 716                 }
 717
 718                 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
 719                                (u32*) fw_image->data, fw_image->size);
 720                 return 0;
 721         }
 722
 723
 724         for (blk = (const struct block_header *) fw_image->data;
 725              (const u8*) blk < fw_image->data + fw_image->size;
 726              blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
 727                 if (blk->size == 0)
 728                         continue;
 729
 730                 if (in_range(blk->addr, itcm_base, SZ_16K)) {
 731                         reg_offset = (blk->addr - itcm_base) >> 2;
 732                         gmu_write_bulk(gmu,
 733                                 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
 734                                 blk->data, blk->size);
 735                 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
 736                         reg_offset = (blk->addr - dtcm_base) >> 2;
 737                         gmu_write_bulk(gmu,
 738                                 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
 739                                 blk->data, blk->size);
 740                 } else if (!fw_block_mem(&gmu->icache, blk) &&
 741                            !fw_block_mem(&gmu->dcache, blk) &&
 742                            !fw_block_mem(&gmu->dummy, blk)) {
 743                         DRM_DEV_ERROR(gmu->dev,
 744                                 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
 745                                 blk->addr, blk->size, blk->data[0]);
 746                 }
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
 753 {
 754         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 755         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 756         int ret;
 757         u32 chipid;
 758
 759         if (adreno_is_a650_family(adreno_gpu)) {
 760                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
 761                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
 762         }
 763
 764         if (state == GMU_WARM_BOOT) {
 765                 ret = a6xx_rpmh_start(gmu);
 766                 if (ret)
 767                         return ret;
 768         } else {
 769                 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
 770                         "GMU firmware is not loaded\n"))
 771                         return -ENOENT;
 772
 773                 /* Turn on register retention */
 774                 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
 775
 776                 ret = a6xx_rpmh_start(gmu);
 777                 if (ret)
 778                         return ret;
 779
 780                 ret = a6xx_gmu_fw_load(gmu);
 781                 if (ret)
 782                         return ret;
 783         }
 784
 785         gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
 786         gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
 787
 788         /* Write the iova of the HFI table */
 789         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
 790         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
 791
 792         gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
 793                 (1 << 31) | (0xa << 18) | (0xa0));
 794
 795         /*
 796          * Snapshots toggle the NMI bit which will result in a jump to the NMI
 797          * handler instead of __main. Set the M3 config value to avoid that.
 798          */
 799         gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
 800
 801         /*
 802          * Note that the GMU has a slightly different layout for
 803          * chip_id, for whatever reason, so a bit of massaging
 804          * is needed.  The upper 16b are the same, but minor and
 805          * patchid are packed in four bits each with the lower
 806          * 8b unused:
 807          */
 808         chipid  = adreno_gpu->chip_id & 0xffff0000;
 809         chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
 810         chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
 811
 812         gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
 813
 814         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
 815                   gmu->log.iova | (gmu->log.size / SZ_4K - 1));
 816
 817         /* Set up the lowest idle level on the GMU */
 818         a6xx_gmu_power_config(gmu);
 819
 820         ret = a6xx_gmu_start(gmu);
 821         if (ret)
 822                 return ret;
 823
 824         if (gmu->legacy) {
 825                 ret = a6xx_gmu_gfx_rail_on(gmu);
 826                 if (ret)
 827                         return ret;
 828         }
 829
 830         /* Enable SPTP_PC if the CPU is responsible for it */
 831         if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
 832                 ret = a6xx_sptprac_enable(gmu);
 833                 if (ret)
 834                         return ret;
 835         }
 836
 837         ret = a6xx_gmu_hfi_start(gmu);
 838         if (ret)
 839                 return ret;
 840
 841         /* FIXME: Do we need this wmb() here? */
 842         wmb();
 843
 844         return 0;
 845 }
 846
 847 #define A6XX_HFI_IRQ_MASK \
 848         (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
 849
 850 #define A6XX_GMU_IRQ_MASK \
 851         (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
 852          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
 853          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
 854
 855 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
 856 {
 857         disable_irq(gmu->gmu_irq);
 858         disable_irq(gmu->hfi_irq);
 859
 860         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
 861         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
 862 }
 863
 864 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
 865 {
 866         u32 val;
 867
 868         /* Make sure there are no outstanding RPMh votes */
 869         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
 870                 (val & 1), 100, 10000);
 871         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
 872                 (val & 1), 100, 10000);
 873         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
 874                 (val & 1), 100, 10000);
 875         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
 876                 (val & 1), 100, 1000);
 877 }
 878
 879 /* Force the GMU off in case it isn't responsive */
 880 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
 881 {
 882         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
 883         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 884         struct msm_gpu *gpu = &adreno_gpu->base;
 885
 886         /*
 887          * Turn off keep alive that might have been enabled by the hang
 888          * interrupt
 889          */
 890         gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
 891
 892         /* Flush all the queues */
 893         a6xx_hfi_stop(gmu);
 894
 895         /* Stop the interrupts */
 896         a6xx_gmu_irq_disable(gmu);
 897
 898         /* Force off SPTP in case the GMU is managing it */
 899         a6xx_sptprac_disable(gmu);
 900
 901         /* Make sure there are no outstanding RPMh votes */
 902         a6xx_gmu_rpmh_off(gmu);
 903
 904         /* Clear the WRITEDROPPED fields and put fence into allow mode */
 905         gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
 906         gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
 907
 908         /* Make sure the above writes go through */
 909         wmb();
 910
 911         /* Halt the gmu cm3 core */
 912         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
 913
 914         a6xx_bus_clear_pending_transactions(adreno_gpu, true);
 915
 916         /* Reset GPU core blocks */
 917         a6xx_gpu_sw_reset(gpu, true);
 918 }
 919
 920 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 921 {
 922         struct dev_pm_opp *gpu_opp;
 923         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
 924
 925         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
 926         if (IS_ERR(gpu_opp))
 927                 return;
 928
 929         gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
 930         a6xx_gmu_set_freq(gpu, gpu_opp, false);
 931         dev_pm_opp_put(gpu_opp);
 932 }
 933
 934 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
 935 {
 936         struct dev_pm_opp *gpu_opp;
 937         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
 938
 939         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
 940         if (IS_ERR(gpu_opp))
 941                 return;
 942
 943         dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
 944         dev_pm_opp_put(gpu_opp);
 945 }
 946
 947 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 948 {
 949         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
 950         struct msm_gpu *gpu = &adreno_gpu->base;
 951         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 952         int status, ret;
 953
 954         if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
 955                 return -EINVAL;
 956
 957         gmu->hung = false;
 958
 959         /* Turn on the resources */
 960         pm_runtime_get_sync(gmu->dev);
 961
 962         /*
 963          * "enable" the GX power domain which won't actually do anything but it
 964          * will make sure that the refcounting is correct in case we need to
 965          * bring down the GX after a GMU failure
 966          */
 967         if (!IS_ERR_OR_NULL(gmu->gxpd))
 968                 pm_runtime_get_sync(gmu->gxpd);
 969
 970         /* Use a known rate to bring up the GMU */
 971         clk_set_rate(gmu->core_clk, 200000000);
 972         clk_set_rate(gmu->hub_clk, 150000000);
 973         ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
 974         if (ret) {
 975                 pm_runtime_put(gmu->gxpd);
 976                 pm_runtime_put(gmu->dev);
 977                 return ret;
 978         }
 979
 980         /* Set the bus quota to a reasonable value for boot */
 981         a6xx_gmu_set_initial_bw(gpu, gmu);
 982
 983         /* Enable the GMU interrupt */
 984         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
 985         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
 986         enable_irq(gmu->gmu_irq);
 987
 988         /* Check to see if we are doing a cold or warm boot */
 989         status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
 990                 GMU_WARM_BOOT : GMU_COLD_BOOT;
 991
 992         /*
 993          * Warm boot path does not work on newer GPUs
 994          * Presumably this is because icache/dcache regions must be restored
 995          */
 996         if (!gmu->legacy)
 997                 status = GMU_COLD_BOOT;
 998
 999         ret = a6xx_gmu_fw_start(gmu, status);
1000         if (ret)
1001                 goto out;
1002
1003         ret = a6xx_hfi_start(gmu, status);
1004         if (ret)
1005                 goto out;
1006
1007         /*
1008          * Turn on the GMU firmware fault interrupt after we know the boot
1009          * sequence is successful
1010          */
1011         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
1012         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
1013         enable_irq(gmu->hfi_irq);
1014
1015         /* Set the GPU to the current freq */
1016         a6xx_gmu_set_initial_freq(gpu, gmu);
1017
1018 out:
1019         /* On failure, shut down the GMU to leave it in a good state */
1020         if (ret) {
1021                 disable_irq(gmu->gmu_irq);
1022                 a6xx_rpmh_stop(gmu);
1023                 pm_runtime_put(gmu->gxpd);
1024                 pm_runtime_put(gmu->dev);
1025         }
1026
1027         return ret;
1028 }
1029
1030 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
1031 {
1032         u32 reg;
1033
1034         if (!gmu->initialized)
1035                 return true;
1036
1037         reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1038
1039         if (reg &  A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1040                 return false;
1041
1042         return true;
1043 }
1044
1045 /* Gracefully try to shut down the GMU and by extension the GPU */
1046 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1047 {
1048         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1049         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1050         u32 val;
1051
1052         /*
1053          * The GMU may still be in slumber unless the GPU started so check and
1054          * skip putting it back into slumber if so
1055          */
1056         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1057
1058         if (val != 0xf) {
1059                 int ret = a6xx_gmu_wait_for_idle(gmu);
1060
1061                 /* If the GMU isn't responding assume it is hung */
1062                 if (ret) {
1063                         a6xx_gmu_force_off(gmu);
1064                         return;
1065                 }
1066
1067                 a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
1068
1069                 /* tell the GMU we want to slumber */
1070                 ret = a6xx_gmu_notify_slumber(gmu);
1071                 if (ret) {
1072                         a6xx_gmu_force_off(gmu);
1073                         return;
1074                 }
1075
1076                 ret = gmu_poll_timeout(gmu,
1077                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1078                         !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1079                         100, 10000);
1080
1081                 /*
1082                  * Let the user know we failed to slumber but don't worry too
1083                  * much because we are powering down anyway
1084                  */
1085
1086                 if (ret)
1087                         DRM_DEV_ERROR(gmu->dev,
1088                                 "Unable to slumber GMU: status = 0%x/0%x\n",
1089                                 gmu_read(gmu,
1090                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1091                                 gmu_read(gmu,
1092                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1093         }
1094
1095         /* Turn off HFI */
1096         a6xx_hfi_stop(gmu);
1097
1098         /* Stop the interrupts and mask the hardware */
1099         a6xx_gmu_irq_disable(gmu);
1100
1101         /* Tell RPMh to power off the GPU */
1102         a6xx_rpmh_stop(gmu);
1103 }
1104
1105
1106 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1107 {
1108         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1109         struct msm_gpu *gpu = &a6xx_gpu->base.base;
1110
1111         if (!pm_runtime_active(gmu->dev))
1112                 return 0;
1113
1114         /*
1115          * Force the GMU off if we detected a hang, otherwise try to shut it
1116          * down gracefully
1117          */
1118         if (gmu->hung)
1119                 a6xx_gmu_force_off(gmu);
1120         else
1121                 a6xx_gmu_shutdown(gmu);
1122
1123         /* Remove the bus vote */
1124         dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1125
1126         /*
1127          * Make sure the GX domain is off before turning off the GMU (CX)
1128          * domain. Usually the GMU does this but only if the shutdown sequence
1129          * was successful
1130          */
1131         if (!IS_ERR_OR_NULL(gmu->gxpd))
1132                 pm_runtime_put_sync(gmu->gxpd);
1133
1134         clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1135
1136         pm_runtime_put_sync(gmu->dev);
1137
1138         return 0;
1139 }
1140
1141 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1142 {
1143         msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1144         msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1145         msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1146         msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1147         msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1148         msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1149
1150         gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1151         msm_gem_address_space_put(gmu->aspace);
1152 }
1153
1154 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1155                 size_t size, u64 iova, const char *name)
1156 {
1157         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1158         struct drm_device *dev = a6xx_gpu->base.base.dev;
1159         uint32_t flags = MSM_BO_WC;
1160         u64 range_start, range_end;
1161         int ret;
1162
1163         size = PAGE_ALIGN(size);
1164         if (!iova) {
1165                 /* no fixed address - use GMU's uncached range */
1166                 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1167                 range_end = 0x80000000;
1168         } else {
1169                 /* range for fixed address */
1170                 range_start = iova;
1171                 range_end = iova + size;
1172                 /* use IOMMU_PRIV for icache/dcache */
1173                 flags |= MSM_BO_MAP_PRIV;
1174         }
1175
1176         bo->obj = msm_gem_new(dev, size, flags);
1177         if (IS_ERR(bo->obj))
1178                 return PTR_ERR(bo->obj);
1179
1180         ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1181                                              range_start, range_end);
1182         if (ret) {
1183                 drm_gem_object_put(bo->obj);
1184                 return ret;
1185         }
1186
1187         bo->virt = msm_gem_get_vaddr(bo->obj);
1188         bo->size = size;
1189
1190         msm_gem_object_set_name(bo->obj, name);
1191
1192         return 0;
1193 }
1194
1195 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1196 {
1197         struct msm_mmu *mmu;
1198
1199         mmu = msm_iommu_new(gmu->dev, 0);
1200         if (!mmu)
1201                 return -ENODEV;
1202         if (IS_ERR(mmu))
1203                 return PTR_ERR(mmu);
1204
1205         gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1206         if (IS_ERR(gmu->aspace))
1207                 return PTR_ERR(gmu->aspace);
1208
1209         return 0;
1210 }
1211
1212 /* Return the 'arc-level' for the given frequency */
1213 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1214                                            unsigned long freq)
1215 {
1216         struct dev_pm_opp *opp;
1217         unsigned int val;
1218
1219         if (!freq)
1220                 return 0;
1221
1222         opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1223         if (IS_ERR(opp))
1224                 return 0;
1225
1226         val = dev_pm_opp_get_level(opp);
1227
1228         dev_pm_opp_put(opp);
1229
1230         return val;
1231 }
1232
1233 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1234                 unsigned long *freqs, int freqs_count, const char *id)
1235 {
1236         int i, j;
1237         const u16 *pri, *sec;
1238         size_t pri_count, sec_count;
1239
1240         pri = cmd_db_read_aux_data(id, &pri_count);
1241         if (IS_ERR(pri))
1242                 return PTR_ERR(pri);
1243         /*
1244          * The data comes back as an array of unsigned shorts so adjust the
1245          * count accordingly
1246          */
1247         pri_count >>= 1;
1248         if (!pri_count)
1249                 return -EINVAL;
1250
1251         sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1252         if (IS_ERR(sec))
1253                 return PTR_ERR(sec);
1254
1255         sec_count >>= 1;
1256         if (!sec_count)
1257                 return -EINVAL;
1258
1259         /* Construct a vote for each frequency */
1260         for (i = 0; i < freqs_count; i++) {
1261                 u8 pindex = 0, sindex = 0;
1262                 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1263
1264                 /* Get the primary index that matches the arc level */
1265                 for (j = 0; j < pri_count; j++) {
1266                         if (pri[j] >= level) {
1267                                 pindex = j;
1268                                 break;
1269                         }
1270                 }
1271
1272                 if (j == pri_count) {
1273                         DRM_DEV_ERROR(dev,
1274                                       "Level %u not found in the RPMh list\n",
1275                                       level);
1276                         DRM_DEV_ERROR(dev, "Available levels:\n");
1277                         for (j = 0; j < pri_count; j++)
1278                                 DRM_DEV_ERROR(dev, "  %u\n", pri[j]);
1279
1280                         return -EINVAL;
1281                 }
1282
1283                 /*
1284                  * Look for a level in in the secondary list that matches. If
1285                  * nothing fits, use the maximum non zero vote
1286                  */
1287
1288                 for (j = 0; j < sec_count; j++) {
1289                         if (sec[j] >= level) {
1290                                 sindex = j;
1291                                 break;
1292                         } else if (sec[j]) {
1293                                 sindex = j;
1294                         }
1295                 }
1296
1297                 /* Construct the vote */
1298                 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1299                         (sindex << 8) | pindex;
1300         }
1301
1302         return 0;
1303 }
1304
1305 /*
1306  * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1307  * to construct the list of votes on the CPU and send it over. Query the RPMh
1308  * voltage levels and build the votes
1309  */
1310
1311 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1312 {
1313         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1314         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1315         struct msm_gpu *gpu = &adreno_gpu->base;
1316         int ret;
1317
1318         /* Build the GX votes */
1319         ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1320                 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1321
1322         /* Build the CX votes */
1323         ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1324                 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1325
1326         return ret;
1327 }
1328
1329 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1330                 u32 size)
1331 {
1332         int count = dev_pm_opp_get_opp_count(dev);
1333         struct dev_pm_opp *opp;
1334         int i, index = 0;
1335         unsigned long freq = 1;
1336
1337         /*
1338          * The OPP table doesn't contain the "off" frequency level so we need to
1339          * add 1 to the table size to account for it
1340          */
1341
1342         if (WARN(count + 1 > size,
1343                 "The GMU frequency table is being truncated\n"))
1344                 count = size - 1;
1345
1346         /* Set the "off" frequency */
1347         freqs[index++] = 0;
1348
1349         for (i = 0; i < count; i++) {
1350                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1351                 if (IS_ERR(opp))
1352                         break;
1353
1354                 dev_pm_opp_put(opp);
1355                 freqs[index++] = freq++;
1356         }
1357
1358         return index;
1359 }
1360
1361 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1362 {
1363         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1364         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1365         struct msm_gpu *gpu = &adreno_gpu->base;
1366
1367         int ret = 0;
1368
1369         /*
1370          * The GMU handles its own frequency switching so build a list of
1371          * available frequencies to send during initialization
1372          */
1373         ret = devm_pm_opp_of_add_table(gmu->dev);
1374         if (ret) {
1375                 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1376                 return ret;
1377         }
1378
1379         gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1380                 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1381
1382         /*
1383          * The GMU also handles GPU frequency switching so build a list
1384          * from the GPU OPP table
1385          */
1386         gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1387                 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1388
1389         gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1390
1391         /* Build the list of RPMh votes that we'll send to the GMU */
1392         return a6xx_gmu_rpmh_votes_init(gmu);
1393 }
1394
1395 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1396 {
1397         int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1398
1399         if (ret < 1)
1400                 return ret;
1401
1402         gmu->nr_clocks = ret;
1403
1404         gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1405                 gmu->nr_clocks, "gmu");
1406
1407         gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
1408                 gmu->nr_clocks, "hub");
1409
1410         return 0;
1411 }
1412
1413 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1414                 const char *name)
1415 {
1416         void __iomem *ret;
1417         struct resource *res = platform_get_resource_byname(pdev,
1418                         IORESOURCE_MEM, name);
1419
1420         if (!res) {
1421                 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1422                 return ERR_PTR(-EINVAL);
1423         }
1424
1425         ret = ioremap(res->start, resource_size(res));
1426         if (!ret) {
1427                 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1428                 return ERR_PTR(-EINVAL);
1429         }
1430
1431         return ret;
1432 }
1433
1434 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1435                 const char *name, irq_handler_t handler)
1436 {
1437         int irq, ret;
1438
1439         irq = platform_get_irq_byname(pdev, name);
1440
1441         ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1442         if (ret) {
1443                 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1444                               name, ret);
1445                 return ret;
1446         }
1447
1448         disable_irq(irq);
1449
1450         return irq;
1451 }
1452
1453 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1454 {
1455         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1456         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1457         struct platform_device *pdev = to_platform_device(gmu->dev);
1458
1459         mutex_lock(&gmu->lock);
1460         if (!gmu->initialized) {
1461                 mutex_unlock(&gmu->lock);
1462                 return;
1463         }
1464
1465         gmu->initialized = false;
1466
1467         mutex_unlock(&gmu->lock);
1468
1469         pm_runtime_force_suspend(gmu->dev);
1470
1471         /*
1472          * Since cxpd is a virt device, the devlink with gmu-dev will be removed
1473          * automatically when we do detach
1474          */
1475         dev_pm_domain_detach(gmu->cxpd, false);
1476
1477         if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1478                 pm_runtime_disable(gmu->gxpd);
1479                 dev_pm_domain_detach(gmu->gxpd, false);
1480         }
1481
1482         iounmap(gmu->mmio);
1483         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1484                 iounmap(gmu->rscc);
1485         gmu->mmio = NULL;
1486         gmu->rscc = NULL;
1487
1488         if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1489                 a6xx_gmu_memory_free(gmu);
1490
1491                 free_irq(gmu->gmu_irq, gmu);
1492                 free_irq(gmu->hfi_irq, gmu);
1493         }
1494
1495         /* Drop reference taken in of_find_device_by_node */
1496         put_device(gmu->dev);
1497 }
1498
1499 static int cxpd_notifier_cb(struct notifier_block *nb,
1500                         unsigned long action, void *data)
1501 {
1502         struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb);
1503
1504         if (action == GENPD_NOTIFY_OFF)
1505                 complete_all(&gmu->pd_gate);
1506
1507         return 0;
1508 }
1509
1510 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1511 {
1512         struct platform_device *pdev = of_find_device_by_node(node);
1513         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1514         int ret;
1515
1516         if (!pdev)
1517                 return -ENODEV;
1518
1519         gmu->dev = &pdev->dev;
1520
1521         of_dma_configure(gmu->dev, node, true);
1522
1523         pm_runtime_enable(gmu->dev);
1524
1525         /* Mark legacy for manual SPTPRAC control */
1526         gmu->legacy = true;
1527
1528         /* Map the GMU registers */
1529         gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1530         if (IS_ERR(gmu->mmio)) {
1531                 ret = PTR_ERR(gmu->mmio);
1532                 goto err_mmio;
1533         }
1534
1535         gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1536         if (IS_ERR(gmu->cxpd)) {
1537                 ret = PTR_ERR(gmu->cxpd);
1538                 goto err_mmio;
1539         }
1540
1541         if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
1542                 ret = -ENODEV;
1543                 goto detach_cxpd;
1544         }
1545
1546         init_completion(&gmu->pd_gate);
1547         complete_all(&gmu->pd_gate);
1548         gmu->pd_nb.notifier_call = cxpd_notifier_cb;
1549
1550         /* Get a link to the GX power domain to reset the GPU */
1551         gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1552         if (IS_ERR(gmu->gxpd)) {
1553                 ret = PTR_ERR(gmu->gxpd);
1554                 goto err_mmio;
1555         }
1556
1557         gmu->initialized = true;
1558
1559         return 0;
1560
1561 detach_cxpd:
1562         dev_pm_domain_detach(gmu->cxpd, false);
1563
1564 err_mmio:
1565         iounmap(gmu->mmio);
1566
1567         /* Drop reference taken in of_find_device_by_node */
1568         put_device(gmu->dev);
1569
1570         return ret;
1571 }
1572
1573 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1574 {
1575         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1576         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1577         struct platform_device *pdev = of_find_device_by_node(node);
1578         int ret;
1579
1580         if (!pdev)
1581                 return -ENODEV;
1582
1583         gmu->dev = &pdev->dev;
1584
1585         of_dma_configure(gmu->dev, node, true);
1586
1587         /* Fow now, don't do anything fancy until we get our feet under us */
1588         gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1589
1590         pm_runtime_enable(gmu->dev);
1591
1592         /* Get the list of clocks */
1593         ret = a6xx_gmu_clocks_probe(gmu);
1594         if (ret)
1595                 goto err_put_device;
1596
1597         ret = a6xx_gmu_memory_probe(gmu);
1598         if (ret)
1599                 goto err_put_device;
1600
1601
1602         /* A660 now requires handling "prealloc requests" in GMU firmware
1603          * For now just hardcode allocations based on the known firmware.
1604          * note: there is no indication that these correspond to "dummy" or
1605          * "debug" regions, but this "guess" allows reusing these BOs which
1606          * are otherwise unused by a660.
1607          */
1608         gmu->dummy.size = SZ_4K;
1609         if (adreno_is_a660_family(adreno_gpu)) {
1610                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,
1611                                             0x60400000, "debug");
1612                 if (ret)
1613                         goto err_memory;
1614
1615                 gmu->dummy.size = SZ_8K;
1616         }
1617
1618         /* Allocate memory for the GMU dummy page */
1619         ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size,
1620                                     0x60000000, "dummy");
1621         if (ret)
1622                 goto err_memory;
1623
1624         /* Note that a650 family also includes a660 family: */
1625         if (adreno_is_a650_family(adreno_gpu)) {
1626                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1627                         SZ_16M - SZ_16K, 0x04000, "icache");
1628                 if (ret)
1629                         goto err_memory;
1630         /*
1631          * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition
1632          * to allocate icache/dcache here, as per downstream code flow, but it may not actually be
1633          * necessary. If you omit this step and you don't get random pagefaults, you are likely
1634          * good to go without this!
1635          */
1636         } else if (adreno_is_a640_family(adreno_gpu)) {
1637                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1638                         SZ_256K - SZ_16K, 0x04000, "icache");
1639                 if (ret)
1640                         goto err_memory;
1641
1642                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1643                         SZ_256K - SZ_16K, 0x44000, "dcache");
1644                 if (ret)
1645                         goto err_memory;
1646         } else if (adreno_is_a630_family(adreno_gpu)) {
1647                 /* HFI v1, has sptprac */
1648                 gmu->legacy = true;
1649
1650                 /* Allocate memory for the GMU debug region */
1651                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");
1652                 if (ret)
1653                         goto err_memory;
1654         }
1655
1656         /* Allocate memory for the GMU log region */
1657         ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log");
1658         if (ret)
1659                 goto err_memory;
1660
1661         /* Allocate memory for for the HFI queues */
1662         ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
1663         if (ret)
1664                 goto err_memory;
1665
1666         /* Map the GMU registers */
1667         gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1668         if (IS_ERR(gmu->mmio)) {
1669                 ret = PTR_ERR(gmu->mmio);
1670                 goto err_memory;
1671         }
1672
1673         if (adreno_is_a650_family(adreno_gpu)) {
1674                 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1675                 if (IS_ERR(gmu->rscc)) {
1676                         ret = -ENODEV;
1677                         goto err_mmio;
1678                 }
1679         } else {
1680                 gmu->rscc = gmu->mmio + 0x23000;
1681         }
1682
1683         /* Get the HFI and GMU interrupts */
1684         gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1685         gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1686
1687         if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {
1688                 ret = -ENODEV;
1689                 goto err_mmio;
1690         }
1691
1692         gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1693         if (IS_ERR(gmu->cxpd)) {
1694                 ret = PTR_ERR(gmu->cxpd);
1695                 goto err_mmio;
1696         }
1697
1698         if (!device_link_add(gmu->dev, gmu->cxpd,
1699                                         DL_FLAG_PM_RUNTIME)) {
1700                 ret = -ENODEV;
1701                 goto detach_cxpd;
1702         }
1703
1704         init_completion(&gmu->pd_gate);
1705         complete_all(&gmu->pd_gate);
1706         gmu->pd_nb.notifier_call = cxpd_notifier_cb;
1707
1708         /*
1709          * Get a link to the GX power domain to reset the GPU in case of GMU
1710          * crash
1711          */
1712         gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1713
1714         /* Get the power levels for the GMU and GPU */
1715         a6xx_gmu_pwrlevels_probe(gmu);
1716
1717         /* Set up the HFI queues */
1718         a6xx_hfi_init(gmu);
1719
1720         /* Initialize RPMh */
1721         a6xx_gmu_rpmh_init(gmu);
1722
1723         gmu->initialized = true;
1724
1725         return 0;
1726
1727 detach_cxpd:
1728         dev_pm_domain_detach(gmu->cxpd, false);
1729
1730 err_mmio:
1731         iounmap(gmu->mmio);
1732         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1733                 iounmap(gmu->rscc);
1734         free_irq(gmu->gmu_irq, gmu);
1735         free_irq(gmu->hfi_irq, gmu);
1736
1737 err_memory:
1738         a6xx_gmu_memory_free(gmu);
1739 err_put_device:
1740         /* Drop reference taken in of_find_device_by_node */
1741         put_device(gmu->dev);
1742
1743         return ret;
1744 }