1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/cpufreq.h>
14 #include <linux/devfreq.h>
15 #include <linux/module.h>
16 #include <linux/component.h>
17 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/slab.h>
21 #include <linux/list.h>
22 #include <linux/iommu.h>
23 #include <linux/types.h>
24 #include <linux/of_graph.h>
25 #include <linux/of_device.h>
26 #include <linux/sizes.h>
27 #include <linux/kthread.h>
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_atomic_helper.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/display/drm_dsc.h>
33 #include <drm/msm_drm.h>
34 #include <drm/drm_gem.h>
36 #ifdef CONFIG_FAULT_INJECTION
37 extern struct fault_attr fail_gem_alloc;
38 extern struct fault_attr fail_gem_iova;
40 # define should_fail(attr, size) 0
48 struct msm_perf_state;
49 struct msm_gem_submit;
50 struct msm_fence_context;
51 struct msm_gem_address_space;
53 struct msm_disp_state;
58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
60 enum msm_dp_controller {
65 MSM_DP_CONTROLLER_COUNT,
68 #define MSM_GPU_MAX_RINGS 4
69 #define MAX_H_TILES_PER_DISPLAY 2
72 * enum msm_event_wait - type of HW events to wait for
73 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
74 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
75 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
78 MSM_ENC_COMMIT_DONE = 0,
84 * struct msm_display_topology - defines a display topology pipeline
85 * @num_lm: number of layer mixers used
86 * @num_intf: number of interfaces the panel is mounted on
87 * @num_dspp: number of dspp blocks used
88 * @num_dsc: number of Display Stream Compression (DSC) blocks used
90 struct msm_display_topology {
97 /* Commit/Event thread specific structure */
98 struct msm_drm_thread {
99 struct drm_device *dev;
100 unsigned int crtc_id;
101 struct kthread_worker *worker;
104 struct msm_drm_private {
106 struct drm_device *dev;
109 int (*kms_init)(struct drm_device *dev);
111 /* subordinate devices, if present: */
112 struct platform_device *gpu_pdev;
114 /* possibly this should be in the kms component, but it is
115 * shared by both mdp4 and mdp5..
119 /* DSI is shared by mdp4 and mdp5 */
120 struct msm_dsi *dsi[2];
122 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
124 /* when we have more than one 'msm_gpu' these need to be an array: */
127 /* gpu is only set on open(), but we need this info earlier */
129 bool has_cached_coherent;
131 struct msm_rd_state *rd; /* debugfs to dump all submits */
132 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
133 struct msm_perf_state *perf;
136 * List of all GEM objects (mainly for debugfs, protected by obj_lock
137 * (acquire before per GEM object lock)
139 struct list_head objects;
140 struct mutex obj_lock;
145 * The various LRU's that a GEM object is in at various stages of
146 * it's lifetime. Objects start out in the unbacked LRU. When
147 * pinned (for scannout or permanently mapped GPU buffers, like
148 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When
149 * unpinned, it moves into willneed or dontneed LRU depending on
150 * madvise state. When backing pages are evicted (willneed) or
151 * purged (dontneed) it moves back into the unbacked LRU.
153 * The dontneed LRU is considered by the shrinker for objects
154 * that are candidate for purging, and the willneed LRU is
155 * considered for objects that could be evicted.
161 * The LRU for GEM objects without backing pages allocated.
162 * This mostly exists so that objects are always is one
165 struct drm_gem_lru unbacked;
170 * The LRU for pinned GEM objects
172 struct drm_gem_lru pinned;
177 * The LRU for unpinned GEM objects which are in madvise
178 * WILLNEED state (ie. can be evicted)
180 struct drm_gem_lru willneed;
185 * The LRU for unpinned GEM objects which are in madvise
186 * DONTNEED state (ie. can be purged)
188 struct drm_gem_lru dontneed;
193 * Protects manipulation of all of the LRUs.
198 struct workqueue_struct *wq;
200 unsigned int num_crtcs;
201 struct drm_crtc *crtcs[MAX_CRTCS];
203 struct msm_drm_thread event_thread[MAX_CRTCS];
205 unsigned int num_bridges;
206 struct drm_bridge *bridges[MAX_BRIDGES];
208 /* VRAM carveout, used when no IOMMU: */
212 /* NOTE: mm managed at the page level, size is in # of pages
213 * and position mm_node->start is in # of pages:
216 spinlock_t lock; /* Protects drm_mm node allocation/removal */
219 struct notifier_block vmap_notifier;
220 struct shrinker shrinker;
222 struct drm_atomic_state *pm_state;
225 * hangcheck_period: For hang detection, in ms
227 * Note that in practice, a submit/job will get at least two hangcheck
228 * periods, due to checking for progress being implemented as simply
229 * "have the CP position registers changed since last time?"
231 unsigned int hangcheck_period;
233 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */
234 struct devfreq_simple_ondemand_data gpu_devfreq_config;
237 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive
239 bool gpu_clamp_to_idle;
244 * Disable handling of GPU hw error interrupts, to force fallback to
245 * sw hangcheck timer. Written (via debugfs) by igt tests to test
246 * the sw hangcheck mechanism.
248 bool disable_err_irq;
252 uint32_t pixel_format;
255 struct msm_pending_timer;
257 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
258 struct msm_kms *kms, int crtc_idx);
259 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
260 void msm_atomic_commit_tail(struct drm_atomic_state *state);
261 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
262 void msm_atomic_state_clear(struct drm_atomic_state *state);
263 void msm_atomic_state_free(struct drm_atomic_state *state);
265 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
266 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
268 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
269 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
271 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
272 bool msm_use_mmu(struct drm_device *dev);
274 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
275 struct drm_file *file);
277 #ifdef CONFIG_DEBUG_FS
278 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
281 void msm_gem_shrinker_init(struct drm_device *dev);
282 void msm_gem_shrinker_cleanup(struct drm_device *dev);
284 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
285 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
286 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
287 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
288 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
289 struct dma_buf_attachment *attach, struct sg_table *sg);
290 int msm_gem_prime_pin(struct drm_gem_object *obj);
291 void msm_gem_prime_unpin(struct drm_gem_object *obj);
293 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
294 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
295 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
296 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
297 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
298 struct msm_gem_address_space *aspace, int plane);
299 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
300 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
301 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
302 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
303 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
304 int w, int h, int p, uint32_t format);
306 #ifdef CONFIG_DRM_FBDEV_EMULATION
307 void msm_fbdev_setup(struct drm_device *dev);
309 static inline void msm_fbdev_setup(struct drm_device *dev)
315 #ifdef CONFIG_DRM_MSM_HDMI
316 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
317 struct drm_encoder *encoder);
318 void __init msm_hdmi_register(void);
319 void __exit msm_hdmi_unregister(void);
321 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
322 struct drm_encoder *encoder)
326 static inline void __init msm_hdmi_register(void) {}
327 static inline void __exit msm_hdmi_unregister(void) {}
331 #ifdef CONFIG_DRM_MSM_DSI
332 int dsi_dev_attach(struct platform_device *pdev);
333 void dsi_dev_detach(struct platform_device *pdev);
334 void __init msm_dsi_register(void);
335 void __exit msm_dsi_unregister(void);
336 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
337 struct drm_encoder *encoder);
338 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
339 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
340 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
341 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
342 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
344 static inline void __init msm_dsi_register(void)
347 static inline void __exit msm_dsi_unregister(void)
350 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
351 struct drm_device *dev,
352 struct drm_encoder *encoder)
356 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
359 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
363 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
367 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
372 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
378 #ifdef CONFIG_DRM_MSM_DP
379 int __init msm_dp_register(void);
380 void __exit msm_dp_unregister(void);
381 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
382 struct drm_encoder *encoder);
383 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
384 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
386 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
387 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
390 static inline int __init msm_dp_register(void)
394 static inline void __exit msm_dp_unregister(void)
397 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
398 struct drm_device *dev,
399 struct drm_encoder *encoder)
404 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
408 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
412 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
413 struct drm_minor *minor)
417 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
424 #ifdef CONFIG_DRM_MSM_MDP4
425 void msm_mdp4_register(void);
426 void msm_mdp4_unregister(void);
428 static inline void msm_mdp4_register(void) {}
429 static inline void msm_mdp4_unregister(void) {}
432 #ifdef CONFIG_DRM_MSM_MDP5
433 void msm_mdp_register(void);
434 void msm_mdp_unregister(void);
436 static inline void msm_mdp_register(void) {}
437 static inline void msm_mdp_unregister(void) {}
440 #ifdef CONFIG_DRM_MSM_DPU
441 void msm_dpu_register(void);
442 void msm_dpu_unregister(void);
444 static inline void msm_dpu_register(void) {}
445 static inline void msm_dpu_unregister(void) {}
448 #ifdef CONFIG_DRM_MSM_MDSS
449 void msm_mdss_register(void);
450 void msm_mdss_unregister(void);
452 static inline void msm_mdss_register(void) {}
453 static inline void msm_mdss_unregister(void) {}
456 #ifdef CONFIG_DEBUG_FS
457 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
458 int msm_debugfs_late_init(struct drm_device *dev);
459 int msm_rd_debugfs_init(struct drm_minor *minor);
460 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
462 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
463 const char *fmt, ...);
464 int msm_perf_debugfs_init(struct drm_minor *minor);
465 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
467 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
469 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
470 struct msm_gem_submit *submit,
471 const char *fmt, ...) {}
472 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
473 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
476 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
478 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
480 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
481 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
483 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
485 struct icc_path *msm_icc_get(struct device *dev, const char *name);
487 #define msm_writel(data, addr) writel((data), (addr))
488 #define msm_readl(addr) readl((addr))
490 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
492 u32 val = msm_readl(addr);
495 msm_writel(val | or, addr);
499 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
501 * @timer: hrtimer to control when the kthread work is triggered
502 * @work: the kthread work
503 * @worker: the kthread worker the work will be scheduled on
505 struct msm_hrtimer_work {
506 struct hrtimer timer;
507 struct kthread_work work;
508 struct kthread_worker *worker;
511 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
513 enum hrtimer_mode mode);
514 void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
515 struct kthread_worker *worker,
516 kthread_work_func_t fn,
518 enum hrtimer_mode mode);
520 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
521 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
523 static inline int align_pitch(int width, int bpp)
525 int bytespp = (bpp + 7) / 8;
526 /* adreno needs pitch aligned to 32 pixels: */
527 return bytespp * ALIGN(width, 32);
530 /* for the generated headers: */
531 #define INVALID_IDX(idx) ({BUG(); 0;})
532 #define fui(x) ({BUG(); 0;})
533 #define _mesa_float_to_half(x) ({BUG(); 0;})
536 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
538 /* for conditionally setting boolean flag(s): */
539 #define COND(bool, val) ((bool) ? (val) : 0)
541 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
543 ktime_t now = ktime_get();
544 s64 remaining_jiffies;
546 if (ktime_compare(*timeout, now) < 0) {
547 remaining_jiffies = 0;
549 ktime_t rem = ktime_sub(*timeout, now);
550 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
553 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX);
558 extern const struct component_master_ops msm_drm_ops;
560 int msm_pm_prepare(struct device *dev);
561 void msm_pm_complete(struct device *dev);
563 int msm_drv_probe(struct device *dev,
564 int (*kms_init)(struct drm_device *dev));
565 void msm_drv_shutdown(struct platform_device *pdev);
568 #endif /* __MSM_DRV_H__ */