drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

   1 /*
   2  * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  16 #include "sde_encoder_phys.h"
  17 #include "sde_hw_interrupts.h"
  18 #include "sde_core_irq.h"
  19 #include "sde_formats.h"
  20
  21 #define SDE_DEBUG_CMDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
  22                 (e) && (e)->base.parent ? \
  23                 (e)->base.parent->base.id : -1, \
  24                 (e) ? (e)->intf_idx - INTF_0 : -1, ##__VA_ARGS__)
  25
  26 #define SDE_ERROR_CMDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
  27                 (e) && (e)->base.parent ? \
  28                 (e)->base.parent->base.id : -1, \
  29                 (e) ? (e)->intf_idx - INTF_0 : -1, ##__VA_ARGS__)
  30
  31 #define to_sde_encoder_phys_cmd(x) \
  32         container_of(x, struct sde_encoder_phys_cmd, base)
  33
  34 /*
  35  * Tearcheck sync start and continue thresholds are empirically found
  36  * based on common panels In the future, may want to allow panels to override
  37  * these default values
  38  */
  39 #define DEFAULT_TEARCHECK_SYNC_THRESH_START     4
  40 #define DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE  4
  41
  42 static inline bool sde_encoder_phys_cmd_is_master(
  43                 struct sde_encoder_phys *phys_enc)
  44 {
  45         return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false;
  46 }
  47
  48 static bool sde_encoder_phys_cmd_mode_fixup(
  49                 struct sde_encoder_phys *phys_enc,
  50                 const struct drm_display_mode *mode,
  51                 struct drm_display_mode *adj_mode)
  52 {
  53         if (phys_enc)
  54                 SDE_DEBUG_CMDENC(to_sde_encoder_phys_cmd(phys_enc), "\n");
  55         return true;
  56 }
  57
  58 static void sde_encoder_phys_cmd_mode_set(
  59                 struct sde_encoder_phys *phys_enc,
  60                 struct drm_display_mode *mode,
  61                 struct drm_display_mode *adj_mode)
  62 {
  63         struct sde_encoder_phys_cmd *cmd_enc =
  64                 to_sde_encoder_phys_cmd(phys_enc);
  65         struct sde_rm *rm = &phys_enc->sde_kms->rm;
  66         struct sde_rm_hw_iter iter;
  67         int i, instance;
  68
  69         if (!phys_enc || !mode || !adj_mode) {
  70                 SDE_ERROR("invalid arg(s), enc %d mode %d adj_mode %d\n",
  71                                 phys_enc != 0, mode != 0, adj_mode != 0);
  72                 return;
  73         }
  74         phys_enc->cached_mode = *adj_mode;
  75         SDE_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
  76         drm_mode_debug_printmodeline(adj_mode);
  77
  78         instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
  79
  80         /* Retrieve previously allocated HW Resources. Shouldn't fail */
  81         sde_rm_init_hw_iter(&iter, phys_enc->parent->base.id, SDE_HW_BLK_CTL);
  82         for (i = 0; i <= instance; i++) {
  83                 if (sde_rm_get_hw(rm, &iter))
  84                         phys_enc->hw_ctl = (struct sde_hw_ctl *)iter.hw;
  85         }
  86
  87         if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
  88                 SDE_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
  89                                 PTR_ERR(phys_enc->hw_ctl));
  90                 phys_enc->hw_ctl = NULL;
  91                 return;
  92         }
  93 }
  94
  95 static void sde_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
  96 {
  97         struct sde_encoder_phys_cmd *cmd_enc = arg;
  98         struct sde_encoder_phys *phys_enc;
  99         unsigned long lock_flags;
 100         int new_cnt;
 101
 102         if (!cmd_enc)
 103                 return;
 104
 105         phys_enc = &cmd_enc->base;
 106
 107         /* notify all synchronous clients first, then asynchronous clients */
 108         if (phys_enc->parent_ops.handle_frame_done)
 109                 phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
 110                                 phys_enc, SDE_ENCODER_FRAME_EVENT_DONE);
 111
 112         spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
 113         new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
 114         spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 115
 116         SDE_EVT32_IRQ(DRMID(phys_enc->parent),
 117                         phys_enc->hw_pp->idx - PINGPONG_0, new_cnt);
 118
 119         /* Signal any waiting atomic commit thread */
 120         wake_up_all(&phys_enc->pending_kickoff_wq);
 121 }
 122
 123 static void sde_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx)
 124 {
 125         struct sde_encoder_phys_cmd *cmd_enc = arg;
 126         struct sde_encoder_phys *phys_enc = &cmd_enc->base;
 127
 128         if (!cmd_enc)
 129                 return;
 130
 131         if (phys_enc->parent_ops.handle_vblank_virt)
 132                 phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
 133                         phys_enc);
 134 }
 135
 136 static bool _sde_encoder_phys_is_ppsplit_slave(
 137                 struct sde_encoder_phys *phys_enc)
 138 {
 139         enum sde_rm_topology_name topology;
 140
 141         if (!phys_enc)
 142                 return false;
 143
 144         topology = sde_connector_get_topology_name(phys_enc->connector);
 145         if (topology == SDE_RM_TOPOLOGY_PPSPLIT &&
 146                         phys_enc->split_role == ENC_ROLE_SLAVE)
 147                 return true;
 148
 149         return false;
 150 }
 151
 152 static int _sde_encoder_phys_cmd_wait_for_idle(
 153                 struct sde_encoder_phys *phys_enc)
 154 {
 155         struct sde_encoder_phys_cmd *cmd_enc =
 156                         to_sde_encoder_phys_cmd(phys_enc);
 157         u32 irq_status;
 158         int ret;
 159
 160         if (!phys_enc) {
 161                 SDE_ERROR("invalid encoder\n");
 162                 return -EINVAL;
 163         }
 164
 165         /* slave encoder doesn't enable for ppsplit */
 166         if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
 167                 return 0;
 168
 169         /* return EWOULDBLOCK since we know the wait isn't necessary */
 170         if (phys_enc->enable_state == SDE_ENC_DISABLED) {
 171                 SDE_ERROR_CMDENC(cmd_enc, "encoder is disabled\n");
 172                 return -EWOULDBLOCK;
 173         }
 174
 175         /* wait for previous kickoff to complete */
 176         ret = sde_encoder_helper_wait_event_timeout(
 177                         DRMID(phys_enc->parent),
 178                         phys_enc->hw_pp->idx - PINGPONG_0,
 179                         &phys_enc->pending_kickoff_wq,
 180                         &phys_enc->pending_kickoff_cnt,
 181                         KICKOFF_TIMEOUT_MS);
 182         if (ret <= 0) {
 183                 irq_status = sde_core_irq_read(phys_enc->sde_kms,
 184                                 INTR_IDX_PINGPONG, true);
 185                 if (irq_status) {
 186                         SDE_EVT32(DRMID(phys_enc->parent),
 187                                         phys_enc->hw_pp->idx - PINGPONG_0);
 188                         SDE_DEBUG_CMDENC(cmd_enc,
 189                                         "pp:%d done but irq not triggered\n",
 190                                         phys_enc->hw_pp->idx - PINGPONG_0);
 191                         sde_encoder_phys_cmd_pp_tx_done_irq(cmd_enc,
 192                                         INTR_IDX_PINGPONG);
 193                         ret = 0;
 194                 } else {
 195                         SDE_EVT32(DRMID(phys_enc->parent),
 196                                         phys_enc->hw_pp->idx - PINGPONG_0);
 197                         SDE_ERROR_CMDENC(cmd_enc, "pp:%d kickoff timed out\n",
 198                                         phys_enc->hw_pp->idx - PINGPONG_0);
 199                         if (phys_enc->parent_ops.handle_frame_done)
 200                                 phys_enc->parent_ops.handle_frame_done(
 201                                                 phys_enc->parent, phys_enc,
 202                                                 SDE_ENCODER_FRAME_EVENT_ERROR);
 203                         ret = -ETIMEDOUT;
 204                 }
 205         } else {
 206                 ret = 0;
 207         }
 208
 209         return ret;
 210 }
 211
 212 static void sde_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
 213 {
 214         struct sde_encoder_phys_cmd *cmd_enc = arg;
 215         struct sde_encoder_phys *phys_enc;
 216
 217         if (!cmd_enc)
 218                 return;
 219
 220         phys_enc = &cmd_enc->base;
 221         if (phys_enc->parent_ops.handle_underrun_virt)
 222                 phys_enc->parent_ops.handle_underrun_virt(phys_enc->parent,
 223                         phys_enc);
 224 }
 225
 226 static int sde_encoder_phys_cmd_register_irq(struct sde_encoder_phys *phys_enc,
 227         enum sde_intr_type intr_type, int idx,
 228         void (*irq_func)(void *, int), const char *irq_name)
 229 {
 230         struct sde_encoder_phys_cmd *cmd_enc =
 231                         to_sde_encoder_phys_cmd(phys_enc);
 232         int ret = 0;
 233
 234         if (!phys_enc) {
 235                 SDE_ERROR("invalid encoder\n");
 236                 return -EINVAL;
 237         }
 238
 239         cmd_enc->irq_idx[idx] = sde_core_irq_idx_lookup(phys_enc->sde_kms,
 240                         intr_type, phys_enc->hw_pp->idx);
 241         if (cmd_enc->irq_idx[idx] < 0) {
 242                 SDE_ERROR_CMDENC(cmd_enc,
 243                         "failed to lookup IRQ index for %s with pp=%d\n",
 244                         irq_name,
 245                         phys_enc->hw_pp->idx - PINGPONG_0);
 246                 return -EINVAL;
 247         }
 248
 249         cmd_enc->irq_cb[idx].func = irq_func;
 250         cmd_enc->irq_cb[idx].arg = cmd_enc;
 251         ret = sde_core_irq_register_callback(phys_enc->sde_kms,
 252                         cmd_enc->irq_idx[idx], &cmd_enc->irq_cb[idx]);
 253         if (ret) {
 254                 SDE_ERROR_CMDENC(cmd_enc,
 255                                 "failed to register IRQ callback %s\n",
 256                                 irq_name);
 257                 return ret;
 258         }
 259
 260         ret = sde_core_irq_enable(phys_enc->sde_kms, &cmd_enc->irq_idx[idx], 1);
 261         if (ret) {
 262                 SDE_ERROR_CMDENC(cmd_enc,
 263                         "failed to enable IRQ for %s, pp %d, irq_idx %d\n",
 264                         irq_name,
 265                         phys_enc->hw_pp->idx - PINGPONG_0,
 266                         cmd_enc->irq_idx[idx]);
 267                 cmd_enc->irq_idx[idx] = -EINVAL;
 268
 269                 /* Unregister callback on IRQ enable failure */
 270                 sde_core_irq_unregister_callback(phys_enc->sde_kms,
 271                                 cmd_enc->irq_idx[idx], &cmd_enc->irq_cb[idx]);
 272                 return ret;
 273         }
 274
 275         SDE_DEBUG_CMDENC(cmd_enc, "registered IRQ %s for pp %d, irq_idx %d\n",
 276                         irq_name,
 277                         phys_enc->hw_pp->idx - PINGPONG_0,
 278                         cmd_enc->irq_idx[idx]);
 279
 280         return ret;
 281 }
 282
 283 static int sde_encoder_phys_cmd_unregister_irq(
 284                 struct sde_encoder_phys *phys_enc, int idx)
 285 {
 286         struct sde_encoder_phys_cmd *cmd_enc =
 287                         to_sde_encoder_phys_cmd(phys_enc);
 288
 289         if (!phys_enc) {
 290                 SDE_ERROR("invalid encoder\n");
 291                 return -EINVAL;
 292         }
 293
 294         sde_core_irq_disable(phys_enc->sde_kms, &cmd_enc->irq_idx[idx], 1);
 295         sde_core_irq_unregister_callback(phys_enc->sde_kms,
 296                         cmd_enc->irq_idx[idx], &cmd_enc->irq_cb[idx]);
 297
 298         SDE_DEBUG_CMDENC(cmd_enc, "unregistered IRQ for pp %d, irq_idx %d\n",
 299                         phys_enc->hw_pp->idx - PINGPONG_0,
 300                         cmd_enc->irq_idx[idx]);
 301
 302         return 0;
 303 }
 304
 305 static void sde_encoder_phys_cmd_tearcheck_config(
 306                 struct sde_encoder_phys *phys_enc)
 307 {
 308         struct sde_encoder_phys_cmd *cmd_enc =
 309                 to_sde_encoder_phys_cmd(phys_enc);
 310         struct sde_hw_tear_check tc_cfg = { 0 };
 311         struct drm_display_mode *mode = &phys_enc->cached_mode;
 312         bool tc_enable = true;
 313         u32 vsync_hz;
 314         struct msm_drm_private *priv;
 315         struct sde_kms *sde_kms;
 316
 317         if (!phys_enc) {
 318                 SDE_ERROR("invalid encoder\n");
 319                 return;
 320         }
 321
 322         SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 323
 324         if (!phys_enc->hw_pp->ops.setup_tearcheck ||
 325                 !phys_enc->hw_pp->ops.enable_tearcheck) {
 326                 SDE_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n");
 327                 return;
 328         }
 329
 330         sde_kms = phys_enc->sde_kms;
 331         priv = sde_kms->dev->dev_private;
 332         /*
 333          * TE default: dsi byte clock calculated base on 70 fps;
 334          * around 14 ms to complete a kickoff cycle if te disabled;
 335          * vclk_line base on 60 fps; write is faster than read;
 336          * init == start == rdptr;
 337          *
 338          * vsync_count is ratio of MDP VSYNC clock frequency to LCD panel
 339          * frequency divided by the no. of rows (lines) in the LCDpanel.
 340          */
 341         vsync_hz = sde_power_clk_get_rate(&priv->phandle, "vsync_clk");
 342         if (!vsync_hz) {
 343                 SDE_DEBUG_CMDENC(cmd_enc, "invalid vsync clock rate\n");
 344                 return;
 345         }
 346
 347         tc_cfg.vsync_count = vsync_hz / (mode->vtotal * mode->vrefresh);
 348         tc_cfg.hw_vsync_mode = 1;
 349
 350         /*
 351          * By setting sync_cfg_height to near max register value, we essentially
 352          * disable sde hw generated TE signal, since hw TE will arrive first.
 353          * Only caveat is if due to error, we hit wrap-around.
 354          */
 355         tc_cfg.sync_cfg_height = 0xFFF0;
 356         tc_cfg.vsync_init_val = mode->vdisplay;
 357         tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START;
 358         tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
 359         tc_cfg.start_pos = mode->vdisplay;
 360         tc_cfg.rd_ptr_irq = mode->vdisplay + 1;
 361
 362         SDE_DEBUG_CMDENC(cmd_enc,
 363                 "tc %d vsync_clk_speed_hz %u vtotal %u vrefresh %u\n",
 364                 phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
 365                 mode->vtotal, mode->vrefresh);
 366         SDE_DEBUG_CMDENC(cmd_enc,
 367                 "tc %d enable %u start_pos %u rd_ptr_irq %u\n",
 368                 phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,
 369                 tc_cfg.rd_ptr_irq);
 370         SDE_DEBUG_CMDENC(cmd_enc,
 371                 "tc %d hw_vsync_mode %u vsync_count %u vsync_init_val %u\n",
 372                 phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.hw_vsync_mode,
 373                 tc_cfg.vsync_count, tc_cfg.vsync_init_val);
 374         SDE_DEBUG_CMDENC(cmd_enc,
 375                 "tc %d cfgheight %u thresh_start %u thresh_cont %u\n",
 376                 phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height,
 377                 tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
 378
 379         phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg);
 380         phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable);
 381 }
 382
 383 static void sde_encoder_phys_cmd_pingpong_config(
 384                 struct sde_encoder_phys *phys_enc)
 385 {
 386         struct sde_encoder_phys_cmd *cmd_enc =
 387                 to_sde_encoder_phys_cmd(phys_enc);
 388         struct sde_hw_intf_cfg intf_cfg = { 0 };
 389
 390         if (!phys_enc || !phys_enc->hw_ctl ||
 391                         !phys_enc->hw_ctl->ops.setup_intf_cfg) {
 392                 SDE_ERROR("invalid arg(s), enc %d\n", phys_enc != 0);
 393                 return;
 394         }
 395
 396         SDE_DEBUG_CMDENC(cmd_enc, "pp %d, enabling mode:\n",
 397                         phys_enc->hw_pp->idx - PINGPONG_0);
 398         drm_mode_debug_printmodeline(&phys_enc->cached_mode);
 399
 400         intf_cfg.intf = cmd_enc->intf_idx;
 401         intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
 402         intf_cfg.stream_sel = cmd_enc->stream_sel;
 403         intf_cfg.mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
 404
 405         phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
 406
 407         sde_encoder_phys_cmd_tearcheck_config(phys_enc);
 408 }
 409
 410 static bool sde_encoder_phys_cmd_needs_single_flush(
 411                 struct sde_encoder_phys *phys_enc)
 412 {
 413         enum sde_rm_topology_name topology;
 414
 415         if (!phys_enc)
 416                 return false;
 417
 418         topology = sde_connector_get_topology_name(phys_enc->connector);
 419         return topology == SDE_RM_TOPOLOGY_PPSPLIT;
 420 }
 421
 422 static int sde_encoder_phys_cmd_control_vblank_irq(
 423                 struct sde_encoder_phys *phys_enc,
 424                 bool enable)
 425 {
 426         struct sde_encoder_phys_cmd *cmd_enc =
 427                 to_sde_encoder_phys_cmd(phys_enc);
 428         int ret = 0;
 429
 430         if (!phys_enc) {
 431                 SDE_ERROR("invalid encoder\n");
 432                 return -EINVAL;
 433         }
 434
 435         /* Slave encoders don't report vblank */
 436         if (!sde_encoder_phys_cmd_is_master(phys_enc))
 437                 goto end;
 438
 439         SDE_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
 440                         __builtin_return_address(0),
 441                         enable, atomic_read(&phys_enc->vblank_refcount));
 442
 443         SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
 444                         enable, atomic_read(&phys_enc->vblank_refcount));
 445
 446         if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
 447                 ret = sde_encoder_phys_cmd_register_irq(phys_enc,
 448                                 SDE_IRQ_TYPE_PING_PONG_RD_PTR,
 449                                 INTR_IDX_RDPTR,
 450                                 sde_encoder_phys_cmd_pp_rd_ptr_irq,
 451                                 "pp_rd_ptr");
 452         else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
 453                 ret = sde_encoder_phys_cmd_unregister_irq(phys_enc,
 454                                 INTR_IDX_RDPTR);
 455
 456 end:
 457         if (ret)
 458                 SDE_ERROR_CMDENC(cmd_enc,
 459                                 "control vblank irq error %d, enable %d\n",
 460                                 ret, enable);
 461
 462         return ret;
 463 }
 464
 465 static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
 466 {
 467         struct sde_encoder_phys_cmd *cmd_enc =
 468                 to_sde_encoder_phys_cmd(phys_enc);
 469         struct sde_hw_ctl *ctl;
 470         u32 flush_mask;
 471         int ret;
 472
 473         if (!phys_enc || !phys_enc->hw_ctl) {
 474                 SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
 475                 return;
 476         }
 477         SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 478
 479         if (phys_enc->enable_state == SDE_ENC_ENABLED) {
 480                 SDE_ERROR("already enabled\n");
 481                 return;
 482         }
 483
 484         sde_encoder_helper_split_config(phys_enc, cmd_enc->intf_idx);
 485
 486         sde_encoder_phys_cmd_pingpong_config(phys_enc);
 487
 488         if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
 489                 goto update_flush;
 490
 491         /* Both master and slave need to register for pp_tx_done */
 492         ret = sde_encoder_phys_cmd_register_irq(phys_enc,
 493                         SDE_IRQ_TYPE_PING_PONG_COMP,
 494                         INTR_IDX_PINGPONG,
 495                         sde_encoder_phys_cmd_pp_tx_done_irq,
 496                         "pp_tx_done");
 497         if (ret)
 498                 return;
 499
 500         ret = sde_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
 501         if (ret) {
 502                 sde_encoder_phys_cmd_unregister_irq(phys_enc,
 503                                 INTR_IDX_PINGPONG);
 504                 return;
 505         }
 506
 507         ret = sde_encoder_phys_cmd_register_irq(phys_enc,
 508                         SDE_IRQ_TYPE_INTF_UNDER_RUN,
 509                         INTR_IDX_UNDERRUN,
 510                         sde_encoder_phys_cmd_underrun_irq,
 511                         "underrun");
 512         if (ret) {
 513                 sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
 514                 sde_encoder_phys_cmd_unregister_irq(phys_enc,
 515                                 INTR_IDX_PINGPONG);
 516                 return;
 517         }
 518
 519 update_flush:
 520         ctl = phys_enc->hw_ctl;
 521         ctl->ops.get_bitmask_intf(ctl, &flush_mask, cmd_enc->intf_idx);
 522         ctl->ops.update_pending_flush(ctl, flush_mask);
 523         phys_enc->enable_state = SDE_ENC_ENABLED;
 524
 525         SDE_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d flush_mask %x\n",
 526                         ctl->idx - CTL_0, flush_mask);
 527 }
 528
 529 static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
 530 {
 531         struct sde_encoder_phys_cmd *cmd_enc =
 532                 to_sde_encoder_phys_cmd(phys_enc);
 533         int ret;
 534
 535         if (!phys_enc) {
 536                 SDE_ERROR("invalid encoder\n");
 537                 return;
 538         }
 539         SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 540
 541         if (phys_enc->enable_state == SDE_ENC_DISABLED) {
 542                 SDE_ERROR_CMDENC(cmd_enc, "already disabled\n");
 543                 return;
 544         }
 545
 546         SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0);
 547
 548         if (!_sde_encoder_phys_is_ppsplit_slave(phys_enc)) {
 549                 ret = _sde_encoder_phys_cmd_wait_for_idle(phys_enc);
 550                 if (ret) {
 551                         atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 552                         SDE_ERROR_CMDENC(cmd_enc,
 553                                         "pp %d failed wait for idle, %d\n",
 554                                         phys_enc->hw_pp->idx - PINGPONG_0, ret);
 555                         SDE_EVT32(DRMID(phys_enc->parent),
 556                                         phys_enc->hw_pp->idx - PINGPONG_0, ret);
 557                 }
 558
 559                 sde_encoder_phys_cmd_unregister_irq(
 560                                 phys_enc, INTR_IDX_UNDERRUN);
 561                 sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
 562                 sde_encoder_phys_cmd_unregister_irq(
 563                                 phys_enc, INTR_IDX_PINGPONG);
 564         }
 565
 566         phys_enc->enable_state = SDE_ENC_DISABLED;
 567
 568         if (atomic_read(&phys_enc->vblank_refcount))
 569                 SDE_ERROR("enc:%d role:%d invalid vblank refcount %d\n",
 570                                 phys_enc->parent->base.id,
 571                                 phys_enc->split_role,
 572                                 atomic_read(&phys_enc->vblank_refcount));
 573 }
 574
 575 static void sde_encoder_phys_cmd_post_disable(
 576                 struct sde_encoder_phys *phys_enc)
 577 {
 578         if (!phys_enc || !phys_enc->hw_ctl) {
 579                 SDE_ERROR("invalid encoder %d\n", phys_enc != NULL);
 580                 return;
 581         }
 582
 583         if (!_sde_encoder_phys_is_ppsplit_slave(phys_enc) &&
 584                         phys_enc->hw_ctl->ops.clear_intf_cfg)
 585                 phys_enc->hw_ctl->ops.clear_intf_cfg(phys_enc->hw_ctl);
 586 }
 587
 588 static void sde_encoder_phys_cmd_destroy(struct sde_encoder_phys *phys_enc)
 589 {
 590         struct sde_encoder_phys_cmd *cmd_enc =
 591                 to_sde_encoder_phys_cmd(phys_enc);
 592
 593         if (!phys_enc) {
 594                 SDE_ERROR("invalid encoder\n");
 595                 return;
 596         }
 597         kfree(cmd_enc);
 598 }
 599
 600 static void sde_encoder_phys_cmd_get_hw_resources(
 601                 struct sde_encoder_phys *phys_enc,
 602                 struct sde_encoder_hw_resources *hw_res,
 603                 struct drm_connector_state *conn_state)
 604 {
 605         struct sde_encoder_phys_cmd *cmd_enc =
 606                 to_sde_encoder_phys_cmd(phys_enc);
 607
 608         if (!phys_enc) {
 609                 SDE_ERROR("invalid encoder\n");
 610                 return;
 611         }
 612         SDE_DEBUG_CMDENC(cmd_enc, "\n");
 613         hw_res->intfs[cmd_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
 614 }
 615
 616 static int sde_encoder_phys_cmd_wait_for_commit_done(
 617                 struct sde_encoder_phys *phys_enc)
 618 {
 619         /*
 620          * Since ctl_start "commits" the transaction to hardware, and the
 621          * tearcheck block takes it from there, there is no need to have a
 622          * separate wait for committed, a la wait-for-vsync in video mode
 623          */
 624
 625         return 0;
 626 }
 627
 628 static void sde_encoder_phys_cmd_prepare_for_kickoff(
 629                 struct sde_encoder_phys *phys_enc)
 630 {
 631         struct sde_encoder_phys_cmd *cmd_enc =
 632                         to_sde_encoder_phys_cmd(phys_enc);
 633         int ret;
 634
 635         if (!phys_enc) {
 636                 SDE_ERROR("invalid encoder\n");
 637                 return;
 638         }
 639         SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
 640         SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0);
 641
 642         /*
 643          * Mark kickoff request as outstanding. If there are more than one,
 644          * outstanding, then we have to wait for the previous one to complete
 645          */
 646         ret = _sde_encoder_phys_cmd_wait_for_idle(phys_enc);
 647         if (ret) {
 648                 /* force pending_kickoff_cnt 0 to discard failed kickoff */
 649                 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 650                 SDE_EVT32(DRMID(phys_enc->parent),
 651                                 phys_enc->hw_pp->idx - PINGPONG_0);
 652                 SDE_ERROR("failed wait_for_idle: %d\n", ret);
 653         }
 654 }
 655
 656 static void sde_encoder_phys_cmd_init_ops(
 657                 struct sde_encoder_phys_ops *ops)
 658 {
 659         ops->is_master = sde_encoder_phys_cmd_is_master;
 660         ops->mode_set = sde_encoder_phys_cmd_mode_set;
 661         ops->mode_fixup = sde_encoder_phys_cmd_mode_fixup;
 662         ops->enable = sde_encoder_phys_cmd_enable;
 663         ops->disable = sde_encoder_phys_cmd_disable;
 664         ops->post_disable = sde_encoder_phys_cmd_post_disable;
 665         ops->destroy = sde_encoder_phys_cmd_destroy;
 666         ops->get_hw_resources = sde_encoder_phys_cmd_get_hw_resources;
 667         ops->control_vblank_irq = sde_encoder_phys_cmd_control_vblank_irq;
 668         ops->wait_for_commit_done = sde_encoder_phys_cmd_wait_for_commit_done;
 669         ops->prepare_for_kickoff = sde_encoder_phys_cmd_prepare_for_kickoff;
 670         ops->trigger_start = sde_encoder_helper_trigger_start;
 671         ops->needs_single_flush = sde_encoder_phys_cmd_needs_single_flush;
 672 }
 673
 674 struct sde_encoder_phys *sde_encoder_phys_cmd_init(
 675                 struct sde_enc_phys_init_params *p)
 676 {
 677         struct sde_encoder_phys *phys_enc = NULL;
 678         struct sde_encoder_phys_cmd *cmd_enc = NULL;
 679         struct sde_hw_mdp *hw_mdp;
 680         int i, ret = 0;
 681
 682         SDE_DEBUG("intf %d\n", p->intf_idx - INTF_0);
 683
 684         cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);
 685         if (!cmd_enc) {
 686                 ret = -ENOMEM;
 687                 SDE_ERROR("failed to allocate\n");
 688                 goto fail;
 689         }
 690         phys_enc = &cmd_enc->base;
 691
 692         hw_mdp = sde_rm_get_mdp(&p->sde_kms->rm);
 693         if (IS_ERR_OR_NULL(hw_mdp)) {
 694                 ret = PTR_ERR(hw_mdp);
 695                 SDE_ERROR("failed to get mdptop\n");
 696                 goto fail_mdp_init;
 697         }
 698         phys_enc->hw_mdptop = hw_mdp;
 699
 700         cmd_enc->intf_idx = p->intf_idx;
 701         phys_enc->intf_idx = p->intf_idx;
 702
 703         sde_encoder_phys_cmd_init_ops(&phys_enc->ops);
 704         phys_enc->parent = p->parent;
 705         phys_enc->parent_ops = p->parent_ops;
 706         phys_enc->sde_kms = p->sde_kms;
 707         phys_enc->split_role = p->split_role;
 708         phys_enc->intf_mode = INTF_MODE_CMD;
 709         phys_enc->enc_spinlock = p->enc_spinlock;
 710         cmd_enc->stream_sel = 0;
 711         phys_enc->enable_state = SDE_ENC_DISABLED;
 712         for (i = 0; i < INTR_IDX_MAX; i++)
 713                 INIT_LIST_HEAD(&cmd_enc->irq_cb[i].list);
 714         atomic_set(&phys_enc->vblank_refcount, 0);
 715         atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 716         init_waitqueue_head(&phys_enc->pending_kickoff_wq);
 717
 718         SDE_DEBUG_CMDENC(cmd_enc, "created\n");
 719
 720         return phys_enc;
 721
 722 fail_mdp_init:
 723         kfree(cmd_enc);
 724 fail:
 725         return ERR_PTR(ret);
 726 }