2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
26 #include <core/class.h>
28 #include <subdev/fb.h>
29 #include <subdev/vm/nv04.h>
31 #include <engine/dmaobj.h>
33 struct nv04_dmaeng_priv {
34 struct nouveau_dmaeng base;
37 struct nv04_dmaobj_priv {
38 struct nouveau_dmaobj base;
42 nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
43 struct nouveau_object *parent,
44 struct nouveau_dmaobj *dmaobj,
45 struct nouveau_gpuobj **pgpuobj)
47 struct nouveau_gpuobj *gpuobj;
48 u32 flags0 = nv_mclass(dmaobj);
49 u32 flags2 = 0x00000000;
50 u32 offset = (dmaobj->start & 0xfffff000);
51 u32 adjust = (dmaobj->start & 0x00000fff);
52 u32 length = dmaobj->limit - dmaobj->start;
55 if (dmaobj->target == NV_MEM_TARGET_VM) {
56 gpuobj = nv04_vmmgr(dmaeng)->vm->pgt[0].obj[0];
57 if (dmaobj->start == 0)
58 return nouveau_gpuobj_dup(parent, gpuobj, pgpuobj);
60 offset = nv_ro32(gpuobj, 8 + (offset >> 10));
62 dmaobj->target = NV_MEM_TARGET_PCI;
63 dmaobj->access = NV_MEM_ACCESS_RW;
66 switch (dmaobj->target) {
67 case NV_MEM_TARGET_VRAM:
70 case NV_MEM_TARGET_PCI:
73 case NV_MEM_TARGET_PCI_NOSNOOP:
80 switch (dmaobj->access) {
81 case NV_MEM_ACCESS_RO:
84 case NV_MEM_ACCESS_WO:
86 case NV_MEM_ACCESS_RW:
93 ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
96 nv_wo32(*pgpuobj, 0x00, flags0 | (adjust << 20));
97 nv_wo32(*pgpuobj, 0x04, length);
98 nv_wo32(*pgpuobj, 0x08, flags2 | offset);
99 nv_wo32(*pgpuobj, 0x0c, flags2 | offset);
106 nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
107 struct nouveau_oclass *oclass, void *data, u32 size,
108 struct nouveau_object **pobject)
110 struct nouveau_dmaeng *dmaeng = (void *)engine;
111 struct nv04_dmaobj_priv *dmaobj;
112 struct nouveau_gpuobj *gpuobj;
115 ret = nouveau_dmaobj_create(parent, engine, oclass,
116 data, size, &dmaobj);
117 *pobject = nv_object(dmaobj);
121 switch (nv_mclass(parent)) {
122 case NV_DEVICE_CLASS:
124 case NV03_CHANNEL_DMA_CLASS:
125 case NV10_CHANNEL_DMA_CLASS:
126 case NV17_CHANNEL_DMA_CLASS:
127 case NV40_CHANNEL_DMA_CLASS:
128 ret = dmaeng->bind(dmaeng, *pobject, &dmaobj->base, &gpuobj);
129 nouveau_object_ref(NULL, pobject);
130 *pobject = nv_object(gpuobj);
139 static struct nouveau_ofuncs
140 nv04_dmaobj_ofuncs = {
141 .ctor = nv04_dmaobj_ctor,
142 .dtor = _nouveau_dmaobj_dtor,
143 .init = _nouveau_dmaobj_init,
144 .fini = _nouveau_dmaobj_fini,
147 static struct nouveau_oclass
148 nv04_dmaobj_sclass[] = {
149 { 0x0002, &nv04_dmaobj_ofuncs },
150 { 0x0003, &nv04_dmaobj_ofuncs },
151 { 0x003d, &nv04_dmaobj_ofuncs },
156 nv04_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
157 struct nouveau_oclass *oclass, void *data, u32 size,
158 struct nouveau_object **pobject)
160 struct nv04_dmaeng_priv *priv;
163 ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
164 *pobject = nv_object(priv);
168 priv->base.base.sclass = nv04_dmaobj_sclass;
169 priv->base.bind = nv04_dmaobj_bind;
173 struct nouveau_oclass
174 nv04_dmaeng_oclass = {
175 .handle = NV_ENGINE(DMAOBJ, 0x04),
176 .ofuncs = &(struct nouveau_ofuncs) {
177 .ctor = nv04_dmaeng_ctor,
178 .dtor = _nouveau_dmaeng_dtor,
179 .init = _nouveau_dmaeng_init,
180 .fini = _nouveau_dmaeng_fini,