drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/class.h>
  27 #include <core/engctx.h>
  28 #include <core/namedb.h>
  29 #include <core/handle.h>
  30 #include <core/ramht.h>
  31
  32 #include <subdev/instmem.h>
  33 #include <subdev/instmem/nv04.h>
  34 #include <subdev/timer.h>
  35 #include <subdev/fb.h>
  36
  37 #include <engine/fifo.h>
  38
  39 #include "nv04.h"
  40
  41 static struct ramfc_desc
  42 nv04_ramfc[] = {
  43         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  44         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  45         { 16,  0, 0x08,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  46         { 16, 16, 0x08,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  47         { 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  48         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  49         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_ENGINE },
  50         { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_PULL1 },
  51         {}
  52 };
  53
  54 /*******************************************************************************
  55  * FIFO channel objects
  56  ******************************************************************************/
  57
  58 int
  59 nv04_fifo_object_attach(struct nouveau_object *parent,
  60                         struct nouveau_object *object, u32 handle)
  61 {
  62         struct nv04_fifo_priv *priv = (void *)parent->engine;
  63         struct nv04_fifo_chan *chan = (void *)parent;
  64         u32 context, chid = chan->base.chid;
  65         int ret;
  66
  67         if (nv_iclass(object, NV_GPUOBJ_CLASS))
  68                 context = nv_gpuobj(object)->addr >> 4;
  69         else
  70                 context = 0x00000004; /* just non-zero */
  71
  72         switch (nv_engidx(object->engine)) {
  73         case NVDEV_ENGINE_DMAOBJ:
  74         case NVDEV_ENGINE_SW:
  75                 context |= 0x00000000;
  76                 break;
  77         case NVDEV_ENGINE_GR:
  78                 context |= 0x00010000;
  79                 break;
  80         case NVDEV_ENGINE_MPEG:
  81                 context |= 0x00020000;
  82                 break;
  83         default:
  84                 return -EINVAL;
  85         }
  86
  87         context |= 0x80000000; /* valid */
  88         context |= chid << 24;
  89
  90         mutex_lock(&nv_subdev(priv)->mutex);
  91         ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
  92         mutex_unlock(&nv_subdev(priv)->mutex);
  93         return ret;
  94 }
  95
  96 void
  97 nv04_fifo_object_detach(struct nouveau_object *parent, int cookie)
  98 {
  99         struct nv04_fifo_priv *priv = (void *)parent->engine;
 100         mutex_lock(&nv_subdev(priv)->mutex);
 101         nouveau_ramht_remove(priv->ramht, cookie);
 102         mutex_unlock(&nv_subdev(priv)->mutex);
 103 }
 104
 105 int
 106 nv04_fifo_context_attach(struct nouveau_object *parent,
 107                          struct nouveau_object *object)
 108 {
 109         nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid;
 110         return 0;
 111 }
 112
 113 static int
 114 nv04_fifo_chan_ctor(struct nouveau_object *parent,
 115                     struct nouveau_object *engine,
 116                     struct nouveau_oclass *oclass, void *data, u32 size,
 117                     struct nouveau_object **pobject)
 118 {
 119         struct nv04_fifo_priv *priv = (void *)engine;
 120         struct nv04_fifo_chan *chan;
 121         struct nv03_channel_dma_class *args = data;
 122         int ret;
 123
 124         if (size < sizeof(*args))
 125                 return -EINVAL;
 126
 127         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
 128                                           0x10000, args->pushbuf,
 129                                           (1 << NVDEV_ENGINE_DMAOBJ) |
 130                                           (1 << NVDEV_ENGINE_SW) |
 131                                           (1 << NVDEV_ENGINE_GR), &chan);
 132         *pobject = nv_object(chan);
 133         if (ret)
 134                 return ret;
 135
 136         nv_parent(chan)->object_attach = nv04_fifo_object_attach;
 137         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
 138         nv_parent(chan)->context_attach = nv04_fifo_context_attach;
 139         chan->ramfc = chan->base.chid * 32;
 140
 141         nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset);
 142         nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset);
 143         nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4);
 144         nv_wo32(priv->ramfc, chan->ramfc + 0x10,
 145                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 146                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 147 #ifdef __BIG_ENDIAN
 148                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 149 #endif
 150                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 151         return 0;
 152 }
 153
 154 void
 155 nv04_fifo_chan_dtor(struct nouveau_object *object)
 156 {
 157         struct nv04_fifo_priv *priv = (void *)object->engine;
 158         struct nv04_fifo_chan *chan = (void *)object;
 159         struct ramfc_desc *c = priv->ramfc_desc;
 160
 161         do {
 162                 nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000);
 163         } while ((++c)->bits);
 164
 165         nouveau_fifo_channel_destroy(&chan->base);
 166 }
 167
 168 int
 169 nv04_fifo_chan_init(struct nouveau_object *object)
 170 {
 171         struct nv04_fifo_priv *priv = (void *)object->engine;
 172         struct nv04_fifo_chan *chan = (void *)object;
 173         u32 mask = 1 << chan->base.chid;
 174         unsigned long flags;
 175         int ret;
 176
 177         ret = nouveau_fifo_channel_init(&chan->base);
 178         if (ret)
 179                 return ret;
 180
 181         spin_lock_irqsave(&priv->base.lock, flags);
 182         nv_mask(priv, NV04_PFIFO_MODE, mask, mask);
 183         spin_unlock_irqrestore(&priv->base.lock, flags);
 184         return 0;
 185 }
 186
 187 int
 188 nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 189 {
 190         struct nv04_fifo_priv *priv = (void *)object->engine;
 191         struct nv04_fifo_chan *chan = (void *)object;
 192         struct nouveau_gpuobj *fctx = priv->ramfc;
 193         struct ramfc_desc *c;
 194         unsigned long flags;
 195         u32 data = chan->ramfc;
 196         u32 chid;
 197
 198         /* prevent fifo context switches */
 199         spin_lock_irqsave(&priv->base.lock, flags);
 200         nv_wr32(priv, NV03_PFIFO_CACHES, 0);
 201
 202         /* if this channel is active, replace it with a null context */
 203         chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
 204         if (chid == chan->base.chid) {
 205                 nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
 206                 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0);
 207                 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
 208
 209                 c = priv->ramfc_desc;
 210                 do {
 211                         u32 rm = ((1ULL << c->bits) - 1) << c->regs;
 212                         u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
 213                         u32 rv = (nv_rd32(priv, c->regp) &  rm) >> c->regs;
 214                         u32 cv = (nv_ro32(fctx, c->ctxp + data) & ~cm);
 215                         nv_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
 216                 } while ((++c)->bits);
 217
 218                 c = priv->ramfc_desc;
 219                 do {
 220                         nv_wr32(priv, c->regp, 0x00000000);
 221                 } while ((++c)->bits);
 222
 223                 nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0);
 224                 nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0);
 225                 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
 226                 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
 227                 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 228         }
 229
 230         /* restore normal operation, after disabling dma mode */
 231         nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0);
 232         nv_wr32(priv, NV03_PFIFO_CACHES, 1);
 233         spin_unlock_irqrestore(&priv->base.lock, flags);
 234
 235         return nouveau_fifo_channel_fini(&chan->base, suspend);
 236 }
 237
 238 static struct nouveau_ofuncs
 239 nv04_fifo_ofuncs = {
 240         .ctor = nv04_fifo_chan_ctor,
 241         .dtor = nv04_fifo_chan_dtor,
 242         .init = nv04_fifo_chan_init,
 243         .fini = nv04_fifo_chan_fini,
 244         .rd32 = _nouveau_fifo_channel_rd32,
 245         .wr32 = _nouveau_fifo_channel_wr32,
 246 };
 247
 248 static struct nouveau_oclass
 249 nv04_fifo_sclass[] = {
 250         { NV03_CHANNEL_DMA_CLASS, &nv04_fifo_ofuncs },
 251         {}
 252 };
 253
 254 /*******************************************************************************
 255  * FIFO context - basically just the instmem reserved for the channel
 256  ******************************************************************************/
 257
 258 int
 259 nv04_fifo_context_ctor(struct nouveau_object *parent,
 260                        struct nouveau_object *engine,
 261                        struct nouveau_oclass *oclass, void *data, u32 size,
 262                        struct nouveau_object **pobject)
 263 {
 264         struct nv04_fifo_base *base;
 265         int ret;
 266
 267         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 268                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 269         *pobject = nv_object(base);
 270         if (ret)
 271                 return ret;
 272
 273         return 0;
 274 }
 275
 276 static struct nouveau_oclass
 277 nv04_fifo_cclass = {
 278         .handle = NV_ENGCTX(FIFO, 0x04),
 279         .ofuncs = &(struct nouveau_ofuncs) {
 280                 .ctor = nv04_fifo_context_ctor,
 281                 .dtor = _nouveau_fifo_context_dtor,
 282                 .init = _nouveau_fifo_context_init,
 283                 .fini = _nouveau_fifo_context_fini,
 284                 .rd32 = _nouveau_fifo_context_rd32,
 285                 .wr32 = _nouveau_fifo_context_wr32,
 286         },
 287 };
 288
 289 /*******************************************************************************
 290  * PFIFO engine
 291  ******************************************************************************/
 292
 293 void
 294 nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags)
 295 __acquires(priv->base.lock)
 296 {
 297         struct nv04_fifo_priv *priv = (void *)pfifo;
 298         unsigned long flags;
 299
 300         spin_lock_irqsave(&priv->base.lock, flags);
 301         *pflags = flags;
 302
 303         nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000);
 304         nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000);
 305
 306         /* in some cases the puller may be left in an inconsistent state
 307          * if you try to stop it while it's busy translating handles.
 308          * sometimes you get a CACHE_ERROR, sometimes it just fails
 309          * silently; sending incorrect instance offsets to PGRAPH after
 310          * it's started up again.
 311          *
 312          * to avoid this, we invalidate the most recently calculated
 313          * instance.
 314          */
 315         if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0,
 316                            NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0x00000000))
 317                 nv_warn(priv, "timeout idling puller\n");
 318
 319         if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) &
 320                           NV04_PFIFO_CACHE1_PULL0_HASH_FAILED)
 321                 nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
 322
 323         nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0x00000000);
 324 }
 325
 326 void
 327 nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags)
 328 __releases(priv->base.lock)
 329 {
 330         struct nv04_fifo_priv *priv = (void *)pfifo;
 331         unsigned long flags = *pflags;
 332
 333         nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001);
 334         nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000001);
 335
 336         spin_unlock_irqrestore(&priv->base.lock, flags);
 337 }
 338
 339 static const char *
 340 nv_dma_state_err(u32 state)
 341 {
 342         static const char * const desc[] = {
 343                 "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE",
 344                 "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK"
 345         };
 346         return desc[(state >> 29) & 0x7];
 347 }
 348
 349 static bool
 350 nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data)
 351 {
 352         struct nv04_fifo_chan *chan = NULL;
 353         struct nouveau_handle *bind;
 354         const int subc = (addr >> 13) & 0x7;
 355         const int mthd = addr & 0x1ffc;
 356         bool handled = false;
 357         unsigned long flags;
 358         u32 engine;
 359
 360         spin_lock_irqsave(&priv->base.lock, flags);
 361         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 362                 chan = (void *)priv->base.channel[chid];
 363         if (unlikely(!chan))
 364                 goto out;
 365
 366         switch (mthd) {
 367         case 0x0000:
 368                 bind = nouveau_namedb_get(nv_namedb(chan), data);
 369                 if (unlikely(!bind))
 370                         break;
 371
 372                 if (nv_engidx(bind->object->engine) == NVDEV_ENGINE_SW) {
 373                         engine = 0x0000000f << (subc * 4);
 374                         chan->subc[subc] = data;
 375                         handled = true;
 376
 377                         nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0);
 378                 }
 379
 380                 nouveau_namedb_put(bind);
 381                 break;
 382         default:
 383                 engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE);
 384                 if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
 385                         break;
 386
 387                 bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]);
 388                 if (likely(bind)) {
 389                         if (!nv_call(bind->object, mthd, data))
 390                                 handled = true;
 391                         nouveau_namedb_put(bind);
 392                 }
 393                 break;
 394         }
 395
 396 out:
 397         spin_unlock_irqrestore(&priv->base.lock, flags);
 398         return handled;
 399 }
 400
 401 void
 402 nv04_fifo_intr(struct nouveau_subdev *subdev)
 403 {
 404         struct nouveau_device *device = nv_device(subdev);
 405         struct nv04_fifo_priv *priv = (void *)subdev;
 406         uint32_t status, reassign;
 407         int cnt = 0;
 408
 409         reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1;
 410         while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
 411                 uint32_t chid, get;
 412
 413                 nv_wr32(priv, NV03_PFIFO_CACHES, 0);
 414
 415                 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;
 416                 get  = nv_rd32(priv, NV03_PFIFO_CACHE1_GET);
 417
 418                 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
 419                         uint32_t mthd, data;
 420                         int ptr;
 421
 422                         /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
 423                          * wrapping on my G80 chips, but CACHE1 isn't big
 424                          * enough for this much data.. Tests show that it
 425                          * wraps around to the start at GET=0x800.. No clue
 426                          * as to why..
 427                          */
 428                         ptr = (get & 0x7ff) >> 2;
 429
 430                         if (device->card_type < NV_40) {
 431                                 mthd = nv_rd32(priv,
 432                                         NV04_PFIFO_CACHE1_METHOD(ptr));
 433                                 data = nv_rd32(priv,
 434                                         NV04_PFIFO_CACHE1_DATA(ptr));
 435                         } else {
 436                                 mthd = nv_rd32(priv,
 437                                         NV40_PFIFO_CACHE1_METHOD(ptr));
 438                                 data = nv_rd32(priv,
 439                                         NV40_PFIFO_CACHE1_DATA(ptr));
 440                         }
 441
 442                         if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
 443                                 nv_info(priv, "CACHE_ERROR - Ch %d/%d "
 444                                               "Mthd 0x%04x Data 0x%08x\n",
 445                                         chid, (mthd >> 13) & 7, mthd & 0x1ffc,
 446                                         data);
 447                         }
 448
 449                         nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
 450                         nv_wr32(priv, NV03_PFIFO_INTR_0,
 451                                                 NV_PFIFO_INTR_CACHE_ERROR);
 452
 453                         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
 454                                 nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1);
 455                         nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
 456                         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0,
 457                                 nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1);
 458                         nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0);
 459
 460                         nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH,
 461                                 nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
 462                         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 463
 464                         status &= ~NV_PFIFO_INTR_CACHE_ERROR;
 465                 }
 466
 467                 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 468                         u32 dma_get = nv_rd32(priv, 0x003244);
 469                         u32 dma_put = nv_rd32(priv, 0x003240);
 470                         u32 push = nv_rd32(priv, 0x003220);
 471                         u32 state = nv_rd32(priv, 0x003228);
 472
 473                         if (device->card_type == NV_50) {
 474                                 u32 ho_get = nv_rd32(priv, 0x003328);
 475                                 u32 ho_put = nv_rd32(priv, 0x003320);
 476                                 u32 ib_get = nv_rd32(priv, 0x003334);
 477                                 u32 ib_put = nv_rd32(priv, 0x003330);
 478
 479                                 nv_info(priv, "DMA_PUSHER - Ch %d Get 0x%02x%08x "
 480                                      "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
 481                                      "State 0x%08x (err: %s) Push 0x%08x\n",
 482                                         chid, ho_get, dma_get, ho_put,
 483                                         dma_put, ib_get, ib_put, state,
 484                                         nv_dma_state_err(state),
 485                                         push);
 486
 487                                 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
 488                                 nv_wr32(priv, 0x003364, 0x00000000);
 489                                 if (dma_get != dma_put || ho_get != ho_put) {
 490                                         nv_wr32(priv, 0x003244, dma_put);
 491                                         nv_wr32(priv, 0x003328, ho_put);
 492                                 } else
 493                                 if (ib_get != ib_put) {
 494                                         nv_wr32(priv, 0x003334, ib_put);
 495                                 }
 496                         } else {
 497                                 nv_info(priv, "DMA_PUSHER - Ch %d Get 0x%08x "
 498                                              "Put 0x%08x State 0x%08x (err: %s) Push 0x%08x\n",
 499                                         chid, dma_get, dma_put, state,
 500                                         nv_dma_state_err(state), push);
 501
 502                                 if (dma_get != dma_put)
 503                                         nv_wr32(priv, 0x003244, dma_put);
 504                         }
 505
 506                         nv_wr32(priv, 0x003228, 0x00000000);
 507                         nv_wr32(priv, 0x003220, 0x00000001);
 508                         nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
 509                         status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 510                 }
 511
 512                 if (status & NV_PFIFO_INTR_SEMAPHORE) {
 513                         uint32_t sem;
 514
 515                         status &= ~NV_PFIFO_INTR_SEMAPHORE;
 516                         nv_wr32(priv, NV03_PFIFO_INTR_0,
 517                                 NV_PFIFO_INTR_SEMAPHORE);
 518
 519                         sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE);
 520                         nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
 521
 522                         nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4);
 523                         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 524                 }
 525
 526                 if (device->card_type == NV_50) {
 527                         if (status & 0x00000010) {
 528                                 nv50_fb_trap(nouveau_fb(priv), 1);
 529                                 status &= ~0x00000010;
 530                                 nv_wr32(priv, 0x002100, 0x00000010);
 531                         }
 532                 }
 533
 534                 if (status) {
 535                         nv_info(priv, "unknown intr 0x%08x, ch %d\n",
 536                                 status, chid);
 537                         nv_wr32(priv, NV03_PFIFO_INTR_0, status);
 538                         status = 0;
 539                 }
 540
 541                 nv_wr32(priv, NV03_PFIFO_CACHES, reassign);
 542         }
 543
 544         if (status) {
 545                 nv_info(priv, "still angry after %d spins, halt\n", cnt);
 546                 nv_wr32(priv, 0x002140, 0);
 547                 nv_wr32(priv, 0x000140, 0);
 548         }
 549
 550         nv_wr32(priv, 0x000100, 0x00000100);
 551 }
 552
 553 static int
 554 nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 555                struct nouveau_oclass *oclass, void *data, u32 size,
 556                struct nouveau_object **pobject)
 557 {
 558         struct nv04_instmem_priv *imem = nv04_instmem(parent);
 559         struct nv04_fifo_priv *priv;
 560         int ret;
 561
 562         ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv);
 563         *pobject = nv_object(priv);
 564         if (ret)
 565                 return ret;
 566
 567         nouveau_ramht_ref(imem->ramht, &priv->ramht);
 568         nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
 569         nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
 570
 571         nv_subdev(priv)->unit = 0x00000100;
 572         nv_subdev(priv)->intr = nv04_fifo_intr;
 573         nv_engine(priv)->cclass = &nv04_fifo_cclass;
 574         nv_engine(priv)->sclass = nv04_fifo_sclass;
 575         priv->base.pause = nv04_fifo_pause;
 576         priv->base.start = nv04_fifo_start;
 577         priv->ramfc_desc = nv04_ramfc;
 578         return 0;
 579 }
 580
 581 void
 582 nv04_fifo_dtor(struct nouveau_object *object)
 583 {
 584         struct nv04_fifo_priv *priv = (void *)object;
 585         nouveau_gpuobj_ref(NULL, &priv->ramfc);
 586         nouveau_gpuobj_ref(NULL, &priv->ramro);
 587         nouveau_ramht_ref(NULL, &priv->ramht);
 588         nouveau_fifo_destroy(&priv->base);
 589 }
 590
 591 int
 592 nv04_fifo_init(struct nouveau_object *object)
 593 {
 594         struct nv04_fifo_priv *priv = (void *)object;
 595         int ret;
 596
 597         ret = nouveau_fifo_init(&priv->base);
 598         if (ret)
 599                 return ret;
 600
 601         nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
 602         nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
 603
 604         nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 605                                        ((priv->ramht->bits - 9) << 16) |
 606                                         (priv->ramht->base.addr >> 8));
 607         nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
 608         nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8);
 609
 610         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
 611
 612         nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
 613         nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
 614
 615         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
 616         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 617         nv_wr32(priv, NV03_PFIFO_CACHES, 1);
 618         return 0;
 619 }
 620
 621 struct nouveau_oclass
 622 nv04_fifo_oclass = {
 623         .handle = NV_ENGINE(FIFO, 0x04),
 624         .ofuncs = &(struct nouveau_ofuncs) {
 625                 .ctor = nv04_fifo_ctor,
 626                 .dtor = nv04_fifo_dtor,
 627                 .init = nv04_fifo_init,
 628                 .fini = _nouveau_fifo_fini,
 629         },
 630 };