drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/engctx.h>
  27 #include <core/ramht.h>
  28 #include <core/class.h>
  29 #include <core/math.h>
  30
  31 #include <subdev/timer.h>
  32 #include <subdev/bar.h>
  33
  34 #include <engine/dmaobj.h>
  35 #include <engine/fifo.h>
  36
  37 #include "nv50.h"
  38
  39 /*******************************************************************************
  40  * FIFO channel objects
  41  ******************************************************************************/
  42
  43 void
  44 nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
  45 {
  46         struct nouveau_bar *bar = nouveau_bar(priv);
  47         struct nouveau_gpuobj *cur;
  48         int i, p;
  49
  50         cur = priv->playlist[priv->cur_playlist];
  51         priv->cur_playlist = !priv->cur_playlist;
  52
  53         for (i = priv->base.min, p = 0; i < priv->base.max; i++) {
  54                 if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000)
  55                         nv_wo32(cur, p++ * 4, i);
  56         }
  57
  58         bar->flush(bar);
  59
  60         nv_wr32(priv, 0x0032f4, cur->addr >> 12);
  61         nv_wr32(priv, 0x0032ec, p);
  62         nv_wr32(priv, 0x002500, 0x00000101);
  63 }
  64
  65 static int
  66 nv50_fifo_context_attach(struct nouveau_object *parent,
  67                          struct nouveau_object *object)
  68 {
  69         struct nouveau_bar *bar = nouveau_bar(parent);
  70         struct nv50_fifo_base *base = (void *)parent->parent;
  71         struct nouveau_gpuobj *ectx = (void *)object;
  72         u64 limit = ectx->addr + ectx->size - 1;
  73         u64 start = ectx->addr;
  74         u32 addr;
  75
  76         switch (nv_engidx(object->engine)) {
  77         case NVDEV_ENGINE_SW   : return 0;
  78         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
  79         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  80         default:
  81                 return -EINVAL;
  82         }
  83
  84         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  85         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  86         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  87         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  88         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  89                                         upper_32_bits(start));
  90         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  91         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  92         bar->flush(bar);
  93         return 0;
  94 }
  95
  96 static int
  97 nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
  98                          struct nouveau_object *object)
  99 {
 100         struct nouveau_bar *bar = nouveau_bar(parent);
 101         struct nv50_fifo_priv *priv = (void *)parent->engine;
 102         struct nv50_fifo_base *base = (void *)parent->parent;
 103         struct nv50_fifo_chan *chan = (void *)parent;
 104         u32 addr, me;
 105         int ret = 0;
 106
 107         switch (nv_engidx(object->engine)) {
 108         case NVDEV_ENGINE_SW   : return 0;
 109         case NVDEV_ENGINE_GR   : addr = 0x0000; break;
 110         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
 111         default:
 112                 return -EINVAL;
 113         }
 114
 115         nv_wo32(base->eng, addr + 0x00, 0x00000000);
 116         nv_wo32(base->eng, addr + 0x04, 0x00000000);
 117         nv_wo32(base->eng, addr + 0x08, 0x00000000);
 118         nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 119         nv_wo32(base->eng, addr + 0x10, 0x00000000);
 120         nv_wo32(base->eng, addr + 0x14, 0x00000000);
 121         bar->flush(bar);
 122
 123         /* HW bug workaround:
 124          *
 125          * PFIFO will hang forever if the connected engines don't report
 126          * that they've processed the context switch request.
 127          *
 128          * In order for the kickoff to work, we need to ensure all the
 129          * connected engines are in a state where they can answer.
 130          *
 131          * Newer chipsets don't seem to suffer from this issue, and well,
 132          * there's also a "ignore these engines" bitmask reg we can use
 133          * if we hit the issue there..
 134          */
 135         me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001);
 136
 137         /* do the kickoff... */
 138         nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 139         if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
 140                 nv_error(priv, "channel %d unload timeout\n", chan->base.chid);
 141                 if (suspend)
 142                         ret = -EBUSY;
 143         }
 144
 145         nv_wr32(priv, 0x00b860, me);
 146         return ret;
 147 }
 148
 149 static int
 150 nv50_fifo_object_attach(struct nouveau_object *parent,
 151                         struct nouveau_object *object, u32 handle)
 152 {
 153         struct nv50_fifo_chan *chan = (void *)parent;
 154         u32 context;
 155
 156         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 157                 context = nv_gpuobj(object)->node->offset >> 4;
 158         else
 159                 context = 0x00000004; /* just non-zero */
 160
 161         switch (nv_engidx(object->engine)) {
 162         case NVDEV_ENGINE_DMAOBJ:
 163         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 164         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 165         case NVDEV_ENGINE_MPEG  : context |= 0x00200000; break;
 166         default:
 167                 return -EINVAL;
 168         }
 169
 170         return nouveau_ramht_insert(chan->ramht, 0, handle, context);
 171 }
 172
 173 void
 174 nv50_fifo_object_detach(struct nouveau_object *parent, int cookie)
 175 {
 176         struct nv50_fifo_chan *chan = (void *)parent;
 177         nouveau_ramht_remove(chan->ramht, cookie);
 178 }
 179
 180 static int
 181 nv50_fifo_chan_ctor_dma(struct nouveau_object *parent,
 182                         struct nouveau_object *engine,
 183                         struct nouveau_oclass *oclass, void *data, u32 size,
 184                         struct nouveau_object **pobject)
 185 {
 186         struct nouveau_bar *bar = nouveau_bar(parent);
 187         struct nv50_fifo_base *base = (void *)parent;
 188         struct nv50_fifo_chan *chan;
 189         struct nv03_channel_dma_class *args = data;
 190         int ret;
 191
 192         if (size < sizeof(*args))
 193                 return -EINVAL;
 194
 195         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 196                                           0x2000, args->pushbuf,
 197                                           (1 << NVDEV_ENGINE_DMAOBJ) |
 198                                           (1 << NVDEV_ENGINE_SW) |
 199                                           (1 << NVDEV_ENGINE_GR) |
 200                                           (1 << NVDEV_ENGINE_MPEG), &chan);
 201         *pobject = nv_object(chan);
 202         if (ret)
 203                 return ret;
 204
 205         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 206         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 207         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 208         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 209
 210         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 211         if (ret)
 212                 return ret;
 213
 214         nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
 215         nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
 216         nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
 217         nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
 218         nv_wo32(base->ramfc, 0x3c, 0x003f6078);
 219         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 220         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 221         nv_wo32(base->ramfc, 0x4c, 0xffffffff);
 222         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 223         nv_wo32(base->ramfc, 0x78, 0x00000000);
 224         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 225         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 226                                    (4 << 24) /* SEARCH_FULL */ |
 227                                    (chan->ramht->base.node->offset >> 4));
 228         bar->flush(bar);
 229         return 0;
 230 }
 231
 232 static int
 233 nv50_fifo_chan_ctor_ind(struct nouveau_object *parent,
 234                         struct nouveau_object *engine,
 235                         struct nouveau_oclass *oclass, void *data, u32 size,
 236                         struct nouveau_object **pobject)
 237 {
 238         struct nv50_channel_ind_class *args = data;
 239         struct nouveau_bar *bar = nouveau_bar(parent);
 240         struct nv50_fifo_base *base = (void *)parent;
 241         struct nv50_fifo_chan *chan;
 242         u64 ioffset, ilength;
 243         int ret;
 244
 245         if (size < sizeof(*args))
 246                 return -EINVAL;
 247
 248         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 249                                           0x2000, args->pushbuf,
 250                                           (1 << NVDEV_ENGINE_DMAOBJ) |
 251                                           (1 << NVDEV_ENGINE_SW) |
 252                                           (1 << NVDEV_ENGINE_GR) |
 253                                           (1 << NVDEV_ENGINE_MPEG), &chan);
 254         *pobject = nv_object(chan);
 255         if (ret)
 256                 return ret;
 257
 258         nv_parent(chan)->context_attach = nv50_fifo_context_attach;
 259         nv_parent(chan)->context_detach = nv50_fifo_context_detach;
 260         nv_parent(chan)->object_attach = nv50_fifo_object_attach;
 261         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 262
 263         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 264         if (ret)
 265                 return ret;
 266
 267         ioffset = args->ioffset;
 268         ilength = log2i(args->ilength / 8);
 269
 270         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 271         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 272         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 273         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 274         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 275         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 276         nv_wo32(base->ramfc, 0x78, 0x00000000);
 277         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 278         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 279                                    (4 << 24) /* SEARCH_FULL */ |
 280                                    (chan->ramht->base.node->offset >> 4));
 281         bar->flush(bar);
 282         return 0;
 283 }
 284
 285 void
 286 nv50_fifo_chan_dtor(struct nouveau_object *object)
 287 {
 288         struct nv50_fifo_chan *chan = (void *)object;
 289         nouveau_ramht_ref(NULL, &chan->ramht);
 290         nouveau_fifo_channel_destroy(&chan->base);
 291 }
 292
 293 static int
 294 nv50_fifo_chan_init(struct nouveau_object *object)
 295 {
 296         struct nv50_fifo_priv *priv = (void *)object->engine;
 297         struct nv50_fifo_base *base = (void *)object->parent;
 298         struct nv50_fifo_chan *chan = (void *)object;
 299         struct nouveau_gpuobj *ramfc = base->ramfc;
 300         u32 chid = chan->base.chid;
 301         int ret;
 302
 303         ret = nouveau_fifo_channel_init(&chan->base);
 304         if (ret)
 305                 return ret;
 306
 307         nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12);
 308         nv50_fifo_playlist_update(priv);
 309         return 0;
 310 }
 311
 312 int
 313 nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 314 {
 315         struct nv50_fifo_priv *priv = (void *)object->engine;
 316         struct nv50_fifo_chan *chan = (void *)object;
 317         u32 chid = chan->base.chid;
 318
 319         /* remove channel from playlist, fifo will unload context */
 320         nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000);
 321         nv50_fifo_playlist_update(priv);
 322         nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000);
 323
 324         return nouveau_fifo_channel_fini(&chan->base, suspend);
 325 }
 326
 327 static struct nouveau_ofuncs
 328 nv50_fifo_ofuncs_dma = {
 329         .ctor = nv50_fifo_chan_ctor_dma,
 330         .dtor = nv50_fifo_chan_dtor,
 331         .init = nv50_fifo_chan_init,
 332         .fini = nv50_fifo_chan_fini,
 333         .rd32 = _nouveau_fifo_channel_rd32,
 334         .wr32 = _nouveau_fifo_channel_wr32,
 335 };
 336
 337 static struct nouveau_ofuncs
 338 nv50_fifo_ofuncs_ind = {
 339         .ctor = nv50_fifo_chan_ctor_ind,
 340         .dtor = nv50_fifo_chan_dtor,
 341         .init = nv50_fifo_chan_init,
 342         .fini = nv50_fifo_chan_fini,
 343         .rd32 = _nouveau_fifo_channel_rd32,
 344         .wr32 = _nouveau_fifo_channel_wr32,
 345 };
 346
 347 static struct nouveau_oclass
 348 nv50_fifo_sclass[] = {
 349         { 0x506e, &nv50_fifo_ofuncs_dma },
 350         { 0x506f, &nv50_fifo_ofuncs_ind },
 351         {}
 352 };
 353
 354 /*******************************************************************************
 355  * FIFO context - basically just the instmem reserved for the channel
 356  ******************************************************************************/
 357
 358 static int
 359 nv50_fifo_context_ctor(struct nouveau_object *parent,
 360                        struct nouveau_object *engine,
 361                        struct nouveau_oclass *oclass, void *data, u32 size,
 362                        struct nouveau_object **pobject)
 363 {
 364         struct nv50_fifo_base *base;
 365         int ret;
 366
 367         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 368                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 369         *pobject = nv_object(base);
 370         if (ret)
 371                 return ret;
 372
 373         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0200, 0x1000,
 374                                  NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 375         if (ret)
 376                 return ret;
 377
 378         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x1200, 0,
 379                                  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 380         if (ret)
 381                 return ret;
 382
 383         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x4000, 0, 0,
 384                                 &base->pgd);
 385         if (ret)
 386                 return ret;
 387
 388         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 389         if (ret)
 390                 return ret;
 391
 392         return 0;
 393 }
 394
 395 void
 396 nv50_fifo_context_dtor(struct nouveau_object *object)
 397 {
 398         struct nv50_fifo_base *base = (void *)object;
 399         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 400         nouveau_gpuobj_ref(NULL, &base->pgd);
 401         nouveau_gpuobj_ref(NULL, &base->eng);
 402         nouveau_gpuobj_ref(NULL, &base->ramfc);
 403         nouveau_gpuobj_ref(NULL, &base->cache);
 404         nouveau_fifo_context_destroy(&base->base);
 405 }
 406
 407 static struct nouveau_oclass
 408 nv50_fifo_cclass = {
 409         .handle = NV_ENGCTX(FIFO, 0x50),
 410         .ofuncs = &(struct nouveau_ofuncs) {
 411                 .ctor = nv50_fifo_context_ctor,
 412                 .dtor = nv50_fifo_context_dtor,
 413                 .init = _nouveau_fifo_context_init,
 414                 .fini = _nouveau_fifo_context_fini,
 415                 .rd32 = _nouveau_fifo_context_rd32,
 416                 .wr32 = _nouveau_fifo_context_wr32,
 417         },
 418 };
 419
 420 /*******************************************************************************
 421  * PFIFO engine
 422  ******************************************************************************/
 423
 424 static int
 425 nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 426                struct nouveau_oclass *oclass, void *data, u32 size,
 427                struct nouveau_object **pobject)
 428 {
 429         struct nv50_fifo_priv *priv;
 430         int ret;
 431
 432         ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
 433         *pobject = nv_object(priv);
 434         if (ret)
 435                 return ret;
 436
 437         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 438                                 &priv->playlist[0]);
 439         if (ret)
 440                 return ret;
 441
 442         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 443                                 &priv->playlist[1]);
 444         if (ret)
 445                 return ret;
 446
 447         nv_subdev(priv)->unit = 0x00000100;
 448         nv_subdev(priv)->intr = nv04_fifo_intr;
 449         nv_engine(priv)->cclass = &nv50_fifo_cclass;
 450         nv_engine(priv)->sclass = nv50_fifo_sclass;
 451         return 0;
 452 }
 453
 454 void
 455 nv50_fifo_dtor(struct nouveau_object *object)
 456 {
 457         struct nv50_fifo_priv *priv = (void *)object;
 458
 459         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 460         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 461
 462         nouveau_fifo_destroy(&priv->base);
 463 }
 464
 465 int
 466 nv50_fifo_init(struct nouveau_object *object)
 467 {
 468         struct nv50_fifo_priv *priv = (void *)object;
 469         int ret, i;
 470
 471         ret = nouveau_fifo_init(&priv->base);
 472         if (ret)
 473                 return ret;
 474
 475         nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
 476         nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
 477         nv_wr32(priv, 0x00250c, 0x6f3cfc34);
 478         nv_wr32(priv, 0x002044, 0x01003fff);
 479
 480         nv_wr32(priv, 0x002100, 0xffffffff);
 481         nv_wr32(priv, 0x002140, 0xffffffff);
 482
 483         for (i = 0; i < 128; i++)
 484                 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
 485         nv50_fifo_playlist_update(priv);
 486
 487         nv_wr32(priv, 0x003200, 0x00000001);
 488         nv_wr32(priv, 0x003250, 0x00000001);
 489         nv_wr32(priv, 0x002500, 0x00000001);
 490         return 0;
 491 }
 492
 493 struct nouveau_oclass
 494 nv50_fifo_oclass = {
 495         .handle = NV_ENGINE(FIFO, 0x50),
 496         .ofuncs = &(struct nouveau_ofuncs) {
 497                 .ctor = nv50_fifo_ctor,
 498                 .dtor = nv50_fifo_dtor,
 499                 .init = nv50_fifo_init,
 500                 .fini = _nouveau_fifo_fini,
 501         },
 502 };