drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/class.h>
  31 #include <core/math.h>
  32 #include <core/enum.h>
  33
  34 #include <subdev/timer.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/vm.h>
  37
  38 #include <engine/dmaobj.h>
  39 #include <engine/fifo.h>
  40
  41 struct nvc0_fifo_priv {
  42         struct nouveau_fifo base;
  43         struct nouveau_gpuobj *playlist[2];
  44         int cur_playlist;
  45         struct {
  46                 struct nouveau_gpuobj *mem;
  47                 struct nouveau_vma bar;
  48         } user;
  49         int spoon_nr;
  50 };
  51
  52 struct nvc0_fifo_base {
  53         struct nouveau_fifo_base base;
  54         struct nouveau_gpuobj *pgd;
  55         struct nouveau_vm *vm;
  56 };
  57
  58 struct nvc0_fifo_chan {
  59         struct nouveau_fifo_chan base;
  60 };
  61
  62 /*******************************************************************************
  63  * FIFO channel objects
  64  ******************************************************************************/
  65
  66 static void
  67 nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv)
  68 {
  69         struct nouveau_bar *bar = nouveau_bar(priv);
  70         struct nouveau_gpuobj *cur;
  71         int i, p;
  72
  73         cur = priv->playlist[priv->cur_playlist];
  74         priv->cur_playlist = !priv->cur_playlist;
  75
  76         for (i = 0, p = 0; i < 128; i++) {
  77                 if (!(nv_rd32(priv, 0x003004 + (i * 8)) & 1))
  78                         continue;
  79                 nv_wo32(cur, p + 0, i);
  80                 nv_wo32(cur, p + 4, 0x00000004);
  81                 p += 8;
  82         }
  83         bar->flush(bar);
  84
  85         nv_wr32(priv, 0x002270, cur->addr >> 12);
  86         nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
  87         if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000))
  88                 nv_error(priv, "playlist update failed\n");
  89 }
  90
  91 static int
  92 nvc0_fifo_context_attach(struct nouveau_object *parent,
  93                          struct nouveau_object *object)
  94 {
  95         struct nouveau_bar *bar = nouveau_bar(parent);
  96         struct nvc0_fifo_base *base = (void *)parent->parent;
  97         struct nouveau_engctx *ectx = (void *)object;
  98         u32 addr;
  99         int ret;
 100
 101         switch (nv_engidx(object->engine)) {
 102         case NVDEV_ENGINE_SW   : return 0;
 103         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 104         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 105         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 106         default:
 107                 return -EINVAL;
 108         }
 109
 110         if (!ectx->vma.node) {
 111                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 112                                             NV_MEM_ACCESS_RW, &ectx->vma);
 113                 if (ret)
 114                         return ret;
 115
 116                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 117         }
 118
 119         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 120         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 121         bar->flush(bar);
 122         return 0;
 123 }
 124
 125 static int
 126 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 127                          struct nouveau_object *object)
 128 {
 129         struct nouveau_bar *bar = nouveau_bar(parent);
 130         struct nvc0_fifo_priv *priv = (void *)parent->engine;
 131         struct nvc0_fifo_base *base = (void *)parent->parent;
 132         struct nvc0_fifo_chan *chan = (void *)parent;
 133         u32 addr;
 134
 135         switch (nv_engidx(object->engine)) {
 136         case NVDEV_ENGINE_SW   : return 0;
 137         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 138         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 139         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 140         default:
 141                 return -EINVAL;
 142         }
 143
 144         nv_wo32(base, addr + 0x00, 0x00000000);
 145         nv_wo32(base, addr + 0x04, 0x00000000);
 146         bar->flush(bar);
 147
 148         nv_wr32(priv, 0x002634, chan->base.chid);
 149         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 150                 nv_error(priv, "channel %d kick timeout\n", chan->base.chid);
 151                 if (suspend)
 152                         return -EBUSY;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int
 159 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
 160                     struct nouveau_object *engine,
 161                     struct nouveau_oclass *oclass, void *data, u32 size,
 162                     struct nouveau_object **pobject)
 163 {
 164         struct nouveau_bar *bar = nouveau_bar(parent);
 165         struct nvc0_fifo_priv *priv = (void *)engine;
 166         struct nvc0_fifo_base *base = (void *)parent;
 167         struct nvc0_fifo_chan *chan;
 168         struct nv50_channel_ind_class *args = data;
 169         u64 usermem, ioffset, ilength;
 170         int ret, i;
 171
 172         if (size < sizeof(*args))
 173                 return -EINVAL;
 174
 175         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 176                                           priv->user.bar.offset, 0x1000,
 177                                           args->pushbuf,
 178                                           (1 << NVDEV_ENGINE_SW) |
 179                                           (1 << NVDEV_ENGINE_GR) |
 180                                           (1 << NVDEV_ENGINE_COPY0) |
 181                                           (1 << NVDEV_ENGINE_COPY1), &chan);
 182         *pobject = nv_object(chan);
 183         if (ret)
 184                 return ret;
 185
 186         nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
 187         nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
 188
 189         usermem = chan->base.chid * 0x1000;
 190         ioffset = args->ioffset;
 191         ilength = log2i(args->ilength / 8);
 192
 193         for (i = 0; i < 0x1000; i += 4)
 194                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 195
 196         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 197         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 198         nv_wo32(base, 0x10, 0x0000face);
 199         nv_wo32(base, 0x30, 0xfffff902);
 200         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 201         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 202         nv_wo32(base, 0x54, 0x00000002);
 203         nv_wo32(base, 0x84, 0x20400000);
 204         nv_wo32(base, 0x94, 0x30000001);
 205         nv_wo32(base, 0x9c, 0x00000100);
 206         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 207         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 208         nv_wo32(base, 0xac, 0x0000001f);
 209         nv_wo32(base, 0xb8, 0xf8000000);
 210         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 211         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 212         bar->flush(bar);
 213         return 0;
 214 }
 215
 216 static int
 217 nvc0_fifo_chan_init(struct nouveau_object *object)
 218 {
 219         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 220         struct nvc0_fifo_priv *priv = (void *)object->engine;
 221         struct nvc0_fifo_chan *chan = (void *)object;
 222         u32 chid = chan->base.chid;
 223         int ret;
 224
 225         ret = nouveau_fifo_channel_init(&chan->base);
 226         if (ret)
 227                 return ret;
 228
 229         nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 230         nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
 231         nvc0_fifo_playlist_update(priv);
 232         return 0;
 233 }
 234
 235 static int
 236 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 237 {
 238         struct nvc0_fifo_priv *priv = (void *)object->engine;
 239         struct nvc0_fifo_chan *chan = (void *)object;
 240         u32 chid = chan->base.chid;
 241
 242         nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 243         nvc0_fifo_playlist_update(priv);
 244         nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
 245
 246         return nouveau_fifo_channel_fini(&chan->base, suspend);
 247 }
 248
 249 static struct nouveau_ofuncs
 250 nvc0_fifo_ofuncs = {
 251         .ctor = nvc0_fifo_chan_ctor,
 252         .dtor = _nouveau_fifo_channel_dtor,
 253         .init = nvc0_fifo_chan_init,
 254         .fini = nvc0_fifo_chan_fini,
 255         .rd32 = _nouveau_fifo_channel_rd32,
 256         .wr32 = _nouveau_fifo_channel_wr32,
 257 };
 258
 259 static struct nouveau_oclass
 260 nvc0_fifo_sclass[] = {
 261         { 0x906f, &nvc0_fifo_ofuncs },
 262         {}
 263 };
 264
 265 /*******************************************************************************
 266  * FIFO context - instmem heap and vm setup
 267  ******************************************************************************/
 268
 269 static int
 270 nvc0_fifo_context_ctor(struct nouveau_object *parent,
 271                        struct nouveau_object *engine,
 272                        struct nouveau_oclass *oclass, void *data, u32 size,
 273                        struct nouveau_object **pobject)
 274 {
 275         struct nvc0_fifo_base *base;
 276         int ret;
 277
 278         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 279                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 280                                           NVOBJ_FLAG_HEAP, &base);
 281         *pobject = nv_object(base);
 282         if (ret)
 283                 return ret;
 284
 285         ret = nouveau_gpuobj_new(parent, NULL, 0x10000, 0x1000, 0, &base->pgd);
 286         if (ret)
 287                 return ret;
 288
 289         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 290         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 291         nv_wo32(base, 0x0208, 0xffffffff);
 292         nv_wo32(base, 0x020c, 0x000000ff);
 293
 294         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 295         if (ret)
 296                 return ret;
 297
 298         return 0;
 299 }
 300
 301 static void
 302 nvc0_fifo_context_dtor(struct nouveau_object *object)
 303 {
 304         struct nvc0_fifo_base *base = (void *)object;
 305         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 306         nouveau_gpuobj_ref(NULL, &base->pgd);
 307         nouveau_fifo_context_destroy(&base->base);
 308 }
 309
 310 static struct nouveau_oclass
 311 nvc0_fifo_cclass = {
 312         .handle = NV_ENGCTX(FIFO, 0xc0),
 313         .ofuncs = &(struct nouveau_ofuncs) {
 314                 .ctor = nvc0_fifo_context_ctor,
 315                 .dtor = nvc0_fifo_context_dtor,
 316                 .init = _nouveau_fifo_context_init,
 317                 .fini = _nouveau_fifo_context_fini,
 318                 .rd32 = _nouveau_fifo_context_rd32,
 319                 .wr32 = _nouveau_fifo_context_wr32,
 320         },
 321 };
 322
 323 /*******************************************************************************
 324  * PFIFO engine
 325  ******************************************************************************/
 326
 327 struct nouveau_enum nvc0_fifo_fault_unit[] = {
 328         { 0x00, "PGRAPH" },
 329         { 0x03, "PEEPHOLE" },
 330         { 0x04, "BAR1" },
 331         { 0x05, "BAR3" },
 332         { 0x07, "PFIFO" },
 333         { 0x10, "PBSP" },
 334         { 0x11, "PPPP" },
 335         { 0x13, "PCOUNTER" },
 336         { 0x14, "PVP" },
 337         { 0x15, "PCOPY0" },
 338         { 0x16, "PCOPY1" },
 339         { 0x17, "PDAEMON" },
 340         {}
 341 };
 342
 343 struct nouveau_enum nvc0_fifo_fault_reason[] = {
 344         { 0x00, "PT_NOT_PRESENT" },
 345         { 0x01, "PT_TOO_SHORT" },
 346         { 0x02, "PAGE_NOT_PRESENT" },
 347         { 0x03, "VM_LIMIT_EXCEEDED" },
 348         { 0x04, "NO_CHANNEL" },
 349         { 0x05, "PAGE_SYSTEM_ONLY" },
 350         { 0x06, "PAGE_READ_ONLY" },
 351         { 0x0a, "COMPRESSED_SYSRAM" },
 352         { 0x0c, "INVALID_STORAGE_TYPE" },
 353         {}
 354 };
 355
 356 struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
 357         { 0x01, "PCOPY0" },
 358         { 0x02, "PCOPY1" },
 359         { 0x04, "DISPATCH" },
 360         { 0x05, "CTXCTL" },
 361         { 0x06, "PFIFO" },
 362         { 0x07, "BAR_READ" },
 363         { 0x08, "BAR_WRITE" },
 364         { 0x0b, "PVP" },
 365         { 0x0c, "PPPP" },
 366         { 0x0d, "PBSP" },
 367         { 0x11, "PCOUNTER" },
 368         { 0x12, "PDAEMON" },
 369         { 0x14, "CCACHE" },
 370         { 0x15, "CCACHE_POST" },
 371         {}
 372 };
 373
 374 struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
 375         { 0x01, "TEX" },
 376         { 0x0c, "ESETUP" },
 377         { 0x0e, "CTXCTL" },
 378         { 0x0f, "PROP" },
 379         {}
 380 };
 381
 382 struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
 383 /*      { 0x00008000, "" }      seen with null ib push */
 384         { 0x00200000, "ILLEGAL_MTHD" },
 385         { 0x00800000, "EMPTY_SUBC" },
 386         {}
 387 };
 388
 389 static void
 390 nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
 391 {
 392         u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
 393         u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
 394         u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
 395         u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
 396         u32 client = (stat & 0x00001f00) >> 8;
 397
 398         nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ?
 399                  "write" : "read", (u64)vahi << 32 | valo);
 400         nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
 401         printk("] from ");
 402         nouveau_enum_print(nvc0_fifo_fault_unit, unit);
 403         if (stat & 0x00000040) {
 404                 printk("/");
 405                 nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
 406         } else {
 407                 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
 408                 nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
 409         }
 410         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 411 }
 412
 413 static int
 414 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 415 {
 416         struct nvc0_fifo_chan *chan = NULL;
 417         struct nouveau_handle *bind;
 418         unsigned long flags;
 419         int ret = -EINVAL;
 420
 421         spin_lock_irqsave(&priv->base.lock, flags);
 422         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 423                 chan = (void *)priv->base.channel[chid];
 424         if (unlikely(!chan))
 425                 goto out;
 426
 427         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 428         if (likely(bind)) {
 429                 if (!mthd || !nv_call(bind->object, mthd, data))
 430                         ret = 0;
 431                 nouveau_namedb_put(bind);
 432         }
 433
 434 out:
 435         spin_unlock_irqrestore(&priv->base.lock, flags);
 436         return ret;
 437 }
 438
 439 static void
 440 nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
 441 {
 442         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 443         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 444         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 445         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
 446         u32 subc = (addr & 0x00070000) >> 16;
 447         u32 mthd = (addr & 0x00003ffc);
 448         u32 show = stat;
 449
 450         if (stat & 0x00200000) {
 451                 if (mthd == 0x0054) {
 452                         if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
 453                                 show &= ~0x00200000;
 454                 }
 455         }
 456
 457         if (stat & 0x00800000) {
 458                 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
 459                         show &= ~0x00800000;
 460         }
 461
 462         if (show) {
 463                 nv_error(priv, "SUBFIFO%d:", unit);
 464                 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
 465                 printk("\n");
 466                 nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
 467                                "data 0x%08x\n",
 468                          unit, chid, subc, mthd, data);
 469         }
 470
 471         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 472         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 473 }
 474
 475 static void
 476 nvc0_fifo_intr(struct nouveau_subdev *subdev)
 477 {
 478         struct nvc0_fifo_priv *priv = (void *)subdev;
 479         u32 mask = nv_rd32(priv, 0x002140);
 480         u32 stat = nv_rd32(priv, 0x002100) & mask;
 481
 482         if (stat & 0x00000100) {
 483                 nv_info(priv, "unknown status 0x00000100\n");
 484                 nv_wr32(priv, 0x002100, 0x00000100);
 485                 stat &= ~0x00000100;
 486         }
 487
 488         if (stat & 0x10000000) {
 489                 u32 units = nv_rd32(priv, 0x00259c);
 490                 u32 u = units;
 491
 492                 while (u) {
 493                         int i = ffs(u) - 1;
 494                         nvc0_fifo_isr_vm_fault(priv, i);
 495                         u &= ~(1 << i);
 496                 }
 497
 498                 nv_wr32(priv, 0x00259c, units);
 499                 stat &= ~0x10000000;
 500         }
 501
 502         if (stat & 0x20000000) {
 503                 u32 units = nv_rd32(priv, 0x0025a0);
 504                 u32 u = units;
 505
 506                 while (u) {
 507                         int i = ffs(u) - 1;
 508                         nvc0_fifo_isr_subfifo_intr(priv, i);
 509                         u &= ~(1 << i);
 510                 }
 511
 512                 nv_wr32(priv, 0x0025a0, units);
 513                 stat &= ~0x20000000;
 514         }
 515
 516         if (stat & 0x40000000) {
 517                 nv_warn(priv, "unknown status 0x40000000\n");
 518                 nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
 519                 stat &= ~0x40000000;
 520         }
 521
 522         if (stat) {
 523                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 524                 nv_wr32(priv, 0x002100, stat);
 525                 nv_wr32(priv, 0x002140, 0);
 526         }
 527 }
 528
 529 static int
 530 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 531                struct nouveau_oclass *oclass, void *data, u32 size,
 532                struct nouveau_object **pobject)
 533 {
 534         struct nvc0_fifo_priv *priv;
 535         int ret;
 536
 537         ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
 538         *pobject = nv_object(priv);
 539         if (ret)
 540                 return ret;
 541
 542         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0x1000, 0,
 543                                 &priv->playlist[0]);
 544         if (ret)
 545                 return ret;
 546
 547         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0x1000, 0,
 548                                 &priv->playlist[1]);
 549         if (ret)
 550                 return ret;
 551
 552         ret = nouveau_gpuobj_new(parent, NULL, 128 * 0x1000, 0x1000, 0,
 553                                 &priv->user.mem);
 554         if (ret)
 555                 return ret;
 556
 557         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 558                                 &priv->user.bar);
 559         if (ret)
 560                 return ret;
 561
 562         nv_subdev(priv)->unit = 0x00000100;
 563         nv_subdev(priv)->intr = nvc0_fifo_intr;
 564         nv_engine(priv)->cclass = &nvc0_fifo_cclass;
 565         nv_engine(priv)->sclass = nvc0_fifo_sclass;
 566         return 0;
 567 }
 568
 569 static void
 570 nvc0_fifo_dtor(struct nouveau_object *object)
 571 {
 572         struct nvc0_fifo_priv *priv = (void *)object;
 573
 574         nouveau_gpuobj_unmap(&priv->user.bar);
 575         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 576         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 577         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 578
 579         nouveau_fifo_destroy(&priv->base);
 580 }
 581
 582 static int
 583 nvc0_fifo_init(struct nouveau_object *object)
 584 {
 585         struct nvc0_fifo_priv *priv = (void *)object;
 586         int ret, i;
 587
 588         ret = nouveau_fifo_init(&priv->base);
 589         if (ret)
 590                 return ret;
 591
 592         nv_wr32(priv, 0x000204, 0xffffffff);
 593         nv_wr32(priv, 0x002204, 0xffffffff);
 594
 595         priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
 596         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 597
 598         /* assign engines to subfifos */
 599         if (priv->spoon_nr >= 3) {
 600                 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
 601                 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
 602                 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
 603                 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
 604                 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
 605                 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
 606         }
 607
 608         /* PSUBFIFO[n] */
 609         for (i = 0; i < priv->spoon_nr; i++) {
 610                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 611                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 612                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 613         }
 614
 615         nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
 616         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 617
 618         nv_wr32(priv, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
 619         nv_wr32(priv, 0x002100, 0xffffffff);
 620         nv_wr32(priv, 0x002140, 0xbfffffff);
 621         return 0;
 622 }
 623
 624 struct nouveau_oclass
 625 nvc0_fifo_oclass = {
 626         .handle = NV_ENGINE(FIFO, 0xc0),
 627         .ofuncs = &(struct nouveau_ofuncs) {
 628                 .ctor = nvc0_fifo_ctor,
 629                 .dtor = nvc0_fifo_dtor,
 630                 .init = nvc0_fifo_init,
 631                 .fini = _nouveau_fifo_fini,
 632         },
 633 };