drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25
  26 #include "priv.h"
  27
  28 struct nv40_therm_priv {
  29         struct nouveau_therm_priv base;
  30 };
  31
  32 static int
  33 nv40_sensor_setup(struct nouveau_therm *therm)
  34 {
  35         struct nouveau_device *device = nv_device(therm);
  36
  37         /* enable ADC readout and disable the ALARM threshold */
  38         if (device->chipset >= 0x46) {
  39                 nv_mask(therm, 0x15b8, 0x80000000, 0);
  40                 nv_wr32(therm, 0x15b0, 0x80003fff);
  41                 mdelay(10); /* wait for the temperature to stabilize */
  42                 return nv_rd32(therm, 0x15b4) & 0x3fff;
  43         } else {
  44                 nv_wr32(therm, 0x15b0, 0xff);
  45                 return nv_rd32(therm, 0x15b4) & 0xff;
  46         }
  47 }
  48
  49 static int
  50 nv40_temp_get(struct nouveau_therm *therm)
  51 {
  52         struct nouveau_therm_priv *priv = (void *)therm;
  53         struct nouveau_device *device = nv_device(therm);
  54         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
  55         int core_temp;
  56
  57         if (device->chipset >= 0x46) {
  58                 nv_wr32(therm, 0x15b0, 0x80003fff);
  59                 core_temp = nv_rd32(therm, 0x15b4) & 0x3fff;
  60         } else {
  61                 nv_wr32(therm, 0x15b0, 0xff);
  62                 core_temp = nv_rd32(therm, 0x15b4) & 0xff;
  63         }
  64
  65         /* Setup the sensor if the temperature is 0 */
  66         if (core_temp == 0)
  67                 core_temp = nv40_sensor_setup(therm);
  68
  69         if (sensor->slope_div == 0)
  70                 sensor->slope_div = 1;
  71         if (sensor->offset_den == 0)
  72                 sensor->offset_den = 1;
  73         if (sensor->slope_mult < 1)
  74                 sensor->slope_mult = 1;
  75
  76         core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
  77         core_temp = core_temp + sensor->offset_num / sensor->offset_den;
  78         core_temp = core_temp + sensor->offset_constant - 8;
  79
  80         return core_temp;
  81 }
  82
  83 static int
  84 nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable)
  85 {
  86         u32 mask = enable ? 0x80000000 : 0x0000000;
  87         if      (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);
  88         else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask);
  89         else {
  90                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
  91                 return -ENODEV;
  92         }
  93         return 0;
  94 }
  95
  96 static int
  97 nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty)
  98 {
  99         if (line == 2) {
 100                 u32 reg = nv_rd32(therm, 0x0010f0);
 101                 if (reg & 0x80000000) {
 102                         *duty = (reg & 0x7fff0000) >> 16;
 103                         *divs = (reg & 0x00007fff);
 104                         return 0;
 105                 }
 106         } else
 107         if (line == 9) {
 108                 u32 reg = nv_rd32(therm, 0x0015f4);
 109                 if (reg & 0x80000000) {
 110                         *divs = nv_rd32(therm, 0x0015f8);
 111                         *duty = (reg & 0x7fffffff);
 112                         return 0;
 113                 }
 114         } else {
 115                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 116                 return -ENODEV;
 117         }
 118
 119         return -EINVAL;
 120 }
 121
 122 static int
 123 nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty)
 124 {
 125         if (line == 2) {
 126                 nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
 127         } else
 128         if (line == 9) {
 129                 nv_wr32(therm, 0x0015f8, divs);
 130                 nv_mask(therm, 0x0015f4, 0x7fffffff, duty);
 131         } else {
 132                 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
 133                 return -ENODEV;
 134         }
 135
 136         return 0;
 137 }
 138
 139 static void
 140 nv40_therm_intr(struct nouveau_subdev *subdev)
 141 {
 142         struct nouveau_therm *therm = nouveau_therm(subdev);
 143         uint32_t stat = nv_rd32(therm, 0x1100);
 144
 145         /* traitement */
 146
 147         /* ack all IRQs */
 148         nv_wr32(therm, 0x1100, 0x70000);
 149
 150         nv_error(therm, "THERM received an IRQ: stat = %x\n", stat);
 151 }
 152
 153 static int
 154 nv40_therm_ctor(struct nouveau_object *parent,
 155                 struct nouveau_object *engine,
 156                 struct nouveau_oclass *oclass, void *data, u32 size,
 157                 struct nouveau_object **pobject)
 158 {
 159         struct nv40_therm_priv *priv;
 160         int ret;
 161
 162         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 163         *pobject = nv_object(priv);
 164         if (ret)
 165                 return ret;
 166
 167         priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl;
 168         priv->base.base.pwm_get = nv40_fan_pwm_get;
 169         priv->base.base.pwm_set = nv40_fan_pwm_set;
 170         priv->base.base.temp_get = nv40_temp_get;
 171         priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling;
 172         nv_subdev(priv)->intr = nv40_therm_intr;
 173         return nouveau_therm_preinit(&priv->base.base);
 174 }
 175
 176 static int
 177 nv40_therm_init(struct nouveau_object *object)
 178 {
 179         struct nouveau_therm *therm = (void *)object;
 180
 181         nv40_sensor_setup(therm);
 182
 183         return _nouveau_therm_init(object);
 184 }
 185
 186 struct nouveau_oclass
 187 nv40_therm_oclass = {
 188         .handle = NV_SUBDEV(THERM, 0x40),
 189         .ofuncs = &(struct nouveau_ofuncs) {
 190                 .ctor = nv40_therm_ctor,
 191                 .dtor = _nouveau_therm_dtor,
 192                 .init = nv40_therm_init,
 193                 .fini = _nouveau_therm_fini,
 194         },
 195 };