drivers/gpu/drm/nouveau/include/nvif/class.h

   1 #ifndef __NVIF_CLASS_H__
   2 #define __NVIF_CLASS_H__
   3
   4 /*******************************************************************************
   5  * class identifiers
   6  ******************************************************************************/
   7
   8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
   9 #define NV_DEVICE                                                    0x00000080
  10
  11 #define NV_DMA_FROM_MEMORY                                           0x00000002
  12 #define NV_DMA_TO_MEMORY                                             0x00000003
  13 #define NV_DMA_IN_MEMORY                                             0x0000003d
  14
  15 #define FERMI_TWOD_A                                                 0x0000902d
  16
  17 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
  18
  19 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
  20 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
  21
  22 #define NV04_DISP                                                    0x00000046
  23
  24 #define NV03_CHANNEL_DMA                                             0x0000006b
  25 #define NV10_CHANNEL_DMA                                             0x0000006e
  26 #define NV17_CHANNEL_DMA                                             0x0000176e
  27 #define NV40_CHANNEL_DMA                                             0x0000406e
  28 #define NV50_CHANNEL_DMA                                             0x0000506e
  29 #define G82_CHANNEL_DMA                                              0x0000826e
  30
  31 #define NV50_CHANNEL_GPFIFO                                          0x0000506f
  32 #define G82_CHANNEL_GPFIFO                                           0x0000826f
  33 #define FERMI_CHANNEL_GPFIFO                                         0x0000906f
  34 #define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
  35 #define MAXWELL_CHANNEL_GPFIFO_A                                     0x0000b06f
  36
  37 #define NV50_DISP                                                    0x00005070
  38 #define G82_DISP                                                     0x00008270
  39 #define GT200_DISP                                                   0x00008370
  40 #define GT214_DISP                                                   0x00008570
  41 #define GT206_DISP                                                   0x00008870
  42 #define GF110_DISP                                                   0x00009070
  43 #define GK104_DISP                                                   0x00009170
  44 #define GK110_DISP                                                   0x00009270
  45 #define GM107_DISP                                                   0x00009470
  46 #define GM204_DISP                                                   0x00009570
  47
  48 #define NV50_DISP_CURSOR                                             0x0000507a
  49 #define G82_DISP_CURSOR                                              0x0000827a
  50 #define GT214_DISP_CURSOR                                            0x0000857a
  51 #define GF110_DISP_CURSOR                                            0x0000907a
  52 #define GK104_DISP_CURSOR                                            0x0000917a
  53
  54 #define NV50_DISP_OVERLAY                                            0x0000507b
  55 #define G82_DISP_OVERLAY                                             0x0000827b
  56 #define GT214_DISP_OVERLAY                                           0x0000857b
  57 #define GF110_DISP_OVERLAY                                           0x0000907b
  58 #define GK104_DISP_OVERLAY                                           0x0000917b
  59
  60 #define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
  61 #define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
  62 #define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
  63 #define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
  64 #define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
  65 #define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
  66 #define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c
  67
  68 #define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
  69 #define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
  70 #define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
  71 #define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
  72 #define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
  73 #define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
  74 #define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
  75 #define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
  76 #define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
  77 #define GM204_DISP_CORE_CHANNEL_DMA                                  0x0000957d
  78
  79 #define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
  80 #define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
  81 #define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
  82 #define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
  83 #define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
  84 #define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e
  85
  86 #define FERMI_A                                                      0x00009097
  87 #define FERMI_B                                                      0x00009197
  88 #define FERMI_C                                                      0x00009297
  89
  90 #define KEPLER_A                                                     0x0000a097
  91 #define KEPLER_B                                                     0x0000a197
  92 #define KEPLER_C                                                     0x0000a297
  93
  94 #define MAXWELL_A                                                    0x0000b097
  95 #define MAXWELL_B                                                    0x0000b197
  96
  97 #define FERMI_COMPUTE_A                                              0x000090c0
  98 #define FERMI_COMPUTE_B                                              0x000091c0
  99
 100 #define KEPLER_COMPUTE_A                                             0x0000a0c0
 101 #define KEPLER_COMPUTE_B                                             0x0000a1c0
 102
 103 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
 104 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
 105
 106
 107 /*******************************************************************************
 108  * client
 109  ******************************************************************************/
 110
 111 #define NV_CLIENT_DEVLIST                                                  0x00
 112
 113 struct nv_client_devlist_v0 {
 114         __u8  version;
 115         __u8  count;
 116         __u8  pad02[6];
 117         __u64 device[];
 118 };
 119
 120
 121 /*******************************************************************************
 122  * device
 123  ******************************************************************************/
 124
 125 struct nv_device_v0 {
 126         __u8  version;
 127         __u8  pad01[7];
 128         __u64 device;   /* device identifier, ~0 for client default */
 129 };
 130
 131 #define NV_DEVICE_V0_INFO                                                  0x00
 132
 133 struct nv_device_info_v0 {
 134         __u8  version;
 135 #define NV_DEVICE_INFO_V0_IGP                                              0x00
 136 #define NV_DEVICE_INFO_V0_PCI                                              0x01
 137 #define NV_DEVICE_INFO_V0_AGP                                              0x02
 138 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
 139 #define NV_DEVICE_INFO_V0_SOC                                              0x04
 140         __u8  platform;
 141         __u16 chipset;  /* from NV_PMC_BOOT_0 */
 142         __u8  revision; /* from NV_PMC_BOOT_0 */
 143 #define NV_DEVICE_INFO_V0_TNT                                              0x01
 144 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
 145 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
 146 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
 147 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
 148 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
 149 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
 150 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
 151 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
 152         __u8  family;
 153         __u8  pad06[2];
 154         __u64 ram_size;
 155         __u64 ram_user;
 156         char  chip[16];
 157         char  name[64];
 158 };
 159
 160
 161 /*******************************************************************************
 162  * context dma
 163  ******************************************************************************/
 164
 165 struct nv_dma_v0 {
 166         __u8  version;
 167 #define NV_DMA_V0_TARGET_VM                                                0x00
 168 #define NV_DMA_V0_TARGET_VRAM                                              0x01
 169 #define NV_DMA_V0_TARGET_PCI                                               0x02
 170 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
 171 #define NV_DMA_V0_TARGET_AGP                                               0x04
 172         __u8  target;
 173 #define NV_DMA_V0_ACCESS_VM                                                0x00
 174 #define NV_DMA_V0_ACCESS_RD                                                0x01
 175 #define NV_DMA_V0_ACCESS_WR                                                0x02
 176 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
 177         __u8  access;
 178         __u8  pad03[5];
 179         __u64 start;
 180         __u64 limit;
 181         /* ... chipset-specific class data */
 182 };
 183
 184 struct nv50_dma_v0 {
 185         __u8  version;
 186 #define NV50_DMA_V0_PRIV_VM                                                0x00
 187 #define NV50_DMA_V0_PRIV_US                                                0x01
 188 #define NV50_DMA_V0_PRIV__S                                                0x02
 189         __u8  priv;
 190 #define NV50_DMA_V0_PART_VM                                                0x00
 191 #define NV50_DMA_V0_PART_256                                               0x01
 192 #define NV50_DMA_V0_PART_1KB                                               0x02
 193         __u8  part;
 194 #define NV50_DMA_V0_COMP_NONE                                              0x00
 195 #define NV50_DMA_V0_COMP_1                                                 0x01
 196 #define NV50_DMA_V0_COMP_2                                                 0x02
 197 #define NV50_DMA_V0_COMP_VM                                                0x03
 198         __u8  comp;
 199 #define NV50_DMA_V0_KIND_PITCH                                             0x00
 200 #define NV50_DMA_V0_KIND_VM                                                0x7f
 201         __u8  kind;
 202         __u8  pad05[3];
 203 };
 204
 205 struct gf100_dma_v0 {
 206         __u8  version;
 207 #define GF100_DMA_V0_PRIV_VM                                               0x00
 208 #define GF100_DMA_V0_PRIV_US                                               0x01
 209 #define GF100_DMA_V0_PRIV__S                                               0x02
 210         __u8  priv;
 211 #define GF100_DMA_V0_KIND_PITCH                                            0x00
 212 #define GF100_DMA_V0_KIND_VM                                               0xff
 213         __u8  kind;
 214         __u8  pad03[5];
 215 };
 216
 217 struct gf110_dma_v0 {
 218         __u8  version;
 219 #define GF110_DMA_V0_PAGE_LP                                               0x00
 220 #define GF110_DMA_V0_PAGE_SP                                               0x01
 221         __u8  page;
 222 #define GF110_DMA_V0_KIND_PITCH                                            0x00
 223 #define GF110_DMA_V0_KIND_VM                                               0xff
 224         __u8  kind;
 225         __u8  pad03[5];
 226 };
 227
 228
 229 /*******************************************************************************
 230  * perfmon
 231  ******************************************************************************/
 232
 233 #define NVIF_PERFMON_V0_QUERY_DOMAIN                                       0x00
 234 #define NVIF_PERFMON_V0_QUERY_SIGNAL                                       0x01
 235 #define NVIF_PERFMON_V0_QUERY_SOURCE                                       0x02
 236
 237 struct nvif_perfmon_query_domain_v0 {
 238         __u8  version;
 239         __u8  id;
 240         __u8  counter_nr;
 241         __u8  iter;
 242         __u16 signal_nr;
 243         __u8  pad05[2];
 244         char  name[64];
 245 };
 246
 247 struct nvif_perfmon_query_signal_v0 {
 248         __u8  version;
 249         __u8  domain;
 250         __u16 iter;
 251         __u8  signal;
 252         __u8  source_nr;
 253         __u8  pad05[2];
 254         char  name[64];
 255 };
 256
 257 struct nvif_perfmon_query_source_v0 {
 258         __u8  version;
 259         __u8  domain;
 260         __u8  signal;
 261         __u8  iter;
 262         __u8  pad04[4];
 263         __u32 source;
 264         __u32 mask;
 265         char  name[64];
 266 };
 267
 268
 269 /*******************************************************************************
 270  * perfdom
 271  ******************************************************************************/
 272
 273 struct nvif_perfdom_v0 {
 274         __u8  version;
 275         __u8  domain;
 276         __u8  mode;
 277         __u8  pad03[1];
 278         struct {
 279                 __u8  signal[4];
 280                 __u64 source[4][8];
 281                 __u16 logic_op;
 282         } ctr[4];
 283 };
 284
 285 #define NVIF_PERFDOM_V0_INIT                                               0x00
 286 #define NVIF_PERFDOM_V0_SAMPLE                                             0x01
 287 #define NVIF_PERFDOM_V0_READ                                               0x02
 288
 289 struct nvif_perfdom_init {
 290 };
 291
 292 struct nvif_perfdom_sample {
 293 };
 294
 295 struct nvif_perfdom_read_v0 {
 296         __u8  version;
 297         __u8  pad01[7];
 298         __u32 ctr[4];
 299         __u32 clk;
 300         __u8  pad04[4];
 301 };
 302
 303
 304 /*******************************************************************************
 305  * device control
 306  ******************************************************************************/
 307
 308 #define NVIF_CONTROL_PSTATE_INFO                                           0x00
 309 #define NVIF_CONTROL_PSTATE_ATTR                                           0x01
 310 #define NVIF_CONTROL_PSTATE_USER                                           0x02
 311
 312 struct nvif_control_pstate_info_v0 {
 313         __u8  version;
 314         __u8  count; /* out: number of power states */
 315 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
 316 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
 317         __s8  ustate_ac; /* out: target pstate index */
 318         __s8  ustate_dc; /* out: target pstate index */
 319         __s8  pwrsrc; /* out: current power source */
 320 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
 321 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
 322         __s8  pstate; /* out: current pstate index */
 323         __u8  pad06[2];
 324 };
 325
 326 struct nvif_control_pstate_attr_v0 {
 327         __u8  version;
 328 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
 329         __s8  state; /*  in: index of pstate to query
 330                       * out: pstate identifier
 331                       */
 332         __u8  index; /*  in: index of attribute to query
 333                       * out: index of next attribute, or 0 if no more
 334                       */
 335         __u8  pad03[5];
 336         __u32 min;
 337         __u32 max;
 338         char  name[32];
 339         char  unit[16];
 340 };
 341
 342 struct nvif_control_pstate_user_v0 {
 343         __u8  version;
 344 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
 345 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
 346         __s8  ustate; /*  in: pstate identifier */
 347         __s8  pwrsrc; /*  in: target power source */
 348         __u8  pad03[5];
 349 };
 350
 351
 352 /*******************************************************************************
 353  * DMA FIFO channels
 354  ******************************************************************************/
 355
 356 struct nv03_channel_dma_v0 {
 357         __u8  version;
 358         __u8  chid;
 359         __u8  pad02[2];
 360         __u32 offset;
 361         __u64 pushbuf;
 362 };
 363
 364 struct nv50_channel_dma_v0 {
 365         __u8  version;
 366         __u8  chid;
 367         __u8  pad02[6];
 368         __u64 vm;
 369         __u64 pushbuf;
 370         __u64 offset;
 371 };
 372
 373 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00
 374
 375 /*******************************************************************************
 376  * GPFIFO channels
 377  ******************************************************************************/
 378
 379 struct nv50_channel_gpfifo_v0 {
 380         __u8  version;
 381         __u8  chid;
 382         __u8  pad02[2];
 383         __u32 ilength;
 384         __u64 ioffset;
 385         __u64 pushbuf;
 386         __u64 vm;
 387 };
 388
 389 struct fermi_channel_gpfifo_v0 {
 390         __u8  version;
 391         __u8  chid;
 392         __u8  pad02[2];
 393         __u32 ilength;
 394         __u64 ioffset;
 395         __u64 vm;
 396 };
 397
 398 struct kepler_channel_gpfifo_a_v0 {
 399         __u8  version;
 400 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
 401 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
 402 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
 403 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
 404 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
 405 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
 406 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
 407         __u8  engine;
 408         __u16 chid;
 409         __u32 ilength;
 410         __u64 ioffset;
 411         __u64 vm;
 412 };
 413
 414 /*******************************************************************************
 415  * legacy display
 416  ******************************************************************************/
 417
 418 #define NV04_DISP_NTFY_VBLANK                                              0x00
 419 #define NV04_DISP_NTFY_CONN                                                0x01
 420
 421 struct nv04_disp_mthd_v0 {
 422         __u8  version;
 423 #define NV04_DISP_SCANOUTPOS                                               0x00
 424         __u8  method;
 425         __u8  head;
 426         __u8  pad03[5];
 427 };
 428
 429 struct nv04_disp_scanoutpos_v0 {
 430         __u8  version;
 431         __u8  pad01[7];
 432         __s64 time[2];
 433         __u16 vblanks;
 434         __u16 vblanke;
 435         __u16 vtotal;
 436         __u16 vline;
 437         __u16 hblanks;
 438         __u16 hblanke;
 439         __u16 htotal;
 440         __u16 hline;
 441 };
 442
 443 /*******************************************************************************
 444  * display
 445  ******************************************************************************/
 446
 447 #define NV50_DISP_MTHD                                                     0x00
 448
 449 struct nv50_disp_mthd_v0 {
 450         __u8  version;
 451 #define NV50_DISP_SCANOUTPOS                                               0x00
 452         __u8  method;
 453         __u8  head;
 454         __u8  pad03[5];
 455 };
 456
 457 struct nv50_disp_mthd_v1 {
 458         __u8  version;
 459 #define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
 460 #define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
 461 #define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
 462 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
 463 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
 464 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
 465 #define NV50_DISP_MTHD_V1_SOR_DP_PWR                                       0x24
 466 #define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
 467         __u8  method;
 468         __u16 hasht;
 469         __u16 hashm;
 470         __u8  pad06[2];
 471 };
 472
 473 struct nv50_disp_dac_pwr_v0 {
 474         __u8  version;
 475         __u8  state;
 476         __u8  data;
 477         __u8  vsync;
 478         __u8  hsync;
 479         __u8  pad05[3];
 480 };
 481
 482 struct nv50_disp_dac_load_v0 {
 483         __u8  version;
 484         __u8  load;
 485         __u8  pad02[2];
 486         __u32 data;
 487 };
 488
 489 struct nv50_disp_sor_pwr_v0 {
 490         __u8  version;
 491         __u8  state;
 492         __u8  pad02[6];
 493 };
 494
 495 struct nv50_disp_sor_hda_eld_v0 {
 496         __u8  version;
 497         __u8  pad01[7];
 498         __u8  data[];
 499 };
 500
 501 struct nv50_disp_sor_hdmi_pwr_v0 {
 502         __u8  version;
 503         __u8  state;
 504         __u8  max_ac_packet;
 505         __u8  rekey;
 506         __u8  pad04[4];
 507 };
 508
 509 struct nv50_disp_sor_lvds_script_v0 {
 510         __u8  version;
 511         __u8  pad01[1];
 512         __u16 script;
 513         __u8  pad04[4];
 514 };
 515
 516 struct nv50_disp_sor_dp_pwr_v0 {
 517         __u8  version;
 518         __u8  state;
 519         __u8  pad02[6];
 520 };
 521
 522 struct nv50_disp_pior_pwr_v0 {
 523         __u8  version;
 524         __u8  state;
 525         __u8  type;
 526         __u8  pad03[5];
 527 };
 528
 529 /* core */
 530 struct nv50_disp_core_channel_dma_v0 {
 531         __u8  version;
 532         __u8  pad01[7];
 533         __u64 pushbuf;
 534 };
 535
 536 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
 537
 538 /* cursor immediate */
 539 struct nv50_disp_cursor_v0 {
 540         __u8  version;
 541         __u8  head;
 542         __u8  pad02[6];
 543 };
 544
 545 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00
 546
 547 /* base */
 548 struct nv50_disp_base_channel_dma_v0 {
 549         __u8  version;
 550         __u8  head;
 551         __u8  pad02[6];
 552         __u64 pushbuf;
 553 };
 554
 555 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
 556
 557 /* overlay */
 558 struct nv50_disp_overlay_channel_dma_v0 {
 559         __u8  version;
 560         __u8  head;
 561         __u8  pad02[6];
 562         __u64 pushbuf;
 563 };
 564
 565 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00
 566
 567 /* overlay immediate */
 568 struct nv50_disp_overlay_v0 {
 569         __u8  version;
 570         __u8  head;
 571         __u8  pad02[6];
 572 };
 573
 574 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
 575
 576 /*******************************************************************************
 577  * fermi
 578  ******************************************************************************/
 579
 580 #define FERMI_A_ZBC_COLOR                                                  0x00
 581 #define FERMI_A_ZBC_DEPTH                                                  0x01
 582
 583 struct fermi_a_zbc_color_v0 {
 584         __u8  version;
 585 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO                                      0x01
 586 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE                                 0x02
 587 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32                       0x04
 588 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16                           0x08
 589 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16                       0x0c
 590 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16                       0x10
 591 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16                       0x14
 592 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16                       0x16
 593 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8                                  0x18
 594 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8                               0x1c
 595 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10                               0x20
 596 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10                           0x24
 597 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8                                  0x28
 598 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8                               0x2c
 599 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8                              0x30
 600 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8                              0x34
 601 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8                              0x38
 602 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10                               0x3c
 603 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11                              0x40
 604         __u8  format;
 605         __u8  index;
 606         __u8  pad03[5];
 607         __u32 ds[4];
 608         __u32 l2[4];
 609 };
 610
 611 struct fermi_a_zbc_depth_v0 {
 612         __u8  version;
 613 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32                                      0x01
 614         __u8  format;
 615         __u8  index;
 616         __u8  pad03[5];
 617         __u32 ds;
 618         __u32 l2;
 619 };
 620
 621 #endif